2 * Port for PPC64 David Engebretsen, IBM Corp.
3 * Contains common pci routines for ppc64 platform, pSeries and iSeries brands.
5 * Copyright (C) 2003 Anton Blanchard <anton@au.ibm.com>, IBM
6 * Rework, based on alpha PCI code.
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License
10 * as published by the Free Software Foundation; either version
11 * 2 of the License, or (at your option) any later version.
14 #include <linux/config.h>
15 #include <linux/kernel.h>
16 #include <linux/pci.h>
17 #include <linux/delay.h>
18 #include <linux/string.h>
19 #include <linux/init.h>
20 #include <linux/capability.h>
21 #include <linux/sched.h>
22 #include <linux/errno.h>
23 #include <linux/bootmem.h>
24 #include <linux/module.h>
26 #include <linux/list.h>
28 #include <asm/processor.h>
31 #include <asm/pci-bridge.h>
32 #include <asm/byteorder.h>
34 #include <asm/uaccess.h>
35 #include <asm/ppcdebug.h>
37 #include <asm/iommu.h>
38 #include <asm/machdep.h>
42 unsigned long pci_probe_only = 1;
43 unsigned long pci_assign_all_buses = 0;
45 /* legal IO pages under MAX_ISA_PORT. This is to ensure we don't touch
46 devices we don't have access to. */
47 unsigned long io_page_mask;
49 EXPORT_SYMBOL(io_page_mask);
52 unsigned int pcibios_assign_all_busses(void)
54 return pci_assign_all_buses;
57 /* pci_io_base -- the base address from which io bars are offsets.
58 * This is the lowest I/O base address (so bar values are always positive),
59 * and it *must* be the start of ISA space if an ISA bus exists because
60 * ISA drivers use hard coded offsets. If no ISA bus exists a dummy
61 * page is mapped and isa_io_limit prevents access to it.
63 unsigned long isa_io_base; /* NULL if no ISA bus */
64 unsigned long pci_io_base;
66 void iSeries_pcibios_init(void);
70 struct pci_dma_ops pci_dma_ops;
71 EXPORT_SYMBOL(pci_dma_ops);
73 int global_phb_number; /* Global phb counter */
75 /* Cached ISA bridge dev. */
76 struct pci_dev *ppc64_isabridge_dev = NULL;
78 static void fixup_broken_pcnet32(struct pci_dev* dev)
80 if ((dev->class>>8 == PCI_CLASS_NETWORK_ETHERNET)) {
81 dev->vendor = PCI_VENDOR_ID_AMD;
82 pci_write_config_word(dev, PCI_VENDOR_ID, PCI_VENDOR_ID_AMD);
86 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TRIDENT, PCI_ANY_ID, fixup_broken_pcnet32);
88 static void fixup_windbond_82c105(struct pci_dev* dev)
90 /* Assume the windbond 82c105 is the IDE controller on a
91 * p610. We should probably be more careful in case
92 * someone tries to plug in a similar adapter.
97 printk("Using INTC for W82c105 IDE controller.\n");
98 pci_read_config_dword(dev, 0x40, ®);
99 /* Enable LEGIRQ to use INTC instead of ISA interrupts */
100 pci_write_config_dword(dev, 0x40, reg | (1<<11));
102 for (i = 0; i < DEVICE_COUNT_RESOURCE; ++i) {
103 /* zap the 2nd function of the winbond chip */
104 if (dev->resource[i].flags & IORESOURCE_IO
105 && dev->bus->number == 0 && dev->devfn == 0x81)
106 dev->resource[i].flags &= ~IORESOURCE_IO;
109 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_WINBOND, PCI_DEVICE_ID_WINBOND_82C105, fixup_windbond_82c105);
112 pcibios_resource_to_bus(struct pci_dev *dev, struct pci_bus_region *region,
113 struct resource *res)
115 unsigned long offset = 0;
116 struct pci_controller *hose = PCI_GET_PHB_PTR(dev);
121 if (res->flags & IORESOURCE_IO)
122 offset = (unsigned long)hose->io_base_virt - pci_io_base;
124 if (res->flags & IORESOURCE_MEM)
125 offset = hose->pci_mem_offset;
127 region->start = res->start - offset;
128 region->end = res->end - offset;
131 #ifdef CONFIG_HOTPLUG
132 EXPORT_SYMBOL(pcibios_resource_to_bus);
136 * We need to avoid collisions with `mirrored' VGA ports
137 * and other strange ISA hardware, so we always want the
138 * addresses to be allocated in the 0x000-0x0ff region
141 * Why? Because some silly external IO cards only decode
142 * the low 10 bits of the IO address. The 0x00-0xff region
143 * is reserved for motherboard devices that decode all 16
144 * bits, so it's ok to allocate at, say, 0x2800-0x28ff,
145 * but we want to try to avoid allocating at 0x2900-0x2bff
146 * which might have be mirrored at 0x0100-0x03ff..
148 void pcibios_align_resource(void *data, struct resource *res,
149 unsigned long size, unsigned long align)
151 struct pci_dev *dev = data;
152 struct pci_controller *hose = PCI_GET_PHB_PTR(dev);
153 unsigned long start = res->start;
154 unsigned long alignto;
156 if (res->flags & IORESOURCE_IO) {
157 unsigned long offset = (unsigned long)hose->io_base_virt -
159 /* Make sure we start at our min on all hoses */
160 if (start - offset < PCIBIOS_MIN_IO)
161 start = PCIBIOS_MIN_IO + offset;
164 * Put everything into 0x00-0xff region modulo 0x400
167 start = (start + 0x3ff) & ~0x3ff;
169 } else if (res->flags & IORESOURCE_MEM) {
170 /* Make sure we start at our min on all hoses */
171 if (start - hose->pci_mem_offset < PCIBIOS_MIN_MEM)
172 start = PCIBIOS_MIN_MEM + hose->pci_mem_offset;
174 /* Align to multiple of size of minimum base. */
175 alignto = max(0x1000UL, align);
176 start = ALIGN(start, alignto);
182 static void phb_set_model(struct pci_controller *hose,
183 enum phb_types controller_type)
187 switch(controller_type) {
188 #ifdef CONFIG_PPC_ISERIES
189 case phb_type_hypervisor:
193 case phb_type_python:
196 case phb_type_speedwagon:
199 case phb_type_winnipeg:
210 if(strlen(model) < 8)
211 strcpy(hose->what,model);
213 memcpy(hose->what,model,7);
216 * Allocate pci_controller(phb) initialized common variables.
218 struct pci_controller * __init
219 pci_alloc_pci_controller(enum phb_types controller_type)
221 struct pci_controller *hose;
223 #ifdef CONFIG_PPC_ISERIES
224 hose = (struct pci_controller *)kmalloc(sizeof(struct pci_controller),
227 hose = (struct pci_controller *)alloc_bootmem(sizeof(struct pci_controller));
230 printk(KERN_ERR "PCI: Allocate pci_controller failed.\n");
233 memset(hose, 0, sizeof(struct pci_controller));
235 phb_set_model(hose, controller_type);
237 hose->is_dynamic = 0;
238 hose->type = controller_type;
239 hose->global_number = global_phb_number++;
241 list_add_tail(&hose->list_node, &hose_list);
247 * Dymnamically allocate pci_controller(phb), initialize common variables.
249 struct pci_controller *
250 pci_alloc_phb_dynamic(enum phb_types controller_type)
252 struct pci_controller *hose;
254 hose = (struct pci_controller *)kmalloc(sizeof(struct pci_controller),
257 printk(KERN_ERR "PCI: Allocate pci_controller failed.\n");
260 memset(hose, 0, sizeof(struct pci_controller));
262 phb_set_model(hose, controller_type);
264 hose->is_dynamic = 1;
265 hose->type = controller_type;
266 hose->global_number = global_phb_number++;
268 list_add_tail(&hose->list_node, &hose_list);
273 static void __init pcibios_claim_one_bus(struct pci_bus *b)
275 struct list_head *ld;
276 struct pci_bus *child_bus;
278 for (ld = b->devices.next; ld != &b->devices; ld = ld->next) {
279 struct pci_dev *dev = pci_dev_b(ld);
282 for (i = 0; i < PCI_NUM_RESOURCES; i++) {
283 struct resource *r = &dev->resource[i];
285 if (r->parent || !r->start || !r->flags)
287 pci_claim_resource(dev, i);
291 list_for_each_entry(child_bus, &b->children, node)
292 pcibios_claim_one_bus(child_bus);
295 #ifndef CONFIG_PPC_ISERIES
296 static void __init pcibios_claim_of_setup(void)
298 struct list_head *lb;
300 for (lb = pci_root_buses.next; lb != &pci_root_buses; lb = lb->next) {
301 struct pci_bus *b = pci_bus_b(lb);
302 pcibios_claim_one_bus(b);
307 static int __init pcibios_init(void)
309 struct pci_controller *hose, *tmp;
312 #ifdef CONFIG_PPC_ISERIES
313 iSeries_pcibios_init();
316 printk("PCI: Probing PCI hardware\n");
318 /* Scan all of the recorded PCI controllers. */
319 list_for_each_entry_safe(hose, tmp, &hose_list, list_node) {
320 hose->last_busno = 0xff;
321 bus = pci_scan_bus(hose->first_busno, hose->ops,
324 hose->last_busno = bus->subordinate;
327 #ifndef CONFIG_PPC_ISERIES
329 pcibios_claim_of_setup();
331 /* FIXME: `else' will be removed when
332 pci_assign_unassigned_resources() is able to work
333 correctly with [partially] allocated PCI tree. */
334 pci_assign_unassigned_resources();
335 #endif /* !CONFIG_PPC_ISERIES */
337 /* Call machine dependent final fixup */
338 if (ppc_md.pcibios_fixup)
339 ppc_md.pcibios_fixup();
341 /* Cache the location of the ISA bridge (if we have one) */
342 ppc64_isabridge_dev = pci_find_class(PCI_CLASS_BRIDGE_ISA << 8, NULL);
343 if (ppc64_isabridge_dev != NULL)
344 printk("ISA bridge at %s\n", pci_name(ppc64_isabridge_dev));
346 printk("PCI: Probing PCI hardware done\n");
351 subsys_initcall(pcibios_init);
353 char __init *pcibios_setup(char *str)
358 int pcibios_enable_device(struct pci_dev *dev, int mask)
363 pci_read_config_word(dev, PCI_COMMAND, &cmd);
366 for (i = 0; i < PCI_NUM_RESOURCES; i++) {
367 struct resource *res = &dev->resource[i];
369 /* Only set up the requested stuff */
370 if (!(mask & (1<<i)))
373 if (res->flags & IORESOURCE_IO)
374 cmd |= PCI_COMMAND_IO;
375 if (res->flags & IORESOURCE_MEM)
376 cmd |= PCI_COMMAND_MEMORY;
380 printk(KERN_DEBUG "PCI: Enabling device: (%s), cmd %x\n",
382 /* Enable the appropriate bits in the PCI command register. */
383 pci_write_config_word(dev, PCI_COMMAND, cmd);
389 * Return the domain number for this bus.
391 int pci_domain_nr(struct pci_bus *bus)
393 #ifdef CONFIG_PPC_ISERIES
396 struct pci_controller *hose = PCI_GET_PHB_PTR(bus);
398 return hose->global_number;
402 EXPORT_SYMBOL(pci_domain_nr);
404 /* Set the name of the bus as it appears in /proc/bus/pci */
405 int pci_name_bus(char *name, struct pci_bus *bus)
407 #ifndef CONFIG_PPC_ISERIES
408 struct pci_controller *hose = PCI_GET_PHB_PTR(bus);
411 sprintf(name, "%04x:%02x", pci_domain_nr(bus), bus->number);
414 sprintf(name, "%02x", bus->number);
420 * Platform support for /proc/bus/pci/X/Y mmap()s,
421 * modelled on the sparc64 implementation by Dave Miller.
426 * Adjust vm_pgoff of VMA such that it is the physical page offset
427 * corresponding to the 32-bit pci bus offset for DEV requested by the user.
429 * Basically, the user finds the base address for his device which he wishes
430 * to mmap. They read the 32-bit value from the config space base register,
431 * add whatever PAGE_SIZE multiple offset they wish, and feed this into the
432 * offset parameter of mmap on /proc/bus/pci/XXX for that device.
434 * Returns negative error code on failure, zero on success.
436 static __inline__ int
437 __pci_mmap_make_offset(struct pci_dev *dev, struct vm_area_struct *vma,
438 enum pci_mmap_state mmap_state)
440 struct pci_controller *hose = PCI_GET_PHB_PTR(dev);
441 unsigned long offset = vma->vm_pgoff << PAGE_SHIFT;
442 unsigned long io_offset = 0;
446 return -EINVAL; /* should never happen */
448 /* If memory, add on the PCI bridge address offset */
449 if (mmap_state == pci_mmap_mem) {
450 offset += hose->pci_mem_offset;
451 res_bit = IORESOURCE_MEM;
453 io_offset = (unsigned long)hose->io_base_virt;
455 res_bit = IORESOURCE_IO;
459 * Check that the offset requested corresponds to one of the
460 * resources of the device.
462 for (i = 0; i <= PCI_ROM_RESOURCE; i++) {
463 struct resource *rp = &dev->resource[i];
464 int flags = rp->flags;
466 /* treat ROM as memory (should be already) */
467 if (i == PCI_ROM_RESOURCE)
468 flags |= IORESOURCE_MEM;
470 /* Active and same type? */
471 if ((flags & res_bit) == 0)
474 /* In the range of this resource? */
475 if (offset < (rp->start & PAGE_MASK) || offset > rp->end)
478 /* found it! construct the final physical address */
479 if (mmap_state == pci_mmap_io)
480 offset += hose->io_base_phys - io_offset;
482 vma->vm_pgoff = offset >> PAGE_SHIFT;
490 * Set vm_flags of VMA, as appropriate for this architecture, for a pci device
493 static __inline__ void
494 __pci_mmap_set_flags(struct pci_dev *dev, struct vm_area_struct *vma,
495 enum pci_mmap_state mmap_state)
497 vma->vm_flags |= VM_SHM | VM_LOCKED | VM_IO;
501 * Set vm_page_prot of VMA, as appropriate for this architecture, for a pci
504 static __inline__ void
505 __pci_mmap_set_pgprot(struct pci_dev *dev, struct vm_area_struct *vma,
506 enum pci_mmap_state mmap_state, int write_combine)
508 long prot = pgprot_val(vma->vm_page_prot);
510 /* XXX would be nice to have a way to ask for write-through */
511 prot |= _PAGE_NO_CACHE;
513 prot |= _PAGE_GUARDED;
514 vma->vm_page_prot = __pgprot(prot);
518 * Perform the actual remap of the pages for a PCI device mapping, as
519 * appropriate for this architecture. The region in the process to map
520 * is described by vm_start and vm_end members of VMA, the base physical
521 * address is found in vm_pgoff.
522 * The pci device structure is provided so that architectures may make mapping
523 * decisions on a per-device or per-bus basis.
525 * Returns a negative error code on failure, zero on success.
527 int pci_mmap_page_range(struct pci_dev *dev, struct vm_area_struct *vma,
528 enum pci_mmap_state mmap_state,
533 ret = __pci_mmap_make_offset(dev, vma, mmap_state);
537 __pci_mmap_set_flags(dev, vma, mmap_state);
538 __pci_mmap_set_pgprot(dev, vma, mmap_state, write_combine);
540 ret = remap_page_range(vma, vma->vm_start, vma->vm_pgoff << PAGE_SHIFT,
541 vma->vm_end - vma->vm_start, vma->vm_page_prot);
546 #ifdef CONFIG_PPC_MULTIPLATFORM
547 static ssize_t pci_show_devspec(struct device *dev, char *buf)
549 struct pci_dev *pdev;
550 struct device_node *np;
552 pdev = to_pci_dev (dev);
553 np = pci_device_to_OF_node(pdev);
554 if (np == NULL || np->full_name == NULL)
556 return sprintf(buf, "%s", np->full_name);
558 static DEVICE_ATTR(devspec, S_IRUGO, pci_show_devspec, NULL);
559 #endif /* CONFIG_PPC_MULTIPLATFORM */
561 void pcibios_add_platform_entries(struct pci_dev *pdev)
563 #ifdef CONFIG_PPC_MULTIPLATFORM
564 device_create_file(&pdev->dev, &dev_attr_devspec);
565 #endif /* CONFIG_PPC_MULTIPLATFORM */
568 #ifdef CONFIG_PPC_MULTIPLATFORM
570 #define ISA_SPACE_MASK 0x1
571 #define ISA_SPACE_IO 0x1
573 static void __devinit pci_process_ISA_OF_ranges(struct device_node *isa_node,
574 unsigned long phb_io_base_phys,
575 void * phb_io_base_virt)
577 struct isa_range *range;
578 unsigned long pci_addr;
579 unsigned int isa_addr;
583 range = (struct isa_range *) get_property(isa_node, "ranges", &rlen);
584 if (rlen < sizeof(struct isa_range)) {
585 printk(KERN_ERR "unexpected isa range size: %s\n",
590 /* From "ISA Binding to 1275"
591 * The ranges property is laid out as an array of elements,
592 * each of which comprises:
593 * cells 0 - 1: an ISA address
594 * cells 2 - 4: a PCI address
595 * (size depending on dev->n_addr_cells)
596 * cell 5: the size of the range
598 if ((range->isa_addr.a_hi && ISA_SPACE_MASK) == ISA_SPACE_IO) {
599 isa_addr = range->isa_addr.a_lo;
600 pci_addr = (unsigned long) range->pci_addr.a_mid << 32 |
601 range->pci_addr.a_lo;
603 /* Assume these are both zero */
604 if ((pci_addr != 0) || (isa_addr != 0)) {
605 printk(KERN_ERR "unexpected isa to pci mapping: %s\n",
610 size = PAGE_ALIGN(range->size);
612 __ioremap_explicit(phb_io_base_phys,
613 (unsigned long) phb_io_base_virt,
614 size, _PAGE_NO_CACHE);
618 void __devinit pci_process_bridge_OF_ranges(struct pci_controller *hose,
619 struct device_node *dev)
621 unsigned int *ranges;
625 struct resource *res;
626 int np, na = prom_n_addr_cells(dev);
627 unsigned long pci_addr, cpu_phys_addr;
631 /* From "PCI Binding to 1275"
632 * The ranges property is laid out as an array of elements,
633 * each of which comprises:
634 * cells 0 - 2: a PCI address
635 * cells 3 or 3+4: a CPU physical address
636 * (size depending on dev->n_addr_cells)
637 * cells 4+5 or 5+6: the size of the range
640 hose->io_base_phys = 0;
641 ranges = (unsigned int *) get_property(dev, "ranges", &rlen);
642 while ((rlen -= np * sizeof(unsigned int)) >= 0) {
644 pci_addr = (unsigned long)ranges[1] << 32 | ranges[2];
646 cpu_phys_addr = ranges[3];
648 cpu_phys_addr = cpu_phys_addr << 32 | ranges[4];
650 size = (unsigned long)ranges[na+3] << 32 | ranges[na+4];
652 switch (ranges[0] >> 24) {
653 case 1: /* I/O space */
654 hose->io_base_phys = cpu_phys_addr;
655 hose->pci_io_size = size;
657 res = &hose->io_resource;
658 res->flags = IORESOURCE_IO;
659 res->start = pci_addr;
661 case 2: /* memory space */
663 while (memno < 3 && hose->mem_resources[memno].flags)
667 hose->pci_mem_offset = cpu_phys_addr - pci_addr;
669 res = &hose->mem_resources[memno];
670 res->flags = IORESOURCE_MEM;
671 res->start = cpu_phys_addr;
676 res->name = dev->full_name;
677 res->end = res->start + size - 1;
686 void __init pci_setup_phb_io(struct pci_controller *hose, int primary)
688 unsigned long size = hose->pci_io_size;
689 unsigned long io_virt_offset;
690 struct resource *res;
691 struct device_node *isa_dn;
693 hose->io_base_virt = reserve_phb_iospace(size);
694 PPCDBG(PPCDBG_PHBINIT, "phb%d io_base_phys 0x%lx io_base_virt 0x%lx\n",
695 hose->global_number, hose->io_base_phys,
696 (unsigned long) hose->io_base_virt);
699 pci_io_base = (unsigned long)hose->io_base_virt;
700 isa_dn = of_find_node_by_type(NULL, "isa");
702 isa_io_base = pci_io_base;
703 pci_process_ISA_OF_ranges(isa_dn, hose->io_base_phys,
711 io_virt_offset = (unsigned long)hose->io_base_virt - pci_io_base;
712 res = &hose->io_resource;
713 res->start += io_virt_offset;
714 res->end += io_virt_offset;
717 void __devinit pci_setup_phb_io_dynamic(struct pci_controller *hose)
719 unsigned long size = hose->pci_io_size;
720 unsigned long io_virt_offset;
721 struct resource *res;
723 hose->io_base_virt = __ioremap(hose->io_base_phys, size,
725 PPCDBG(PPCDBG_PHBINIT, "phb%d io_base_phys 0x%lx io_base_virt 0x%lx\n",
726 hose->global_number, hose->io_base_phys,
727 (unsigned long) hose->io_base_virt);
729 io_virt_offset = (unsigned long)hose->io_base_virt - pci_io_base;
730 res = &hose->io_resource;
731 res->start += io_virt_offset;
732 res->end += io_virt_offset;
735 /***********************************************************************
736 * pci_find_hose_for_OF_device
738 * This function finds the PHB that matching device_node in the
739 * OpenFirmware by scanning all the pci_controllers.
741 ***********************************************************************/
742 struct pci_controller* pci_find_hose_for_OF_device(struct device_node *node)
745 struct pci_controller *hose, *tmp;
746 list_for_each_entry_safe(hose, tmp, &hose_list, list_node)
747 if (hose->arch_data == node)
755 * ppc64 can have multifunction devices that do not respond to function 0.
756 * In this case we must scan all functions.
758 int pcibios_scan_all_fns(struct pci_bus *bus, int devfn)
760 struct device_node *busdn, *dn;
763 busdn = pci_device_to_OF_node(bus->self);
765 busdn = bus->sysdata; /* must be a phb */
768 * Check to see if there is any of the 8 functions are in the
769 * device tree. If they are then we need to scan all the
770 * functions of this slot.
772 for (dn = busdn->child; dn; dn = dn->sibling)
773 if ((dn->devfn >> 3) == (devfn >> 3))
780 void __devinit pcibios_fixup_device_resources(struct pci_dev *dev,
783 /* Update device resources. */
784 struct pci_controller *hose = PCI_GET_PHB_PTR(bus);
787 for (i = 0; i < PCI_NUM_RESOURCES; i++) {
788 if (dev->resource[i].flags & IORESOURCE_IO) {
789 unsigned long offset = (unsigned long)hose->io_base_virt - pci_io_base;
790 unsigned long start, end, mask;
792 start = dev->resource[i].start += offset;
793 end = dev->resource[i].end += offset;
795 /* Need to allow IO access to pages that are in the
797 if (start < MAX_ISA_PORT) {
798 if (end > MAX_ISA_PORT)
801 start >>= PAGE_SHIFT;
804 /* get the range of pages for the map */
805 mask = ((1 << (end+1))-1) ^ ((1 << start)-1);
806 io_page_mask |= mask;
809 else if (dev->resource[i].flags & IORESOURCE_MEM) {
810 dev->resource[i].start += hose->pci_mem_offset;
811 dev->resource[i].end += hose->pci_mem_offset;
815 EXPORT_SYMBOL(pcibios_fixup_device_resources);
817 void __devinit pcibios_fixup_bus(struct pci_bus *bus)
819 struct pci_controller *hose = PCI_GET_PHB_PTR(bus);
820 struct list_head *ln;
822 /* XXX or bus->parent? */
823 struct pci_dev *dev = bus->self;
824 struct resource *res;
831 bus->resource[0] = res = &hose->io_resource;
833 BUG(); /* No I/O resource for this PHB? */
835 if (request_resource(&ioport_resource, res))
836 printk(KERN_ERR "Failed to request IO on "
837 "PCI domain %d\n", pci_domain_nr(bus));
840 for (i = 0; i < 3; ++i) {
841 res = &hose->mem_resources[i];
842 if (!res->flags && i == 0)
843 BUG(); /* No memory resource for this PHB? */
844 bus->resource[i+1] = res;
845 if (res->flags && request_resource(&iomem_resource, res))
846 printk(KERN_ERR "Failed to request MEM on "
850 } else if (pci_probe_only &&
851 (dev->class >> 8) == PCI_CLASS_BRIDGE_PCI) {
852 /* This is a subordinate bridge */
854 pci_read_bridge_bases(bus);
855 pcibios_fixup_device_resources(dev, bus);
858 /* XXX Need to check why Alpha doesnt do this - Anton */
862 for (ln = bus->devices.next; ln != &bus->devices; ln = ln->next) {
863 struct pci_dev *dev = pci_dev_b(ln);
864 if ((dev->class >> 8) != PCI_CLASS_BRIDGE_PCI)
865 pcibios_fixup_device_resources(dev, bus);
868 EXPORT_SYMBOL(pcibios_fixup_bus);
870 /******************************************************************
873 * Reads the Interrupt Pin to determine if interrupt is use by card.
874 * If the interrupt is used, then gets the interrupt line from the
875 * openfirmware and sets it in the pci_dev and pci_config line.
877 ******************************************************************/
878 int pci_read_irq_line(struct pci_dev *pci_dev)
881 struct device_node *node;
883 pci_read_config_byte(pci_dev, PCI_INTERRUPT_PIN, &intpin);
886 PPCDBG(PPCDBG_BUSWALK,"\tDevice: %s No Interrupt used by device.\n",
891 node = pci_device_to_OF_node(pci_dev);
893 PPCDBG(PPCDBG_BUSWALK,"\tDevice: %s Device Node not found.\n",
897 if (node->n_intrs == 0) {
898 PPCDBG(PPCDBG_BUSWALK,"\tDevice: %s No Device OF interrupts defined.\n",
902 pci_dev->irq = node->intrs[0].line;
904 pci_write_config_byte(pci_dev, PCI_INTERRUPT_LINE, pci_dev->irq);
906 PPCDBG(PPCDBG_BUSWALK,"\tDevice: %s pci_dev->irq = 0x%02X\n",
907 pci_name(pci_dev), pci_dev->irq);
910 EXPORT_SYMBOL(pci_read_irq_line);
912 #endif /* CONFIG_PPC_MULTIPLATFORM */