2 * Port for PPC64 David Engebretsen, IBM Corp.
3 * Contains common pci routines for ppc64 platform, pSeries and iSeries brands.
5 * Copyright (C) 2003 Anton Blanchard <anton@au.ibm.com>, IBM
6 * Rework, based on alpha PCI code.
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License
10 * as published by the Free Software Foundation; either version
11 * 2 of the License, or (at your option) any later version.
16 #include <linux/config.h>
17 #include <linux/kernel.h>
18 #include <linux/pci.h>
19 #include <linux/string.h>
20 #include <linux/init.h>
21 #include <linux/bootmem.h>
23 #include <linux/list.h>
25 #include <asm/processor.h>
28 #include <asm/pci-bridge.h>
29 #include <asm/byteorder.h>
31 #include <asm/machdep.h>
37 #define DBG(fmt...) udbg_printf(fmt)
42 unsigned long pci_probe_only = 1;
43 unsigned long pci_assign_all_buses = 0;
46 * legal IO pages under MAX_ISA_PORT. This is to ensure we don't touch
47 * devices we don't have access to.
49 unsigned long io_page_mask;
51 EXPORT_SYMBOL(io_page_mask);
54 unsigned int pcibios_assign_all_busses(void)
56 return pci_assign_all_buses;
59 /* pci_io_base -- the base address from which io bars are offsets.
60 * This is the lowest I/O base address (so bar values are always positive),
61 * and it *must* be the start of ISA space if an ISA bus exists because
62 * ISA drivers use hard coded offsets. If no ISA bus exists a dummy
63 * page is mapped and isa_io_limit prevents access to it.
65 unsigned long isa_io_base; /* NULL if no ISA bus */
66 unsigned long pci_io_base;
68 void iSeries_pcibios_init(void);
72 struct pci_dma_ops pci_dma_ops;
73 EXPORT_SYMBOL(pci_dma_ops);
75 int global_phb_number; /* Global phb counter */
77 /* Cached ISA bridge dev. */
78 struct pci_dev *ppc64_isabridge_dev = NULL;
80 static void fixup_broken_pcnet32(struct pci_dev* dev)
82 if ((dev->class>>8 == PCI_CLASS_NETWORK_ETHERNET)) {
83 dev->vendor = PCI_VENDOR_ID_AMD;
84 pci_write_config_word(dev, PCI_VENDOR_ID, PCI_VENDOR_ID_AMD);
88 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TRIDENT, PCI_ANY_ID, fixup_broken_pcnet32);
90 void pcibios_resource_to_bus(struct pci_dev *dev, struct pci_bus_region *region,
93 unsigned long offset = 0;
94 struct pci_controller *hose = pci_bus_to_host(dev->bus);
99 if (res->flags & IORESOURCE_IO)
100 offset = (unsigned long)hose->io_base_virt - pci_io_base;
102 if (res->flags & IORESOURCE_MEM)
103 offset = hose->pci_mem_offset;
105 region->start = res->start - offset;
106 region->end = res->end - offset;
109 #ifdef CONFIG_HOTPLUG
110 EXPORT_SYMBOL(pcibios_resource_to_bus);
114 * We need to avoid collisions with `mirrored' VGA ports
115 * and other strange ISA hardware, so we always want the
116 * addresses to be allocated in the 0x000-0x0ff region
119 * Why? Because some silly external IO cards only decode
120 * the low 10 bits of the IO address. The 0x00-0xff region
121 * is reserved for motherboard devices that decode all 16
122 * bits, so it's ok to allocate at, say, 0x2800-0x28ff,
123 * but we want to try to avoid allocating at 0x2900-0x2bff
124 * which might have be mirrored at 0x0100-0x03ff..
126 void pcibios_align_resource(void *data, struct resource *res,
127 unsigned long size, unsigned long align)
129 struct pci_dev *dev = data;
130 struct pci_controller *hose = pci_bus_to_host(dev->bus);
131 unsigned long start = res->start;
132 unsigned long alignto;
134 if (res->flags & IORESOURCE_IO) {
135 unsigned long offset = (unsigned long)hose->io_base_virt -
137 /* Make sure we start at our min on all hoses */
138 if (start - offset < PCIBIOS_MIN_IO)
139 start = PCIBIOS_MIN_IO + offset;
142 * Put everything into 0x00-0xff region modulo 0x400
145 start = (start + 0x3ff) & ~0x3ff;
147 } else if (res->flags & IORESOURCE_MEM) {
148 /* Make sure we start at our min on all hoses */
149 if (start - hose->pci_mem_offset < PCIBIOS_MIN_MEM)
150 start = PCIBIOS_MIN_MEM + hose->pci_mem_offset;
152 /* Align to multiple of size of minimum base. */
153 alignto = max(0x1000UL, align);
154 start = ALIGN(start, alignto);
160 static DEFINE_SPINLOCK(hose_spinlock);
163 * pci_controller(phb) initialized common variables.
165 void __devinit pci_setup_pci_controller(struct pci_controller *hose)
167 memset(hose, 0, sizeof(struct pci_controller));
169 spin_lock(&hose_spinlock);
170 hose->global_number = global_phb_number++;
171 list_add_tail(&hose->list_node, &hose_list);
172 spin_unlock(&hose_spinlock);
175 static void __init pcibios_claim_one_bus(struct pci_bus *b)
178 struct pci_bus *child_bus;
180 list_for_each_entry(dev, &b->devices, bus_list) {
183 for (i = 0; i < PCI_NUM_RESOURCES; i++) {
184 struct resource *r = &dev->resource[i];
186 if (r->parent || !r->start || !r->flags)
188 pci_claim_resource(dev, i);
192 list_for_each_entry(child_bus, &b->children, node)
193 pcibios_claim_one_bus(child_bus);
196 #ifndef CONFIG_PPC_ISERIES
197 static void __init pcibios_claim_of_setup(void)
201 list_for_each_entry(b, &pci_root_buses, node)
202 pcibios_claim_one_bus(b);
206 static int __init pcibios_init(void)
208 struct pci_controller *hose, *tmp;
211 #ifdef CONFIG_PPC_ISERIES
212 iSeries_pcibios_init();
215 printk("PCI: Probing PCI hardware\n");
217 /* Scan all of the recorded PCI controllers. */
218 list_for_each_entry_safe(hose, tmp, &hose_list, list_node) {
219 hose->last_busno = 0xff;
220 bus = pci_scan_bus(hose->first_busno, hose->ops,
223 hose->last_busno = bus->subordinate;
226 #ifndef CONFIG_PPC_ISERIES
228 pcibios_claim_of_setup();
230 /* FIXME: `else' will be removed when
231 pci_assign_unassigned_resources() is able to work
232 correctly with [partially] allocated PCI tree. */
233 pci_assign_unassigned_resources();
234 #endif /* !CONFIG_PPC_ISERIES */
236 /* Call machine dependent final fixup */
237 if (ppc_md.pcibios_fixup)
238 ppc_md.pcibios_fixup();
240 /* Cache the location of the ISA bridge (if we have one) */
241 ppc64_isabridge_dev = pci_get_class(PCI_CLASS_BRIDGE_ISA << 8, NULL);
242 if (ppc64_isabridge_dev != NULL)
243 printk("ISA bridge at %s\n", pci_name(ppc64_isabridge_dev));
245 printk("PCI: Probing PCI hardware done\n");
250 subsys_initcall(pcibios_init);
252 char __init *pcibios_setup(char *str)
257 int pcibios_enable_device(struct pci_dev *dev, int mask)
262 pci_read_config_word(dev, PCI_COMMAND, &cmd);
265 for (i = 0; i < PCI_NUM_RESOURCES; i++) {
266 struct resource *res = &dev->resource[i];
268 /* Only set up the requested stuff */
269 if (!(mask & (1<<i)))
272 if (res->flags & IORESOURCE_IO)
273 cmd |= PCI_COMMAND_IO;
274 if (res->flags & IORESOURCE_MEM)
275 cmd |= PCI_COMMAND_MEMORY;
279 printk(KERN_DEBUG "PCI: Enabling device: (%s), cmd %x\n",
281 /* Enable the appropriate bits in the PCI command register. */
282 pci_write_config_word(dev, PCI_COMMAND, cmd);
288 * Return the domain number for this bus.
290 int pci_domain_nr(struct pci_bus *bus)
292 #ifdef CONFIG_PPC_ISERIES
295 struct pci_controller *hose = pci_bus_to_host(bus);
297 return hose->global_number;
301 EXPORT_SYMBOL(pci_domain_nr);
303 /* Set the name of the bus as it appears in /proc/bus/pci */
304 int pci_name_bus(char *name, struct pci_bus *bus)
306 #ifndef CONFIG_PPC_ISERIES
307 struct pci_controller *hose = pci_bus_to_host(bus);
310 sprintf(name, "%04x:%02x", pci_domain_nr(bus), bus->number);
313 sprintf(name, "%02x", bus->number);
319 * Platform support for /proc/bus/pci/X/Y mmap()s,
320 * modelled on the sparc64 implementation by Dave Miller.
325 * Adjust vm_pgoff of VMA such that it is the physical page offset
326 * corresponding to the 32-bit pci bus offset for DEV requested by the user.
328 * Basically, the user finds the base address for his device which he wishes
329 * to mmap. They read the 32-bit value from the config space base register,
330 * add whatever PAGE_SIZE multiple offset they wish, and feed this into the
331 * offset parameter of mmap on /proc/bus/pci/XXX for that device.
333 * Returns negative error code on failure, zero on success.
335 static __inline__ int __pci_mmap_make_offset(struct pci_dev *dev,
336 struct vm_area_struct *vma,
337 enum pci_mmap_state mmap_state)
339 struct pci_controller *hose = pci_bus_to_host(dev->bus);
340 unsigned long offset = vma->vm_pgoff << PAGE_SHIFT;
341 unsigned long io_offset = 0;
345 return -EINVAL; /* should never happen */
347 /* If memory, add on the PCI bridge address offset */
348 if (mmap_state == pci_mmap_mem) {
349 offset += hose->pci_mem_offset;
350 res_bit = IORESOURCE_MEM;
352 io_offset = (unsigned long)hose->io_base_virt;
354 res_bit = IORESOURCE_IO;
358 * Check that the offset requested corresponds to one of the
359 * resources of the device.
361 for (i = 0; i <= PCI_ROM_RESOURCE; i++) {
362 struct resource *rp = &dev->resource[i];
363 int flags = rp->flags;
365 /* treat ROM as memory (should be already) */
366 if (i == PCI_ROM_RESOURCE)
367 flags |= IORESOURCE_MEM;
369 /* Active and same type? */
370 if ((flags & res_bit) == 0)
373 /* In the range of this resource? */
374 if (offset < (rp->start & PAGE_MASK) || offset > rp->end)
377 /* found it! construct the final physical address */
378 if (mmap_state == pci_mmap_io)
379 offset += hose->io_base_phys - io_offset;
381 vma->vm_pgoff = offset >> PAGE_SHIFT;
389 * Set vm_flags of VMA, as appropriate for this architecture, for a pci device
392 static __inline__ void __pci_mmap_set_flags(struct pci_dev *dev,
393 struct vm_area_struct *vma,
394 enum pci_mmap_state mmap_state)
396 vma->vm_flags |= VM_SHM | VM_LOCKED | VM_IO;
400 * Set vm_page_prot of VMA, as appropriate for this architecture, for a pci
403 static __inline__ void __pci_mmap_set_pgprot(struct pci_dev *dev,
404 struct vm_area_struct *vma,
405 enum pci_mmap_state mmap_state,
408 long prot = pgprot_val(vma->vm_page_prot);
410 /* XXX would be nice to have a way to ask for write-through */
411 prot |= _PAGE_NO_CACHE;
413 prot |= _PAGE_GUARDED;
414 vma->vm_page_prot = __pgprot(prot);
418 * Perform the actual remap of the pages for a PCI device mapping, as
419 * appropriate for this architecture. The region in the process to map
420 * is described by vm_start and vm_end members of VMA, the base physical
421 * address is found in vm_pgoff.
422 * The pci device structure is provided so that architectures may make mapping
423 * decisions on a per-device or per-bus basis.
425 * Returns a negative error code on failure, zero on success.
427 int pci_mmap_page_range(struct pci_dev *dev, struct vm_area_struct *vma,
428 enum pci_mmap_state mmap_state,
433 ret = __pci_mmap_make_offset(dev, vma, mmap_state);
437 __pci_mmap_set_flags(dev, vma, mmap_state);
438 __pci_mmap_set_pgprot(dev, vma, mmap_state, write_combine);
440 ret = remap_pfn_range(vma, vma->vm_start, vma->vm_pgoff,
441 vma->vm_end - vma->vm_start, vma->vm_page_prot);
446 #ifdef CONFIG_PPC_MULTIPLATFORM
447 static ssize_t pci_show_devspec(struct device *dev, char *buf)
449 struct pci_dev *pdev;
450 struct device_node *np;
452 pdev = to_pci_dev (dev);
453 np = pci_device_to_OF_node(pdev);
454 if (np == NULL || np->full_name == NULL)
456 return sprintf(buf, "%s", np->full_name);
458 static DEVICE_ATTR(devspec, S_IRUGO, pci_show_devspec, NULL);
459 #endif /* CONFIG_PPC_MULTIPLATFORM */
461 void pcibios_add_platform_entries(struct pci_dev *pdev)
463 #ifdef CONFIG_PPC_MULTIPLATFORM
464 device_create_file(&pdev->dev, &dev_attr_devspec);
465 #endif /* CONFIG_PPC_MULTIPLATFORM */
468 #ifdef CONFIG_PPC_MULTIPLATFORM
470 #define ISA_SPACE_MASK 0x1
471 #define ISA_SPACE_IO 0x1
473 static void __devinit pci_process_ISA_OF_ranges(struct device_node *isa_node,
474 unsigned long phb_io_base_phys,
475 void __iomem * phb_io_base_virt)
477 struct isa_range *range;
478 unsigned long pci_addr;
479 unsigned int isa_addr;
483 range = (struct isa_range *) get_property(isa_node, "ranges", &rlen);
484 if (range == NULL || (rlen < sizeof(struct isa_range))) {
485 printk(KERN_ERR "no ISA ranges or unexpected isa range size,"
487 __ioremap_explicit(phb_io_base_phys, (unsigned long)phb_io_base_virt,
488 0x10000, _PAGE_NO_CACHE);
492 /* From "ISA Binding to 1275"
493 * The ranges property is laid out as an array of elements,
494 * each of which comprises:
495 * cells 0 - 1: an ISA address
496 * cells 2 - 4: a PCI address
497 * (size depending on dev->n_addr_cells)
498 * cell 5: the size of the range
500 if ((range->isa_addr.a_hi && ISA_SPACE_MASK) == ISA_SPACE_IO) {
501 isa_addr = range->isa_addr.a_lo;
502 pci_addr = (unsigned long) range->pci_addr.a_mid << 32 |
503 range->pci_addr.a_lo;
505 /* Assume these are both zero */
506 if ((pci_addr != 0) || (isa_addr != 0)) {
507 printk(KERN_ERR "unexpected isa to pci mapping: %s\n",
512 size = PAGE_ALIGN(range->size);
514 __ioremap_explicit(phb_io_base_phys,
515 (unsigned long) phb_io_base_virt,
516 size, _PAGE_NO_CACHE);
520 void __devinit pci_process_bridge_OF_ranges(struct pci_controller *hose,
521 struct device_node *dev)
523 unsigned int *ranges;
527 struct resource *res;
528 int np, na = prom_n_addr_cells(dev);
529 unsigned long pci_addr, cpu_phys_addr;
533 /* From "PCI Binding to 1275"
534 * The ranges property is laid out as an array of elements,
535 * each of which comprises:
536 * cells 0 - 2: a PCI address
537 * cells 3 or 3+4: a CPU physical address
538 * (size depending on dev->n_addr_cells)
539 * cells 4+5 or 5+6: the size of the range
542 hose->io_base_phys = 0;
543 ranges = (unsigned int *) get_property(dev, "ranges", &rlen);
544 while ((rlen -= np * sizeof(unsigned int)) >= 0) {
546 pci_addr = (unsigned long)ranges[1] << 32 | ranges[2];
548 cpu_phys_addr = ranges[3];
550 cpu_phys_addr = cpu_phys_addr << 32 | ranges[4];
552 size = (unsigned long)ranges[na+3] << 32 | ranges[na+4];
555 switch ((ranges[0] >> 24) & 0x3) {
556 case 1: /* I/O space */
557 hose->io_base_phys = cpu_phys_addr;
558 hose->pci_io_size = size;
560 res = &hose->io_resource;
561 res->flags = IORESOURCE_IO;
562 res->start = pci_addr;
563 DBG("phb%d: IO 0x%lx -> 0x%lx\n", hose->global_number,
564 res->start, res->start + size - 1);
566 case 2: /* memory space */
568 while (memno < 3 && hose->mem_resources[memno].flags)
572 hose->pci_mem_offset = cpu_phys_addr - pci_addr;
574 res = &hose->mem_resources[memno];
575 res->flags = IORESOURCE_MEM;
576 res->start = cpu_phys_addr;
577 DBG("phb%d: MEM 0x%lx -> 0x%lx\n", hose->global_number,
578 res->start, res->start + size - 1);
583 res->name = dev->full_name;
584 res->end = res->start + size - 1;
593 void __init pci_setup_phb_io(struct pci_controller *hose, int primary)
595 unsigned long size = hose->pci_io_size;
596 unsigned long io_virt_offset;
597 struct resource *res;
598 struct device_node *isa_dn;
600 hose->io_base_virt = reserve_phb_iospace(size);
601 DBG("phb%d io_base_phys 0x%lx io_base_virt 0x%lx\n",
602 hose->global_number, hose->io_base_phys,
603 (unsigned long) hose->io_base_virt);
606 pci_io_base = (unsigned long)hose->io_base_virt;
607 isa_dn = of_find_node_by_type(NULL, "isa");
609 isa_io_base = pci_io_base;
610 pci_process_ISA_OF_ranges(isa_dn, hose->io_base_phys,
618 io_virt_offset = (unsigned long)hose->io_base_virt - pci_io_base;
619 res = &hose->io_resource;
620 res->start += io_virt_offset;
621 res->end += io_virt_offset;
624 void __devinit pci_setup_phb_io_dynamic(struct pci_controller *hose)
626 unsigned long size = hose->pci_io_size;
627 unsigned long io_virt_offset;
628 struct resource *res;
630 hose->io_base_virt = __ioremap(hose->io_base_phys, size,
632 DBG("phb%d io_base_phys 0x%lx io_base_virt 0x%lx\n",
633 hose->global_number, hose->io_base_phys,
634 (unsigned long) hose->io_base_virt);
636 io_virt_offset = (unsigned long)hose->io_base_virt - pci_io_base;
637 res = &hose->io_resource;
638 res->start += io_virt_offset;
639 res->end += io_virt_offset;
643 static int get_bus_io_range(struct pci_bus *bus, unsigned long *start_phys,
644 unsigned long *start_virt, unsigned long *size)
646 struct pci_controller *hose = pci_bus_to_host(bus);
647 struct pci_bus_region region;
648 struct resource *res;
651 res = bus->resource[0];
652 pcibios_resource_to_bus(bus->self, ®ion, res);
653 *start_phys = hose->io_base_phys + region.start;
654 *start_virt = (unsigned long) hose->io_base_virt +
656 if (region.end > region.start)
657 *size = region.end - region.start + 1;
659 printk("%s(): unexpected region 0x%lx->0x%lx\n",
660 __FUNCTION__, region.start, region.end);
666 res = &hose->io_resource;
667 *start_phys = hose->io_base_phys;
668 *start_virt = (unsigned long) hose->io_base_virt;
669 if (res->end > res->start)
670 *size = res->end - res->start + 1;
672 printk("%s(): unexpected region 0x%lx->0x%lx\n",
673 __FUNCTION__, res->start, res->end);
681 int unmap_bus_range(struct pci_bus *bus)
683 unsigned long start_phys;
684 unsigned long start_virt;
688 printk(KERN_ERR "%s() expected bus\n", __FUNCTION__);
692 if (get_bus_io_range(bus, &start_phys, &start_virt, &size))
694 if (iounmap_explicit((void __iomem *) start_virt, size))
699 EXPORT_SYMBOL(unmap_bus_range);
701 int remap_bus_range(struct pci_bus *bus)
703 unsigned long start_phys;
704 unsigned long start_virt;
708 printk(KERN_ERR "%s() expected bus\n", __FUNCTION__);
713 if (get_bus_io_range(bus, &start_phys, &start_virt, &size))
715 printk("mapping IO %lx -> %lx, size: %lx\n", start_phys, start_virt, size);
716 if (__ioremap_explicit(start_phys, start_virt, size, _PAGE_NO_CACHE))
721 EXPORT_SYMBOL(remap_bus_range);
723 void phbs_remap_io(void)
725 struct pci_controller *hose, *tmp;
727 list_for_each_entry_safe(hose, tmp, &hose_list, list_node)
728 remap_bus_range(hose->bus);
732 * ppc64 can have multifunction devices that do not respond to function 0.
733 * In this case we must scan all functions.
735 int pcibios_scan_all_fns(struct pci_bus *bus, int devfn)
737 struct device_node *busdn, *dn;
740 busdn = pci_device_to_OF_node(bus->self);
742 busdn = bus->sysdata; /* must be a phb */
748 * Check to see if there is any of the 8 functions are in the
749 * device tree. If they are then we need to scan all the
750 * functions of this slot.
752 for (dn = busdn->child; dn; dn = dn->sibling)
753 if ((dn->devfn >> 3) == (devfn >> 3))
760 void __devinit pcibios_fixup_device_resources(struct pci_dev *dev,
763 /* Update device resources. */
764 struct pci_controller *hose = pci_bus_to_host(bus);
767 for (i = 0; i < PCI_NUM_RESOURCES; i++) {
768 if (dev->resource[i].flags & IORESOURCE_IO) {
769 unsigned long offset = (unsigned long)hose->io_base_virt
771 unsigned long start, end, mask;
773 start = dev->resource[i].start += offset;
774 end = dev->resource[i].end += offset;
776 /* Need to allow IO access to pages that are in the
778 if (start < MAX_ISA_PORT) {
779 if (end > MAX_ISA_PORT)
782 start >>= PAGE_SHIFT;
785 /* get the range of pages for the map */
786 mask = ((1 << (end+1))-1) ^ ((1 << start)-1);
787 io_page_mask |= mask;
790 else if (dev->resource[i].flags & IORESOURCE_MEM) {
791 dev->resource[i].start += hose->pci_mem_offset;
792 dev->resource[i].end += hose->pci_mem_offset;
796 EXPORT_SYMBOL(pcibios_fixup_device_resources);
798 void __devinit pcibios_fixup_bus(struct pci_bus *bus)
800 struct pci_controller *hose = pci_bus_to_host(bus);
801 struct pci_dev *dev = bus->self;
802 struct resource *res;
809 bus->resource[0] = res = &hose->io_resource;
811 if (res->flags && request_resource(&ioport_resource, res))
812 printk(KERN_ERR "Failed to request IO on "
813 "PCI domain %d\n", pci_domain_nr(bus));
815 for (i = 0; i < 3; ++i) {
816 res = &hose->mem_resources[i];
817 bus->resource[i+1] = res;
818 if (res->flags && request_resource(&iomem_resource, res))
819 printk(KERN_ERR "Failed to request MEM on "
823 } else if (pci_probe_only &&
824 (dev->class >> 8) == PCI_CLASS_BRIDGE_PCI) {
825 /* This is a subordinate bridge */
827 pci_read_bridge_bases(bus);
828 pcibios_fixup_device_resources(dev, bus);
831 ppc_md.iommu_bus_setup(bus);
833 list_for_each_entry(dev, &bus->devices, bus_list)
834 ppc_md.iommu_dev_setup(dev);
839 list_for_each_entry(dev, &bus->devices, bus_list) {
840 if ((dev->class >> 8) != PCI_CLASS_BRIDGE_PCI)
841 pcibios_fixup_device_resources(dev, bus);
844 EXPORT_SYMBOL(pcibios_fixup_bus);
847 * Reads the interrupt pin to determine if interrupt is use by card.
848 * If the interrupt is used, then gets the interrupt line from the
849 * openfirmware and sets it in the pci_dev and pci_config line.
851 int pci_read_irq_line(struct pci_dev *pci_dev)
854 struct device_node *node;
856 pci_read_config_byte(pci_dev, PCI_INTERRUPT_PIN, &intpin);
860 node = pci_device_to_OF_node(pci_dev);
864 if (node->n_intrs == 0)
867 pci_dev->irq = node->intrs[0].line;
869 pci_write_config_byte(pci_dev, PCI_INTERRUPT_LINE, pci_dev->irq);
873 EXPORT_SYMBOL(pci_read_irq_line);
875 #endif /* CONFIG_PPC_MULTIPLATFORM */