2 * Support for PCI bridges found on Power Macintoshes.
3 * At present the "bandit" and "chaos" bridges are supported.
4 * Fortunately you access configuration space in the same
5 * way with either bridge.
7 * Copyright (C) 2003 Benjamin Herrenschmuidt (benh@kernel.crashing.org)
8 * Copyright (C) 1997 Paul Mackerras (paulus@samba.org)
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License
12 * as published by the Free Software Foundation; either version
13 * 2 of the License, or (at your option) any later version.
16 #include <linux/kernel.h>
17 #include <linux/pci.h>
18 #include <linux/delay.h>
19 #include <linux/string.h>
20 #include <linux/init.h>
21 #include <linux/bootmem.h>
23 #include <asm/sections.h>
26 #include <asm/pci-bridge.h>
27 #include <asm/machdep.h>
28 #include <asm/pmac_feature.h>
29 #include <asm/iommu.h>
37 #define DBG(x...) printk(x)
42 extern int pci_probe_only;
43 extern int pci_read_irq_line(struct pci_dev *pci_dev);
45 /* XXX Could be per-controller, but I don't think we risk anything by
46 * assuming we won't have both UniNorth and Bandit */
47 static int has_uninorth;
48 static struct pci_controller *u3_agp;
49 u8 pci_cache_line_size;
50 struct pci_dev *k2_skiplist[2];
52 static int __init fixup_one_level_bus_range(struct device_node *node, int higher)
54 for (; node != 0;node = node->sibling) {
56 unsigned int *class_code;
59 /* For PCI<->PCI bridges or CardBus bridges, we go down */
60 class_code = (unsigned int *) get_property(node, "class-code", 0);
61 if (!class_code || ((*class_code >> 8) != PCI_CLASS_BRIDGE_PCI &&
62 (*class_code >> 8) != PCI_CLASS_BRIDGE_CARDBUS))
64 bus_range = (int *) get_property(node, "bus-range", &len);
65 if (bus_range != NULL && len > 2 * sizeof(int)) {
66 if (bus_range[1] > higher)
67 higher = bus_range[1];
69 higher = fixup_one_level_bus_range(node->child, higher);
74 /* This routine fixes the "bus-range" property of all bridges in the
75 * system since they tend to have their "last" member wrong on macs
77 * Note that the bus numbers manipulated here are OF bus numbers, they
78 * are not Linux bus numbers.
80 static void __init fixup_bus_range(struct device_node *bridge)
85 /* Lookup the "bus-range" property for the hose */
86 bus_range = (int *) get_property(bridge, "bus-range", &len);
87 if (bus_range == NULL || len < 2 * sizeof(int)) {
88 printk(KERN_WARNING "Can't get bus-range for %s\n",
92 bus_range[1] = fixup_one_level_bus_range(bridge->child, bus_range[1]);
96 * Apple MacRISC (U3, UniNorth, Bandit, Chaos) PCI controllers.
98 * The "Bandit" version is present in all early PCI PowerMacs,
99 * and up to the first ones using Grackle. Some machines may
100 * have 2 bandit controllers (2 PCI busses).
102 * "Chaos" is used in some "Bandit"-type machines as a bridge
103 * for the separate display bus. It is accessed the same
104 * way as bandit, but cannot be probed for devices. It therefore
105 * has its own config access functions.
107 * The "UniNorth" version is present in all Core99 machines
108 * (iBook, G4, new IMacs, and all the recent Apple machines).
109 * It contains 3 controllers in one ASIC.
111 * The U3 is the bridge used on G5 machines. It contains on
112 * AGP bus which is dealt with the old UniNorth access routines
113 * and an HyperTransport bus which uses its own set of access
117 #define MACRISC_CFA0(devfn, off) \
118 ((1 << (unsigned long)PCI_SLOT(dev_fn)) \
119 | (((unsigned long)PCI_FUNC(dev_fn)) << 8) \
120 | (((unsigned long)(off)) & 0xFCUL))
122 #define MACRISC_CFA1(bus, devfn, off) \
123 ((((unsigned long)(bus)) << 16) \
124 |(((unsigned long)(devfn)) << 8) \
125 |(((unsigned long)(off)) & 0xFCUL) \
128 static unsigned long __pmac macrisc_cfg_access(struct pci_controller* hose,
129 u8 bus, u8 dev_fn, u8 offset)
133 if (bus == hose->first_busno) {
134 if (dev_fn < (11 << 3))
136 caddr = MACRISC_CFA0(dev_fn, offset);
138 caddr = MACRISC_CFA1(bus, dev_fn, offset);
140 /* Uninorth will return garbage if we don't read back the value ! */
142 out_le32(hose->cfg_addr, caddr);
143 } while (in_le32(hose->cfg_addr) != caddr);
145 offset &= has_uninorth ? 0x07 : 0x03;
146 return ((unsigned long)hose->cfg_data) + offset;
149 static int __pmac macrisc_read_config(struct pci_bus *bus, unsigned int devfn,
150 int offset, int len, u32 *val)
152 struct pci_controller *hose;
153 struct device_node *busdn;
157 busdn = pci_device_to_OF_node(bus->self);
159 busdn = bus->sysdata; /* must be a phb */
161 return PCIBIOS_DEVICE_NOT_FOUND;
164 return PCIBIOS_DEVICE_NOT_FOUND;
166 addr = macrisc_cfg_access(hose, bus->number, devfn, offset);
168 return PCIBIOS_DEVICE_NOT_FOUND;
170 * Note: the caller has already checked that offset is
171 * suitably aligned and that len is 1, 2 or 4.
175 *val = in_8((u8 *)addr);
178 *val = in_le16((u16 *)addr);
181 *val = in_le32((u32 *)addr);
184 return PCIBIOS_SUCCESSFUL;
187 static int __pmac macrisc_write_config(struct pci_bus *bus, unsigned int devfn,
188 int offset, int len, u32 val)
190 struct pci_controller *hose;
191 struct device_node *busdn;
195 busdn = pci_device_to_OF_node(bus->self);
197 busdn = bus->sysdata; /* must be a phb */
199 return PCIBIOS_DEVICE_NOT_FOUND;
202 return PCIBIOS_DEVICE_NOT_FOUND;
204 addr = macrisc_cfg_access(hose, bus->number, devfn, offset);
206 return PCIBIOS_DEVICE_NOT_FOUND;
208 * Note: the caller has already checked that offset is
209 * suitably aligned and that len is 1, 2 or 4.
213 out_8((u8 *)addr, val);
214 (void) in_8((u8 *)addr);
217 out_le16((u16 *)addr, val);
218 (void) in_le16((u16 *)addr);
221 out_le32((u32 *)addr, val);
222 (void) in_le32((u32 *)addr);
225 return PCIBIOS_SUCCESSFUL;
228 static struct pci_ops macrisc_pci_ops =
235 * These versions of U3 HyperTransport config space access ops do not
236 * implement self-view of the HT host yet
239 static int skip_k2_device(struct pci_bus *bus, unsigned int devfn)
244 if (k2_skiplist[i] && k2_skiplist[i]->bus == bus &&
245 k2_skiplist[i]->devfn == devfn)
250 #define U3_HT_CFA0(devfn, off) \
251 ((((unsigned long)devfn) << 8) | offset)
252 #define U3_HT_CFA1(bus, devfn, off) \
253 (U3_HT_CFA0(devfn, off) \
254 + (((unsigned long)bus) << 16) \
257 static unsigned long __pmac u3_ht_cfg_access(struct pci_controller* hose,
258 u8 bus, u8 devfn, u8 offset)
260 if (bus == hose->first_busno) {
261 /* For now, we don't self probe U3 HT bridge */
262 if (PCI_FUNC(devfn) != 0 || PCI_SLOT(devfn) > 7 ||
265 return ((unsigned long)hose->cfg_data) + U3_HT_CFA0(devfn, offset);
267 return ((unsigned long)hose->cfg_data) + U3_HT_CFA1(bus, devfn, offset);
270 static int __pmac u3_ht_read_config(struct pci_bus *bus, unsigned int devfn,
271 int offset, int len, u32 *val)
273 struct pci_controller *hose;
274 struct device_node *busdn;
278 busdn = pci_device_to_OF_node(bus->self);
280 busdn = bus->sysdata; /* must be a phb */
282 return PCIBIOS_DEVICE_NOT_FOUND;
285 return PCIBIOS_DEVICE_NOT_FOUND;
287 addr = u3_ht_cfg_access(hose, bus->number, devfn, offset);
289 return PCIBIOS_DEVICE_NOT_FOUND;
291 * When a device in K2 is powered down, we die on config
292 * cycle accesses. Fix that here. We may ultimately want
293 * to cache the config space for those instead of returning
294 * 0xffffffff's to make life easier to HW detection tools
296 if (skip_k2_device(bus, devfn)) {
301 *val = 0xffff; break;
303 *val = 0xfffffffful; break;
305 return PCIBIOS_SUCCESSFUL;
309 * Note: the caller has already checked that offset is
310 * suitably aligned and that len is 1, 2 or 4.
314 *val = in_8((u8 *)addr);
317 *val = in_le16((u16 *)addr);
320 *val = in_le32((u32 *)addr);
323 return PCIBIOS_SUCCESSFUL;
326 static int __pmac u3_ht_write_config(struct pci_bus *bus, unsigned int devfn,
327 int offset, int len, u32 val)
329 struct pci_controller *hose;
330 struct device_node *busdn;
334 busdn = pci_device_to_OF_node(bus->self);
336 busdn = bus->sysdata; /* must be a phb */
338 return PCIBIOS_DEVICE_NOT_FOUND;
341 return PCIBIOS_DEVICE_NOT_FOUND;
343 addr = u3_ht_cfg_access(hose, bus->number, devfn, offset);
345 return PCIBIOS_DEVICE_NOT_FOUND;
347 * When a device in K2 is powered down, we die on config
348 * cycle accesses. Fix that here.
350 if (skip_k2_device(bus, devfn))
351 return PCIBIOS_SUCCESSFUL;
354 * Note: the caller has already checked that offset is
355 * suitably aligned and that len is 1, 2 or 4.
359 out_8((u8 *)addr, val);
360 (void) in_8((u8 *)addr);
363 out_le16((u16 *)addr, val);
364 (void) in_le16((u16 *)addr);
367 out_le32((u32 *)addr, val);
368 (void) in_le32((u32 *)addr);
371 return PCIBIOS_SUCCESSFUL;
374 static struct pci_ops u3_ht_pci_ops =
380 static void __init setup_u3_agp(struct pci_controller* hose)
382 /* On G5, we move AGP up to high bus number so we don't need
383 * to reassign bus numbers for HT. If we ever have P2P bridges
384 * on AGP, we'll have to move pci_assign_all_busses to the
385 * pci_controller structure so we enable it for AGP and not for
387 * We hard code the address because of the different size of
388 * the reg address cell, we shall fix that by killing struct
389 * reg_property and using some accessor functions instead
391 hose->first_busno = 0xf0;
392 hose->last_busno = 0xff;
394 hose->ops = ¯isc_pci_ops;
395 hose->cfg_addr = ioremap(0xf0000000 + 0x800000, 0x1000);
396 hose->cfg_data = ioremap(0xf0000000 + 0xc00000, 0x1000);
401 static void __init setup_u3_ht(struct pci_controller* hose)
403 struct device_node *np = (struct device_node *)hose->arch_data;
406 hose->ops = &u3_ht_pci_ops;
408 /* We hard code the address because of the different size of
409 * the reg address cell, we shall fix that by killing struct
410 * reg_property and using some accessor functions instead
412 hose->cfg_data = (volatile unsigned char *)ioremap(0xf2000000, 0x02000000);
415 * /ht node doesn't expose a "ranges" property, so we "remove" regions that
416 * have been allocated to AGP. So far, this version of the code doesn't assign
417 * any of the 0xfxxxxxxx "fine" memory regions to /ht.
418 * We need to fix that sooner or later by either parsing all child "ranges"
419 * properties or figuring out the U3 address space decoding logic and
420 * then read it's configuration register (if any).
422 hose->io_base_phys = 0xf4000000 + 0x00400000;
423 hose->io_base_virt = ioremap(hose->io_base_phys, 0x00400000);
424 isa_io_base = pci_io_base = (unsigned long) hose->io_base_virt;
425 hose->io_resource.name = np->full_name;
426 hose->io_resource.start = 0;
427 hose->io_resource.end = 0x003fffff;
428 hose->io_resource.flags = IORESOURCE_IO;
429 hose->pci_mem_offset = 0;
430 hose->first_busno = 0;
431 hose->last_busno = 0xef;
432 hose->mem_resources[0].name = np->full_name;
433 hose->mem_resources[0].start = 0x80000000;
434 hose->mem_resources[0].end = 0xefffffff;
435 hose->mem_resources[0].flags = IORESOURCE_MEM;
437 if (u3_agp == NULL) {
438 DBG("U3 has no AGP, using full resource range\n");
442 /* We "remove" the AGP resources from the resources allocated to HT, that
443 * is we create "holes". However, that code does assumptions that so far
444 * happen to be true (cross fingers...), typically that resources in the
445 * AGP node are properly ordered
448 for (i=0; i<3; i++) {
449 struct resource *res = &u3_agp->mem_resources[i];
450 if (res->flags != IORESOURCE_MEM)
452 /* We don't care about "fine" resources */
453 if (res->start >= 0xf0000000)
455 /* Check if it's just a matter of "shrinking" us in one direction */
456 if (hose->mem_resources[cur].start == res->start) {
457 DBG("U3/HT: shrink start of %d, %08lx -> %08lx\n",
458 cur, hose->mem_resources[cur].start, res->end + 1);
459 hose->mem_resources[cur].start = res->end + 1;
462 if (hose->mem_resources[cur].end == res->end) {
463 DBG("U3/HT: shrink end of %d, %08lx -> %08lx\n",
464 cur, hose->mem_resources[cur].end, res->start - 1);
465 hose->mem_resources[cur].end = res->start - 1;
468 /* No, it's not the case, we need a hole */
470 /* not enough resources for a hole, we drop part of the range */
471 printk(KERN_WARNING "Running out of resources for /ht host !\n");
472 hose->mem_resources[cur].end = res->start - 1;
476 DBG("U3/HT: hole, %d end at %08lx, %d start at %08lx\n",
477 cur-1, res->start - 1, cur, res->end + 1);
478 hose->mem_resources[cur].name = np->full_name;
479 hose->mem_resources[cur].flags = IORESOURCE_MEM;
480 hose->mem_resources[cur].start = res->end + 1;
481 hose->mem_resources[cur].end = hose->mem_resources[cur-1].end;
482 hose->mem_resources[cur-1].end = res->start - 1;
486 static void __init pmac_process_bridge_OF_ranges(struct pci_controller *hose,
487 struct device_node *dev, int primary)
489 static unsigned int static_lc_ranges[2024];
490 unsigned int *dt_ranges, *lc_ranges, *ranges, *prev;
492 int rlen = 0, orig_rlen;
494 struct resource *res;
495 int np, na = prom_n_addr_cells(dev);
499 /* First we try to merge ranges to fix a problem with some pmacs
500 * that can have more than 3 ranges, fortunately using contiguous
503 dt_ranges = (unsigned int *) get_property(dev, "ranges", &rlen);
506 /* lc_ranges = (unsigned int *) alloc_bootmem(rlen);*/
507 lc_ranges = static_lc_ranges;
509 return; /* what can we do here ? */
510 memcpy(lc_ranges, dt_ranges, rlen);
513 /* Let's work on a copy of the "ranges" property instead of damaging
514 * the device-tree image in memory
518 while ((rlen -= np * sizeof(unsigned int)) >= 0) {
520 if (prev[0] == ranges[0] && prev[1] == ranges[1] &&
521 (prev[2] + prev[na+4]) == ranges[2] &&
522 (prev[na+2] + prev[na+4]) == ranges[na+2]) {
523 prev[na+4] += ranges[na+4];
534 * The ranges property is laid out as an array of elements,
535 * each of which comprises:
536 * cells 0 - 2: a PCI address
537 * cells 3 or 3+4: a CPU physical address
538 * (size depending on dev->n_addr_cells)
539 * cells 4+5 or 5+6: the size of the range
543 while (ranges && (rlen -= np * sizeof(unsigned int)) >= 0) {
546 switch (ranges[0] >> 24) {
547 case 1: /* I/O space */
550 hose->io_base_phys = ranges[na+2];
551 /* limit I/O space to 16MB */
552 if (size > 0x01000000)
554 hose->io_base_virt = ioremap(ranges[na+2], size);
556 isa_io_base = (unsigned long) hose->io_base_virt;
557 res = &hose->io_resource;
558 res->flags = IORESOURCE_IO;
559 res->start = ranges[2];
561 case 2: /* memory space */
563 if (ranges[1] == 0 && ranges[2] == 0
564 && ranges[na+4] <= (16 << 20)) {
565 /* 1st 16MB, i.e. ISA memory area */
568 isa_mem_base = ranges[na+2];
572 while (memno < 3 && hose->mem_resources[memno].flags)
575 hose->pci_mem_offset = ranges[na+2] - ranges[2];
577 res = &hose->mem_resources[memno];
578 res->flags = IORESOURCE_MEM;
579 res->start = ranges[na+2];
584 res->name = dev->full_name;
585 res->end = res->start + size - 1;
595 * We assume that if we have a G3 powermac, we have one bridge called
596 * "pci" (a MPC106) and no bandit or chaos bridges, and contrariwise,
597 * if we have one or more bandit or chaos bridges, we don't have a MPC106.
599 static int __init add_bridge(struct device_node *dev)
602 struct pci_controller *hose;
606 struct property *of_prop;
608 DBG("Adding PCI host bridge %s\n", dev->full_name);
610 bus_range = (int *) get_property(dev, "bus-range", &len);
611 if (bus_range == NULL || len < 2 * sizeof(int)) {
612 printk(KERN_WARNING "Can't get bus-range for %s, assume bus 0\n",
616 hose = pci_alloc_pci_controller(phb_type_apple);
619 hose->arch_data = dev;
620 hose->first_busno = bus_range ? bus_range[0] : 0;
621 hose->last_busno = bus_range ? bus_range[1] : 0xff;
623 of_prop = (struct property *)alloc_bootmem(sizeof(struct property) +
624 sizeof(hose->global_number));
626 memset(of_prop, 0, sizeof(struct property));
627 of_prop->name = "linux,pci-domain";
628 of_prop->length = sizeof(hose->global_number);
629 of_prop->value = (unsigned char *)&of_prop[1];
630 memcpy(of_prop->value, &hose->global_number, sizeof(hose->global_number));
631 prom_add_property(dev, of_prop);
635 if (device_is_compatible(dev, "u3-agp")) {
637 disp_name = "U3-AGP";
639 } else if (device_is_compatible(dev, "u3-ht")) {
644 printk(KERN_INFO "Found %s PCI host bridge. Firmware bus number: %d->%d\n",
645 disp_name, hose->first_busno, hose->last_busno);
647 /* Interpret the "ranges" property */
648 /* This also maps the I/O region and sets isa_io/mem_base */
649 pmac_process_bridge_OF_ranges(hose, dev, primary);
651 /* Fixup "bus-range" OF property */
652 fixup_bus_range(dev);
658 void __init pmac_pcibios_fixup(void)
660 struct pci_dev *dev = NULL;
662 while ((dev = pci_find_device(PCI_ANY_ID, PCI_ANY_ID, dev)) != NULL)
663 pci_read_irq_line(dev);
665 pci_fix_bus_sysdata();
667 #ifdef CONFIG_PMAC_DART
669 #endif /* CONFIG_PMAC_DART */
673 static void __init pmac_fixup_phb_resources(void)
675 struct pci_controller *hose;
677 for (hose = hose_head; hose; hose = hose->next) {
678 unsigned long offset = (unsigned long)hose->io_base_virt - pci_io_base;
679 hose->io_resource.start += offset;
680 hose->io_resource.end += offset;
681 printk(KERN_INFO "PCI Host %d, io start: %lx; io end: %lx\n",
683 hose->io_resource.start, hose->io_resource.end);
687 void __init pmac_pci_init(void)
689 struct device_node *np, *root;
690 struct device_node *ht = NULL;
692 /* Probe root PCI hosts, that is on U3 the AGP host and the
693 * HyperTransport host. That one is actually "kept" around
694 * and actually added last as it's resource management relies
695 * on the AGP resources to have been setup first
697 root = of_find_node_by_path("/");
699 printk(KERN_CRIT "pmac_find_bridges: can't find root of device tree\n");
702 for (np = NULL; (np = of_get_next_child(root, np)) != NULL;) {
703 if (np->name == NULL)
705 if (strcmp(np->name, "pci") == 0) {
706 if (add_bridge(np) == 0)
709 if (strcmp(np->name, "ht") == 0) {
716 /* Now setup the HyperTransport host if we found any
718 if (ht && add_bridge(ht) != 0)
721 /* Fixup the IO resources on our host bridges as the common code
722 * does it only for childs of the host bridges
724 pmac_fixup_phb_resources();
726 /* Setup the linkage between OF nodes and PHBs */
729 /* Fixup the PCI<->OF mapping for U3 AGP due to bus renumbering. We
730 * assume there is no P2P bridge on the AGP bus, which should be a
731 * safe assumptions hopefully.
734 struct device_node *np = u3_agp->arch_data;
736 for (np = np->child; np; np = np->sibling)
740 pmac_check_ht_link();
742 /* Tell pci.c to use the common resource allocation mecanism */
745 /* HT don't do more than 64 bytes transfers. FIXME: Deal with
746 * the exception of U3/AGP (hook into pci_set_mwi)
748 pci_cache_line_size = 16; /* 64 bytes */
752 * Disable second function on K2-SATA, it's broken
753 * and disable IO BARs on first one
755 void fixup_k2_sata(struct pci_dev* dev)
760 if (PCI_FUNC(dev->devfn) > 0) {
761 pci_read_config_word(dev, PCI_COMMAND, &cmd);
762 cmd &= ~(PCI_COMMAND_IO | PCI_COMMAND_MEMORY);
763 pci_write_config_word(dev, PCI_COMMAND, cmd);
764 for (i = 0; i < 6; i++) {
765 dev->resource[i].start = dev->resource[i].end = 0;
766 dev->resource[i].flags = 0;
767 pci_write_config_dword(dev, PCI_BASE_ADDRESS_0 + 4 * i, 0);
770 pci_read_config_word(dev, PCI_COMMAND, &cmd);
771 cmd &= ~PCI_COMMAND_IO;
772 pci_write_config_word(dev, PCI_COMMAND, cmd);
773 for (i = 0; i < 5; i++) {
774 dev->resource[i].start = dev->resource[i].end = 0;
775 dev->resource[i].flags = 0;
776 pci_write_config_dword(dev, PCI_BASE_ADDRESS_0 + 4 * i, 0);