2 * Support for PCI bridges found on Power Macintoshes.
3 * At present the "bandit" and "chaos" bridges are supported.
4 * Fortunately you access configuration space in the same
5 * way with either bridge.
7 * Copyright (C) 2003 Benjamin Herrenschmuidt (benh@kernel.crashing.org)
8 * Copyright (C) 1997 Paul Mackerras (paulus@samba.org)
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License
12 * as published by the Free Software Foundation; either version
13 * 2 of the License, or (at your option) any later version.
16 #include <linux/kernel.h>
17 #include <linux/pci.h>
18 #include <linux/delay.h>
19 #include <linux/string.h>
20 #include <linux/init.h>
21 #include <linux/bootmem.h>
23 #include <asm/sections.h>
26 #include <asm/pci-bridge.h>
27 #include <asm/machdep.h>
28 #include <asm/pmac_feature.h>
29 #include <asm/iommu.h>
37 #define DBG(x...) printk(x)
42 /* XXX Could be per-controller, but I don't think we risk anything by
43 * assuming we won't have both UniNorth and Bandit */
44 static int has_uninorth;
45 static struct pci_controller *u3_agp;
46 struct pci_dev *k2_skiplist[2];
48 static int __init fixup_one_level_bus_range(struct device_node *node, int higher)
50 for (; node != 0;node = node->sibling) {
52 unsigned int *class_code;
55 /* For PCI<->PCI bridges or CardBus bridges, we go down */
56 class_code = (unsigned int *) get_property(node, "class-code", NULL);
57 if (!class_code || ((*class_code >> 8) != PCI_CLASS_BRIDGE_PCI &&
58 (*class_code >> 8) != PCI_CLASS_BRIDGE_CARDBUS))
60 bus_range = (int *) get_property(node, "bus-range", &len);
61 if (bus_range != NULL && len > 2 * sizeof(int)) {
62 if (bus_range[1] > higher)
63 higher = bus_range[1];
65 higher = fixup_one_level_bus_range(node->child, higher);
70 /* This routine fixes the "bus-range" property of all bridges in the
71 * system since they tend to have their "last" member wrong on macs
73 * Note that the bus numbers manipulated here are OF bus numbers, they
74 * are not Linux bus numbers.
76 static void __init fixup_bus_range(struct device_node *bridge)
81 /* Lookup the "bus-range" property for the hose */
82 bus_range = (int *) get_property(bridge, "bus-range", &len);
83 if (bus_range == NULL || len < 2 * sizeof(int)) {
84 printk(KERN_WARNING "Can't get bus-range for %s\n",
88 bus_range[1] = fixup_one_level_bus_range(bridge->child, bus_range[1]);
92 * Apple MacRISC (U3, UniNorth, Bandit, Chaos) PCI controllers.
94 * The "Bandit" version is present in all early PCI PowerMacs,
95 * and up to the first ones using Grackle. Some machines may
96 * have 2 bandit controllers (2 PCI busses).
98 * "Chaos" is used in some "Bandit"-type machines as a bridge
99 * for the separate display bus. It is accessed the same
100 * way as bandit, but cannot be probed for devices. It therefore
101 * has its own config access functions.
103 * The "UniNorth" version is present in all Core99 machines
104 * (iBook, G4, new IMacs, and all the recent Apple machines).
105 * It contains 3 controllers in one ASIC.
107 * The U3 is the bridge used on G5 machines. It contains on
108 * AGP bus which is dealt with the old UniNorth access routines
109 * and an HyperTransport bus which uses its own set of access
113 #define MACRISC_CFA0(devfn, off) \
114 ((1 << (unsigned long)PCI_SLOT(dev_fn)) \
115 | (((unsigned long)PCI_FUNC(dev_fn)) << 8) \
116 | (((unsigned long)(off)) & 0xFCUL))
118 #define MACRISC_CFA1(bus, devfn, off) \
119 ((((unsigned long)(bus)) << 16) \
120 |(((unsigned long)(devfn)) << 8) \
121 |(((unsigned long)(off)) & 0xFCUL) \
124 static unsigned long __pmac macrisc_cfg_access(struct pci_controller* hose,
125 u8 bus, u8 dev_fn, u8 offset)
129 if (bus == hose->first_busno) {
130 if (dev_fn < (11 << 3))
132 caddr = MACRISC_CFA0(dev_fn, offset);
134 caddr = MACRISC_CFA1(bus, dev_fn, offset);
136 /* Uninorth will return garbage if we don't read back the value ! */
138 out_le32(hose->cfg_addr, caddr);
139 } while (in_le32(hose->cfg_addr) != caddr);
141 offset &= has_uninorth ? 0x07 : 0x03;
142 return ((unsigned long)hose->cfg_data) + offset;
145 static int __pmac macrisc_read_config(struct pci_bus *bus, unsigned int devfn,
146 int offset, int len, u32 *val)
148 struct pci_controller *hose;
151 hose = pci_bus_to_host(bus);
153 return PCIBIOS_DEVICE_NOT_FOUND;
155 addr = macrisc_cfg_access(hose, bus->number, devfn, offset);
157 return PCIBIOS_DEVICE_NOT_FOUND;
159 * Note: the caller has already checked that offset is
160 * suitably aligned and that len is 1, 2 or 4.
164 *val = in_8((u8 *)addr);
167 *val = in_le16((u16 *)addr);
170 *val = in_le32((u32 *)addr);
173 return PCIBIOS_SUCCESSFUL;
176 static int __pmac macrisc_write_config(struct pci_bus *bus, unsigned int devfn,
177 int offset, int len, u32 val)
179 struct pci_controller *hose;
182 hose = pci_bus_to_host(bus);
184 return PCIBIOS_DEVICE_NOT_FOUND;
186 addr = macrisc_cfg_access(hose, bus->number, devfn, offset);
188 return PCIBIOS_DEVICE_NOT_FOUND;
190 * Note: the caller has already checked that offset is
191 * suitably aligned and that len is 1, 2 or 4.
195 out_8((u8 *)addr, val);
196 (void) in_8((u8 *)addr);
199 out_le16((u16 *)addr, val);
200 (void) in_le16((u16 *)addr);
203 out_le32((u32 *)addr, val);
204 (void) in_le32((u32 *)addr);
207 return PCIBIOS_SUCCESSFUL;
210 static struct pci_ops macrisc_pci_ops =
217 * These versions of U3 HyperTransport config space access ops do not
218 * implement self-view of the HT host yet
222 * This function deals with some "special cases" devices.
224 * 0 -> No special case
225 * 1 -> Skip the device but act as if the access was successfull
226 * (return 0xff's on reads, eventually, cache config space
227 * accesses in a later version)
228 * -1 -> Hide the device (unsuccessful acess)
230 static int u3_ht_skip_device(struct pci_controller *hose,
231 struct pci_bus *bus, unsigned int devfn)
233 struct device_node *busdn, *dn;
237 * When a device in K2 is powered down, we die on config
238 * cycle accesses. Fix that here.
241 if (k2_skiplist[i] && k2_skiplist[i]->bus == bus &&
242 k2_skiplist[i]->devfn == devfn)
245 /* We only allow config cycles to devices that are in OF device-tree
246 * as we are apparently having some weird things going on with some
247 * revs of K2 on recent G5s
250 busdn = pci_device_to_OF_node(bus->self);
252 busdn = hose->arch_data;
253 for (dn = busdn->child; dn; dn = dn->sibling)
254 if (dn->devfn == devfn)
262 #define U3_HT_CFA0(devfn, off) \
263 ((((unsigned long)devfn) << 8) | offset)
264 #define U3_HT_CFA1(bus, devfn, off) \
265 (U3_HT_CFA0(devfn, off) \
266 + (((unsigned long)bus) << 16) \
269 static unsigned long __pmac u3_ht_cfg_access(struct pci_controller* hose,
270 u8 bus, u8 devfn, u8 offset)
272 if (bus == hose->first_busno) {
273 /* For now, we don't self probe U3 HT bridge */
274 if (PCI_SLOT(devfn) == 0)
276 return ((unsigned long)hose->cfg_data) + U3_HT_CFA0(devfn, offset);
278 return ((unsigned long)hose->cfg_data) + U3_HT_CFA1(bus, devfn, offset);
281 static int __pmac u3_ht_read_config(struct pci_bus *bus, unsigned int devfn,
282 int offset, int len, u32 *val)
284 struct pci_controller *hose;
288 hose = pci_bus_to_host(bus);
290 return PCIBIOS_DEVICE_NOT_FOUND;
292 addr = u3_ht_cfg_access(hose, bus->number, devfn, offset);
294 return PCIBIOS_DEVICE_NOT_FOUND;
296 switch (u3_ht_skip_device(hose, bus, devfn)) {
304 *val = 0xffff; break;
306 *val = 0xfffffffful; break;
308 return PCIBIOS_SUCCESSFUL;
310 return PCIBIOS_DEVICE_NOT_FOUND;
314 * Note: the caller has already checked that offset is
315 * suitably aligned and that len is 1, 2 or 4.
319 *val = in_8((u8 *)addr);
322 *val = in_le16((u16 *)addr);
325 *val = in_le32((u32 *)addr);
328 return PCIBIOS_SUCCESSFUL;
331 static int __pmac u3_ht_write_config(struct pci_bus *bus, unsigned int devfn,
332 int offset, int len, u32 val)
334 struct pci_controller *hose;
337 hose = pci_bus_to_host(bus);
339 return PCIBIOS_DEVICE_NOT_FOUND;
341 addr = u3_ht_cfg_access(hose, bus->number, devfn, offset);
343 return PCIBIOS_DEVICE_NOT_FOUND;
345 switch (u3_ht_skip_device(hose, bus, devfn)) {
349 return PCIBIOS_SUCCESSFUL;
351 return PCIBIOS_DEVICE_NOT_FOUND;
355 * Note: the caller has already checked that offset is
356 * suitably aligned and that len is 1, 2 or 4.
360 out_8((u8 *)addr, val);
361 (void) in_8((u8 *)addr);
364 out_le16((u16 *)addr, val);
365 (void) in_le16((u16 *)addr);
368 out_le32((u32 *)addr, val);
369 (void) in_le32((u32 *)addr);
372 return PCIBIOS_SUCCESSFUL;
375 static struct pci_ops u3_ht_pci_ops =
381 static void __init setup_u3_agp(struct pci_controller* hose)
383 /* On G5, we move AGP up to high bus number so we don't need
384 * to reassign bus numbers for HT. If we ever have P2P bridges
385 * on AGP, we'll have to move pci_assign_all_busses to the
386 * pci_controller structure so we enable it for AGP and not for
388 * We hard code the address because of the different size of
389 * the reg address cell, we shall fix that by killing struct
390 * reg_property and using some accessor functions instead
392 hose->first_busno = 0xf0;
393 hose->last_busno = 0xff;
395 hose->ops = ¯isc_pci_ops;
396 hose->cfg_addr = ioremap(0xf0000000 + 0x800000, 0x1000);
397 hose->cfg_data = ioremap(0xf0000000 + 0xc00000, 0x1000);
402 static void __init setup_u3_ht(struct pci_controller* hose)
404 struct device_node *np = (struct device_node *)hose->arch_data;
407 hose->ops = &u3_ht_pci_ops;
409 /* We hard code the address because of the different size of
410 * the reg address cell, we shall fix that by killing struct
411 * reg_property and using some accessor functions instead
413 hose->cfg_data = (volatile unsigned char *)ioremap(0xf2000000, 0x02000000);
416 * /ht node doesn't expose a "ranges" property, so we "remove" regions that
417 * have been allocated to AGP. So far, this version of the code doesn't assign
418 * any of the 0xfxxxxxxx "fine" memory regions to /ht.
419 * We need to fix that sooner or later by either parsing all child "ranges"
420 * properties or figuring out the U3 address space decoding logic and
421 * then read it's configuration register (if any).
423 hose->io_base_phys = 0xf4000000;
424 hose->io_base_virt = ioremap(hose->io_base_phys, 0x00400000);
425 isa_io_base = pci_io_base = (unsigned long) hose->io_base_virt;
426 hose->io_resource.name = np->full_name;
427 hose->io_resource.start = 0;
428 hose->io_resource.end = 0x003fffff;
429 hose->io_resource.flags = IORESOURCE_IO;
430 hose->pci_mem_offset = 0;
431 hose->first_busno = 0;
432 hose->last_busno = 0xef;
433 hose->mem_resources[0].name = np->full_name;
434 hose->mem_resources[0].start = 0x80000000;
435 hose->mem_resources[0].end = 0xefffffff;
436 hose->mem_resources[0].flags = IORESOURCE_MEM;
438 if (u3_agp == NULL) {
439 DBG("U3 has no AGP, using full resource range\n");
443 /* We "remove" the AGP resources from the resources allocated to HT, that
444 * is we create "holes". However, that code does assumptions that so far
445 * happen to be true (cross fingers...), typically that resources in the
446 * AGP node are properly ordered
449 for (i=0; i<3; i++) {
450 struct resource *res = &u3_agp->mem_resources[i];
451 if (res->flags != IORESOURCE_MEM)
453 /* We don't care about "fine" resources */
454 if (res->start >= 0xf0000000)
456 /* Check if it's just a matter of "shrinking" us in one direction */
457 if (hose->mem_resources[cur].start == res->start) {
458 DBG("U3/HT: shrink start of %d, %08lx -> %08lx\n",
459 cur, hose->mem_resources[cur].start, res->end + 1);
460 hose->mem_resources[cur].start = res->end + 1;
463 if (hose->mem_resources[cur].end == res->end) {
464 DBG("U3/HT: shrink end of %d, %08lx -> %08lx\n",
465 cur, hose->mem_resources[cur].end, res->start - 1);
466 hose->mem_resources[cur].end = res->start - 1;
469 /* No, it's not the case, we need a hole */
471 /* not enough resources for a hole, we drop part of the range */
472 printk(KERN_WARNING "Running out of resources for /ht host !\n");
473 hose->mem_resources[cur].end = res->start - 1;
477 DBG("U3/HT: hole, %d end at %08lx, %d start at %08lx\n",
478 cur-1, res->start - 1, cur, res->end + 1);
479 hose->mem_resources[cur].name = np->full_name;
480 hose->mem_resources[cur].flags = IORESOURCE_MEM;
481 hose->mem_resources[cur].start = res->end + 1;
482 hose->mem_resources[cur].end = hose->mem_resources[cur-1].end;
483 hose->mem_resources[cur-1].end = res->start - 1;
487 static void __init pmac_process_bridge_OF_ranges(struct pci_controller *hose,
488 struct device_node *dev, int primary)
490 static unsigned int static_lc_ranges[2024];
491 unsigned int *dt_ranges, *lc_ranges, *ranges, *prev;
493 int rlen = 0, orig_rlen;
495 struct resource *res;
496 int np, na = prom_n_addr_cells(dev);
500 /* First we try to merge ranges to fix a problem with some pmacs
501 * that can have more than 3 ranges, fortunately using contiguous
504 dt_ranges = (unsigned int *) get_property(dev, "ranges", &rlen);
507 /* lc_ranges = alloc_bootmem(rlen);*/
508 lc_ranges = static_lc_ranges;
510 return; /* what can we do here ? */
511 memcpy(lc_ranges, dt_ranges, rlen);
514 /* Let's work on a copy of the "ranges" property instead of damaging
515 * the device-tree image in memory
519 while ((rlen -= np * sizeof(unsigned int)) >= 0) {
521 if (prev[0] == ranges[0] && prev[1] == ranges[1] &&
522 (prev[2] + prev[na+4]) == ranges[2] &&
523 (prev[na+2] + prev[na+4]) == ranges[na+2]) {
524 prev[na+4] += ranges[na+4];
535 * The ranges property is laid out as an array of elements,
536 * each of which comprises:
537 * cells 0 - 2: a PCI address
538 * cells 3 or 3+4: a CPU physical address
539 * (size depending on dev->n_addr_cells)
540 * cells 4+5 or 5+6: the size of the range
544 while (ranges && (rlen -= np * sizeof(unsigned int)) >= 0) {
547 switch (ranges[0] >> 24) {
548 case 1: /* I/O space */
551 hose->io_base_phys = ranges[na+2];
552 /* limit I/O space to 16MB */
553 if (size > 0x01000000)
555 hose->io_base_virt = ioremap(ranges[na+2], size);
557 isa_io_base = (unsigned long) hose->io_base_virt;
558 res = &hose->io_resource;
559 res->flags = IORESOURCE_IO;
560 res->start = ranges[2];
562 case 2: /* memory space */
564 if (ranges[1] == 0 && ranges[2] == 0
565 && ranges[na+4] <= (16 << 20)) {
566 /* 1st 16MB, i.e. ISA memory area */
569 isa_mem_base = ranges[na+2];
573 while (memno < 3 && hose->mem_resources[memno].flags)
576 hose->pci_mem_offset = ranges[na+2] - ranges[2];
578 res = &hose->mem_resources[memno];
579 res->flags = IORESOURCE_MEM;
580 res->start = ranges[na+2];
585 res->name = dev->full_name;
586 res->end = res->start + size - 1;
596 * We assume that if we have a G3 powermac, we have one bridge called
597 * "pci" (a MPC106) and no bandit or chaos bridges, and contrariwise,
598 * if we have one or more bandit or chaos bridges, we don't have a MPC106.
600 static int __init add_bridge(struct device_node *dev)
603 struct pci_controller *hose;
607 struct property *of_prop;
609 DBG("Adding PCI host bridge %s\n", dev->full_name);
611 bus_range = (int *) get_property(dev, "bus-range", &len);
612 if (bus_range == NULL || len < 2 * sizeof(int)) {
613 printk(KERN_WARNING "Can't get bus-range for %s, assume bus 0\n",
617 hose = alloc_bootmem(sizeof(struct pci_controller));
620 pci_setup_pci_controller(hose);
622 hose->arch_data = dev;
623 hose->first_busno = bus_range ? bus_range[0] : 0;
624 hose->last_busno = bus_range ? bus_range[1] : 0xff;
626 of_prop = alloc_bootmem(sizeof(struct property) +
627 sizeof(hose->global_number));
629 memset(of_prop, 0, sizeof(struct property));
630 of_prop->name = "linux,pci-domain";
631 of_prop->length = sizeof(hose->global_number);
632 of_prop->value = (unsigned char *)&of_prop[1];
633 memcpy(of_prop->value, &hose->global_number, sizeof(hose->global_number));
634 prom_add_property(dev, of_prop);
638 if (device_is_compatible(dev, "u3-agp")) {
640 disp_name = "U3-AGP";
642 } else if (device_is_compatible(dev, "u3-ht")) {
647 printk(KERN_INFO "Found %s PCI host bridge. Firmware bus number: %d->%d\n",
648 disp_name, hose->first_busno, hose->last_busno);
650 /* Interpret the "ranges" property */
651 /* This also maps the I/O region and sets isa_io/mem_base */
652 pmac_process_bridge_OF_ranges(hose, dev, primary);
654 /* Fixup "bus-range" OF property */
655 fixup_bus_range(dev);
661 void __init pmac_pcibios_fixup(void)
663 struct pci_dev *dev = NULL;
665 for_each_pci_dev(dev)
666 pci_read_irq_line(dev);
668 pci_fix_bus_sysdata();
673 static void __init pmac_fixup_phb_resources(void)
675 struct pci_controller *hose, *tmp;
677 list_for_each_entry_safe(hose, tmp, &hose_list, list_node) {
678 unsigned long offset = (unsigned long)hose->io_base_virt - pci_io_base;
679 hose->io_resource.start += offset;
680 hose->io_resource.end += offset;
681 printk(KERN_INFO "PCI Host %d, io start: %lx; io end: %lx\n",
683 hose->io_resource.start, hose->io_resource.end);
687 void __init pmac_pci_init(void)
689 struct device_node *np, *root;
690 struct device_node *ht = NULL;
692 /* Probe root PCI hosts, that is on U3 the AGP host and the
693 * HyperTransport host. That one is actually "kept" around
694 * and actually added last as it's resource management relies
695 * on the AGP resources to have been setup first
697 root = of_find_node_by_path("/");
699 printk(KERN_CRIT "pmac_find_bridges: can't find root of device tree\n");
702 for (np = NULL; (np = of_get_next_child(root, np)) != NULL;) {
703 if (np->name == NULL)
705 if (strcmp(np->name, "pci") == 0) {
706 if (add_bridge(np) == 0)
709 if (strcmp(np->name, "ht") == 0) {
716 /* Now setup the HyperTransport host if we found any
718 if (ht && add_bridge(ht) != 0)
721 /* Fixup the IO resources on our host bridges as the common code
722 * does it only for childs of the host bridges
724 pmac_fixup_phb_resources();
726 /* Setup the linkage between OF nodes and PHBs */
729 /* Fixup the PCI<->OF mapping for U3 AGP due to bus renumbering. We
730 * assume there is no P2P bridge on the AGP bus, which should be a
731 * safe assumptions hopefully.
734 struct device_node *np = u3_agp->arch_data;
736 for (np = np->child; np; np = np->sibling)
740 pmac_check_ht_link();
742 /* Tell pci.c to not use the common resource allocation mecanism */
750 * Disable second function on K2-SATA, it's broken
751 * and disable IO BARs on first one
753 static void fixup_k2_sata(struct pci_dev* dev)
758 if (PCI_FUNC(dev->devfn) > 0) {
759 pci_read_config_word(dev, PCI_COMMAND, &cmd);
760 cmd &= ~(PCI_COMMAND_IO | PCI_COMMAND_MEMORY);
761 pci_write_config_word(dev, PCI_COMMAND, cmd);
762 for (i = 0; i < 6; i++) {
763 dev->resource[i].start = dev->resource[i].end = 0;
764 dev->resource[i].flags = 0;
765 pci_write_config_dword(dev, PCI_BASE_ADDRESS_0 + 4 * i, 0);
768 pci_read_config_word(dev, PCI_COMMAND, &cmd);
769 cmd &= ~PCI_COMMAND_IO;
770 pci_write_config_word(dev, PCI_COMMAND, cmd);
771 for (i = 0; i < 5; i++) {
772 dev->resource[i].start = dev->resource[i].end = 0;
773 dev->resource[i].flags = 0;
774 pci_write_config_dword(dev, PCI_BASE_ADDRESS_0 + 4 * i, 0);
778 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SERVERWORKS, 0x0240, fixup_k2_sata);