2 * PowerPC64 SLB support.
4 * Copyright (C) 2004 David Gibson <dwg@au.ibm.com>, IBM
5 * Based on earlier code writteh by:
6 * Dave Engebretsen and Mike Corrigan {engebret|mikejc}@us.ibm.com
7 * Copyright (c) 2001 Dave Engebretsen
8 * Copyright (C) 2002 Anton Blanchard <anton@au.ibm.com>, IBM
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License
13 * as published by the Free Software Foundation; either version
14 * 2 of the License, or (at your option) any later version.
17 #include <linux/config.h>
18 #include <asm/pgtable.h>
20 #include <asm/mmu_context.h>
23 #include <asm/cputable.h>
25 extern void slb_allocate(unsigned long ea);
27 static inline void create_slbe(unsigned long ea, unsigned long vsid,
28 unsigned long flags, unsigned long entry)
30 ea = (ea & ESID_MASK) | SLB_ESID_V | entry;
31 vsid = (vsid << SLB_VSID_SHIFT) | flags;
32 asm volatile("slbmte %0,%1" :
33 : "r" (vsid), "r" (ea)
37 static void slb_add_bolted(void)
39 #ifndef CONFIG_PPC_ISERIES
40 WARN_ON(!irqs_disabled());
42 /* If you change this make sure you change SLB_NUM_BOLTED
43 * appropriately too */
45 /* Slot 1 - first VMALLOC segment
46 * Since modules end up there it gets hit very heavily.
48 create_slbe(VMALLOCBASE, get_kernel_vsid(VMALLOCBASE),
51 asm volatile("isync":::"memory");
55 /* Flush all user entries from the segment table of the current processor. */
56 void switch_slb(struct task_struct *tsk, struct mm_struct *mm)
58 unsigned long offset = get_paca()->slb_cache_ptr;
59 unsigned long esid_data;
60 unsigned long pc = KSTK_EIP(tsk);
61 unsigned long stack = KSTK_ESP(tsk);
62 unsigned long unmapped_base;
64 if (offset <= SLB_CACHE_ENTRIES) {
66 asm volatile("isync" : : : "memory");
67 for (i = 0; i < offset; i++) {
68 esid_data = (unsigned long)get_paca()->slb_cache[i]
70 asm volatile("slbie %0" : : "r" (esid_data));
72 asm volatile("isync" : : : "memory");
74 asm volatile("isync; slbia; isync" : : : "memory");
78 /* Workaround POWER5 < DD2.1 issue */
79 if (offset == 1 || offset > SLB_CACHE_ENTRIES) {
80 /* flush segment in EEH region, we shouldn't ever
81 * access addresses in this region. */
82 asm volatile("slbie %0" : : "r"(EEHREGIONBASE));
85 get_paca()->slb_cache_ptr = 0;
86 get_paca()->context = mm->context;
89 * preload some userspace segments into the SLB.
91 if (test_tsk_thread_flag(tsk, TIF_32BIT))
92 unmapped_base = TASK_UNMAPPED_BASE_USER32;
94 unmapped_base = TASK_UNMAPPED_BASE_USER64;
100 if (GET_ESID(pc) == GET_ESID(stack))
103 if (stack >= KERNELBASE)
107 if ((GET_ESID(pc) == GET_ESID(unmapped_base))
108 || (GET_ESID(stack) == GET_ESID(unmapped_base)))
111 if (unmapped_base >= KERNELBASE)
113 slb_allocate(unmapped_base);
116 void slb_initialize(void)
118 #ifdef CONFIG_PPC_ISERIES
119 asm volatile("isync; slbia; isync":::"memory");
121 unsigned long flags = SLB_VSID_KERNEL;
123 /* Invalidate the entire SLB (even slot 0) & all the ERATS */
124 if (cur_cpu_spec->cpu_features & CPU_FTR_16M_PAGE)
127 asm volatile("isync":::"memory");
128 asm volatile("slbmte %0,%0"::"r" (0) : "memory");
129 asm volatile("isync; slbia; isync":::"memory");
130 create_slbe(KERNELBASE, get_kernel_vsid(KERNELBASE),
135 get_paca()->stab_rr = SLB_NUM_BOLTED;