2 * Low-Level PCI Support for the SH7751
4 * Dustin McIntire (dustin@sensoria.com)
5 * Derived from arch/i386/kernel/pci-*.c which bore the message:
6 * (c) 1999--2000 Martin Mares <mj@ucw.cz>
8 * Ported to the new API by Paul Mundt <lethal@linux-sh.org>
9 * With cleanup by Paul van Gool <pvangool@mimotech.com>
11 * May be copied or modified under the terms of the GNU General Public
12 * License. See linux/COPYING for more information.
18 #include <linux/config.h>
19 #include <linux/types.h>
20 #include <linux/kernel.h>
21 #include <linux/init.h>
22 #include <linux/pci.h>
23 #include <linux/sched.h>
24 #include <linux/ioport.h>
25 #include <linux/errno.h>
26 #include <linux/irq.h>
27 #include <linux/delay.h>
29 #include <asm/machvec.h>
31 #include "pci-sh7751.h"
33 static unsigned int pci_probe = PCI_PROBE_CONF1;
34 extern int pci_fixup_pcic(void);
37 * Direct access to PCI hardware...
40 #define CONFIG_CMD(bus, devfn, where) (0x80000000 | (bus->number << 16) | (devfn << 8) | (where & ~3))
43 * Functions for accessing PCI configuration space with type 1 accesses
45 static int sh7751_pci_read(struct pci_bus *bus, unsigned int devfn,
46 int where, int size, u32 *val)
52 * PCIPDR may only be accessed as 32 bit words,
53 * so we must do byte alignment by hand
55 local_irq_save(flags);
56 outl(CONFIG_CMD(bus,devfn,where), PCI_REG(SH7751_PCIPAR));
57 data = inl(PCI_REG(SH7751_PCIPDR));
58 local_irq_restore(flags);
62 *val = (data >> ((where & 3) << 3)) & 0xff;
65 *val = (data >> ((where & 2) << 3)) & 0xffff;
71 return PCIBIOS_FUNC_NOT_SUPPORTED;
74 return PCIBIOS_SUCCESSFUL;
78 * Since SH7751 only does 32bit access we'll have to do a read,
79 * mask,write operation.
80 * We'll allow an odd byte offset, though it should be illegal.
82 static int sh7751_pci_write(struct pci_bus *bus, unsigned int devfn,
83 int where, int size, u32 val)
89 local_irq_save(flags);
90 outl(CONFIG_CMD(bus,devfn,where), PCI_REG(SH7751_PCIPAR));
91 data = inl(PCI_REG(SH7751_PCIPDR));
92 local_irq_restore(flags);
96 shift = (where & 3) << 3;
97 data &= ~(0xff << shift);
98 data |= ((val & 0xff) << shift);
101 shift = (where & 2) << 3;
102 data &= ~(0xffff << shift);
103 data |= ((val & 0xffff) << shift);
109 return PCIBIOS_FUNC_NOT_SUPPORTED;
112 outl(data, PCI_REG(SH7751_PCIPDR));
114 return PCIBIOS_SUCCESSFUL;
119 struct pci_ops sh7751_pci_ops = {
120 .read = sh7751_pci_read,
121 .write = sh7751_pci_write,
124 static int __init pci_check_direct(void)
126 unsigned int tmp, id;
128 /* check for SH7751/SH7751R hardware */
129 id = inl(SH7751_PCIREG_BASE+SH7751_PCICONF0);
130 if (id != ((SH7751_DEVICE_ID << 16) | SH7751_VENDOR_ID) &&
131 id != ((SH7751R_DEVICE_ID << 16) | SH7751_VENDOR_ID)) {
132 pr_debug("PCI: This is not an SH7751(R) (%x)\n", id);
137 * Check if configuration works.
139 if (pci_probe & PCI_PROBE_CONF1) {
140 tmp = inl (PCI_REG(SH7751_PCIPAR));
141 outl (0x80000000, PCI_REG(SH7751_PCIPAR));
142 if (inl (PCI_REG(SH7751_PCIPAR)) == 0x80000000) {
143 outl (tmp, PCI_REG(SH7751_PCIPAR));
144 printk(KERN_INFO "PCI: Using configuration type 1\n");
145 request_region(PCI_REG(SH7751_PCIPAR), 8, "PCI conf1");
148 outl (tmp, PCI_REG(SH7751_PCIPAR));
151 pr_debug("PCI: pci_check_direct failed\n");
155 /***************************************************************************************/
158 * Handle bus scanning and fixups ....
161 #if !defined(CONFIG_SH_HS7751RVOIP) && !defined(CONFIG_SH_RTS7751R2D)
162 static void __init pci_fixup_ide_bases(struct pci_dev *d)
167 * PCI IDE controllers use non-standard I/O port decoding, respect it.
169 if ((d->class >> 8) != PCI_CLASS_STORAGE_IDE)
171 pr_debug("PCI: IDE base address fixup for %s\n", d->slot_name);
173 struct resource *r = &d->resource[i];
174 if ((r->start & ~0x80) == 0x374) {
182 /* Add future fixups here... */
183 struct pci_fixup pcibios_fixups[] = {
184 #if !defined(CONFIG_SH_HS7751RVOIP) && !defined(CONFIG_SH_RTS7751R2D)
185 { PCI_FIXUP_HEADER, PCI_ANY_ID, PCI_ANY_ID, pci_fixup_ide_bases },
191 * Called after each bus is probed, but before its children
195 void __init pcibios_fixup_bus(struct pci_bus *b)
197 pci_read_bridge_bases(b);
201 * Initialization. Try all known PCI access methods. Note that we support
202 * using both PCI BIOS and direct access: in such cases, we use I/O ports
203 * to access config space.
205 * Note that the platform specific initialization (BSC registers, and memory
206 * space mapping) will be called via the machine vectors (sh_mv.mv_pci_init()) if it
207 * exitst and via the platform defined function pcibios_init_platform().
208 * See pci_bigsur.c for implementation;
210 * The BIOS version of the pci functions is not yet implemented but it is left
211 * in for completeness. Currently an error will be genereated at compile time.
214 static int __init sh7751_pci_init(void)
218 pr_debug("PCI: Starting intialization.\n");
219 if ((ret = pci_check_direct()) != 0)
222 return pcibios_init_platform();
225 subsys_initcall(sh7751_pci_init);
227 static int __init __area_sdram_check(unsigned int area)
231 word = inl(SH7751_BCR1);
232 /* check BCR for SDRAM in area */
233 if(((word >> area) & 1) == 0) {
234 printk("PCI: Area %d is not configured for SDRAM. BCR1=0x%x\n",
238 outl(word, PCI_REG(SH7751_PCIBCR1));
240 word = (u16)inw(SH7751_BCR2);
241 /* check BCR2 for 32bit SDRAM interface*/
242 if(((word >> (area << 1)) & 0x3) != 0x3) {
243 printk("PCI: Area %d is not 32 bit SDRAM. BCR2=0x%x\n",
247 outl(word, PCI_REG(SH7751_PCIBCR2));
252 int __init sh7751_pcic_init(struct sh7751_pci_address_map *map)
257 /* Set the BCR's to enable PCI access */
258 reg = inl(SH7751_BCR1);
260 outl(reg, SH7751_BCR1);
262 /* Turn the clocks back on (not done in reset)*/
263 outl(0, PCI_REG(SH7751_PCICLKR));
264 /* Clear Powerdown IRQ's (not done in reset) */
265 word = SH7751_PCIPINT_D3 | SH7751_PCIPINT_D0;
266 outl(word, PCI_REG(SH7751_PCICLKR));
269 * This code is unused for some boards as it is done in the
270 * bootloader and doing it here means the MAC addresses loaded
271 * by the bootloader get lost.
273 if (!(map->flags & SH7751_PCIC_NO_RESET)) {
274 /* toggle PCI reset pin */
275 word = SH7751_PCICR_PREFIX | SH7751_PCICR_PRST;
276 outl(word,PCI_REG(SH7751_PCICR));
277 /* Wait for a long time... not 1 sec. but long enough */
279 word = SH7751_PCICR_PREFIX;
280 outl(word,PCI_REG(SH7751_PCICR));
283 /* set the command/status bits to:
284 * Wait Cycle Control + Parity Enable + Bus Master +
287 word = SH7751_PCICONF1_WCC | SH7751_PCICONF1_PER |
288 SH7751_PCICONF1_BUM | SH7751_PCICONF1_MES;
289 outl(word, PCI_REG(SH7751_PCICONF1));
291 /* define this host as the host bridge */
292 word = SH7751_PCI_HOST_BRIDGE << 24;
293 outl(word, PCI_REG(SH7751_PCICONF2));
295 /* Set IO and Mem windows to local address
296 * Make PCI and local address the same for easy 1 to 1 mapping
297 * Window0 = map->window0.size @ non-cached area base = SDRAM
298 * Window1 = map->window1.size @ cached area base = SDRAM
300 word = map->window0.size - 1;
301 outl(word, PCI_REG(SH7751_PCILSR0));
302 word = map->window1.size - 1;
303 outl(word, PCI_REG(SH7751_PCILSR1));
304 /* Set the values on window 0 PCI config registers */
305 word = P2SEGADDR(map->window0.base);
306 outl(word, PCI_REG(SH7751_PCILAR0));
307 outl(word, PCI_REG(SH7751_PCICONF5));
308 /* Set the values on window 1 PCI config registers */
309 word = PHYSADDR(map->window1.base);
310 outl(word, PCI_REG(SH7751_PCILAR1));
311 outl(word, PCI_REG(SH7751_PCICONF6));
313 /* Set the local 16MB PCI memory space window to
314 * the lowest PCI mapped address
316 word = PCIBIOS_MIN_MEM & SH7751_PCIMBR_MASK;
317 PCIDBG(2,"PCI: Setting upper bits of Memory window to 0x%x\n", word);
318 outl(word , PCI_REG(SH7751_PCIMBR));
320 /* Map IO space into PCI IO window
321 * The IO window is 64K-PCIBIOS_MIN_IO in size
322 * IO addresses will be translated to the
323 * PCI IO window base address
325 PCIDBG(3,"PCI: Mapping IO address 0x%x - 0x%x to base 0x%x\n", PCIBIOS_MIN_IO,
326 (64*1024), SH7751_PCI_IO_BASE+PCIBIOS_MIN_IO);
329 * XXX: For now, leave this board-specific. In the event we have other
330 * boards that need to do similar work, this can be wrapped.
332 #ifdef CONFIG_SH_BIGSUR
333 bigsur_port_map(PCIBIOS_MIN_IO, (64*1024), SH7751_PCI_IO_BASE+PCIBIOS_MIN_IO,0);
336 /* Make sure the MSB's of IO window are set to access PCI space correctly */
337 word = PCIBIOS_MIN_IO & SH7751_PCIIOBR_MASK;
338 PCIDBG(2,"PCI: Setting upper bits of IO window to 0x%x\n", word);
339 outl(word, PCI_REG(SH7751_PCIIOBR));
341 /* Set PCI WCRx, BCRx's, copy from BSC locations */
343 /* check BCR for SDRAM in specified area */
344 switch (map->window0.base) {
345 case SH7751_CS0_BASE_ADDR: word = __area_sdram_check(0); break;
346 case SH7751_CS1_BASE_ADDR: word = __area_sdram_check(1); break;
347 case SH7751_CS2_BASE_ADDR: word = __area_sdram_check(2); break;
348 case SH7751_CS3_BASE_ADDR: word = __area_sdram_check(3); break;
349 case SH7751_CS4_BASE_ADDR: word = __area_sdram_check(4); break;
350 case SH7751_CS5_BASE_ADDR: word = __area_sdram_check(5); break;
351 case SH7751_CS6_BASE_ADDR: word = __area_sdram_check(6); break;
357 /* configure the wait control registers */
358 word = inl(SH7751_WCR1);
359 outl(word, PCI_REG(SH7751_PCIWCR1));
360 word = inl(SH7751_WCR2);
361 outl(word, PCI_REG(SH7751_PCIWCR2));
362 word = inl(SH7751_WCR3);
363 outl(word, PCI_REG(SH7751_PCIWCR3));
364 word = inl(SH7751_MCR);
365 outl(word, PCI_REG(SH7751_PCIMCR));
367 /* NOTE: I'm ignoring the PCI error IRQs for now..
368 * TODO: add support for the internal error interrupts and
372 #ifdef CONFIG_SH_RTS7751R2D
376 /* SH7751 init done, set central function init complete */
377 /* use round robin mode to stop a device starving/overruning */
378 word = SH7751_PCICR_PREFIX | SH7751_PCICR_CFIN | SH7751_PCICR_ARBM;
379 outl(word,PCI_REG(SH7751_PCICR));
384 char * __init pcibios_setup(char *str)
386 if (!strcmp(str, "off")) {
397 static u8 __init sh7751_no_swizzle(struct pci_dev *dev, u8 *pin)
400 return PCI_SLOT(dev->devfn);
403 static int sh7751_pci_lookup_irq(struct pci_dev *dev, u8 slot, u8 pin)
407 /* now lookup the actual IRQ on a platform specific basis (pci-'platform'.c) */
408 irq = pcibios_map_platform_irq(slot,pin);
410 pr_debug("PCI: Error mapping IRQ on device %s\n", dev->slot_name);
414 pr_debug("Setting IRQ for slot %s to %d\n", dev->slot_name, irq);
419 void __init pcibios_fixup_irqs(void)
421 pci_fixup_irqs(sh7751_no_swizzle, sh7751_pci_lookup_irq);