2 * Low-Level PCI Support for the SH7751
4 * Dustin McIntire (dustin@sensoria.com)
5 * Derived from arch/i386/kernel/pci-*.c which bore the message:
6 * (c) 1999--2000 Martin Mares <mj@ucw.cz>
8 * Ported to the new API by Paul Mundt <lethal@linux-sh.org>
9 * With cleanup by Paul van Gool <pvangool@mimotech.com>
11 * May be copied or modified under the terms of the GNU General Public
12 * License. See linux/COPYING for more information.
18 #include <linux/config.h>
19 #include <linux/types.h>
20 #include <linux/kernel.h>
21 #include <linux/init.h>
22 #include <linux/pci.h>
23 #include <linux/sched.h>
24 #include <linux/ioport.h>
25 #include <linux/errno.h>
26 #include <linux/irq.h>
27 #include <linux/delay.h>
29 #include <asm/machvec.h>
31 #include "pci-sh7751.h"
33 static unsigned int pci_probe = PCI_PROBE_CONF1;
36 * Direct access to PCI hardware...
39 #define CONFIG_CMD(bus, devfn, where) (0x80000000 | (bus->number << 16) | (devfn << 8) | (where & ~3))
42 * Functions for accessing PCI configuration space with type 1 accesses
44 static int sh7751_pci_read(struct pci_bus *bus, unsigned int devfn,
45 int where, int size, u32 *val)
51 * PCIPDR may only be accessed as 32 bit words,
52 * so we must do byte alignment by hand
54 local_irq_save(flags);
55 outl(CONFIG_CMD(bus,devfn,where), PCI_REG(SH7751_PCIPAR));
56 data = inl(PCI_REG(SH7751_PCIPDR));
57 local_irq_restore(flags);
61 *val = (data >> ((where & 3) << 3)) & 0xff;
64 *val = (data >> ((where & 2) << 3)) & 0xffff;
70 return PCIBIOS_FUNC_NOT_SUPPORTED;
73 return PCIBIOS_SUCCESSFUL;
77 * Since SH7751 only does 32bit access we'll have to do a read,mask,write operation.
78 * We'll allow an odd byte offset, though it should be illegal.
80 static int sh7751_pci_write(struct pci_bus *bus, unsigned int devfn,
81 int where, int size, u32 val)
87 local_irq_save(flags);
88 outl(CONFIG_CMD(bus,devfn,where), PCI_REG(SH7751_PCIPAR));
89 data = inl(PCI_REG(SH7751_PCIPDR));
90 local_irq_restore(flags);
94 shift = (where & 3) << 3;
95 data &= ~(0xff << shift);
96 data |= ((val & 0xff) << shift);
99 shift = (where & 2) << 3;
100 data &= ~(0xffff << shift);
101 data |= ((val & 0xffff) << shift);
107 return PCIBIOS_FUNC_NOT_SUPPORTED;
110 outl(data, PCI_REG(SH7751_PCIPDR));
112 return PCIBIOS_SUCCESSFUL;
117 struct pci_ops sh7751_pci_ops = {
118 .read = sh7751_pci_read,
119 .write = sh7751_pci_write,
122 static int __init pci_check_direct(void)
124 unsigned int tmp, id;
126 /* check for SH7751/SH7751R hardware */
127 id = inl(SH7751_PCIREG_BASE+SH7751_PCICONF0);
128 if (id != ((SH7751_DEVICE_ID << 16) | SH7751_VENDOR_ID) &&
129 id != ((SH7751R_DEVICE_ID << 16) | SH7751_VENDOR_ID)) {
130 pr_debug("PCI: This is not an SH7751(R) (%x)\n", id);
135 * Check if configuration works.
137 if (pci_probe & PCI_PROBE_CONF1) {
138 tmp = inl (PCI_REG(SH7751_PCIPAR));
139 outl (0x80000000, PCI_REG(SH7751_PCIPAR));
140 if (inl (PCI_REG(SH7751_PCIPAR)) == 0x80000000) {
141 outl (tmp, PCI_REG(SH7751_PCIPAR));
142 printk(KERN_INFO "PCI: Using configuration type 1\n");
143 request_region(PCI_REG(SH7751_PCIPAR), 8, "PCI conf1");
146 outl (tmp, PCI_REG(SH7751_PCIPAR));
149 pr_debug("PCI: pci_check_direct failed\n");
153 /***************************************************************************************/
156 * Handle bus scanning and fixups ....
159 static void __init pci_fixup_ide_bases(struct pci_dev *d)
164 * PCI IDE controllers use non-standard I/O port decoding, respect it.
166 if ((d->class >> 8) != PCI_CLASS_STORAGE_IDE)
168 pr_debug("PCI: IDE base address fixup for %s\n", d->slot_name);
170 struct resource *r = &d->resource[i];
171 if ((r->start & ~0x80) == 0x374) {
179 /* Add future fixups here... */
180 struct pci_fixup pcibios_fixups[] = {
181 { PCI_FIXUP_HEADER, PCI_ANY_ID, PCI_ANY_ID, pci_fixup_ide_bases },
186 * Called after each bus is probed, but before its children
190 void __init pcibios_fixup_bus(struct pci_bus *b)
192 pci_read_bridge_bases(b);
196 * Initialization. Try all known PCI access methods. Note that we support
197 * using both PCI BIOS and direct access: in such cases, we use I/O ports
198 * to access config space.
200 * Note that the platform specific initialization (BSC registers, and memory
201 * space mapping) will be called via the machine vectors (sh_mv.mv_pci_init()) if it
202 * exitst and via the platform defined function pcibios_init_platform().
203 * See pci_bigsur.c for implementation;
205 * The BIOS version of the pci functions is not yet implemented but it is left
206 * in for completeness. Currently an error will be genereated at compile time.
209 static int __init sh7751_pci_init(void)
213 pr_debug("PCI: Starting intialization.\n");
214 if ((ret = pci_check_direct()) != 0)
217 return pcibios_init_platform();
220 subsys_initcall(sh7751_pci_init);
222 static int __init __area_sdram_check(unsigned int area)
226 word = inl(SH7751_BCR1);
227 /* check BCR for SDRAM in area */
228 if(((word >> area) & 1) == 0) {
229 printk("PCI: Area %d is not configured for SDRAM. BCR1=0x%x\n",
233 outl(word, PCI_REG(SH7751_PCIBCR1));
235 word = (u16)inw(SH7751_BCR2);
236 /* check BCR2 for 32bit SDRAM interface*/
237 if(((word >> (area << 1)) & 0x3) != 0x3) {
238 printk("PCI: Area %d is not 32 bit SDRAM. BCR2=0x%x\n",
242 outl(word, PCI_REG(SH7751_PCIBCR2));
247 int __init sh7751_pcic_init(struct sh7751_pci_address_map *map)
252 /* Set the BCR's to enable PCI access */
253 reg = inl(SH7751_BCR1);
255 outl(reg, SH7751_BCR1);
257 /* Turn the clocks back on (not done in reset)*/
258 outl(0, PCI_REG(SH7751_PCICLKR));
259 /* Clear Powerdown IRQ's (not done in reset) */
260 word = SH7751_PCIPINT_D3 | SH7751_PCIPINT_D0;
261 outl(word, PCI_REG(SH7751_PCICLKR));
264 * XXX: This code is unused for the SnapGear boards as it is done in
265 * the bootloader and doing it here means the MAC addresses loaded by
266 * the bootloader get lost.
268 #ifndef CONFIG_SH_SECUREEDGE5410
269 /* toggle PCI reset pin */
270 word = SH7751_PCICR_PREFIX | SH7751_PCICR_PRST;
271 outl(word,PCI_REG(SH7751_PCICR));
272 /* Wait for a long time... not 1 sec. but long enough */
274 word = SH7751_PCICR_PREFIX;
275 outl(word,PCI_REG(SH7751_PCICR));
278 /* set the command/status bits to:
279 * Wait Cycle Control + Parity Enable + Bus Master +
282 word = SH7751_PCICONF1_WCC | SH7751_PCICONF1_PER |
283 SH7751_PCICONF1_BUM | SH7751_PCICONF1_MES;
284 outl(word, PCI_REG(SH7751_PCICONF1));
286 /* define this host as the host bridge */
287 word = SH7751_PCI_HOST_BRIDGE << 24;
288 outl(word, PCI_REG(SH7751_PCICONF2));
290 /* Set IO and Mem windows to local address
291 * Make PCI and local address the same for easy 1 to 1 mapping
292 * Window0 = map->window0.size @ non-cached area base = SDRAM
293 * Window1 = map->window1.size @ cached area base = SDRAM
295 word = map->window0.size - 1;
296 outl(word, PCI_REG(SH7751_PCILSR0));
297 word = map->window1.size - 1;
298 outl(word, PCI_REG(SH7751_PCILSR1));
299 /* Set the values on window 0 PCI config registers */
300 word = P2SEGADDR(map->window0.base);
301 outl(word, PCI_REG(SH7751_PCILAR0));
302 outl(word, PCI_REG(SH7751_PCICONF5));
303 /* Set the values on window 1 PCI config registers */
304 word = PHYSADDR(map->window1.base);
305 outl(word, PCI_REG(SH7751_PCILAR1));
306 outl(word, PCI_REG(SH7751_PCICONF6));
308 /* Set the local 16MB PCI memory space window to
309 * the lowest PCI mapped address
311 word = PCIBIOS_MIN_MEM & SH7751_PCIMBR_MASK;
312 PCIDBG(2,"PCI: Setting upper bits of Memory window to 0x%x\n", word);
313 outl(word , PCI_REG(SH7751_PCIMBR));
315 /* Map IO space into PCI IO window
316 * The IO window is 64K-PCIBIOS_MIN_IO in size
317 * IO addresses will be translated to the
318 * PCI IO window base address
320 PCIDBG(3,"PCI: Mapping IO address 0x%x - 0x%x to base 0x%x\n", PCIBIOS_MIN_IO,
321 (64*1024), SH7751_PCI_IO_BASE+PCIBIOS_MIN_IO);
324 * XXX: For now, leave this board-specific. In the event we have other
325 * boards that need to do similar work, this can be wrapped.
327 #ifdef CONFIG_SH_BIGSUR
328 bigsur_port_map(PCIBIOS_MIN_IO, (64*1024), SH7751_PCI_IO_BASE+PCIBIOS_MIN_IO,0);
331 /* Make sure the MSB's of IO window are set to access PCI space correctly */
332 word = PCIBIOS_MIN_IO & SH7751_PCIIOBR_MASK;
333 PCIDBG(2,"PCI: Setting upper bits of IO window to 0x%x\n", word);
334 outl(word, PCI_REG(SH7751_PCIIOBR));
336 /* Set PCI WCRx, BCRx's, copy from BSC locations */
338 /* check BCR for SDRAM in specified area */
339 switch (map->window0.base) {
340 case SH7751_CS0_BASE_ADDR: word = __area_sdram_check(0); break;
341 case SH7751_CS1_BASE_ADDR: word = __area_sdram_check(1); break;
342 case SH7751_CS2_BASE_ADDR: word = __area_sdram_check(2); break;
343 case SH7751_CS3_BASE_ADDR: word = __area_sdram_check(3); break;
344 case SH7751_CS4_BASE_ADDR: word = __area_sdram_check(4); break;
345 case SH7751_CS5_BASE_ADDR: word = __area_sdram_check(5); break;
346 case SH7751_CS6_BASE_ADDR: word = __area_sdram_check(6); break;
352 /* configure the wait control registers */
353 word = inl(SH7751_WCR1);
354 outl(word, PCI_REG(SH7751_PCIWCR1));
355 word = inl(SH7751_WCR2);
356 outl(word, PCI_REG(SH7751_PCIWCR2));
357 word = inl(SH7751_WCR3);
358 outl(word, PCI_REG(SH7751_PCIWCR3));
359 word = inl(SH7751_MCR);
360 outl(word, PCI_REG(SH7751_PCIMCR));
362 /* NOTE: I'm ignoring the PCI error IRQs for now..
363 * TODO: add support for the internal error interrupts and
367 /* SH7751 init done, set central function init complete */
368 /* use round robin mode to stop a device starving/overruning */
369 word = SH7751_PCICR_PREFIX | SH7751_PCICR_CFIN | SH7751_PCICR_ARBM;
370 outl(word,PCI_REG(SH7751_PCICR));
375 char * __init pcibios_setup(char *str)
377 if (!strcmp(str, "off")) {
388 static u8 __init sh7751_no_swizzle(struct pci_dev *dev, u8 *pin)
391 return PCI_SLOT(dev->devfn);
394 static int sh7751_pci_lookup_irq(struct pci_dev *dev, u8 slot, u8 pin)
398 /* now lookup the actual IRQ on a platform specific basis (pci-'platform'.c) */
399 irq = pcibios_map_platform_irq(slot,pin);
401 pr_debug("PCI: Error mapping IRQ on device %s\n", dev->slot_name);
405 pr_debug("Setting IRQ for slot %s to %d\n", dev->slot_name, irq);
410 void __init pcibios_fixup_irqs(void)
412 pci_fixup_irqs(sh7751_no_swizzle, sh7751_pci_lookup_irq);