2 * arch/sh/kernel/cpu/init.c
6 * Copyright (C) 2002, 2003 Paul Mundt
8 * This file is subject to the terms and conditions of the GNU General Public
9 * License. See the file "COPYING" in the main directory of this archive
12 #include <linux/init.h>
13 #include <linux/kernel.h>
14 #include <asm/processor.h>
15 #include <asm/uaccess.h>
16 #include <asm/system.h>
17 #include <asm/cacheflush.h>
18 #include <asm/cache.h>
21 extern void detect_cpu_and_cache_system(void);
24 * Generic wrapper for command line arguments to disable on-chip
25 * peripherals (nofpu, nodsp, and so forth).
27 #define onchip_setup(x) \
28 static int x##_disabled __initdata = 0; \
30 static int __init x##_setup(char *opts) \
35 __setup("no" __stringify(x), x##_setup);
41 * Generic first-level cache init
43 static void __init cache_init(void)
45 unsigned long ccr, flags = 0;
47 if (cpu_data->type == CPU_SH_NONE)
54 * If the cache is already enabled .. flush it.
56 if (ccr & CCR_CACHE_ENABLE) {
57 unsigned long entries, i, j;
59 entries = cpu_data->dcache.sets;
62 * If the OC is already in RAM mode, we only have
63 * half of the entries to flush..
65 if (ccr & CCR_CACHE_ORA)
68 for (i = 0; i < entries; i++) {
69 for (j = 0; j < cpu_data->dcache.ways; j++) {
70 unsigned long data, addr;
72 addr = CACHE_OC_ADDRESS_ARRAY |
73 (j << cpu_data->dcache.way_shift) |
74 (i << cpu_data->dcache.entry_shift);
76 data = ctrl_inl(addr);
78 if ((data & (SH_CACHE_UPDATED | SH_CACHE_VALID))
79 == (SH_CACHE_UPDATED | SH_CACHE_VALID))
80 ctrl_outl(data & ~SH_CACHE_UPDATED, addr);
86 * Default CCR values .. enable the caches
87 * and flush them immediately..
89 flags |= CCR_CACHE_ENABLE | CCR_CACHE_INVALIDATE;
91 #ifdef CCR_CACHE_EMODE
92 flags |= (ccr & CCR_CACHE_EMODE);
95 #ifdef CONFIG_SH_WRITETHROUGH
96 /* Turn on Write-through caching */
97 flags |= CCR_CACHE_WT;
99 /* .. or default to Write-back */
100 flags |= CCR_CACHE_CB;
103 #ifdef CONFIG_SH_OCRAM
104 /* Turn on OCRAM -- halve the OC */
105 flags |= CCR_CACHE_ORA;
106 cpu_data->dcache.sets >>= 1;
109 ctrl_outl(flags, CCR);
114 static void __init release_dsp(void)
118 /* Clear SR.DSP bit */
119 __asm__ __volatile__ (
128 static void __init dsp_init(void)
133 * Set the SR.DSP bit, wait for one instruction, and then read
136 __asm__ __volatile__ (
146 /* If the DSP bit is still set, this CPU has a DSP */
148 set_bit(CPU_HAS_DSP, &(cpu_data->flags));
150 /* Now that we've determined the DSP status, clear the DSP bit. */
153 #endif /* CONFIG_SH_DSP */
158 * This is our initial entry point for each CPU, and is invoked on the boot
159 * CPU prior to calling start_kernel(). For SMP, a combination of this and
160 * start_secondary() will bring up each processor to a ready state prior
161 * to hand forking the idle loop.
163 * We do all of the basic processor init here, including setting up the
164 * caches, FPU, DSP, kicking the UBC, etc. By the time start_kernel() is
165 * hit (and subsequently platform_setup()) things like determining the
166 * CPU subtype and initial configuration will all be done.
168 * Each processor family is still responsible for doing its own probing
169 * and cache configuration in detect_cpu_and_cache_system().
171 asmlinkage void __init sh_cpu_init(void)
173 /* First, probe the CPU */
174 detect_cpu_and_cache_system();
179 /* Disable the FPU */
181 printk("FPU Disabled\n");
182 cpu_data->flags &= ~CPU_HAS_FPU;
186 /* FPU initialization */
187 if (test_bit(CPU_HAS_FPU, &(cpu_data->flags))) {
188 clear_thread_flag(TIF_USEDFPU);
189 current->used_math = 0;
196 /* Disable the DSP */
198 printk("DSP Disabled\n");
199 cpu_data->flags &= ~CPU_HAS_DSP;
204 #ifdef CONFIG_UBC_WAKEUP
206 * Some brain-damaged loaders decided it would be a good idea to put
207 * the UBC to sleep. This causes some issues when it comes to things
208 * like PTRACE_SINGLESTEP or doing hardware watchpoints in GDB. So ..
209 * we wake it up and hope that all is well.