1 /* $Id: time.c,v 1.21 2004/04/21 00:09:15 lethal Exp $
3 * linux/arch/sh/kernel/time.c
5 * Copyright (C) 1999 Tetsuya Okada & Niibe Yutaka
6 * Copyright (C) 2000 Philipp Rumpf <prumpf@tux.org>
7 * Copyright (C) 2002, 2003, 2004 Paul Mundt
8 * Copyright (C) 2002 M. R. Brown <mrbrown@linux-sh.org>
10 * Some code taken from i386 version.
11 * Copyright (C) 1991, 1992, 1995 Linus Torvalds
14 #include <linux/config.h>
15 #include <linux/errno.h>
16 #include <linux/module.h>
17 #include <linux/sched.h>
18 #include <linux/kernel.h>
19 #include <linux/param.h>
20 #include <linux/string.h>
22 #include <linux/interrupt.h>
23 #include <linux/time.h>
24 #include <linux/delay.h>
25 #include <linux/init.h>
26 #include <linux/smp.h>
27 #include <linux/profile.h>
29 #include <asm/processor.h>
30 #include <asm/uaccess.h>
33 #include <asm/delay.h>
34 #include <asm/machvec.h>
41 #include <linux/timex.h>
42 #include <linux/irq.h>
44 #define TMU_TOCR_INIT 0x00
45 #define TMU0_TCR_INIT 0x0020
46 #define TMU_TSTR_INIT 1
48 #define TMU0_TCR_CALIB 0x0000
50 #if defined(CONFIG_CPU_SH3)
51 #if defined(CONFIG_CPU_SUBTYPE_SH7300)
52 #define TMU_TSTR 0xA412FE92 /* Byte access */
54 #define TMU0_TCOR 0xA412FE94 /* Long access */
55 #define TMU0_TCNT 0xA412FE98 /* Long access */
56 #define TMU0_TCR 0xA412FE9C /* Word access */
58 #define TMU1_TCOR 0xA412FEA0 /* Long access */
59 #define TMU1_TCNT 0xA412FEA4 /* Long access */
60 #define TMU1_TCR 0xA412FEA8 /* Word access */
62 #define FRQCR 0xA415FF80
64 #define TMU_TOCR 0xfffffe90 /* Byte access */
65 #define TMU_TSTR 0xfffffe92 /* Byte access */
67 #define TMU0_TCOR 0xfffffe94 /* Long access */
68 #define TMU0_TCNT 0xfffffe98 /* Long access */
69 #define TMU0_TCR 0xfffffe9c /* Word access */
71 #elif defined(CONFIG_CPU_SH4)
72 #define TMU_TOCR 0xffd80000 /* Byte access */
73 #define TMU_TSTR 0xffd80004 /* Byte access */
75 #define TMU0_TCOR 0xffd80008 /* Long access */
76 #define TMU0_TCNT 0xffd8000c /* Long access */
77 #define TMU0_TCR 0xffd80010 /* Word access */
79 #ifdef CONFIG_CPU_SUBTYPE_ST40STB1
80 #define CLOCKGEN_MEMCLKCR 0xbb040038
81 #define MEMCLKCR_RATIO_MASK 0x7
82 #endif /* CONFIG_CPU_SUBTYPE_ST40STB1 */
83 #endif /* CONFIG_CPU_SH3 or CONFIG_CPU_SH4 */
85 extern unsigned long wall_jiffies;
86 #define TICK_SIZE (tick_nsec / 1000)
87 spinlock_t tmu0_lock = SPIN_LOCK_UNLOCKED;
89 u64 jiffies_64 = INITIAL_JIFFIES;
91 EXPORT_SYMBOL(jiffies_64);
93 /* XXX: Can we initialize this in a routine somewhere? Dreamcast doesn't want
94 * these routines anywhere... */
96 void (*rtc_get_time)(struct timespec *) = sh_rtc_gettimeofday;
97 int (*rtc_set_time)(const time_t) = sh_rtc_settimeofday;
99 void (*rtc_get_time)(struct timespec *) = 0;
100 int (*rtc_set_time)(const time_t) = 0;
103 #if defined(CONFIG_CPU_SUBTYPE_SH7300)
104 static int md_table[] = { 1, 2, 3, 4, 6, 8, 12 };
106 #if defined(CONFIG_CPU_SH3)
107 static int stc_multipliers[] = { 1, 2, 3, 4, 6, 1, 1, 1 };
108 static int stc_values[] = { 0, 1, 4, 2, 5, 0, 0, 0 };
109 #define bfc_divisors stc_multipliers
110 #define bfc_values stc_values
111 static int ifc_divisors[] = { 1, 2, 3, 4, 1, 1, 1, 1 };
112 static int ifc_values[] = { 0, 1, 4, 2, 0, 0, 0, 0 };
113 static int pfc_divisors[] = { 1, 2, 3, 4, 6, 1, 1, 1 };
114 static int pfc_values[] = { 0, 1, 4, 2, 5, 0, 0, 0 };
115 #elif defined(CONFIG_CPU_SH4)
116 static int ifc_divisors[] = { 1, 2, 3, 4, 6, 8, 1, 1 };
117 static int ifc_values[] = { 0, 1, 2, 3, 0, 4, 0, 5 };
118 #define bfc_divisors ifc_divisors /* Same */
119 #define bfc_values ifc_values
120 static int pfc_divisors[] = { 2, 3, 4, 6, 8, 2, 2, 2 };
121 static int pfc_values[] = { 0, 0, 1, 2, 0, 3, 0, 4 };
123 #error "Unknown ifc/bfc/pfc/stc values for this processor"
127 * Scheduler clock - returns current time in nanosec units.
129 unsigned long long sched_clock(void)
131 return (unsigned long long)jiffies * (1000000000 / HZ);
134 static unsigned long do_gettimeoffset(void)
139 static int count_p = 0x7fffffff; /* for the first call after boot */
140 static unsigned long jiffies_p = 0;
143 * cache volatile jiffies temporarily; we have IRQs turned off.
145 unsigned long jiffies_t;
147 spin_lock_irqsave(&tmu0_lock, flags);
148 /* timer count may underflow right here */
149 count = ctrl_inl(TMU0_TCNT); /* read the latched count */
154 * avoiding timer inconsistencies (they are rare, but they happen)...
155 * there is one kind of problem that must be avoided here:
156 * 1. the timer counter underflows
159 if( jiffies_t == jiffies_p ) {
160 if( count > count_p ) {
163 if(ctrl_inw(TMU0_TCR) & 0x100) { /* Check UNF bit */
165 * We cannot detect lost timer interrupts ...
166 * well, that's why we call them lost, don't we? :)
167 * [hmm, on the Pentium and Alpha we can ... sort of]
171 printk("do_slow_gettimeoffset(): hardware timer problem?\n");
175 jiffies_p = jiffies_t;
178 spin_unlock_irqrestore(&tmu0_lock, flags);
180 count = ((LATCH-1) - count) * TICK_SIZE;
181 count = (count + LATCH/2) / LATCH;
186 void do_gettimeofday(struct timeval *tv)
189 unsigned long usec, sec;
193 seq = read_seqbegin(&xtime_lock);
194 usec = do_gettimeoffset();
196 lost = jiffies - wall_jiffies;
198 usec += lost * (1000000 / HZ);
201 usec += xtime.tv_nsec / 1000;
202 } while (read_seqretry(&xtime_lock, seq));
204 while (usec >= 1000000) {
213 EXPORT_SYMBOL(do_gettimeofday);
215 int do_settimeofday(struct timespec *tv)
217 time_t wtm_sec, sec = tv->tv_sec;
218 long wtm_nsec, nsec = tv->tv_nsec;
220 if ((unsigned long)tv->tv_nsec >= NSEC_PER_SEC)
223 write_seqlock_irq(&xtime_lock);
225 * This is revolting. We need to set "xtime" correctly. However, the
226 * value in this location is the value at the most recent update of
227 * wall time. Discover what correction gettimeofday() would have
228 * made, and then undo it!
230 nsec -= 1000 * (do_gettimeoffset() +
231 (jiffies - wall_jiffies) * (1000000 / HZ));
233 wtm_sec = wall_to_monotonic.tv_sec + (xtime.tv_sec - sec);
234 wtm_nsec = wall_to_monotonic.tv_nsec + (xtime.tv_nsec - nsec);
236 set_normalized_timespec(&xtime, sec, nsec);
237 set_normalized_timespec(&wall_to_monotonic, wtm_sec, wtm_nsec);
239 time_adjust = 0; /* stop active adjtime() */
240 time_status |= STA_UNSYNC;
241 time_maxerror = NTP_PHASE_LIMIT;
242 time_esterror = NTP_PHASE_LIMIT;
243 write_sequnlock_irq(&xtime_lock);
249 EXPORT_SYMBOL(do_settimeofday);
251 /* last time the RTC clock got updated */
252 static long last_rtc_update;
255 * timer_interrupt() needs to keep up the real-time clock,
256 * as well as call the "do_timer()" routine every clocktick
258 static inline void do_timer_interrupt(int irq, void *dev_id, struct pt_regs *regs)
261 profile_tick(CPU_PROFILING, regs);
263 #ifdef CONFIG_HEARTBEAT
264 if (sh_mv.mv_heartbeat != NULL)
265 sh_mv.mv_heartbeat();
269 * If we have an externally synchronized Linux clock, then update
270 * RTC clock accordingly every ~11 minutes. Set_rtc_mmss() has to be
271 * called as close as possible to 500 ms before the new second starts.
273 if ((time_status & STA_UNSYNC) == 0 &&
274 xtime.tv_sec > last_rtc_update + 660 &&
275 (xtime.tv_nsec / 1000) >= 500000 - ((unsigned) TICK_SIZE) / 2 &&
276 (xtime.tv_nsec / 1000) <= 500000 + ((unsigned) TICK_SIZE) / 2) {
277 if (rtc_set_time(xtime.tv_sec) == 0)
278 last_rtc_update = xtime.tv_sec;
280 last_rtc_update = xtime.tv_sec - 600; /* do it again in 60 s */
285 * This is the same as the above, except we _also_ save the current
286 * Time Stamp Counter value at the time of the timer interrupt, so that
287 * we later on can estimate the time of day more exactly.
289 static irqreturn_t timer_interrupt(int irq, void *dev_id, struct pt_regs *regs)
291 unsigned long timer_status;
294 timer_status = ctrl_inw(TMU0_TCR);
295 timer_status &= ~0x100;
296 ctrl_outw(timer_status, TMU0_TCR);
299 * Here we are in the timer irq handler. We just have irqs locally
300 * disabled but we don't know if the timer_bh is running on the other
301 * CPU. We need to avoid to SMP race with it. NOTE: we don' t need
302 * the irq version of write_lock because as just said we have irq
303 * locally disabled. -arca
305 write_seqlock(&xtime_lock);
306 do_timer_interrupt(irq, NULL, regs);
307 write_sequnlock(&xtime_lock);
313 * Hah! We'll see if this works (switching from usecs to nsecs).
315 static unsigned int __init get_timer_frequency(void)
318 struct timespec ts1, ts2;
319 unsigned long diff_nsec;
320 unsigned long factor;
322 /* Setup the timer: We don't want to generate interrupts, just
323 * have it count down at its natural rate.
325 ctrl_outb(0, TMU_TSTR);
326 #if !defined(CONFIG_CPU_SUBTYPE_SH7300)
327 ctrl_outb(TMU_TOCR_INIT, TMU_TOCR);
329 ctrl_outw(TMU0_TCR_CALIB, TMU0_TCR);
330 ctrl_outl(0xffffffff, TMU0_TCOR);
331 ctrl_outl(0xffffffff, TMU0_TCNT);
337 } while (ts1.tv_nsec == ts2.tv_nsec && ts1.tv_sec == ts2.tv_sec);
339 /* actually start the timer */
340 ctrl_outb(TMU_TSTR_INIT, TMU_TSTR);
344 } while (ts1.tv_nsec == ts2.tv_nsec && ts1.tv_sec == ts2.tv_sec);
346 freq = 0xffffffff - ctrl_inl(TMU0_TCNT);
347 if (ts2.tv_nsec < ts1.tv_nsec) {
348 ts2.tv_nsec += 1000000000;
352 diff_nsec = (ts2.tv_sec - ts1.tv_sec) * 1000000000 + (ts2.tv_nsec - ts1.tv_nsec);
354 /* this should work well if the RTC has a precision of n Hz, where
355 * n is an integer. I don't think we have to worry about the other
357 factor = (1000000000 + diff_nsec/2) / diff_nsec;
359 if (factor * diff_nsec > 1100000000 ||
360 factor * diff_nsec < 900000000)
361 panic("weird RTC (diff_nsec %ld)", diff_nsec);
363 return freq * factor;
366 void (*board_time_init)(void) = 0;
367 void (*board_timer_setup)(struct irqaction *irq) = 0;
369 static unsigned int sh_pclk_freq __initdata = CONFIG_SH_PCLK_FREQ;
371 static int __init sh_pclk_setup(char *str)
375 if (get_option(&str, &freq))
380 __setup("sh_pclk=", sh_pclk_setup);
382 static struct irqaction irq0 = { timer_interrupt, SA_INTERRUPT, CPU_MASK_NONE, "timer", NULL, NULL};
384 void get_current_frequency_divisors(unsigned int *ifc, unsigned int *bfc, unsigned int *pfc)
386 unsigned int frqcr = ctrl_inw(FRQCR);
388 #if defined(CONFIG_CPU_SH3)
389 #if defined(CONFIG_CPU_SUBTYPE_SH7300)
390 *ifc = md_table[((frqcr & 0x0070) >> 4)];
391 *bfc = md_table[((frqcr & 0x0700) >> 8)];
392 *pfc = md_table[frqcr & 0x0007];
393 #elif defined(CONFIG_CPU_SUBTYPE_SH7705)
394 *bfc = stc_multipliers[(frqcr & 0x0300) >> 8];
395 *ifc = ifc_divisors[(frqcr & 0x0030) >> 4];
396 *pfc = pfc_divisors[frqcr & 0x0003];
400 tmp = (frqcr & 0x8000) >> 13;
401 tmp |= (frqcr & 0x0030) >> 4;
402 *bfc = stc_multipliers[tmp];
403 tmp = (frqcr & 0x4000) >> 12;
404 tmp |= (frqcr & 0x000c) >> 2;
405 *ifc = ifc_divisors[tmp];
406 tmp = (frqcr & 0x2000) >> 11;
407 tmp |= frqcr & 0x0003;
408 *pfc = pfc_divisors[tmp];
410 #elif defined(CONFIG_CPU_SH4)
411 *ifc = ifc_divisors[(frqcr >> 6) & 0x0007];
412 *bfc = bfc_divisors[(frqcr >> 3) & 0x0007];
413 *pfc = pfc_divisors[frqcr & 0x0007];
418 * This bit of ugliness builds up accessor routines to get at both
419 * the divisors and the physical values.
421 #define _FREQ_TABLE(x) \
422 unsigned int get_##x##_divisor(unsigned int value) \
423 { return x##_divisors[value]; } \
425 unsigned int get_##x##_value(unsigned int divisor) \
426 { return x##_values[(divisor - 1)]; }
432 #ifdef CONFIG_CPU_SUBTYPE_ST40STB1
434 /* The ST40 divisors are totally different so we set the cpu data
435 ** clocks using a different algorithm
437 ** I've just plugged this from the 2.4 code - Alex Bennee <kernel-hacker@bennee.com>
439 #define CCN_PVR_CHIP_SHIFT 24
440 #define CCN_PVR_CHIP_MASK 0xff
441 #define CCN_PVR_CHIP_ST40STB1 0x4
445 unsigned short frqcr;
447 unsigned char multiplier;
448 unsigned char divisor;
452 static struct frqcr_data st40_frqcr_table[] = {
453 { 0x000, {{1,1}, {1,1}, {1,2}}},
454 { 0x002, {{1,1}, {1,1}, {1,4}}},
455 { 0x004, {{1,1}, {1,1}, {1,8}}},
456 { 0x008, {{1,1}, {1,2}, {1,2}}},
457 { 0x00A, {{1,1}, {1,2}, {1,4}}},
458 { 0x00C, {{1,1}, {1,2}, {1,8}}},
459 { 0x011, {{1,1}, {2,3}, {1,6}}},
460 { 0x013, {{1,1}, {2,3}, {1,3}}},
461 { 0x01A, {{1,1}, {1,2}, {1,4}}},
462 { 0x01C, {{1,1}, {1,2}, {1,8}}},
463 { 0x023, {{1,1}, {2,3}, {1,3}}},
464 { 0x02C, {{1,1}, {1,2}, {1,8}}},
465 { 0x048, {{1,2}, {1,2}, {1,4}}},
466 { 0x04A, {{1,2}, {1,2}, {1,6}}},
467 { 0x04C, {{1,2}, {1,2}, {1,8}}},
468 { 0x05A, {{1,2}, {1,3}, {1,6}}},
469 { 0x05C, {{1,2}, {1,3}, {1,6}}},
470 { 0x063, {{1,2}, {1,4}, {1,4}}},
471 { 0x06C, {{1,2}, {1,4}, {1,8}}},
472 { 0x091, {{1,3}, {1,3}, {1,6}}},
473 { 0x093, {{1,3}, {1,3}, {1,6}}},
474 { 0x0A3, {{1,3}, {1,6}, {1,6}}},
475 { 0x0DA, {{1,4}, {1,4}, {1,8}}},
476 { 0x0DC, {{1,4}, {1,4}, {1,8}}},
477 { 0x0EC, {{1,4}, {1,8}, {1,8}}},
478 { 0x123, {{1,4}, {1,4}, {1,8}}},
479 { 0x16C, {{1,4}, {1,8}, {1,8}}},
483 unsigned char multiplier;
484 unsigned char divisor;
486 static struct memclk_data st40_memclk_table[8] = {
497 static void st40_specific_time_init(unsigned int module_clock, unsigned short frqcr)
499 unsigned int cpu_clock, master_clock, bus_clock, memory_clock;
500 struct frqcr_data *d;
502 unsigned long memclkcr;
503 struct memclk_data *e;
505 for (a=0; a<ARRAY_SIZE(st40_frqcr_table); a++) {
506 d = &st40_frqcr_table[a];
507 if (d->frqcr == (frqcr & 0x1ff))
510 if (a == ARRAY_SIZE(st40_frqcr_table)) {
511 d = st40_frqcr_table;
512 printk("ERROR: Unrecognised FRQCR value (0x%x), using default multipliers\n",frqcr);
515 memclkcr = ctrl_inl(CLOCKGEN_MEMCLKCR);
516 e = &st40_memclk_table[memclkcr & MEMCLKCR_RATIO_MASK];
518 printk("Clock multipliers: CPU: %d/%d Bus: %d/%d Mem: %d/%d Periph: %d/%d\n",
519 d->factor[0].multiplier, d->factor[0].divisor,
520 d->factor[1].multiplier, d->factor[1].divisor,
521 e->multiplier, e->divisor,
522 d->factor[2].multiplier, d->factor[2].divisor);
524 master_clock = module_clock * d->factor[2].divisor / d->factor[2].multiplier;
525 bus_clock = master_clock * d->factor[1].multiplier / d->factor[1].divisor;
526 memory_clock = master_clock * e->multiplier / e->divisor;
527 cpu_clock = master_clock * d->factor[0].multiplier / d->factor[0].divisor;
529 current_cpu_data.cpu_clock = cpu_clock;
530 current_cpu_data.master_clock = master_clock;
531 current_cpu_data.bus_clock = bus_clock;
532 current_cpu_data.memory_clock = memory_clock;
533 current_cpu_data.module_clock = module_clock;
539 void __init time_init(void)
541 unsigned int timer_freq = 0;
542 unsigned int ifc, pfc, bfc;
543 unsigned long interval;
544 #ifdef CONFIG_CPU_SUBTYPE_ST40STB1
546 unsigned short frqcr;
554 * If we don't have an RTC (such as with the SH7300), don't attempt to
555 * probe the timer frequency. Rely on an either hardcoded peripheral
556 * clock value, or on the sh_pclk command line option. Note that we
557 * still need to have CONFIG_SH_PCLK_FREQ set in order for things like
558 * CLOCK_TICK_RATE to be sane.
560 current_cpu_data.module_clock = sh_pclk_freq;
562 #ifdef CONFIG_SH_PCLK_CALC
563 /* XXX: Switch this over to a more generic test. */
568 * If we've specified a peripheral clock frequency, and we have
569 * an RTC, compare it against the autodetected value. Complain
570 * if there's a mismatch.
572 * Note: We should allow for some high and low watermarks for
573 * the frequency here (compensating for potential drift), as
574 * otherwise we'll likely end up triggering this essentially
577 timer_freq = get_timer_frequency();
578 freq = timer_freq * 4;
580 if (sh_pclk_freq && (sh_pclk_freq/100*99 > freq || sh_pclk_freq/100*101 < freq)) {
581 printk(KERN_NOTICE "Calculated peripheral clock value "
582 "%d differs from sh_pclk value %d, fixing..\n",
584 current_cpu_data.module_clock = freq;
589 #ifdef CONFIG_CPU_SUBTYPE_ST40STB1
590 pvr = ctrl_inl(CCN_PVR);
591 frqcr = ctrl_inw(FRQCR);
592 printk("time.c ST40 Probe: PVR %08lx, FRQCR %04hx\n", pvr, frqcr);
593 if (((pvr >>CCN_PVR_CHIP_SHIFT) & CCN_PVR_CHIP_MASK) == CCN_PVR_CHIP_ST40STB1)
594 st40_specific_time_init(current_cpu_data.module_clock, frqcr);
597 get_current_frequency_divisors(&ifc, &bfc, &pfc);
600 rtc_get_time(&xtime);
602 xtime.tv_sec = mktime(2000, 1, 1, 0, 0, 0);
606 set_normalized_timespec(&wall_to_monotonic,
607 -xtime.tv_sec, -xtime.tv_nsec);
609 if (board_timer_setup) {
610 board_timer_setup(&irq0);
612 setup_irq(TIMER_IRQ, &irq0);
616 ** for ST40 chips the current_cpu_data should already be set
617 ** so not having valid pfc/bfc/ifc shouldn't be a problem
619 if (!current_cpu_data.master_clock)
620 current_cpu_data.master_clock = current_cpu_data.module_clock * pfc;
621 if (!current_cpu_data.bus_clock)
622 current_cpu_data.bus_clock = current_cpu_data.master_clock / bfc;
623 if (!current_cpu_data.cpu_clock)
624 current_cpu_data.cpu_clock = current_cpu_data.master_clock / ifc;
626 printk("CPU clock: %d.%02dMHz\n",
627 (current_cpu_data.cpu_clock / 1000000),
628 (current_cpu_data.cpu_clock % 1000000)/10000);
629 printk("Bus clock: %d.%02dMHz\n",
630 (current_cpu_data.bus_clock / 1000000),
631 (current_cpu_data.bus_clock % 1000000)/10000);
632 #ifdef CONFIG_CPU_SUBTYPE_ST40STB1
633 printk("Memory clock: %d.%02dMHz\n",
634 (current_cpu_data.memory_clock / 1000000),
635 (current_cpu_data.memory_clock % 1000000)/10000);
637 printk("Module clock: %d.%02dMHz\n",
638 (current_cpu_data.module_clock / 1000000),
639 (current_cpu_data.module_clock % 1000000)/10000);
640 #if defined(CONFIG_SH_HS7751RVOIP) || defined(CONFIG_SH_RTS7751R2D)
641 interval = ((current_cpu_data.module_clock/4 + HZ/2) / HZ) - 1;
643 interval = (current_cpu_data.module_clock/4 + HZ/2) / HZ;
646 printk("Interval = %ld\n", interval);
649 ctrl_outb(0, TMU_TSTR);
650 #if !defined(CONFIG_CPU_SUBTYPE_SH7300)
651 ctrl_outb(TMU_TOCR_INIT, TMU_TOCR);
653 ctrl_outw(TMU0_TCR_INIT, TMU0_TCR);
654 ctrl_outl(interval, TMU0_TCOR);
655 ctrl_outl(interval, TMU0_TCNT);
656 ctrl_outb(TMU_TSTR_INIT, TMU_TSTR);
658 #if defined(CONFIG_SH_KGDB)
660 * Set up kgdb as requested. We do it here because the serial
661 * init uses the timer vars we just set up for figuring baud.