1 /* $Id: time.c,v 1.21 2004/04/21 00:09:15 lethal Exp $
3 * linux/arch/sh/kernel/time.c
5 * Copyright (C) 1999 Tetsuya Okada & Niibe Yutaka
6 * Copyright (C) 2000 Philipp Rumpf <prumpf@tux.org>
7 * Copyright (C) 2002, 2003, 2004 Paul Mundt
8 * Copyright (C) 2002 M. R. Brown <mrbrown@linux-sh.org>
10 * Some code taken from i386 version.
11 * Copyright (C) 1991, 1992, 1995 Linus Torvalds
14 #include <linux/config.h>
15 #include <linux/errno.h>
16 #include <linux/module.h>
17 #include <linux/sched.h>
18 #include <linux/kernel.h>
19 #include <linux/param.h>
20 #include <linux/string.h>
22 #include <linux/interrupt.h>
23 #include <linux/time.h>
24 #include <linux/delay.h>
25 #include <linux/init.h>
26 #include <linux/smp.h>
28 #include <asm/processor.h>
29 #include <asm/uaccess.h>
32 #include <asm/delay.h>
33 #include <asm/machvec.h>
40 #include <linux/timex.h>
41 #include <linux/irq.h>
43 #define TMU_TOCR_INIT 0x00
44 #define TMU0_TCR_INIT 0x0020
45 #define TMU_TSTR_INIT 1
47 #define TMU0_TCR_CALIB 0x0000
49 #if defined(CONFIG_CPU_SH3)
50 #if defined(CONFIG_CPU_SUBTYPE_SH7300)
51 #define TMU_TSTR 0xA412FE92 /* Byte access */
53 #define TMU0_TCOR 0xA412FE94 /* Long access */
54 #define TMU0_TCNT 0xA412FE98 /* Long access */
55 #define TMU0_TCR 0xA412FE9C /* Word access */
57 #define TMU1_TCOR 0xA412FEA0 /* Long access */
58 #define TMU1_TCNT 0xA412FEA4 /* Long access */
59 #define TMU1_TCR 0xA412FEA8 /* Word access */
61 #define FRQCR 0xA415FF80
63 #define TMU_TOCR 0xfffffe90 /* Byte access */
64 #define TMU_TSTR 0xfffffe92 /* Byte access */
66 #define TMU0_TCOR 0xfffffe94 /* Long access */
67 #define TMU0_TCNT 0xfffffe98 /* Long access */
68 #define TMU0_TCR 0xfffffe9c /* Word access */
70 #elif defined(CONFIG_CPU_SH4)
71 #define TMU_TOCR 0xffd80000 /* Byte access */
72 #define TMU_TSTR 0xffd80004 /* Byte access */
74 #define TMU0_TCOR 0xffd80008 /* Long access */
75 #define TMU0_TCNT 0xffd8000c /* Long access */
76 #define TMU0_TCR 0xffd80010 /* Word access */
78 #ifdef CONFIG_CPU_SUBTYPE_ST40STB1
79 #define CLOCKGEN_MEMCLKCR 0xbb040038
80 #define MEMCLKCR_RATIO_MASK 0x7
81 #endif /* CONFIG_CPU_SUBTYPE_ST40STB1 */
82 #endif /* CONFIG_CPU_SH3 or CONFIG_CPU_SH4 */
84 extern unsigned long wall_jiffies;
85 #define TICK_SIZE (tick_nsec / 1000)
86 spinlock_t tmu0_lock = SPIN_LOCK_UNLOCKED;
88 u64 jiffies_64 = INITIAL_JIFFIES;
90 EXPORT_SYMBOL(jiffies_64);
92 /* XXX: Can we initialize this in a routine somewhere? Dreamcast doesn't want
93 * these routines anywhere... */
95 void (*rtc_get_time)(struct timespec *) = sh_rtc_gettimeofday;
96 int (*rtc_set_time)(const time_t) = sh_rtc_settimeofday;
98 void (*rtc_get_time)(struct timespec *) = 0;
99 int (*rtc_set_time)(const time_t) = 0;
102 #if defined(CONFIG_CPU_SUBTYPE_SH7300)
103 static int md_table[] = { 1, 2, 3, 4, 6, 8, 12 };
105 #if defined(CONFIG_CPU_SH3)
106 static int stc_multipliers[] = { 1, 2, 3, 4, 6, 1, 1, 1 };
107 static int stc_values[] = { 0, 1, 4, 2, 5, 0, 0, 0 };
108 #define bfc_divisors stc_multipliers
109 #define bfc_values stc_values
110 static int ifc_divisors[] = { 1, 2, 3, 4, 1, 1, 1, 1 };
111 static int ifc_values[] = { 0, 1, 4, 2, 0, 0, 0, 0 };
112 static int pfc_divisors[] = { 1, 2, 3, 4, 6, 1, 1, 1 };
113 static int pfc_values[] = { 0, 1, 4, 2, 5, 0, 0, 0 };
114 #elif defined(CONFIG_CPU_SH4)
115 static int ifc_divisors[] = { 1, 2, 3, 4, 6, 8, 1, 1 };
116 static int ifc_values[] = { 0, 1, 2, 3, 0, 4, 0, 5 };
117 #define bfc_divisors ifc_divisors /* Same */
118 #define bfc_values ifc_values
119 static int pfc_divisors[] = { 2, 3, 4, 6, 8, 2, 2, 2 };
120 static int pfc_values[] = { 0, 0, 1, 2, 0, 3, 0, 4 };
122 #error "Unknown ifc/bfc/pfc/stc values for this processor"
126 * Scheduler clock - returns current time in nanosec units.
128 unsigned long long sched_clock(void)
130 return (unsigned long long)jiffies * (1000000000 / HZ);
133 static unsigned long do_gettimeoffset(void)
138 static int count_p = 0x7fffffff; /* for the first call after boot */
139 static unsigned long jiffies_p = 0;
142 * cache volatile jiffies temporarily; we have IRQs turned off.
144 unsigned long jiffies_t;
146 spin_lock_irqsave(&tmu0_lock, flags);
147 /* timer count may underflow right here */
148 count = ctrl_inl(TMU0_TCNT); /* read the latched count */
153 * avoiding timer inconsistencies (they are rare, but they happen)...
154 * there is one kind of problem that must be avoided here:
155 * 1. the timer counter underflows
158 if( jiffies_t == jiffies_p ) {
159 if( count > count_p ) {
162 if(ctrl_inw(TMU0_TCR) & 0x100) { /* Check UNF bit */
164 * We cannot detect lost timer interrupts ...
165 * well, that's why we call them lost, don't we? :)
166 * [hmm, on the Pentium and Alpha we can ... sort of]
170 printk("do_slow_gettimeoffset(): hardware timer problem?\n");
174 jiffies_p = jiffies_t;
177 spin_unlock_irqrestore(&tmu0_lock, flags);
179 count = ((LATCH-1) - count) * TICK_SIZE;
180 count = (count + LATCH/2) / LATCH;
185 void do_gettimeofday(struct timeval *tv)
188 unsigned long usec, sec;
192 seq = read_seqbegin(&xtime_lock);
193 usec = do_gettimeoffset();
195 lost = jiffies - wall_jiffies;
197 usec += lost * (1000000 / HZ);
200 usec += xtime.tv_nsec / 1000;
201 } while (read_seqretry(&xtime_lock, seq));
203 while (usec >= 1000000) {
212 EXPORT_SYMBOL(do_gettimeofday);
214 int do_settimeofday(struct timespec *tv)
216 time_t wtm_sec, sec = tv->tv_sec;
217 long wtm_nsec, nsec = tv->tv_nsec;
219 if ((unsigned long)tv->tv_nsec >= NSEC_PER_SEC)
222 write_seqlock_irq(&xtime_lock);
224 * This is revolting. We need to set "xtime" correctly. However, the
225 * value in this location is the value at the most recent update of
226 * wall time. Discover what correction gettimeofday() would have
227 * made, and then undo it!
229 nsec -= 1000 * (do_gettimeoffset() +
230 (jiffies - wall_jiffies) * (1000000 / HZ));
232 wtm_sec = wall_to_monotonic.tv_sec + (xtime.tv_sec - sec);
233 wtm_nsec = wall_to_monotonic.tv_nsec + (xtime.tv_nsec - nsec);
235 set_normalized_timespec(&xtime, sec, nsec);
236 set_normalized_timespec(&wall_to_monotonic, wtm_sec, wtm_nsec);
238 time_adjust = 0; /* stop active adjtime() */
239 time_status |= STA_UNSYNC;
240 time_maxerror = NTP_PHASE_LIMIT;
241 time_esterror = NTP_PHASE_LIMIT;
242 write_sequnlock_irq(&xtime_lock);
248 EXPORT_SYMBOL(do_settimeofday);
250 /* last time the RTC clock got updated */
251 static long last_rtc_update;
253 /* Profiling definitions */
254 extern unsigned long prof_cpu_mask;
255 extern unsigned int * prof_buffer;
256 extern unsigned long prof_len;
257 extern unsigned long prof_shift;
260 static inline void sh_do_profile(unsigned long pc)
262 /* Don't profile cpu_idle.. */
263 if (!prof_buffer || !current->pid)
266 if (pc >= 0xa0000000UL && pc < 0xc0000000UL)
269 pc -= (unsigned long)&_stext;
273 * Don't ignore out-of-bounds PC values silently,
274 * put them into the last histogram slot, so if
275 * present, they will show up as a sharp peak.
277 if (pc > prof_len - 1)
280 atomic_inc((atomic_t *)&prof_buffer[pc]);
284 * timer_interrupt() needs to keep up the real-time clock,
285 * as well as call the "do_timer()" routine every clocktick
287 static inline void do_timer_interrupt(int irq, void *dev_id, struct pt_regs *regs)
291 if (!user_mode(regs))
292 sh_do_profile(regs->pc);
294 #ifdef CONFIG_HEARTBEAT
295 if (sh_mv.mv_heartbeat != NULL)
296 sh_mv.mv_heartbeat();
300 * If we have an externally synchronized Linux clock, then update
301 * RTC clock accordingly every ~11 minutes. Set_rtc_mmss() has to be
302 * called as close as possible to 500 ms before the new second starts.
304 if ((time_status & STA_UNSYNC) == 0 &&
305 xtime.tv_sec > last_rtc_update + 660 &&
306 (xtime.tv_nsec / 1000) >= 500000 - ((unsigned) TICK_SIZE) / 2 &&
307 (xtime.tv_nsec / 1000) <= 500000 + ((unsigned) TICK_SIZE) / 2) {
308 if (rtc_set_time(xtime.tv_sec) == 0)
309 last_rtc_update = xtime.tv_sec;
311 last_rtc_update = xtime.tv_sec - 600; /* do it again in 60 s */
316 * This is the same as the above, except we _also_ save the current
317 * Time Stamp Counter value at the time of the timer interrupt, so that
318 * we later on can estimate the time of day more exactly.
320 static irqreturn_t timer_interrupt(int irq, void *dev_id, struct pt_regs *regs)
322 unsigned long timer_status;
325 timer_status = ctrl_inw(TMU0_TCR);
326 timer_status &= ~0x100;
327 ctrl_outw(timer_status, TMU0_TCR);
330 * Here we are in the timer irq handler. We just have irqs locally
331 * disabled but we don't know if the timer_bh is running on the other
332 * CPU. We need to avoid to SMP race with it. NOTE: we don' t need
333 * the irq version of write_lock because as just said we have irq
334 * locally disabled. -arca
336 write_seqlock(&xtime_lock);
337 do_timer_interrupt(irq, NULL, regs);
338 write_sequnlock(&xtime_lock);
344 * Hah! We'll see if this works (switching from usecs to nsecs).
346 static unsigned int __init get_timer_frequency(void)
349 struct timespec ts1, ts2;
350 unsigned long diff_nsec;
351 unsigned long factor;
353 /* Setup the timer: We don't want to generate interrupts, just
354 * have it count down at its natural rate.
356 ctrl_outb(0, TMU_TSTR);
357 #if !defined(CONFIG_CPU_SUBTYPE_SH7300)
358 ctrl_outb(TMU_TOCR_INIT, TMU_TOCR);
360 ctrl_outw(TMU0_TCR_CALIB, TMU0_TCR);
361 ctrl_outl(0xffffffff, TMU0_TCOR);
362 ctrl_outl(0xffffffff, TMU0_TCNT);
368 } while (ts1.tv_nsec == ts2.tv_nsec && ts1.tv_sec == ts2.tv_sec);
370 /* actually start the timer */
371 ctrl_outb(TMU_TSTR_INIT, TMU_TSTR);
375 } while (ts1.tv_nsec == ts2.tv_nsec && ts1.tv_sec == ts2.tv_sec);
377 freq = 0xffffffff - ctrl_inl(TMU0_TCNT);
378 if (ts2.tv_nsec < ts1.tv_nsec) {
379 ts2.tv_nsec += 1000000000;
383 diff_nsec = (ts2.tv_sec - ts1.tv_sec) * 1000000000 + (ts2.tv_nsec - ts1.tv_nsec);
385 /* this should work well if the RTC has a precision of n Hz, where
386 * n is an integer. I don't think we have to worry about the other
388 factor = (1000000000 + diff_nsec/2) / diff_nsec;
390 if (factor * diff_nsec > 1100000000 ||
391 factor * diff_nsec < 900000000)
392 panic("weird RTC (diff_nsec %ld)", diff_nsec);
394 return freq * factor;
397 void (*board_time_init)(void) = 0;
398 void (*board_timer_setup)(struct irqaction *irq) = 0;
400 static unsigned int sh_pclk_freq __initdata = CONFIG_SH_PCLK_FREQ;
402 static int __init sh_pclk_setup(char *str)
406 if (get_option(&str, &freq))
411 __setup("sh_pclk=", sh_pclk_setup);
413 static struct irqaction irq0 = { timer_interrupt, SA_INTERRUPT, CPU_MASK_NONE, "timer", NULL, NULL};
415 void get_current_frequency_divisors(unsigned int *ifc, unsigned int *bfc, unsigned int *pfc)
417 unsigned int frqcr = ctrl_inw(FRQCR);
419 #if defined(CONFIG_CPU_SH3)
420 #if defined(CONFIG_CPU_SUBTYPE_SH7300)
421 *ifc = md_table[((frqcr & 0x0070) >> 4)];
422 *bfc = md_table[((frqcr & 0x0700) >> 8)];
423 *pfc = md_table[frqcr & 0x0007];
424 #elif defined(CONFIG_CPU_SUBTYPE_SH7705)
425 *bfc = stc_multipliers[(frqcr & 0x0300) >> 8];
426 *ifc = ifc_divisors[(frqcr & 0x0030) >> 4];
427 *pfc = pfc_divisors[frqcr & 0x0003];
431 tmp = (frqcr & 0x8000) >> 13;
432 tmp |= (frqcr & 0x0030) >> 4;
433 *bfc = stc_multipliers[tmp];
434 tmp = (frqcr & 0x4000) >> 12;
435 tmp |= (frqcr & 0x000c) >> 2;
436 *ifc = ifc_divisors[tmp];
437 tmp = (frqcr & 0x2000) >> 11;
438 tmp |= frqcr & 0x0003;
439 *pfc = pfc_divisors[tmp];
441 #elif defined(CONFIG_CPU_SH4)
442 *ifc = ifc_divisors[(frqcr >> 6) & 0x0007];
443 *bfc = bfc_divisors[(frqcr >> 3) & 0x0007];
444 *pfc = pfc_divisors[frqcr & 0x0007];
449 * This bit of ugliness builds up accessor routines to get at both
450 * the divisors and the physical values.
452 #define _FREQ_TABLE(x) \
453 unsigned int get_##x##_divisor(unsigned int value) \
454 { return x##_divisors[value]; } \
456 unsigned int get_##x##_value(unsigned int divisor) \
457 { return x##_values[(divisor - 1)]; }
463 #ifdef CONFIG_CPU_SUBTYPE_ST40STB1
465 /* The ST40 divisors are totally different so we set the cpu data
466 ** clocks using a different algorithm
468 ** I've just plugged this from the 2.4 code - Alex Bennee <kernel-hacker@bennee.com>
470 #define CCN_PVR_CHIP_SHIFT 24
471 #define CCN_PVR_CHIP_MASK 0xff
472 #define CCN_PVR_CHIP_ST40STB1 0x4
476 unsigned short frqcr;
478 unsigned char multiplier;
479 unsigned char divisor;
483 static struct frqcr_data st40_frqcr_table[] = {
484 { 0x000, {{1,1}, {1,1}, {1,2}}},
485 { 0x002, {{1,1}, {1,1}, {1,4}}},
486 { 0x004, {{1,1}, {1,1}, {1,8}}},
487 { 0x008, {{1,1}, {1,2}, {1,2}}},
488 { 0x00A, {{1,1}, {1,2}, {1,4}}},
489 { 0x00C, {{1,1}, {1,2}, {1,8}}},
490 { 0x011, {{1,1}, {2,3}, {1,6}}},
491 { 0x013, {{1,1}, {2,3}, {1,3}}},
492 { 0x01A, {{1,1}, {1,2}, {1,4}}},
493 { 0x01C, {{1,1}, {1,2}, {1,8}}},
494 { 0x023, {{1,1}, {2,3}, {1,3}}},
495 { 0x02C, {{1,1}, {1,2}, {1,8}}},
496 { 0x048, {{1,2}, {1,2}, {1,4}}},
497 { 0x04A, {{1,2}, {1,2}, {1,6}}},
498 { 0x04C, {{1,2}, {1,2}, {1,8}}},
499 { 0x05A, {{1,2}, {1,3}, {1,6}}},
500 { 0x05C, {{1,2}, {1,3}, {1,6}}},
501 { 0x063, {{1,2}, {1,4}, {1,4}}},
502 { 0x06C, {{1,2}, {1,4}, {1,8}}},
503 { 0x091, {{1,3}, {1,3}, {1,6}}},
504 { 0x093, {{1,3}, {1,3}, {1,6}}},
505 { 0x0A3, {{1,3}, {1,6}, {1,6}}},
506 { 0x0DA, {{1,4}, {1,4}, {1,8}}},
507 { 0x0DC, {{1,4}, {1,4}, {1,8}}},
508 { 0x0EC, {{1,4}, {1,8}, {1,8}}},
509 { 0x123, {{1,4}, {1,4}, {1,8}}},
510 { 0x16C, {{1,4}, {1,8}, {1,8}}},
514 unsigned char multiplier;
515 unsigned char divisor;
517 static struct memclk_data st40_memclk_table[8] = {
528 static void st40_specific_time_init(unsigned int module_clock, unsigned short frqcr)
530 unsigned int cpu_clock, master_clock, bus_clock, memory_clock;
531 struct frqcr_data *d;
533 unsigned long memclkcr;
534 struct memclk_data *e;
536 for (a=0; a<ARRAY_SIZE(st40_frqcr_table); a++) {
537 d = &st40_frqcr_table[a];
538 if (d->frqcr == (frqcr & 0x1ff))
541 if (a == ARRAY_SIZE(st40_frqcr_table)) {
542 d = st40_frqcr_table;
543 printk("ERROR: Unrecognised FRQCR value (0x%x), using default multipliers\n",frqcr);
546 memclkcr = ctrl_inl(CLOCKGEN_MEMCLKCR);
547 e = &st40_memclk_table[memclkcr & MEMCLKCR_RATIO_MASK];
549 printk("Clock multipliers: CPU: %d/%d Bus: %d/%d Mem: %d/%d Periph: %d/%d\n",
550 d->factor[0].multiplier, d->factor[0].divisor,
551 d->factor[1].multiplier, d->factor[1].divisor,
552 e->multiplier, e->divisor,
553 d->factor[2].multiplier, d->factor[2].divisor);
555 master_clock = module_clock * d->factor[2].divisor / d->factor[2].multiplier;
556 bus_clock = master_clock * d->factor[1].multiplier / d->factor[1].divisor;
557 memory_clock = master_clock * e->multiplier / e->divisor;
558 cpu_clock = master_clock * d->factor[0].multiplier / d->factor[0].divisor;
560 current_cpu_data.cpu_clock = cpu_clock;
561 current_cpu_data.master_clock = master_clock;
562 current_cpu_data.bus_clock = bus_clock;
563 current_cpu_data.memory_clock = memory_clock;
564 current_cpu_data.module_clock = module_clock;
570 void __init time_init(void)
572 unsigned int timer_freq = 0;
573 unsigned int ifc, pfc, bfc;
574 unsigned long interval;
575 #ifdef CONFIG_CPU_SUBTYPE_ST40STB1
577 unsigned short frqcr;
585 * If we don't have an RTC (such as with the SH7300), don't attempt to
586 * probe the timer frequency. Rely on an either hardcoded peripheral
587 * clock value, or on the sh_pclk command line option. Note that we
588 * still need to have CONFIG_SH_PCLK_FREQ set in order for things like
589 * CLOCK_TICK_RATE to be sane.
591 current_cpu_data.module_clock = sh_pclk_freq;
593 #ifdef CONFIG_SH_PCLK_CALC
594 /* XXX: Switch this over to a more generic test. */
599 * If we've specified a peripheral clock frequency, and we have
600 * an RTC, compare it against the autodetected value. Complain
601 * if there's a mismatch.
603 * Note: We should allow for some high and low watermarks for
604 * the frequency here (compensating for potential drift), as
605 * otherwise we'll likely end up triggering this essentially
608 timer_freq = get_timer_frequency();
609 freq = timer_freq * 4;
611 if (sh_pclk_freq && (sh_pclk_freq/100*99 > freq || sh_pclk_freq/100*101 < freq)) {
612 printk(KERN_NOTICE "Calculated peripheral clock value "
613 "%d differs from sh_pclk value %d, fixing..\n",
615 current_cpu_data.module_clock = freq;
620 #ifdef CONFIG_CPU_SUBTYPE_ST40STB1
621 pvr = ctrl_inl(CCN_PVR);
622 frqcr = ctrl_inw(FRQCR);
623 printk("time.c ST40 Probe: PVR %08lx, FRQCR %04hx\n", pvr, frqcr);
624 if (((pvr >>CCN_PVR_CHIP_SHIFT) & CCN_PVR_CHIP_MASK) == CCN_PVR_CHIP_ST40STB1)
625 st40_specific_time_init(current_cpu_data.module_clock, frqcr);
628 get_current_frequency_divisors(&ifc, &bfc, &pfc);
631 rtc_get_time(&xtime);
633 xtime.tv_sec = mktime(2000, 1, 1, 0, 0, 0);
637 set_normalized_timespec(&wall_to_monotonic,
638 -xtime.tv_sec, -xtime.tv_nsec);
640 if (board_timer_setup) {
641 board_timer_setup(&irq0);
643 setup_irq(TIMER_IRQ, &irq0);
647 ** for ST40 chips the current_cpu_data should already be set
648 ** so not having valid pfc/bfc/ifc shouldn't be a problem
650 if (!current_cpu_data.master_clock)
651 current_cpu_data.master_clock = current_cpu_data.module_clock * pfc;
652 if (!current_cpu_data.bus_clock)
653 current_cpu_data.bus_clock = current_cpu_data.master_clock / bfc;
654 if (!current_cpu_data.cpu_clock)
655 current_cpu_data.cpu_clock = current_cpu_data.master_clock / ifc;
657 printk("CPU clock: %d.%02dMHz\n",
658 (current_cpu_data.cpu_clock / 1000000),
659 (current_cpu_data.cpu_clock % 1000000)/10000);
660 printk("Bus clock: %d.%02dMHz\n",
661 (current_cpu_data.bus_clock / 1000000),
662 (current_cpu_data.bus_clock % 1000000)/10000);
663 #ifdef CONFIG_CPU_SUBTYPE_ST40STB1
664 printk("Memory clock: %d.%02dMHz\n",
665 (current_cpu_data.memory_clock / 1000000),
666 (current_cpu_data.memory_clock % 1000000)/10000);
668 printk("Module clock: %d.%02dMHz\n",
669 (current_cpu_data.module_clock / 1000000),
670 (current_cpu_data.module_clock % 1000000)/10000);
671 #if defined(CONFIG_SH_HS7751RVOIP) || defined(CONFIG_SH_RTS7751R2D)
672 interval = ((current_cpu_data.module_clock/4 + HZ/2) / HZ) - 1;
674 interval = (current_cpu_data.module_clock/4 + HZ/2) / HZ;
677 printk("Interval = %ld\n", interval);
680 ctrl_outb(0, TMU_TSTR);
681 #if !defined(CONFIG_CPU_SUBTYPE_SH7300)
682 ctrl_outb(TMU_TOCR_INIT, TMU_TOCR);
684 ctrl_outw(TMU0_TCR_INIT, TMU0_TCR);
685 ctrl_outl(interval, TMU0_TCOR);
686 ctrl_outl(interval, TMU0_TCNT);
687 ctrl_outb(TMU_TSTR_INIT, TMU_TSTR);
689 #if defined(CONFIG_SH_KGDB)
691 * Set up kgdb as requested. We do it here because the serial
692 * init uses the timer vars we just set up for figuring baud.