1 /* $Id: cache-sh4.c,v 1.26 2004/02/19 12:47:24 lethal Exp $
3 * linux/arch/sh/mm/cache-sh4.c
5 * Copyright (C) 1999, 2000, 2002 Niibe Yutaka
6 * Copyright (C) 2001, 2002, 2003, 2004 Paul Mundt
7 * Copyright (C) 2003 Richard Curnow
10 #include <linux/config.h>
11 #include <linux/init.h>
12 #include <linux/mman.h>
14 #include <linux/threads.h>
15 #include <asm/addrspace.h>
17 #include <asm/pgtable.h>
18 #include <asm/processor.h>
19 #include <asm/cache.h>
21 #include <asm/uaccess.h>
22 #include <asm/pgalloc.h>
23 #include <asm/mmu_context.h>
24 #include <asm/cacheflush.h>
26 extern void __flush_cache_4096_all(unsigned long start);
27 static void __flush_cache_4096_all_ex(unsigned long start);
28 extern void __flush_dcache_all(void);
29 static void __flush_dcache_all_ex(void);
31 int __init detect_cpu_and_cache_system(void)
33 unsigned long pvr, prr, cvr;
36 static unsigned long sizes[16] = {
44 pvr = (ctrl_inl(CCN_PVR) >> 8) & 0xffff;
45 prr = (ctrl_inl(CCN_PRR) >> 4) & 0xff;
46 cvr = (ctrl_inl(CCN_CVR));
49 * Setup some sane SH-4 defaults for the icache
51 cpu_data->icache.way_incr = (1 << 13);
52 cpu_data->icache.entry_shift = 5;
53 cpu_data->icache.entry_mask = 0x1fe0;
54 cpu_data->icache.sets = 256;
55 cpu_data->icache.ways = 1;
56 cpu_data->icache.linesz = L1_CACHE_BYTES;
59 * And again for the dcache ..
61 cpu_data->dcache.way_incr = (1 << 14);
62 cpu_data->dcache.entry_shift = 5;
63 cpu_data->dcache.entry_mask = 0x3fe0;
64 cpu_data->dcache.sets = 512;
65 cpu_data->dcache.ways = 1;
66 cpu_data->dcache.linesz = L1_CACHE_BYTES;
68 /* Set the FPU flag, virtually all SH-4's have one */
69 cpu_data->flags |= CPU_HAS_FPU;
72 * Probe the underlying processor version/revision and
73 * adjust cpu_data setup accordingly.
77 cpu_data->type = CPU_SH7750;
78 cpu_data->flags |= CPU_HAS_P2_FLUSH_BUG;
81 cpu_data->type = CPU_SH7750S;
84 * FIXME: This is needed for 7750, but do we need it for the
85 * 7750S too? For now, assume we do.. -- PFM
87 cpu_data->flags |= CPU_HAS_P2_FLUSH_BUG;
91 cpu_data->type = CPU_SH7751;
94 cpu_data->type = CPU_ST40RA;
97 cpu_data->type = CPU_ST40GX1;
100 cpu_data->type = CPU_SH4_501;
101 cpu_data->icache.ways = 2;
102 cpu_data->dcache.ways = 2;
104 /* No FPU on the SH4-500 series.. */
105 cpu_data->flags &= ~CPU_HAS_FPU;
108 cpu_data->type = CPU_SH4_202;
109 cpu_data->icache.ways = 2;
110 cpu_data->dcache.ways = 2;
112 case 0x500 ... 0x501:
114 case 0x10: cpu_data->type = CPU_SH7750R; break;
115 case 0x11: cpu_data->type = CPU_SH7751R; break;
116 case 0x50: cpu_data->type = CPU_SH7760; break;
119 cpu_data->icache.ways = 2;
120 cpu_data->dcache.ways = 2;
124 cpu_data->type = CPU_SH_NONE;
129 * On anything that's not a direct-mapped cache, look to the CVR
130 * for I/D-cache specifics.
132 if (cpu_data->icache.ways > 1) {
133 size = sizes[(cvr >> 20) & 0xf];
134 cpu_data->icache.way_incr = size / cpu_data->icache.ways;
135 cpu_data->icache.sets = (size >> 6);
136 cpu_data->icache.entry_mask =
137 ((size / cpu_data->icache.ways) - (1 << 5));
140 if (cpu_data->dcache.ways > 1) {
141 size = sizes[(cvr >> 16) & 0xf];
142 cpu_data->dcache.way_incr = size / cpu_data->dcache.ways;
143 cpu_data->dcache.sets = (size >> 6);
144 cpu_data->dcache.entry_mask =
145 ((size / cpu_data->dcache.ways) - (1 << 5));
152 * SH-4 has virtually indexed and physically tagged cache.
155 struct semaphore p3map_sem[4];
157 void __init p3_cache_init(void)
159 if (remap_area_pages(P3SEG, 0, PAGE_SIZE*4, _PAGE_CACHABLE))
160 panic("%s failed.", __FUNCTION__);
162 sema_init (&p3map_sem[0], 1);
163 sema_init (&p3map_sem[1], 1);
164 sema_init (&p3map_sem[2], 1);
165 sema_init (&p3map_sem[3], 1);
169 * Write back the dirty D-caches, but not invalidate them.
171 * START: Virtual Address (U0, P1, or P3)
172 * SIZE: Size of the region.
174 void __flush_wback_region(void *start, int size)
177 unsigned long begin, end;
179 begin = (unsigned long)start & ~(L1_CACHE_BYTES-1);
180 end = ((unsigned long)start + size + L1_CACHE_BYTES-1)
181 & ~(L1_CACHE_BYTES-1);
182 for (v = begin; v < end; v+=L1_CACHE_BYTES) {
183 asm volatile("ocbwb %0"
190 * Write back the dirty D-caches and invalidate them.
192 * START: Virtual Address (U0, P1, or P3)
193 * SIZE: Size of the region.
195 void __flush_purge_region(void *start, int size)
198 unsigned long begin, end;
200 begin = (unsigned long)start & ~(L1_CACHE_BYTES-1);
201 end = ((unsigned long)start + size + L1_CACHE_BYTES-1)
202 & ~(L1_CACHE_BYTES-1);
203 for (v = begin; v < end; v+=L1_CACHE_BYTES) {
204 asm volatile("ocbp %0"
212 * No write back please
214 void __flush_invalidate_region(void *start, int size)
217 unsigned long begin, end;
219 begin = (unsigned long)start & ~(L1_CACHE_BYTES-1);
220 end = ((unsigned long)start + size + L1_CACHE_BYTES-1)
221 & ~(L1_CACHE_BYTES-1);
222 for (v = begin; v < end; v+=L1_CACHE_BYTES) {
223 asm volatile("ocbi %0"
229 static void __flush_dcache_all_ex(void)
231 unsigned long addr, end_addr, entry_offset;
233 end_addr = CACHE_OC_ADDRESS_ARRAY + (cpu_data->dcache.sets << cpu_data->dcache.entry_shift) * cpu_data->dcache.ways;
234 entry_offset = 1 << cpu_data->dcache.entry_shift;
235 for (addr = CACHE_OC_ADDRESS_ARRAY; addr < end_addr; addr += entry_offset) {
240 static void __flush_cache_4096_all_ex(unsigned long start)
242 unsigned long addr, entry_offset;
245 entry_offset = 1 << cpu_data->dcache.entry_shift;
246 for (i = 0; i < cpu_data->dcache.ways; i++, start += cpu_data->dcache.way_incr) {
247 for (addr = CACHE_OC_ADDRESS_ARRAY + start;
248 addr < CACHE_OC_ADDRESS_ARRAY + 4096 + start;
249 addr += entry_offset) {
255 void flush_cache_4096_all(unsigned long start)
257 if (cpu_data->dcache.ways == 1)
258 __flush_cache_4096_all(start);
260 __flush_cache_4096_all_ex(start);
264 * Write back the range of D-cache, and purge the I-cache.
266 * Called from kernel/module.c:sys_init_module and routine for a.out format.
268 void flush_icache_range(unsigned long start, unsigned long end)
274 * Write back the D-cache and purge the I-cache for signal trampoline.
275 * .. which happens to be the same behavior as flush_icache_range().
276 * So, we simply flush out a line.
278 void flush_cache_sigtramp(unsigned long addr)
280 unsigned long v, index;
284 v = addr & ~(L1_CACHE_BYTES-1);
285 asm volatile("ocbwb %0"
289 index = CACHE_IC_ADDRESS_ARRAY | (v & cpu_data->icache.entry_mask);
291 local_irq_save(flags);
293 for(i = 0; i < cpu_data->icache.ways; i++, index += cpu_data->icache.way_incr)
294 ctrl_outl(0, index); /* Clear out Valid-bit */
296 local_irq_restore(flags);
299 static inline void flush_cache_4096(unsigned long start,
303 extern void __flush_cache_4096(unsigned long addr, unsigned long phys, unsigned long exec_offset);
306 * SH7751, SH7751R, and ST40 have no restriction to handle cache.
307 * (While SH7750 must do that at P2 area.)
309 if ((cpu_data->flags & CPU_HAS_P2_FLUSH_BUG)
310 || start < CACHE_OC_ADDRESS_ARRAY) {
311 local_irq_save(flags);
312 __flush_cache_4096(start | SH_CACHE_ASSOC, P1SEGADDR(phys), 0x20000000);
313 local_irq_restore(flags);
315 __flush_cache_4096(start | SH_CACHE_ASSOC, P1SEGADDR(phys), 0);
320 * Write back & invalidate the D-cache of the page.
321 * (To avoid "alias" issues)
323 void flush_dcache_page(struct page *page)
325 if (test_bit(PG_mapped, &page->flags)) {
326 unsigned long phys = PHYSADDR(page_address(page));
328 /* Loop all the D-cache */
329 flush_cache_4096(CACHE_OC_ADDRESS_ARRAY, phys);
330 flush_cache_4096(CACHE_OC_ADDRESS_ARRAY | 0x1000, phys);
331 flush_cache_4096(CACHE_OC_ADDRESS_ARRAY | 0x2000, phys);
332 flush_cache_4096(CACHE_OC_ADDRESS_ARRAY | 0x3000, phys);
336 static inline void flush_icache_all(void)
338 unsigned long flags, ccr;
340 local_irq_save(flags);
345 ccr |= CCR_CACHE_ICI;
349 local_irq_restore(flags);
352 void flush_cache_all(void)
354 if (cpu_data->dcache.ways == 1)
355 __flush_dcache_all();
357 __flush_dcache_all_ex();
361 void flush_cache_mm(struct mm_struct *mm)
363 /* Is there any good way? */
364 /* XXX: possibly call flush_cache_range for each vm area */
366 * FIXME: Really, the optimal solution here would be able to flush out
367 * individual lines created by the specified context, but this isn't
368 * feasible for a number of architectures (such as MIPS, and some
369 * SPARC) .. is this possible for SuperH?
371 * In the meantime, we'll just flush all of the caches.. this
372 * seems to be the simplest way to avoid at least a few wasted
373 * cache flushes. -Lethal
378 static void __flush_cache_page(struct vm_area_struct *vma,
379 unsigned long address,
382 /* We only need to flush D-cache when we have alias */
383 if ((address^phys) & CACHE_ALIAS) {
384 /* Loop 4K of the D-cache */
386 CACHE_OC_ADDRESS_ARRAY | (address & CACHE_ALIAS),
388 /* Loop another 4K of the D-cache */
390 CACHE_OC_ADDRESS_ARRAY | (phys & CACHE_ALIAS),
394 if (vma->vm_flags & VM_EXEC)
395 /* Loop 4K (half) of the I-cache */
397 CACHE_IC_ADDRESS_ARRAY | (address & 0x1000),
402 * Write back and invalidate D-caches.
404 * START, END: Virtual Address (U0 address)
406 * NOTE: We need to flush the _physical_ page entry.
407 * Flushing the cache lines for U0 only isn't enough.
408 * We need to flush for P1 too, which may contain aliases.
410 void flush_cache_range(struct vm_area_struct *vma, unsigned long start,
413 unsigned long p = start & PAGE_MASK;
421 dir = pgd_offset(vma->vm_mm, p);
422 pmd = pmd_offset(dir, p);
425 if (pmd_none(*pmd) || pmd_bad(*pmd)) {
426 p &= ~((1 << PMD_SHIFT) -1);
427 p += (1 << PMD_SHIFT);
431 pte = pte_offset_kernel(pmd, p);
434 if ((pte_val(entry) & _PAGE_PRESENT)) {
435 phys = pte_val(entry)&PTE_PHYS_MASK;
436 if ((p^phys) & CACHE_ALIAS) {
437 d |= 1 << ((p & CACHE_ALIAS)>>12);
438 d |= 1 << ((phys & CACHE_ALIAS)>>12);
445 } while (p < end && ((unsigned long)pte & ~PAGE_MASK));
450 flush_cache_4096_all(0);
452 flush_cache_4096_all(0x1000);
454 flush_cache_4096_all(0x2000);
456 flush_cache_4096_all(0x3000);
457 if (vma->vm_flags & VM_EXEC)
462 * Write back and invalidate I/D-caches for the page.
464 * ADDR: Virtual Address (U0 address)
466 void flush_cache_page(struct vm_area_struct *vma, unsigned long address)
474 dir = pgd_offset(vma->vm_mm, address);
475 pmd = pmd_offset(dir, address);
476 if (pmd_none(*pmd) || pmd_bad(*pmd))
478 pte = pte_offset_kernel(pmd, address);
480 if (!(pte_val(entry) & _PAGE_PRESENT))
483 phys = pte_val(entry)&PTE_PHYS_MASK;
484 __flush_cache_page(vma, address, phys);
488 * flush_icache_user_range
489 * @vma: VMA of the process
492 * @len: length of the range (< page size)
494 void flush_icache_user_range(struct vm_area_struct *vma,
495 struct page *page, unsigned long addr, int len)
497 __flush_cache_page(vma, addr, PHYSADDR(page_address(page)));