2 * srmmu.c: SRMMU specific routines for memory management.
4 * Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu)
5 * Copyright (C) 1995,2002 Pete Zaitcev (zaitcev@yahoo.com)
6 * Copyright (C) 1996 Eddie C. Dost (ecd@skynet.be)
7 * Copyright (C) 1997,1998 Jakub Jelinek (jj@sunsite.mff.cuni.cz)
8 * Copyright (C) 1999,2000 Anton Blanchard (anton@samba.org)
11 #include <linux/config.h>
12 #include <linux/kernel.h>
14 #include <linux/slab.h>
15 #include <linux/vmalloc.h>
16 #include <linux/pagemap.h>
17 #include <linux/init.h>
18 #include <linux/spinlock.h>
19 #include <linux/bootmem.h>
21 #include <linux/seq_file.h>
23 #include <asm/bitext.h>
25 #include <asm/pgalloc.h>
26 #include <asm/pgtable.h>
28 #include <asm/kdebug.h>
29 #include <asm/vaddrs.h>
30 #include <asm/traps.h>
33 #include <asm/cache.h>
34 #include <asm/oplib.h>
38 #include <asm/a.out.h>
39 #include <asm/mmu_context.h>
40 #include <asm/io-unit.h>
41 #include <asm/cacheflush.h>
42 #include <asm/tlbflush.h>
44 /* Now the cpu specific definitions. */
45 #include <asm/viking.h>
48 #include <asm/tsunami.h>
49 #include <asm/swift.h>
50 #include <asm/turbosparc.h>
52 #include <asm/btfixup.h>
54 enum mbus_module srmmu_modtype;
55 unsigned int hwbug_bitmask;
59 extern struct resource sparc_iomap;
61 extern unsigned long last_valid_pfn;
63 extern unsigned long page_kernel;
65 pgd_t *srmmu_swapper_pg_dir;
68 #define FLUSH_BEGIN(mm)
71 #define FLUSH_BEGIN(mm) if((mm)->context != NO_CONTEXT) {
75 BTFIXUPDEF_CALL(void, flush_page_for_dma, unsigned long)
76 #define flush_page_for_dma(page) BTFIXUP_CALL(flush_page_for_dma)(page)
78 int flush_page_for_dma_global = 1;
81 BTFIXUPDEF_CALL(void, local_flush_page_for_dma, unsigned long)
82 #define local_flush_page_for_dma(page) BTFIXUP_CALL(local_flush_page_for_dma)(page)
87 ctxd_t *srmmu_ctx_table_phys;
88 ctxd_t *srmmu_context_table;
90 int viking_mxcc_present;
91 static spinlock_t srmmu_context_spinlock = SPIN_LOCK_UNLOCKED;
96 * In general all page table modifications should use the V8 atomic
97 * swap instruction. This insures the mmu and the cpu are in sync
98 * with respect to ref/mod bits in the page tables.
100 static inline unsigned long srmmu_swap(unsigned long *addr, unsigned long value)
102 __asm__ __volatile__("swap [%2], %0" : "=&r" (value) : "0" (value), "r" (addr));
106 static inline void srmmu_set_pte(pte_t *ptep, pte_t pteval)
108 srmmu_swap((unsigned long *)ptep, pte_val(pteval));
111 /* The very generic SRMMU page table operations. */
112 static inline int srmmu_device_memory(unsigned long x)
114 return ((x & 0xF0000000) != 0);
117 int srmmu_cache_pagetables;
119 /* these will be initialized in srmmu_nocache_calcsize() */
120 unsigned long srmmu_nocache_size;
121 unsigned long srmmu_nocache_end;
123 /* 1 bit <=> 256 bytes of nocache <=> 64 PTEs */
124 #define SRMMU_NOCACHE_BITMAP_SHIFT (PAGE_SHIFT - 4)
126 /* The context table is a nocache user with the biggest alignment needs. */
127 #define SRMMU_NOCACHE_ALIGN_MAX (sizeof(ctxd_t)*SRMMU_MAX_CONTEXTS)
129 void *srmmu_nocache_pool;
130 void *srmmu_nocache_bitmap;
131 static struct bit_map srmmu_nocache_map;
133 static unsigned long srmmu_pte_pfn(pte_t pte)
135 if (srmmu_device_memory(pte_val(pte))) {
136 /* XXX Anton obviously had something in mind when he did this.
139 /* return (struct page *)~0; */
142 return (pte_val(pte) & SRMMU_PTE_PMASK) >> (PAGE_SHIFT-4);
145 static struct page *srmmu_pmd_page(pmd_t pmd)
148 if (srmmu_device_memory(pmd_val(pmd)))
150 return pfn_to_page((pmd_val(pmd) & SRMMU_PTD_PMASK) >> (PAGE_SHIFT-4));
153 static inline unsigned long srmmu_pgd_page(pgd_t pgd)
154 { return srmmu_device_memory(pgd_val(pgd))?~0:(unsigned long)__nocache_va((pgd_val(pgd) & SRMMU_PTD_PMASK) << 4); }
157 static inline int srmmu_pte_none(pte_t pte)
158 { return !(pte_val(pte) & 0xFFFFFFF); }
160 static inline int srmmu_pte_present(pte_t pte)
161 { return ((pte_val(pte) & SRMMU_ET_MASK) == SRMMU_ET_PTE); }
163 static inline void srmmu_pte_clear(pte_t *ptep)
164 { srmmu_set_pte(ptep, __pte(0)); }
166 static inline int srmmu_pmd_none(pmd_t pmd)
167 { return !(pmd_val(pmd) & 0xFFFFFFF); }
169 static inline int srmmu_pmd_bad(pmd_t pmd)
170 { return (pmd_val(pmd) & SRMMU_ET_MASK) != SRMMU_ET_PTD; }
172 static inline int srmmu_pmd_present(pmd_t pmd)
173 { return ((pmd_val(pmd) & SRMMU_ET_MASK) == SRMMU_ET_PTD); }
175 static inline void srmmu_pmd_clear(pmd_t *pmdp) {
177 for (i = 0; i < PTRS_PER_PTE/SRMMU_REAL_PTRS_PER_PTE; i++)
178 srmmu_set_pte((pte_t *)&pmdp->pmdv[i], __pte(0));
181 static inline int srmmu_pgd_none(pgd_t pgd)
182 { return !(pgd_val(pgd) & 0xFFFFFFF); }
184 static inline int srmmu_pgd_bad(pgd_t pgd)
185 { return (pgd_val(pgd) & SRMMU_ET_MASK) != SRMMU_ET_PTD; }
187 static inline int srmmu_pgd_present(pgd_t pgd)
188 { return ((pgd_val(pgd) & SRMMU_ET_MASK) == SRMMU_ET_PTD); }
190 static inline void srmmu_pgd_clear(pgd_t * pgdp)
191 { srmmu_set_pte((pte_t *)pgdp, __pte(0)); }
193 static inline pte_t srmmu_pte_wrprotect(pte_t pte)
194 { return __pte(pte_val(pte) & ~SRMMU_WRITE);}
196 static inline pte_t srmmu_pte_mkclean(pte_t pte)
197 { return __pte(pte_val(pte) & ~SRMMU_DIRTY);}
199 static inline pte_t srmmu_pte_mkold(pte_t pte)
200 { return __pte(pte_val(pte) & ~SRMMU_REF);}
202 static inline pte_t srmmu_pte_mkwrite(pte_t pte)
203 { return __pte(pte_val(pte) | SRMMU_WRITE);}
205 static inline pte_t srmmu_pte_mkdirty(pte_t pte)
206 { return __pte(pte_val(pte) | SRMMU_DIRTY);}
208 static inline pte_t srmmu_pte_mkyoung(pte_t pte)
209 { return __pte(pte_val(pte) | SRMMU_REF);}
212 * Conversion functions: convert a page and protection to a page entry,
213 * and a page entry and page directory to the page they refer to.
215 static pte_t srmmu_mk_pte(struct page *page, pgprot_t pgprot)
216 { return __pte((page_to_pfn(page) << (PAGE_SHIFT-4)) | pgprot_val(pgprot)); }
218 static pte_t srmmu_mk_pte_phys(unsigned long page, pgprot_t pgprot)
219 { return __pte(((page) >> 4) | pgprot_val(pgprot)); }
221 static pte_t srmmu_mk_pte_io(unsigned long page, pgprot_t pgprot, int space)
222 { return __pte(((page) >> 4) | (space << 28) | pgprot_val(pgprot)); }
224 /* XXX should we hyper_flush_whole_icache here - Anton */
225 static inline void srmmu_ctxd_set(ctxd_t *ctxp, pgd_t *pgdp)
226 { srmmu_set_pte((pte_t *)ctxp, (SRMMU_ET_PTD | (__nocache_pa((unsigned long) pgdp) >> 4))); }
228 static inline void srmmu_pgd_set(pgd_t * pgdp, pmd_t * pmdp)
229 { srmmu_set_pte((pte_t *)pgdp, (SRMMU_ET_PTD | (__nocache_pa((unsigned long) pmdp) >> 4))); }
231 static void srmmu_pmd_set(pmd_t *pmdp, pte_t *ptep)
233 unsigned long ptp; /* Physical address, shifted right by 4 */
236 ptp = __nocache_pa((unsigned long) ptep) >> 4;
237 for (i = 0; i < PTRS_PER_PTE/SRMMU_REAL_PTRS_PER_PTE; i++) {
238 srmmu_set_pte((pte_t *)&pmdp->pmdv[i], SRMMU_ET_PTD | ptp);
239 ptp += (SRMMU_REAL_PTRS_PER_PTE*sizeof(pte_t) >> 4);
243 static void srmmu_pmd_populate(pmd_t *pmdp, struct page *ptep)
245 unsigned long ptp; /* Physical address, shifted right by 4 */
248 ptp = page_to_pfn(ptep) << (PAGE_SHIFT-4); /* watch for overflow */
249 for (i = 0; i < PTRS_PER_PTE/SRMMU_REAL_PTRS_PER_PTE; i++) {
250 srmmu_set_pte((pte_t *)&pmdp->pmdv[i], SRMMU_ET_PTD | ptp);
251 ptp += (SRMMU_REAL_PTRS_PER_PTE*sizeof(pte_t) >> 4);
255 static inline pte_t srmmu_pte_modify(pte_t pte, pgprot_t newprot)
256 { return __pte((pte_val(pte) & SRMMU_CHG_MASK) | pgprot_val(newprot)); }
258 /* to find an entry in a top-level page table... */
259 extern inline pgd_t *srmmu_pgd_offset(struct mm_struct * mm, unsigned long address)
260 { return mm->pgd + (address >> SRMMU_PGDIR_SHIFT); }
262 /* Find an entry in the second-level page table.. */
263 static inline pmd_t *srmmu_pmd_offset(pgd_t * dir, unsigned long address)
265 return (pmd_t *) srmmu_pgd_page(*dir) +
266 ((address >> PMD_SHIFT) & (PTRS_PER_PMD - 1));
269 /* Find an entry in the third-level page table.. */
270 static inline pte_t *srmmu_pte_offset(pmd_t * dir, unsigned long address)
274 pte = __nocache_va((dir->pmdv[0] & SRMMU_PTD_PMASK) << 4);
275 return (pte_t *) pte +
276 ((address >> PAGE_SHIFT) & (PTRS_PER_PTE - 1));
279 static unsigned long srmmu_swp_type(swp_entry_t entry)
281 return (entry.val >> SRMMU_SWP_TYPE_SHIFT) & SRMMU_SWP_TYPE_MASK;
284 static unsigned long srmmu_swp_offset(swp_entry_t entry)
286 return (entry.val >> SRMMU_SWP_OFF_SHIFT) & SRMMU_SWP_OFF_MASK;
289 static swp_entry_t srmmu_swp_entry(unsigned long type, unsigned long offset)
291 return (swp_entry_t) {
292 (type & SRMMU_SWP_TYPE_MASK) << SRMMU_SWP_TYPE_SHIFT
293 | (offset & SRMMU_SWP_OFF_MASK) << SRMMU_SWP_OFF_SHIFT };
297 * size: bytes to allocate in the nocache area.
298 * align: bytes, number to align at.
299 * Returns the virtual address of the allocated area.
301 static unsigned long __srmmu_get_nocache(int size, int align)
305 if (size < SRMMU_NOCACHE_BITMAP_SHIFT) {
306 printk("Size 0x%x too small for nocache request\n", size);
307 size = SRMMU_NOCACHE_BITMAP_SHIFT;
309 if (size & (SRMMU_NOCACHE_BITMAP_SHIFT-1)) {
310 printk("Size 0x%x unaligned int nocache request\n", size);
311 size += SRMMU_NOCACHE_BITMAP_SHIFT-1;
313 BUG_ON(align > SRMMU_NOCACHE_ALIGN_MAX);
315 offset = bit_map_string_get(&srmmu_nocache_map,
316 size >> SRMMU_NOCACHE_BITMAP_SHIFT,
317 align >> SRMMU_NOCACHE_BITMAP_SHIFT);
319 printk("srmmu: out of nocache %d: %d/%d\n",
320 size, (int) srmmu_nocache_size,
321 srmmu_nocache_map.used << SRMMU_NOCACHE_BITMAP_SHIFT);
325 return (SRMMU_NOCACHE_VADDR + (offset << SRMMU_NOCACHE_BITMAP_SHIFT));
328 unsigned inline long srmmu_get_nocache(int size, int align)
332 tmp = __srmmu_get_nocache(size, align);
335 memset((void *)tmp, 0, size);
340 void srmmu_free_nocache(unsigned long vaddr, int size)
344 if (vaddr < SRMMU_NOCACHE_VADDR) {
345 printk("Vaddr %lx is smaller than nocache base 0x%lx\n",
346 vaddr, (unsigned long)SRMMU_NOCACHE_VADDR);
349 if (vaddr+size > srmmu_nocache_end) {
350 printk("Vaddr %lx is bigger than nocache end 0x%lx\n",
351 vaddr, srmmu_nocache_end);
354 if (size & (size-1)) {
355 printk("Size 0x%x is not a power of 2\n", size);
358 if (size < SRMMU_NOCACHE_BITMAP_SHIFT) {
359 printk("Size 0x%x is too small\n", size);
362 if (vaddr & (size-1)) {
363 printk("Vaddr %lx is not aligned to size 0x%x\n", vaddr, size);
367 offset = (vaddr - SRMMU_NOCACHE_VADDR) >> SRMMU_NOCACHE_BITMAP_SHIFT;
368 size = size >> SRMMU_NOCACHE_BITMAP_SHIFT;
370 bit_map_clear(&srmmu_nocache_map, offset, size);
373 void srmmu_early_allocate_ptable_skeleton(unsigned long start, unsigned long end);
375 extern unsigned long probe_memory(void); /* in fault.c */
378 * Reserve nocache dynamically proportionally to the amount of
379 * system RAM. -- Tomas Szepe <szepe@pinerecords.com>, June 2002
381 void srmmu_nocache_calcsize(void)
383 unsigned long sysmemavail = probe_memory() / 1024;
384 int srmmu_nocache_npages;
386 srmmu_nocache_npages =
387 sysmemavail / SRMMU_NOCACHE_ALCRATIO / 1024 * 256;
389 /* P3 XXX The 4x overuse: corroborated by /proc/meminfo. */
390 // if (srmmu_nocache_npages < 256) srmmu_nocache_npages = 256;
391 if (srmmu_nocache_npages < SRMMU_MIN_NOCACHE_PAGES)
392 srmmu_nocache_npages = SRMMU_MIN_NOCACHE_PAGES;
394 /* anything above 1280 blows up */
395 if (srmmu_nocache_npages > SRMMU_MAX_NOCACHE_PAGES)
396 srmmu_nocache_npages = SRMMU_MAX_NOCACHE_PAGES;
398 srmmu_nocache_size = srmmu_nocache_npages * PAGE_SIZE;
399 srmmu_nocache_end = SRMMU_NOCACHE_VADDR + srmmu_nocache_size;
402 void srmmu_nocache_init(void)
404 unsigned int bitmap_bits;
408 unsigned long paddr, vaddr;
409 unsigned long pteval;
411 bitmap_bits = srmmu_nocache_size >> SRMMU_NOCACHE_BITMAP_SHIFT;
413 srmmu_nocache_pool = __alloc_bootmem(srmmu_nocache_size,
414 SRMMU_NOCACHE_ALIGN_MAX, 0UL);
415 memset(srmmu_nocache_pool, 0, srmmu_nocache_size);
417 srmmu_nocache_bitmap = __alloc_bootmem(bitmap_bits >> 3, SMP_CACHE_BYTES, 0UL);
418 bit_map_init(&srmmu_nocache_map, srmmu_nocache_bitmap, bitmap_bits);
420 srmmu_swapper_pg_dir = (pgd_t *)__srmmu_get_nocache(SRMMU_PGD_TABLE_SIZE, SRMMU_PGD_TABLE_SIZE);
421 memset(__nocache_fix(srmmu_swapper_pg_dir), 0, SRMMU_PGD_TABLE_SIZE);
422 init_mm.pgd = srmmu_swapper_pg_dir;
424 srmmu_early_allocate_ptable_skeleton(SRMMU_NOCACHE_VADDR, srmmu_nocache_end);
426 paddr = __pa((unsigned long)srmmu_nocache_pool);
427 vaddr = SRMMU_NOCACHE_VADDR;
429 while (vaddr < srmmu_nocache_end) {
430 pgd = pgd_offset_k(vaddr);
431 pmd = srmmu_pmd_offset(__nocache_fix(pgd), vaddr);
432 pte = srmmu_pte_offset(__nocache_fix(pmd), vaddr);
434 pteval = ((paddr >> 4) | SRMMU_ET_PTE | SRMMU_PRIV);
436 if (srmmu_cache_pagetables)
437 pteval |= SRMMU_CACHE;
439 srmmu_set_pte(__nocache_fix(pte), __pte(pteval));
449 static inline pgd_t *srmmu_get_pgd_fast(void)
453 pgd = (pgd_t *)__srmmu_get_nocache(SRMMU_PGD_TABLE_SIZE, SRMMU_PGD_TABLE_SIZE);
455 pgd_t *init = pgd_offset_k(0);
456 memset(pgd, 0, USER_PTRS_PER_PGD * sizeof(pgd_t));
457 memcpy(pgd + USER_PTRS_PER_PGD, init + USER_PTRS_PER_PGD,
458 (PTRS_PER_PGD - USER_PTRS_PER_PGD) * sizeof(pgd_t));
464 static void srmmu_free_pgd_fast(pgd_t *pgd)
466 srmmu_free_nocache((unsigned long)pgd, SRMMU_PGD_TABLE_SIZE);
469 static pmd_t *srmmu_pmd_alloc_one(struct mm_struct *mm, unsigned long address)
471 return (pmd_t *)srmmu_get_nocache(SRMMU_PMD_TABLE_SIZE, SRMMU_PMD_TABLE_SIZE);
474 static void srmmu_pmd_free(pmd_t * pmd)
476 srmmu_free_nocache((unsigned long)pmd, SRMMU_PMD_TABLE_SIZE);
480 * Hardware needs alignment to 256 only, but we align to whole page size
481 * to reduce fragmentation problems due to the buddy principle.
482 * XXX Provide actual fragmentation statistics in /proc.
484 * Alignments up to the page size are the same for physical and virtual
485 * addresses of the nocache area.
488 srmmu_pte_alloc_one_kernel(struct mm_struct *mm, unsigned long address)
490 return (pte_t *)srmmu_get_nocache(PTE_SIZE, PTE_SIZE);
494 srmmu_pte_alloc_one(struct mm_struct *mm, unsigned long address)
498 if ((pte = (unsigned long)srmmu_pte_alloc_one_kernel(mm, address)) == 0)
500 return pfn_to_page( __nocache_pa(pte) >> PAGE_SHIFT );
503 static void srmmu_free_pte_fast(pte_t *pte)
505 srmmu_free_nocache((unsigned long)pte, PTE_SIZE);
508 static void srmmu_pte_free(struct page *pte)
512 p = (unsigned long)page_address(pte); /* Cached address (for test) */
515 p = page_to_pfn(pte) << PAGE_SHIFT; /* Physical address */
516 p = (unsigned long) __nocache_va(p); /* Nocached virtual */
517 srmmu_free_nocache(p, PTE_SIZE);
522 static inline void alloc_context(struct mm_struct *old_mm, struct mm_struct *mm)
524 struct ctx_list *ctxp;
526 ctxp = ctx_free.next;
527 if(ctxp != &ctx_free) {
528 remove_from_ctx_list(ctxp);
529 add_to_used_ctxlist(ctxp);
530 mm->context = ctxp->ctx_number;
534 ctxp = ctx_used.next;
535 if(ctxp->ctx_mm == old_mm)
537 if(ctxp == &ctx_used)
538 panic("out of mmu contexts");
539 flush_cache_mm(ctxp->ctx_mm);
540 flush_tlb_mm(ctxp->ctx_mm);
541 remove_from_ctx_list(ctxp);
542 add_to_used_ctxlist(ctxp);
543 ctxp->ctx_mm->context = NO_CONTEXT;
545 mm->context = ctxp->ctx_number;
548 static inline void free_context(int context)
550 struct ctx_list *ctx_old;
552 ctx_old = ctx_list_pool + context;
553 remove_from_ctx_list(ctx_old);
554 add_to_free_ctxlist(ctx_old);
558 static void srmmu_switch_mm(struct mm_struct *old_mm, struct mm_struct *mm,
559 struct task_struct *tsk, int cpu)
561 if(mm->context == NO_CONTEXT) {
562 spin_lock(&srmmu_context_spinlock);
563 alloc_context(old_mm, mm);
564 spin_unlock(&srmmu_context_spinlock);
565 srmmu_ctxd_set(&srmmu_context_table[mm->context], mm->pgd);
569 hyper_flush_whole_icache();
571 srmmu_set_context(mm->context);
574 /* Low level IO area allocation on the SRMMU. */
575 static inline void srmmu_mapioaddr(unsigned long physaddr,
576 unsigned long virt_addr, int bus_type)
583 physaddr &= PAGE_MASK;
584 pgdp = pgd_offset_k(virt_addr);
585 pmdp = srmmu_pmd_offset(pgdp, virt_addr);
586 ptep = srmmu_pte_offset(pmdp, virt_addr);
587 tmp = (physaddr >> 4) | SRMMU_ET_PTE;
590 * I need to test whether this is consistent over all
591 * sun4m's. The bus_type represents the upper 4 bits of
592 * 36-bit physical address on the I/O space lines...
594 tmp |= (bus_type << 28);
596 __flush_page_to_ram(virt_addr);
597 srmmu_set_pte(ptep, __pte(tmp));
600 static void srmmu_mapiorange(unsigned int bus, unsigned long xpa,
601 unsigned long xva, unsigned int len)
605 srmmu_mapioaddr(xpa, xva, bus);
612 static inline void srmmu_unmapioaddr(unsigned long virt_addr)
618 pgdp = pgd_offset_k(virt_addr);
619 pmdp = srmmu_pmd_offset(pgdp, virt_addr);
620 ptep = srmmu_pte_offset(pmdp, virt_addr);
622 /* No need to flush uncacheable page. */
623 srmmu_pte_clear(ptep);
626 static void srmmu_unmapiorange(unsigned long virt_addr, unsigned int len)
630 srmmu_unmapioaddr(virt_addr);
631 virt_addr += PAGE_SIZE;
637 * On the SRMMU we do not have the problems with limited tlb entries
638 * for mapping kernel pages, so we just take things from the free page
639 * pool. As a side effect we are putting a little too much pressure
640 * on the gfp() subsystem. This setup also makes the logic of the
641 * iommu mapping code a lot easier as we can transparently handle
642 * mappings on the kernel stack without any special code as we did
645 struct thread_info *srmmu_alloc_thread_info(void)
647 struct thread_info *ret;
649 ret = (struct thread_info *)__get_free_pages(GFP_KERNEL,
651 #ifdef CONFIG_DEBUG_STACK_USAGE
653 memset(ret, 0, PAGE_SIZE << THREAD_INFO_ORDER);
654 #endif /* DEBUG_STACK_USAGE */
659 static void srmmu_free_thread_info(struct thread_info *ti)
661 free_pages((unsigned long)ti, THREAD_INFO_ORDER);
665 extern void tsunami_flush_cache_all(void);
666 extern void tsunami_flush_cache_mm(struct mm_struct *mm);
667 extern void tsunami_flush_cache_range(struct vm_area_struct *vma, unsigned long start, unsigned long end);
668 extern void tsunami_flush_cache_page(struct vm_area_struct *vma, unsigned long page);
669 extern void tsunami_flush_page_to_ram(unsigned long page);
670 extern void tsunami_flush_page_for_dma(unsigned long page);
671 extern void tsunami_flush_sig_insns(struct mm_struct *mm, unsigned long insn_addr);
672 extern void tsunami_flush_tlb_all(void);
673 extern void tsunami_flush_tlb_mm(struct mm_struct *mm);
674 extern void tsunami_flush_tlb_range(struct vm_area_struct *vma, unsigned long start, unsigned long end);
675 extern void tsunami_flush_tlb_page(struct vm_area_struct *vma, unsigned long page);
676 extern void tsunami_setup_blockops(void);
679 * Workaround, until we find what's going on with Swift. When low on memory,
680 * it sometimes loops in fault/handle_mm_fault incl. flush_tlb_page to find
681 * out it is already in page tables/ fault again on the same instruction.
682 * I really don't understand it, have checked it and contexts
683 * are right, flush_tlb_all is done as well, and it faults again...
686 * The following code is a deadwood that may be necessary when
687 * we start to make precise page flushes again. --zaitcev
689 static void swift_update_mmu_cache(struct vm_area_struct * vma, unsigned long address, pte_t pte)
692 static unsigned long last;
694 /* unsigned int n; */
696 if (address == last) {
697 val = srmmu_hwprobe(address);
698 if (val != 0 && pte_val(pte) != val) {
699 printk("swift_update_mmu_cache: "
700 "addr %lx put %08x probed %08x from %p\n",
701 address, pte_val(pte), val,
702 __builtin_return_address(0));
703 srmmu_flush_whole_tlb();
711 extern void swift_flush_cache_all(void);
712 extern void swift_flush_cache_mm(struct mm_struct *mm);
713 extern void swift_flush_cache_range(struct vm_area_struct *vma,
714 unsigned long start, unsigned long end);
715 extern void swift_flush_cache_page(struct vm_area_struct *vma, unsigned long page);
716 extern void swift_flush_page_to_ram(unsigned long page);
717 extern void swift_flush_page_for_dma(unsigned long page);
718 extern void swift_flush_sig_insns(struct mm_struct *mm, unsigned long insn_addr);
719 extern void swift_flush_tlb_all(void);
720 extern void swift_flush_tlb_mm(struct mm_struct *mm);
721 extern void swift_flush_tlb_range(struct vm_area_struct *vma,
722 unsigned long start, unsigned long end);
723 extern void swift_flush_tlb_page(struct vm_area_struct *vma, unsigned long page);
725 #if 0 /* P3: deadwood to debug precise flushes on Swift. */
726 void swift_flush_tlb_page(struct vm_area_struct *vma, unsigned long page)
731 if ((ctx1 = vma->vm_mm->context) != -1) {
732 cctx = srmmu_get_context();
733 /* Is context # ever different from current context? P3 */
735 printk("flush ctx %02x curr %02x\n", ctx1, cctx);
736 srmmu_set_context(ctx1);
737 swift_flush_page(page);
738 __asm__ __volatile__("sta %%g0, [%0] %1\n\t" : :
739 "r" (page), "i" (ASI_M_FLUSH_PROBE));
740 srmmu_set_context(cctx);
742 /* Rm. prot. bits from virt. c. */
743 /* swift_flush_cache_all(); */
744 /* swift_flush_cache_page(vma, page); */
745 swift_flush_page(page);
747 __asm__ __volatile__("sta %%g0, [%0] %1\n\t" : :
748 "r" (page), "i" (ASI_M_FLUSH_PROBE));
749 /* same as above: srmmu_flush_tlb_page() */
756 * The following are all MBUS based SRMMU modules, and therefore could
757 * be found in a multiprocessor configuration. On the whole, these
758 * chips seems to be much more touchy about DVMA and page tables
759 * with respect to cache coherency.
762 /* Cypress flushes. */
763 static void cypress_flush_cache_all(void)
765 volatile unsigned long cypress_sucks;
766 unsigned long faddr, tagval;
768 flush_user_windows();
769 for(faddr = 0; faddr < 0x10000; faddr += 0x20) {
770 __asm__ __volatile__("lda [%1 + %2] %3, %0\n\t" :
772 "r" (faddr), "r" (0x40000),
773 "i" (ASI_M_DATAC_TAG));
775 /* If modified and valid, kick it. */
776 if((tagval & 0x60) == 0x60)
777 cypress_sucks = *(unsigned long *)(0xf0020000 + faddr);
781 static void cypress_flush_cache_mm(struct mm_struct *mm)
783 register unsigned long a, b, c, d, e, f, g;
784 unsigned long flags, faddr;
788 flush_user_windows();
789 local_irq_save(flags);
790 octx = srmmu_get_context();
791 srmmu_set_context(mm->context);
792 a = 0x20; b = 0x40; c = 0x60;
793 d = 0x80; e = 0xa0; f = 0xc0; g = 0xe0;
795 faddr = (0x10000 - 0x100);
800 __asm__ __volatile__("sta %%g0, [%0] %1\n\t"
801 "sta %%g0, [%0 + %2] %1\n\t"
802 "sta %%g0, [%0 + %3] %1\n\t"
803 "sta %%g0, [%0 + %4] %1\n\t"
804 "sta %%g0, [%0 + %5] %1\n\t"
805 "sta %%g0, [%0 + %6] %1\n\t"
806 "sta %%g0, [%0 + %7] %1\n\t"
807 "sta %%g0, [%0 + %8] %1\n\t" : :
808 "r" (faddr), "i" (ASI_M_FLUSH_CTX),
809 "r" (a), "r" (b), "r" (c), "r" (d),
810 "r" (e), "r" (f), "r" (g));
812 srmmu_set_context(octx);
813 local_irq_restore(flags);
817 static void cypress_flush_cache_range(struct vm_area_struct *vma, unsigned long start, unsigned long end)
819 struct mm_struct *mm = vma->vm_mm;
820 register unsigned long a, b, c, d, e, f, g;
821 unsigned long flags, faddr;
825 flush_user_windows();
826 local_irq_save(flags);
827 octx = srmmu_get_context();
828 srmmu_set_context(mm->context);
829 a = 0x20; b = 0x40; c = 0x60;
830 d = 0x80; e = 0xa0; f = 0xc0; g = 0xe0;
832 start &= SRMMU_REAL_PMD_MASK;
834 faddr = (start + (0x10000 - 0x100));
839 __asm__ __volatile__("sta %%g0, [%0] %1\n\t"
840 "sta %%g0, [%0 + %2] %1\n\t"
841 "sta %%g0, [%0 + %3] %1\n\t"
842 "sta %%g0, [%0 + %4] %1\n\t"
843 "sta %%g0, [%0 + %5] %1\n\t"
844 "sta %%g0, [%0 + %6] %1\n\t"
845 "sta %%g0, [%0 + %7] %1\n\t"
846 "sta %%g0, [%0 + %8] %1\n\t" : :
848 "i" (ASI_M_FLUSH_SEG),
849 "r" (a), "r" (b), "r" (c), "r" (d),
850 "r" (e), "r" (f), "r" (g));
851 } while (faddr != start);
852 start += SRMMU_REAL_PMD_SIZE;
854 srmmu_set_context(octx);
855 local_irq_restore(flags);
859 static void cypress_flush_cache_page(struct vm_area_struct *vma, unsigned long page)
861 register unsigned long a, b, c, d, e, f, g;
862 struct mm_struct *mm = vma->vm_mm;
863 unsigned long flags, line;
867 flush_user_windows();
868 local_irq_save(flags);
869 octx = srmmu_get_context();
870 srmmu_set_context(mm->context);
871 a = 0x20; b = 0x40; c = 0x60;
872 d = 0x80; e = 0xa0; f = 0xc0; g = 0xe0;
875 line = (page + PAGE_SIZE) - 0x100;
880 __asm__ __volatile__("sta %%g0, [%0] %1\n\t"
881 "sta %%g0, [%0 + %2] %1\n\t"
882 "sta %%g0, [%0 + %3] %1\n\t"
883 "sta %%g0, [%0 + %4] %1\n\t"
884 "sta %%g0, [%0 + %5] %1\n\t"
885 "sta %%g0, [%0 + %6] %1\n\t"
886 "sta %%g0, [%0 + %7] %1\n\t"
887 "sta %%g0, [%0 + %8] %1\n\t" : :
889 "i" (ASI_M_FLUSH_PAGE),
890 "r" (a), "r" (b), "r" (c), "r" (d),
891 "r" (e), "r" (f), "r" (g));
892 } while(line != page);
893 srmmu_set_context(octx);
894 local_irq_restore(flags);
898 /* Cypress is copy-back, at least that is how we configure it. */
899 static void cypress_flush_page_to_ram(unsigned long page)
901 register unsigned long a, b, c, d, e, f, g;
904 a = 0x20; b = 0x40; c = 0x60; d = 0x80; e = 0xa0; f = 0xc0; g = 0xe0;
906 line = (page + PAGE_SIZE) - 0x100;
911 __asm__ __volatile__("sta %%g0, [%0] %1\n\t"
912 "sta %%g0, [%0 + %2] %1\n\t"
913 "sta %%g0, [%0 + %3] %1\n\t"
914 "sta %%g0, [%0 + %4] %1\n\t"
915 "sta %%g0, [%0 + %5] %1\n\t"
916 "sta %%g0, [%0 + %6] %1\n\t"
917 "sta %%g0, [%0 + %7] %1\n\t"
918 "sta %%g0, [%0 + %8] %1\n\t" : :
920 "i" (ASI_M_FLUSH_PAGE),
921 "r" (a), "r" (b), "r" (c), "r" (d),
922 "r" (e), "r" (f), "r" (g));
923 } while(line != page);
926 /* Cypress is also IO cache coherent. */
927 static void cypress_flush_page_for_dma(unsigned long page)
931 /* Cypress has unified L2 VIPT, from which both instructions and data
932 * are stored. It does not have an onboard icache of any sort, therefore
933 * no flush is necessary.
935 static void cypress_flush_sig_insns(struct mm_struct *mm, unsigned long insn_addr)
939 static void cypress_flush_tlb_all(void)
941 srmmu_flush_whole_tlb();
944 static void cypress_flush_tlb_mm(struct mm_struct *mm)
947 __asm__ __volatile__(
948 "lda [%0] %3, %%g5\n\t"
949 "sta %2, [%0] %3\n\t"
950 "sta %%g0, [%1] %4\n\t"
951 "sta %%g5, [%0] %3\n"
953 : "r" (SRMMU_CTX_REG), "r" (0x300), "r" (mm->context),
954 "i" (ASI_M_MMUREGS), "i" (ASI_M_FLUSH_PROBE)
959 static void cypress_flush_tlb_range(struct vm_area_struct *vma, unsigned long start, unsigned long end)
961 struct mm_struct *mm = vma->vm_mm;
965 start &= SRMMU_PGDIR_MASK;
966 size = SRMMU_PGDIR_ALIGN(end) - start;
967 __asm__ __volatile__(
968 "lda [%0] %5, %%g5\n\t"
971 "subcc %3, %4, %3\n\t"
973 " sta %%g0, [%2 + %3] %6\n\t"
974 "sta %%g5, [%0] %5\n"
976 : "r" (SRMMU_CTX_REG), "r" (mm->context), "r" (start | 0x200),
977 "r" (size), "r" (SRMMU_PGDIR_SIZE), "i" (ASI_M_MMUREGS),
978 "i" (ASI_M_FLUSH_PROBE)
983 static void cypress_flush_tlb_page(struct vm_area_struct *vma, unsigned long page)
985 struct mm_struct *mm = vma->vm_mm;
988 __asm__ __volatile__(
989 "lda [%0] %3, %%g5\n\t"
990 "sta %1, [%0] %3\n\t"
991 "sta %%g0, [%2] %4\n\t"
992 "sta %%g5, [%0] %3\n"
994 : "r" (SRMMU_CTX_REG), "r" (mm->context), "r" (page & PAGE_MASK),
995 "i" (ASI_M_MMUREGS), "i" (ASI_M_FLUSH_PROBE)
1001 extern void viking_flush_cache_all(void);
1002 extern void viking_flush_cache_mm(struct mm_struct *mm);
1003 extern void viking_flush_cache_range(struct vm_area_struct *vma, unsigned long start,
1005 extern void viking_flush_cache_page(struct vm_area_struct *vma,
1006 unsigned long page);
1007 extern void viking_flush_page_to_ram(unsigned long page);
1008 extern void viking_flush_page_for_dma(unsigned long page);
1009 extern void viking_flush_sig_insns(struct mm_struct *mm, unsigned long addr);
1010 extern void viking_flush_page(unsigned long page);
1011 extern void viking_mxcc_flush_page(unsigned long page);
1012 extern void viking_flush_tlb_all(void);
1013 extern void viking_flush_tlb_mm(struct mm_struct *mm);
1014 extern void viking_flush_tlb_range(struct vm_area_struct *vma, unsigned long start,
1016 extern void viking_flush_tlb_page(struct vm_area_struct *vma,
1017 unsigned long page);
1018 extern void sun4dsmp_flush_tlb_all(void);
1019 extern void sun4dsmp_flush_tlb_mm(struct mm_struct *mm);
1020 extern void sun4dsmp_flush_tlb_range(struct vm_area_struct *vma, unsigned long start,
1022 extern void sun4dsmp_flush_tlb_page(struct vm_area_struct *vma,
1023 unsigned long page);
1026 extern void hypersparc_flush_cache_all(void);
1027 extern void hypersparc_flush_cache_mm(struct mm_struct *mm);
1028 extern void hypersparc_flush_cache_range(struct vm_area_struct *vma, unsigned long start, unsigned long end);
1029 extern void hypersparc_flush_cache_page(struct vm_area_struct *vma, unsigned long page);
1030 extern void hypersparc_flush_page_to_ram(unsigned long page);
1031 extern void hypersparc_flush_page_for_dma(unsigned long page);
1032 extern void hypersparc_flush_sig_insns(struct mm_struct *mm, unsigned long insn_addr);
1033 extern void hypersparc_flush_tlb_all(void);
1034 extern void hypersparc_flush_tlb_mm(struct mm_struct *mm);
1035 extern void hypersparc_flush_tlb_range(struct vm_area_struct *vma, unsigned long start, unsigned long end);
1036 extern void hypersparc_flush_tlb_page(struct vm_area_struct *vma, unsigned long page);
1037 extern void hypersparc_setup_blockops(void);
1040 * NOTE: All of this startup code assumes the low 16mb (approx.) of
1041 * kernel mappings are done with one single contiguous chunk of
1042 * ram. On small ram machines (classics mainly) we only get
1043 * around 8mb mapped for us.
1046 void __init early_pgtable_allocfail(char *type)
1048 prom_printf("inherit_prom_mappings: Cannot alloc kernel %s.\n", type);
1052 void __init srmmu_early_allocate_ptable_skeleton(unsigned long start, unsigned long end)
1058 while(start < end) {
1059 pgdp = pgd_offset_k(start);
1060 if(srmmu_pgd_none(*(pgd_t *)__nocache_fix(pgdp))) {
1061 pmdp = (pmd_t *) __srmmu_get_nocache(
1062 SRMMU_PMD_TABLE_SIZE, SRMMU_PMD_TABLE_SIZE);
1064 early_pgtable_allocfail("pmd");
1065 memset(__nocache_fix(pmdp), 0, SRMMU_PMD_TABLE_SIZE);
1066 srmmu_pgd_set(__nocache_fix(pgdp), pmdp);
1068 pmdp = srmmu_pmd_offset(__nocache_fix(pgdp), start);
1069 if(srmmu_pmd_none(*(pmd_t *)__nocache_fix(pmdp))) {
1070 ptep = (pte_t *)__srmmu_get_nocache(PTE_SIZE, PTE_SIZE);
1072 early_pgtable_allocfail("pte");
1073 memset(__nocache_fix(ptep), 0, PTE_SIZE);
1074 srmmu_pmd_set(__nocache_fix(pmdp), ptep);
1076 if (start > (0xffffffffUL - PMD_SIZE))
1078 start = (start + PMD_SIZE) & PMD_MASK;
1082 void __init srmmu_allocate_ptable_skeleton(unsigned long start, unsigned long end)
1088 while(start < end) {
1089 pgdp = pgd_offset_k(start);
1090 if(srmmu_pgd_none(*pgdp)) {
1091 pmdp = (pmd_t *)__srmmu_get_nocache(SRMMU_PMD_TABLE_SIZE, SRMMU_PMD_TABLE_SIZE);
1093 early_pgtable_allocfail("pmd");
1094 memset(pmdp, 0, SRMMU_PMD_TABLE_SIZE);
1095 srmmu_pgd_set(pgdp, pmdp);
1097 pmdp = srmmu_pmd_offset(pgdp, start);
1098 if(srmmu_pmd_none(*pmdp)) {
1099 ptep = (pte_t *) __srmmu_get_nocache(PTE_SIZE,
1102 early_pgtable_allocfail("pte");
1103 memset(ptep, 0, PTE_SIZE);
1104 srmmu_pmd_set(pmdp, ptep);
1106 if (start > (0xffffffffUL - PMD_SIZE))
1108 start = (start + PMD_SIZE) & PMD_MASK;
1113 * This is much cleaner than poking around physical address space
1114 * looking at the prom's page table directly which is what most
1115 * other OS's do. Yuck... this is much better.
1117 void __init srmmu_inherit_prom_mappings(unsigned long start,unsigned long end)
1122 int what = 0; /* 0 = normal-pte, 1 = pmd-level pte, 2 = pgd-level pte */
1123 unsigned long prompte;
1125 while(start <= end) {
1127 break; /* probably wrap around */
1128 if(start == 0xfef00000)
1129 start = KADB_DEBUGGER_BEGVM;
1130 if(!(prompte = srmmu_hwprobe(start))) {
1135 /* A red snapper, see what it really is. */
1138 if(!(start & ~(SRMMU_REAL_PMD_MASK))) {
1139 if(srmmu_hwprobe((start-PAGE_SIZE) + SRMMU_REAL_PMD_SIZE) == prompte)
1143 if(!(start & ~(SRMMU_PGDIR_MASK))) {
1144 if(srmmu_hwprobe((start-PAGE_SIZE) + SRMMU_PGDIR_SIZE) ==
1149 pgdp = pgd_offset_k(start);
1151 *(pgd_t *)__nocache_fix(pgdp) = __pgd(prompte);
1152 start += SRMMU_PGDIR_SIZE;
1155 if(srmmu_pgd_none(*(pgd_t *)__nocache_fix(pgdp))) {
1156 pmdp = (pmd_t *)__srmmu_get_nocache(SRMMU_PMD_TABLE_SIZE, SRMMU_PMD_TABLE_SIZE);
1158 early_pgtable_allocfail("pmd");
1159 memset(__nocache_fix(pmdp), 0, SRMMU_PMD_TABLE_SIZE);
1160 srmmu_pgd_set(__nocache_fix(pgdp), pmdp);
1162 pmdp = srmmu_pmd_offset(__nocache_fix(pgdp), start);
1163 if(srmmu_pmd_none(*(pmd_t *)__nocache_fix(pmdp))) {
1164 ptep = (pte_t *) __srmmu_get_nocache(PTE_SIZE,
1167 early_pgtable_allocfail("pte");
1168 memset(__nocache_fix(ptep), 0, PTE_SIZE);
1169 srmmu_pmd_set(__nocache_fix(pmdp), ptep);
1173 * We bend the rule where all 16 PTPs in a pmd_t point
1174 * inside the same PTE page, and we leak a perfectly
1175 * good hardware PTE piece. Alternatives seem worse.
1177 unsigned int x; /* Index of HW PMD in soft cluster */
1178 x = (start >> PMD_SHIFT) & 15;
1179 *(unsigned long *)__nocache_fix(&pmdp->pmdv[x]) = prompte;
1180 start += SRMMU_REAL_PMD_SIZE;
1183 ptep = srmmu_pte_offset(__nocache_fix(pmdp), start);
1184 *(pte_t *)__nocache_fix(ptep) = __pte(prompte);
1189 #define KERNEL_PTE(page_shifted) ((page_shifted)|SRMMU_CACHE|SRMMU_PRIV|SRMMU_VALID)
1191 /* Create a third-level SRMMU 16MB page mapping. */
1192 static void __init do_large_mapping(unsigned long vaddr, unsigned long phys_base)
1194 pgd_t *pgdp = pgd_offset_k(vaddr);
1195 unsigned long big_pte;
1197 big_pte = KERNEL_PTE(phys_base >> 4);
1198 *(pgd_t *)__nocache_fix(pgdp) = __pgd(big_pte);
1201 /* Map sp_bank entry SP_ENTRY, starting at virtual address VBASE. */
1202 static unsigned long __init map_spbank(unsigned long vbase, int sp_entry)
1204 unsigned long pstart = (sp_banks[sp_entry].base_addr & SRMMU_PGDIR_MASK);
1205 unsigned long vstart = (vbase & SRMMU_PGDIR_MASK);
1206 unsigned long vend = SRMMU_PGDIR_ALIGN(vbase + sp_banks[sp_entry].num_bytes);
1207 /* Map "low" memory only */
1208 const unsigned long min_vaddr = PAGE_OFFSET;
1209 const unsigned long max_vaddr = PAGE_OFFSET + SRMMU_MAXMEM;
1211 if (vstart < min_vaddr || vstart >= max_vaddr)
1214 if (vend > max_vaddr || vend < min_vaddr)
1217 while(vstart < vend) {
1218 do_large_mapping(vstart, pstart);
1219 vstart += SRMMU_PGDIR_SIZE; pstart += SRMMU_PGDIR_SIZE;
1224 static inline void memprobe_error(char *msg)
1227 prom_printf("Halting now...\n");
1231 static inline void map_kernel(void)
1235 if (phys_base > 0) {
1236 do_large_mapping(PAGE_OFFSET, phys_base);
1239 for (i = 0; sp_banks[i].num_bytes != 0; i++) {
1240 map_spbank((unsigned long)__va(sp_banks[i].base_addr), i);
1243 BTFIXUPSET_SIMM13(user_ptrs_per_pgd, PAGE_OFFSET / SRMMU_PGDIR_SIZE);
1246 /* Paging initialization on the Sparc Reference MMU. */
1247 extern void sparc_context_init(int);
1249 void (*poke_srmmu)(void) __initdata = NULL;
1251 extern unsigned long bootmem_init(unsigned long *pages_avail);
1253 void __init srmmu_paging_init(void)
1260 unsigned long pages_avail;
1262 sparc_iomap.start = SUN4M_IOBASE_VADDR; /* 16MB of IOSPACE on all sun4m's. */
1264 if (sparc_cpu_model == sun4d)
1265 num_contexts = 65536; /* We know it is Viking */
1267 /* Find the number of contexts on the srmmu. */
1268 cpunode = prom_getchild(prom_root_node);
1270 while(cpunode != 0) {
1271 prom_getstring(cpunode, "device_type", node_str, sizeof(node_str));
1272 if(!strcmp(node_str, "cpu")) {
1273 num_contexts = prom_getintdefault(cpunode, "mmu-nctx", 0x8);
1276 cpunode = prom_getsibling(cpunode);
1281 prom_printf("Something wrong, can't find cpu node in paging_init.\n");
1286 last_valid_pfn = bootmem_init(&pages_avail);
1288 srmmu_nocache_calcsize();
1289 srmmu_nocache_init();
1290 srmmu_inherit_prom_mappings(0xfe400000,(LINUX_OPPROM_ENDVM-PAGE_SIZE));
1293 /* ctx table has to be physically aligned to its size */
1294 srmmu_context_table = (ctxd_t *)__srmmu_get_nocache(num_contexts*sizeof(ctxd_t), num_contexts*sizeof(ctxd_t));
1295 srmmu_ctx_table_phys = (ctxd_t *)__nocache_pa((unsigned long)srmmu_context_table);
1297 for(i = 0; i < num_contexts; i++)
1298 srmmu_ctxd_set((ctxd_t *)__nocache_fix(&srmmu_context_table[i]), srmmu_swapper_pg_dir);
1301 srmmu_set_ctable_ptr((unsigned long)srmmu_ctx_table_phys);
1305 #ifdef CONFIG_SUN_IO
1306 srmmu_allocate_ptable_skeleton(sparc_iomap.start, IOBASE_END);
1307 srmmu_allocate_ptable_skeleton(DVMA_VADDR, DVMA_END);
1310 srmmu_allocate_ptable_skeleton(
1311 __fix_to_virt(__end_of_fixed_addresses - 1), FIXADDR_TOP);
1312 srmmu_allocate_ptable_skeleton(PKMAP_BASE, PKMAP_END);
1314 pgd = pgd_offset_k(PKMAP_BASE);
1315 pmd = srmmu_pmd_offset(pgd, PKMAP_BASE);
1316 pte = srmmu_pte_offset(pmd, PKMAP_BASE);
1317 pkmap_page_table = pte;
1322 sparc_context_init(num_contexts);
1327 unsigned long zones_size[MAX_NR_ZONES];
1328 unsigned long zholes_size[MAX_NR_ZONES];
1329 unsigned long npages;
1332 for (znum = 0; znum < MAX_NR_ZONES; znum++)
1333 zones_size[znum] = zholes_size[znum] = 0;
1335 npages = max_low_pfn - pfn_base;
1337 zones_size[ZONE_DMA] = npages;
1338 zholes_size[ZONE_DMA] = npages - pages_avail;
1340 npages = highend_pfn - max_low_pfn;
1341 zones_size[ZONE_HIGHMEM] = npages;
1342 zholes_size[ZONE_HIGHMEM] = npages - calc_highpages();
1344 free_area_init_node(0, &contig_page_data, zones_size,
1345 pfn_base, zholes_size);
1346 mem_map = contig_page_data.node_mem_map;
1350 static void srmmu_mmu_info(struct seq_file *m)
1355 "nocache total\t: %ld\n"
1356 "nocache used\t: %d\n",
1360 srmmu_nocache_map.used << SRMMU_NOCACHE_BITMAP_SHIFT);
1363 static void srmmu_update_mmu_cache(struct vm_area_struct * vma, unsigned long address, pte_t pte)
1367 static void srmmu_destroy_context(struct mm_struct *mm)
1370 if(mm->context != NO_CONTEXT) {
1372 srmmu_ctxd_set(&srmmu_context_table[mm->context], srmmu_swapper_pg_dir);
1374 spin_lock(&srmmu_context_spinlock);
1375 free_context(mm->context);
1376 spin_unlock(&srmmu_context_spinlock);
1377 mm->context = NO_CONTEXT;
1381 /* Init various srmmu chip types. */
1382 static void __init srmmu_is_bad(void)
1384 prom_printf("Could not determine SRMMU chip type.\n");
1388 static void __init init_vac_layout(void)
1390 int nd, cache_lines;
1394 unsigned long max_size = 0;
1395 unsigned long min_line_size = 0x10000000;
1398 nd = prom_getchild(prom_root_node);
1399 while((nd = prom_getsibling(nd)) != 0) {
1400 prom_getstring(nd, "device_type", node_str, sizeof(node_str));
1401 if(!strcmp(node_str, "cpu")) {
1402 vac_line_size = prom_getint(nd, "cache-line-size");
1403 if (vac_line_size == -1) {
1404 prom_printf("can't determine cache-line-size, "
1408 cache_lines = prom_getint(nd, "cache-nlines");
1409 if (cache_lines == -1) {
1410 prom_printf("can't determine cache-nlines, halting.\n");
1414 vac_cache_size = cache_lines * vac_line_size;
1416 if(vac_cache_size > max_size)
1417 max_size = vac_cache_size;
1418 if(vac_line_size < min_line_size)
1419 min_line_size = vac_line_size;
1421 if (cpu >= NR_CPUS || !cpu_online(cpu))
1429 prom_printf("No CPU nodes found, halting.\n");
1433 vac_cache_size = max_size;
1434 vac_line_size = min_line_size;
1436 printk("SRMMU: Using VAC size of %d bytes, line size %d bytes.\n",
1437 (int)vac_cache_size, (int)vac_line_size);
1440 static void __init poke_hypersparc(void)
1442 volatile unsigned long clear;
1443 unsigned long mreg = srmmu_get_mmureg();
1445 hyper_flush_unconditional_combined();
1447 mreg &= ~(HYPERSPARC_CWENABLE);
1448 mreg |= (HYPERSPARC_CENABLE | HYPERSPARC_WBENABLE);
1449 mreg |= (HYPERSPARC_CMODE);
1451 srmmu_set_mmureg(mreg);
1453 #if 0 /* XXX I think this is bad news... -DaveM */
1454 hyper_clear_all_tags();
1457 put_ross_icr(HYPERSPARC_ICCR_FTD | HYPERSPARC_ICCR_ICE);
1458 hyper_flush_whole_icache();
1459 clear = srmmu_get_faddr();
1460 clear = srmmu_get_fstatus();
1463 static void __init init_hypersparc(void)
1465 srmmu_name = "ROSS HyperSparc";
1466 srmmu_modtype = HyperSparc;
1472 BTFIXUPSET_CALL(pte_clear, srmmu_pte_clear, BTFIXUPCALL_NORM);
1473 BTFIXUPSET_CALL(pmd_clear, srmmu_pmd_clear, BTFIXUPCALL_NORM);
1474 BTFIXUPSET_CALL(pgd_clear, srmmu_pgd_clear, BTFIXUPCALL_NORM);
1475 BTFIXUPSET_CALL(flush_cache_all, hypersparc_flush_cache_all, BTFIXUPCALL_NORM);
1476 BTFIXUPSET_CALL(flush_cache_mm, hypersparc_flush_cache_mm, BTFIXUPCALL_NORM);
1477 BTFIXUPSET_CALL(flush_cache_range, hypersparc_flush_cache_range, BTFIXUPCALL_NORM);
1478 BTFIXUPSET_CALL(flush_cache_page, hypersparc_flush_cache_page, BTFIXUPCALL_NORM);
1480 BTFIXUPSET_CALL(flush_tlb_all, hypersparc_flush_tlb_all, BTFIXUPCALL_NORM);
1481 BTFIXUPSET_CALL(flush_tlb_mm, hypersparc_flush_tlb_mm, BTFIXUPCALL_NORM);
1482 BTFIXUPSET_CALL(flush_tlb_range, hypersparc_flush_tlb_range, BTFIXUPCALL_NORM);
1483 BTFIXUPSET_CALL(flush_tlb_page, hypersparc_flush_tlb_page, BTFIXUPCALL_NORM);
1485 BTFIXUPSET_CALL(__flush_page_to_ram, hypersparc_flush_page_to_ram, BTFIXUPCALL_NORM);
1486 BTFIXUPSET_CALL(flush_sig_insns, hypersparc_flush_sig_insns, BTFIXUPCALL_NORM);
1487 BTFIXUPSET_CALL(flush_page_for_dma, hypersparc_flush_page_for_dma, BTFIXUPCALL_NOP);
1490 poke_srmmu = poke_hypersparc;
1492 hypersparc_setup_blockops();
1495 static void __init poke_cypress(void)
1497 unsigned long mreg = srmmu_get_mmureg();
1498 unsigned long faddr, tagval;
1499 volatile unsigned long cypress_sucks;
1500 volatile unsigned long clear;
1502 clear = srmmu_get_faddr();
1503 clear = srmmu_get_fstatus();
1505 if (!(mreg & CYPRESS_CENABLE)) {
1506 for(faddr = 0x0; faddr < 0x10000; faddr += 20) {
1507 __asm__ __volatile__("sta %%g0, [%0 + %1] %2\n\t"
1508 "sta %%g0, [%0] %2\n\t" : :
1509 "r" (faddr), "r" (0x40000),
1510 "i" (ASI_M_DATAC_TAG));
1513 for(faddr = 0; faddr < 0x10000; faddr += 0x20) {
1514 __asm__ __volatile__("lda [%1 + %2] %3, %0\n\t" :
1516 "r" (faddr), "r" (0x40000),
1517 "i" (ASI_M_DATAC_TAG));
1519 /* If modified and valid, kick it. */
1520 if((tagval & 0x60) == 0x60)
1521 cypress_sucks = *(unsigned long *)
1522 (0xf0020000 + faddr);
1526 /* And one more, for our good neighbor, Mr. Broken Cypress. */
1527 clear = srmmu_get_faddr();
1528 clear = srmmu_get_fstatus();
1530 mreg |= (CYPRESS_CENABLE | CYPRESS_CMODE);
1531 srmmu_set_mmureg(mreg);
1534 static void __init init_cypress_common(void)
1538 BTFIXUPSET_CALL(pte_clear, srmmu_pte_clear, BTFIXUPCALL_NORM);
1539 BTFIXUPSET_CALL(pmd_clear, srmmu_pmd_clear, BTFIXUPCALL_NORM);
1540 BTFIXUPSET_CALL(pgd_clear, srmmu_pgd_clear, BTFIXUPCALL_NORM);
1541 BTFIXUPSET_CALL(flush_cache_all, cypress_flush_cache_all, BTFIXUPCALL_NORM);
1542 BTFIXUPSET_CALL(flush_cache_mm, cypress_flush_cache_mm, BTFIXUPCALL_NORM);
1543 BTFIXUPSET_CALL(flush_cache_range, cypress_flush_cache_range, BTFIXUPCALL_NORM);
1544 BTFIXUPSET_CALL(flush_cache_page, cypress_flush_cache_page, BTFIXUPCALL_NORM);
1546 BTFIXUPSET_CALL(flush_tlb_all, cypress_flush_tlb_all, BTFIXUPCALL_NORM);
1547 BTFIXUPSET_CALL(flush_tlb_mm, cypress_flush_tlb_mm, BTFIXUPCALL_NORM);
1548 BTFIXUPSET_CALL(flush_tlb_page, cypress_flush_tlb_page, BTFIXUPCALL_NORM);
1549 BTFIXUPSET_CALL(flush_tlb_range, cypress_flush_tlb_range, BTFIXUPCALL_NORM);
1552 BTFIXUPSET_CALL(__flush_page_to_ram, cypress_flush_page_to_ram, BTFIXUPCALL_NORM);
1553 BTFIXUPSET_CALL(flush_sig_insns, cypress_flush_sig_insns, BTFIXUPCALL_NOP);
1554 BTFIXUPSET_CALL(flush_page_for_dma, cypress_flush_page_for_dma, BTFIXUPCALL_NOP);
1556 poke_srmmu = poke_cypress;
1559 static void __init init_cypress_604(void)
1561 srmmu_name = "ROSS Cypress-604(UP)";
1562 srmmu_modtype = Cypress;
1563 init_cypress_common();
1566 static void __init init_cypress_605(unsigned long mrev)
1568 srmmu_name = "ROSS Cypress-605(MP)";
1570 srmmu_modtype = Cypress_vE;
1571 hwbug_bitmask |= HWBUG_COPYBACK_BROKEN;
1574 srmmu_modtype = Cypress_vD;
1575 hwbug_bitmask |= HWBUG_ASIFLUSH_BROKEN;
1577 srmmu_modtype = Cypress;
1580 init_cypress_common();
1583 static void __init poke_swift(void)
1587 /* Clear any crap from the cache or else... */
1588 swift_flush_cache_all();
1590 /* Enable I & D caches */
1591 mreg = srmmu_get_mmureg();
1592 mreg |= (SWIFT_IE | SWIFT_DE);
1594 * The Swift branch folding logic is completely broken. At
1595 * trap time, if things are just right, if can mistakenly
1596 * think that a trap is coming from kernel mode when in fact
1597 * it is coming from user mode (it mis-executes the branch in
1598 * the trap code). So you see things like crashme completely
1599 * hosing your machine which is completely unacceptable. Turn
1600 * this shit off... nice job Fujitsu.
1602 mreg &= ~(SWIFT_BF);
1603 srmmu_set_mmureg(mreg);
1606 #define SWIFT_MASKID_ADDR 0x10003018
1607 static void __init init_swift(void)
1609 unsigned long swift_rev;
1611 __asm__ __volatile__("lda [%1] %2, %0\n\t"
1612 "srl %0, 0x18, %0\n\t" :
1614 "r" (SWIFT_MASKID_ADDR), "i" (ASI_M_BYPASS));
1615 srmmu_name = "Fujitsu Swift";
1621 srmmu_modtype = Swift_lots_o_bugs;
1622 hwbug_bitmask |= (HWBUG_KERN_ACCBROKEN | HWBUG_KERN_CBITBROKEN);
1624 * Gee george, I wonder why Sun is so hush hush about
1625 * this hardware bug... really braindamage stuff going
1626 * on here. However I think we can find a way to avoid
1627 * all of the workaround overhead under Linux. Basically,
1628 * any page fault can cause kernel pages to become user
1629 * accessible (the mmu gets confused and clears some of
1630 * the ACC bits in kernel ptes). Aha, sounds pretty
1631 * horrible eh? But wait, after extensive testing it appears
1632 * that if you use pgd_t level large kernel pte's (like the
1633 * 4MB pages on the Pentium) the bug does not get tripped
1634 * at all. This avoids almost all of the major overhead.
1635 * Welcome to a world where your vendor tells you to,
1636 * "apply this kernel patch" instead of "sorry for the
1637 * broken hardware, send it back and we'll give you
1638 * properly functioning parts"
1643 srmmu_modtype = Swift_bad_c;
1644 hwbug_bitmask |= HWBUG_KERN_CBITBROKEN;
1646 * You see Sun allude to this hardware bug but never
1647 * admit things directly, they'll say things like,
1648 * "the Swift chip cache problems" or similar.
1652 srmmu_modtype = Swift_ok;
1656 BTFIXUPSET_CALL(flush_cache_all, swift_flush_cache_all, BTFIXUPCALL_NORM);
1657 BTFIXUPSET_CALL(flush_cache_mm, swift_flush_cache_mm, BTFIXUPCALL_NORM);
1658 BTFIXUPSET_CALL(flush_cache_page, swift_flush_cache_page, BTFIXUPCALL_NORM);
1659 BTFIXUPSET_CALL(flush_cache_range, swift_flush_cache_range, BTFIXUPCALL_NORM);
1662 BTFIXUPSET_CALL(flush_tlb_all, swift_flush_tlb_all, BTFIXUPCALL_NORM);
1663 BTFIXUPSET_CALL(flush_tlb_mm, swift_flush_tlb_mm, BTFIXUPCALL_NORM);
1664 BTFIXUPSET_CALL(flush_tlb_page, swift_flush_tlb_page, BTFIXUPCALL_NORM);
1665 BTFIXUPSET_CALL(flush_tlb_range, swift_flush_tlb_range, BTFIXUPCALL_NORM);
1667 BTFIXUPSET_CALL(__flush_page_to_ram, swift_flush_page_to_ram, BTFIXUPCALL_NORM);
1668 BTFIXUPSET_CALL(flush_sig_insns, swift_flush_sig_insns, BTFIXUPCALL_NORM);
1669 BTFIXUPSET_CALL(flush_page_for_dma, swift_flush_page_for_dma, BTFIXUPCALL_NORM);
1671 BTFIXUPSET_CALL(update_mmu_cache, swift_update_mmu_cache, BTFIXUPCALL_NORM);
1673 flush_page_for_dma_global = 0;
1676 * Are you now convinced that the Swift is one of the
1677 * biggest VLSI abortions of all time? Bravo Fujitsu!
1678 * Fujitsu, the !#?!%$'d up processor people. I bet if
1679 * you examined the microcode of the Swift you'd find
1680 * XXX's all over the place.
1682 poke_srmmu = poke_swift;
1685 static void turbosparc_flush_cache_all(void)
1687 flush_user_windows();
1688 turbosparc_idflash_clear();
1691 static void turbosparc_flush_cache_mm(struct mm_struct *mm)
1694 flush_user_windows();
1695 turbosparc_idflash_clear();
1699 static void turbosparc_flush_cache_range(struct vm_area_struct *vma, unsigned long start, unsigned long end)
1701 FLUSH_BEGIN(vma->vm_mm)
1702 flush_user_windows();
1703 turbosparc_idflash_clear();
1707 static void turbosparc_flush_cache_page(struct vm_area_struct *vma, unsigned long page)
1709 FLUSH_BEGIN(vma->vm_mm)
1710 flush_user_windows();
1711 if (vma->vm_flags & VM_EXEC)
1712 turbosparc_flush_icache();
1713 turbosparc_flush_dcache();
1717 /* TurboSparc is copy-back, if we turn it on, but this does not work. */
1718 static void turbosparc_flush_page_to_ram(unsigned long page)
1720 #ifdef TURBOSPARC_WRITEBACK
1721 volatile unsigned long clear;
1723 if (srmmu_hwprobe(page))
1724 turbosparc_flush_page_cache(page);
1725 clear = srmmu_get_fstatus();
1729 static void turbosparc_flush_sig_insns(struct mm_struct *mm, unsigned long insn_addr)
1733 static void turbosparc_flush_page_for_dma(unsigned long page)
1735 turbosparc_flush_dcache();
1738 static void turbosparc_flush_tlb_all(void)
1740 srmmu_flush_whole_tlb();
1743 static void turbosparc_flush_tlb_mm(struct mm_struct *mm)
1746 srmmu_flush_whole_tlb();
1750 static void turbosparc_flush_tlb_range(struct vm_area_struct *vma, unsigned long start, unsigned long end)
1752 FLUSH_BEGIN(vma->vm_mm)
1753 srmmu_flush_whole_tlb();
1757 static void turbosparc_flush_tlb_page(struct vm_area_struct *vma, unsigned long page)
1759 FLUSH_BEGIN(vma->vm_mm)
1760 srmmu_flush_whole_tlb();
1765 static void __init poke_turbosparc(void)
1767 unsigned long mreg = srmmu_get_mmureg();
1768 unsigned long ccreg;
1770 /* Clear any crap from the cache or else... */
1771 turbosparc_flush_cache_all();
1772 mreg &= ~(TURBOSPARC_ICENABLE | TURBOSPARC_DCENABLE); /* Temporarily disable I & D caches */
1773 mreg &= ~(TURBOSPARC_PCENABLE); /* Don't check parity */
1774 srmmu_set_mmureg(mreg);
1776 ccreg = turbosparc_get_ccreg();
1778 #ifdef TURBOSPARC_WRITEBACK
1779 ccreg |= (TURBOSPARC_SNENABLE); /* Do DVMA snooping in Dcache */
1780 ccreg &= ~(TURBOSPARC_uS2 | TURBOSPARC_WTENABLE);
1781 /* Write-back D-cache, emulate VLSI
1782 * abortion number three, not number one */
1784 /* For now let's play safe, optimize later */
1785 ccreg |= (TURBOSPARC_SNENABLE | TURBOSPARC_WTENABLE);
1786 /* Do DVMA snooping in Dcache, Write-thru D-cache */
1787 ccreg &= ~(TURBOSPARC_uS2);
1788 /* Emulate VLSI abortion number three, not number one */
1791 switch (ccreg & 7) {
1792 case 0: /* No SE cache */
1793 case 7: /* Test mode */
1796 ccreg |= (TURBOSPARC_SCENABLE);
1798 turbosparc_set_ccreg (ccreg);
1800 mreg |= (TURBOSPARC_ICENABLE | TURBOSPARC_DCENABLE); /* I & D caches on */
1801 mreg |= (TURBOSPARC_ICSNOOP); /* Icache snooping on */
1802 srmmu_set_mmureg(mreg);
1805 static void __init init_turbosparc(void)
1807 srmmu_name = "Fujitsu TurboSparc";
1808 srmmu_modtype = TurboSparc;
1810 BTFIXUPSET_CALL(flush_cache_all, turbosparc_flush_cache_all, BTFIXUPCALL_NORM);
1811 BTFIXUPSET_CALL(flush_cache_mm, turbosparc_flush_cache_mm, BTFIXUPCALL_NORM);
1812 BTFIXUPSET_CALL(flush_cache_page, turbosparc_flush_cache_page, BTFIXUPCALL_NORM);
1813 BTFIXUPSET_CALL(flush_cache_range, turbosparc_flush_cache_range, BTFIXUPCALL_NORM);
1815 BTFIXUPSET_CALL(flush_tlb_all, turbosparc_flush_tlb_all, BTFIXUPCALL_NORM);
1816 BTFIXUPSET_CALL(flush_tlb_mm, turbosparc_flush_tlb_mm, BTFIXUPCALL_NORM);
1817 BTFIXUPSET_CALL(flush_tlb_page, turbosparc_flush_tlb_page, BTFIXUPCALL_NORM);
1818 BTFIXUPSET_CALL(flush_tlb_range, turbosparc_flush_tlb_range, BTFIXUPCALL_NORM);
1820 BTFIXUPSET_CALL(__flush_page_to_ram, turbosparc_flush_page_to_ram, BTFIXUPCALL_NORM);
1822 BTFIXUPSET_CALL(flush_sig_insns, turbosparc_flush_sig_insns, BTFIXUPCALL_NOP);
1823 BTFIXUPSET_CALL(flush_page_for_dma, turbosparc_flush_page_for_dma, BTFIXUPCALL_NORM);
1825 poke_srmmu = poke_turbosparc;
1828 static void __init poke_tsunami(void)
1830 unsigned long mreg = srmmu_get_mmureg();
1832 tsunami_flush_icache();
1833 tsunami_flush_dcache();
1834 mreg &= ~TSUNAMI_ITD;
1835 mreg |= (TSUNAMI_IENAB | TSUNAMI_DENAB);
1836 srmmu_set_mmureg(mreg);
1839 static void __init init_tsunami(void)
1842 * Tsunami's pretty sane, Sun and TI actually got it
1843 * somewhat right this time. Fujitsu should have
1844 * taken some lessons from them.
1847 srmmu_name = "TI Tsunami";
1848 srmmu_modtype = Tsunami;
1850 BTFIXUPSET_CALL(flush_cache_all, tsunami_flush_cache_all, BTFIXUPCALL_NORM);
1851 BTFIXUPSET_CALL(flush_cache_mm, tsunami_flush_cache_mm, BTFIXUPCALL_NORM);
1852 BTFIXUPSET_CALL(flush_cache_page, tsunami_flush_cache_page, BTFIXUPCALL_NORM);
1853 BTFIXUPSET_CALL(flush_cache_range, tsunami_flush_cache_range, BTFIXUPCALL_NORM);
1856 BTFIXUPSET_CALL(flush_tlb_all, tsunami_flush_tlb_all, BTFIXUPCALL_NORM);
1857 BTFIXUPSET_CALL(flush_tlb_mm, tsunami_flush_tlb_mm, BTFIXUPCALL_NORM);
1858 BTFIXUPSET_CALL(flush_tlb_page, tsunami_flush_tlb_page, BTFIXUPCALL_NORM);
1859 BTFIXUPSET_CALL(flush_tlb_range, tsunami_flush_tlb_range, BTFIXUPCALL_NORM);
1861 BTFIXUPSET_CALL(__flush_page_to_ram, tsunami_flush_page_to_ram, BTFIXUPCALL_NOP);
1862 BTFIXUPSET_CALL(flush_sig_insns, tsunami_flush_sig_insns, BTFIXUPCALL_NORM);
1863 BTFIXUPSET_CALL(flush_page_for_dma, tsunami_flush_page_for_dma, BTFIXUPCALL_NORM);
1865 poke_srmmu = poke_tsunami;
1867 tsunami_setup_blockops();
1870 static void __init poke_viking(void)
1872 unsigned long mreg = srmmu_get_mmureg();
1873 static int smp_catch;
1875 if(viking_mxcc_present) {
1876 unsigned long mxcc_control = mxcc_get_creg();
1878 mxcc_control |= (MXCC_CTL_ECE | MXCC_CTL_PRE | MXCC_CTL_MCE);
1879 mxcc_control &= ~(MXCC_CTL_RRC);
1880 mxcc_set_creg(mxcc_control);
1883 * We don't need memory parity checks.
1884 * XXX This is a mess, have to dig out later. ecd.
1885 viking_mxcc_turn_off_parity(&mreg, &mxcc_control);
1888 /* We do cache ptables on MXCC. */
1889 mreg |= VIKING_TCENABLE;
1891 unsigned long bpreg;
1893 mreg &= ~(VIKING_TCENABLE);
1895 /* Must disable mixed-cmd mode here for other cpu's. */
1896 bpreg = viking_get_bpreg();
1897 bpreg &= ~(VIKING_ACTION_MIX);
1898 viking_set_bpreg(bpreg);
1900 /* Just in case PROM does something funny. */
1905 mreg |= VIKING_SPENABLE;
1906 mreg |= (VIKING_ICENABLE | VIKING_DCENABLE);
1907 mreg |= VIKING_SBENABLE;
1908 mreg &= ~(VIKING_ACENABLE);
1909 srmmu_set_mmureg(mreg);
1912 /* Avoid unnecessary cross calls. */
1913 BTFIXUPCOPY_CALL(flush_cache_all, local_flush_cache_all);
1914 BTFIXUPCOPY_CALL(flush_cache_mm, local_flush_cache_mm);
1915 BTFIXUPCOPY_CALL(flush_cache_range, local_flush_cache_range);
1916 BTFIXUPCOPY_CALL(flush_cache_page, local_flush_cache_page);
1917 BTFIXUPCOPY_CALL(__flush_page_to_ram, local_flush_page_to_ram);
1918 BTFIXUPCOPY_CALL(flush_sig_insns, local_flush_sig_insns);
1919 BTFIXUPCOPY_CALL(flush_page_for_dma, local_flush_page_for_dma);
1924 static void __init init_viking(void)
1926 unsigned long mreg = srmmu_get_mmureg();
1928 /* Ahhh, the viking. SRMMU VLSI abortion number two... */
1929 if(mreg & VIKING_MMODE) {
1930 srmmu_name = "TI Viking";
1931 viking_mxcc_present = 0;
1934 BTFIXUPSET_CALL(pte_clear, srmmu_pte_clear, BTFIXUPCALL_NORM);
1935 BTFIXUPSET_CALL(pmd_clear, srmmu_pmd_clear, BTFIXUPCALL_NORM);
1936 BTFIXUPSET_CALL(pgd_clear, srmmu_pgd_clear, BTFIXUPCALL_NORM);
1939 * We need this to make sure old viking takes no hits
1940 * on it's cache for dma snoops to workaround the
1941 * "load from non-cacheable memory" interrupt bug.
1942 * This is only necessary because of the new way in
1943 * which we use the IOMMU.
1945 BTFIXUPSET_CALL(flush_page_for_dma, viking_flush_page, BTFIXUPCALL_NORM);
1947 flush_page_for_dma_global = 0;
1949 srmmu_name = "TI Viking/MXCC";
1950 viking_mxcc_present = 1;
1952 srmmu_cache_pagetables = 1;
1954 /* MXCC vikings lack the DMA snooping bug. */
1955 BTFIXUPSET_CALL(flush_page_for_dma, viking_flush_page_for_dma, BTFIXUPCALL_NOP);
1958 BTFIXUPSET_CALL(flush_cache_all, viking_flush_cache_all, BTFIXUPCALL_NORM);
1959 BTFIXUPSET_CALL(flush_cache_mm, viking_flush_cache_mm, BTFIXUPCALL_NORM);
1960 BTFIXUPSET_CALL(flush_cache_page, viking_flush_cache_page, BTFIXUPCALL_NORM);
1961 BTFIXUPSET_CALL(flush_cache_range, viking_flush_cache_range, BTFIXUPCALL_NORM);
1964 if (sparc_cpu_model == sun4d) {
1965 BTFIXUPSET_CALL(flush_tlb_all, sun4dsmp_flush_tlb_all, BTFIXUPCALL_NORM);
1966 BTFIXUPSET_CALL(flush_tlb_mm, sun4dsmp_flush_tlb_mm, BTFIXUPCALL_NORM);
1967 BTFIXUPSET_CALL(flush_tlb_page, sun4dsmp_flush_tlb_page, BTFIXUPCALL_NORM);
1968 BTFIXUPSET_CALL(flush_tlb_range, sun4dsmp_flush_tlb_range, BTFIXUPCALL_NORM);
1972 BTFIXUPSET_CALL(flush_tlb_all, viking_flush_tlb_all, BTFIXUPCALL_NORM);
1973 BTFIXUPSET_CALL(flush_tlb_mm, viking_flush_tlb_mm, BTFIXUPCALL_NORM);
1974 BTFIXUPSET_CALL(flush_tlb_page, viking_flush_tlb_page, BTFIXUPCALL_NORM);
1975 BTFIXUPSET_CALL(flush_tlb_range, viking_flush_tlb_range, BTFIXUPCALL_NORM);
1978 BTFIXUPSET_CALL(__flush_page_to_ram, viking_flush_page_to_ram, BTFIXUPCALL_NOP);
1979 BTFIXUPSET_CALL(flush_sig_insns, viking_flush_sig_insns, BTFIXUPCALL_NOP);
1981 poke_srmmu = poke_viking;
1984 /* Probe for the srmmu chip version. */
1985 static void __init get_srmmu_type(void)
1987 unsigned long mreg, psr;
1988 unsigned long mod_typ, mod_rev, psr_typ, psr_vers;
1990 srmmu_modtype = SRMMU_INVAL_MOD;
1993 mreg = srmmu_get_mmureg(); psr = get_psr();
1994 mod_typ = (mreg & 0xf0000000) >> 28;
1995 mod_rev = (mreg & 0x0f000000) >> 24;
1996 psr_typ = (psr >> 28) & 0xf;
1997 psr_vers = (psr >> 24) & 0xf;
1999 /* First, check for HyperSparc or Cypress. */
2003 /* UP or MP Hypersparc */
2008 /* Uniprocessor Cypress */
2014 /* _REALLY OLD_ Cypress MP chips... */
2018 /* MP Cypress mmu/cache-controller */
2019 init_cypress_605(mod_rev);
2022 /* Some other Cypress revision, assume a 605. */
2023 init_cypress_605(mod_rev);
2030 * Now Fujitsu TurboSparc. It might happen that it is
2031 * in Swift emulation mode, so we will check later...
2033 if (psr_typ == 0 && psr_vers == 5) {
2038 /* Next check for Fujitsu Swift. */
2039 if(psr_typ == 0 && psr_vers == 4) {
2043 /* Look if it is not a TurboSparc emulating Swift... */
2044 cpunode = prom_getchild(prom_root_node);
2045 while((cpunode = prom_getsibling(cpunode)) != 0) {
2046 prom_getstring(cpunode, "device_type", node_str, sizeof(node_str));
2047 if(!strcmp(node_str, "cpu")) {
2048 if (!prom_getintdefault(cpunode, "psr-implementation", 1) &&
2049 prom_getintdefault(cpunode, "psr-version", 1) == 5) {
2061 /* Now the Viking family of srmmu. */
2064 ((psr_vers == 1) && (mod_typ == 0) && (mod_rev == 0)))) {
2069 /* Finally the Tsunami. */
2070 if(psr_typ == 4 && psr_vers == 1 && (mod_typ || mod_rev)) {
2079 /* don't laugh, static pagetables */
2080 static void srmmu_check_pgt_cache(int low, int high)
2084 extern unsigned long spwin_mmu_patchme, fwin_mmu_patchme,
2085 tsetup_mmu_patchme, rtrap_mmu_patchme;
2087 extern unsigned long spwin_srmmu_stackchk, srmmu_fwin_stackchk,
2088 tsetup_srmmu_stackchk, srmmu_rett_stackchk;
2090 extern unsigned long srmmu_fault;
2092 #define PATCH_BRANCH(insn, dest) do { \
2095 *iaddr = SPARC_BRANCH((unsigned long) daddr, (unsigned long) iaddr); \
2098 static void __init patch_window_trap_handlers(void)
2100 unsigned long *iaddr, *daddr;
2102 PATCH_BRANCH(spwin_mmu_patchme, spwin_srmmu_stackchk);
2103 PATCH_BRANCH(fwin_mmu_patchme, srmmu_fwin_stackchk);
2104 PATCH_BRANCH(tsetup_mmu_patchme, tsetup_srmmu_stackchk);
2105 PATCH_BRANCH(rtrap_mmu_patchme, srmmu_rett_stackchk);
2106 PATCH_BRANCH(sparc_ttable[SP_TRAP_TFLT].inst_three, srmmu_fault);
2107 PATCH_BRANCH(sparc_ttable[SP_TRAP_DFLT].inst_three, srmmu_fault);
2108 PATCH_BRANCH(sparc_ttable[SP_TRAP_DACC].inst_three, srmmu_fault);
2112 /* Local cross-calls. */
2113 static void smp_flush_page_for_dma(unsigned long page)
2115 xc1((smpfunc_t) BTFIXUP_CALL(local_flush_page_for_dma), page);
2116 local_flush_page_for_dma(page);
2121 static pte_t srmmu_pgoff_to_pte(unsigned long pgoff)
2123 return __pte((pgoff << SRMMU_PTE_FILE_SHIFT) | SRMMU_FILE);
2126 static unsigned long srmmu_pte_to_pgoff(pte_t pte)
2128 return pte_val(pte) >> SRMMU_PTE_FILE_SHIFT;
2131 /* Load up routines and constants for sun4m and sun4d mmu */
2132 void __init ld_mmu_srmmu(void)
2134 extern void ld_mmu_iommu(void);
2135 extern void ld_mmu_iounit(void);
2136 extern void ___xchg32_sun4md(void);
2138 BTFIXUPSET_SIMM13(pgdir_shift, SRMMU_PGDIR_SHIFT);
2139 BTFIXUPSET_SETHI(pgdir_size, SRMMU_PGDIR_SIZE);
2140 BTFIXUPSET_SETHI(pgdir_mask, SRMMU_PGDIR_MASK);
2142 BTFIXUPSET_SIMM13(ptrs_per_pmd, SRMMU_PTRS_PER_PMD);
2143 BTFIXUPSET_SIMM13(ptrs_per_pgd, SRMMU_PTRS_PER_PGD);
2145 BTFIXUPSET_INT(page_none, pgprot_val(SRMMU_PAGE_NONE));
2146 BTFIXUPSET_INT(page_shared, pgprot_val(SRMMU_PAGE_SHARED));
2147 BTFIXUPSET_INT(page_copy, pgprot_val(SRMMU_PAGE_COPY));
2148 BTFIXUPSET_INT(page_readonly, pgprot_val(SRMMU_PAGE_RDONLY));
2149 BTFIXUPSET_INT(page_kernel, pgprot_val(SRMMU_PAGE_KERNEL));
2150 page_kernel = pgprot_val(SRMMU_PAGE_KERNEL);
2151 pg_iobits = SRMMU_VALID | SRMMU_WRITE | SRMMU_REF;
2155 BTFIXUPSET_CALL(___xchg32, ___xchg32_sun4md, BTFIXUPCALL_SWAPG1G2);
2157 BTFIXUPSET_CALL(do_check_pgt_cache, srmmu_check_pgt_cache, BTFIXUPCALL_NOP);
2159 BTFIXUPSET_CALL(set_pte, srmmu_set_pte, BTFIXUPCALL_SWAPO0O1);
2160 BTFIXUPSET_CALL(switch_mm, srmmu_switch_mm, BTFIXUPCALL_NORM);
2162 BTFIXUPSET_CALL(pte_pfn, srmmu_pte_pfn, BTFIXUPCALL_NORM);
2163 BTFIXUPSET_CALL(pmd_page, srmmu_pmd_page, BTFIXUPCALL_NORM);
2164 BTFIXUPSET_CALL(pgd_page, srmmu_pgd_page, BTFIXUPCALL_NORM);
2166 BTFIXUPSET_SETHI(none_mask, 0xF0000000);
2168 BTFIXUPSET_CALL(pte_present, srmmu_pte_present, BTFIXUPCALL_NORM);
2169 BTFIXUPSET_CALL(pte_clear, srmmu_pte_clear, BTFIXUPCALL_SWAPO0G0);
2171 BTFIXUPSET_CALL(pmd_bad, srmmu_pmd_bad, BTFIXUPCALL_NORM);
2172 BTFIXUPSET_CALL(pmd_present, srmmu_pmd_present, BTFIXUPCALL_NORM);
2173 BTFIXUPSET_CALL(pmd_clear, srmmu_pmd_clear, BTFIXUPCALL_SWAPO0G0);
2175 BTFIXUPSET_CALL(pgd_none, srmmu_pgd_none, BTFIXUPCALL_NORM);
2176 BTFIXUPSET_CALL(pgd_bad, srmmu_pgd_bad, BTFIXUPCALL_NORM);
2177 BTFIXUPSET_CALL(pgd_present, srmmu_pgd_present, BTFIXUPCALL_NORM);
2178 BTFIXUPSET_CALL(pgd_clear, srmmu_pgd_clear, BTFIXUPCALL_SWAPO0G0);
2180 BTFIXUPSET_CALL(mk_pte, srmmu_mk_pte, BTFIXUPCALL_NORM);
2181 BTFIXUPSET_CALL(mk_pte_phys, srmmu_mk_pte_phys, BTFIXUPCALL_NORM);
2182 BTFIXUPSET_CALL(mk_pte_io, srmmu_mk_pte_io, BTFIXUPCALL_NORM);
2183 BTFIXUPSET_CALL(pgd_set, srmmu_pgd_set, BTFIXUPCALL_NORM);
2184 BTFIXUPSET_CALL(pmd_set, srmmu_pmd_set, BTFIXUPCALL_NORM);
2185 BTFIXUPSET_CALL(pmd_populate, srmmu_pmd_populate, BTFIXUPCALL_NORM);
2187 BTFIXUPSET_INT(pte_modify_mask, SRMMU_CHG_MASK);
2188 BTFIXUPSET_CALL(pmd_offset, srmmu_pmd_offset, BTFIXUPCALL_NORM);
2189 BTFIXUPSET_CALL(pte_offset_kernel, srmmu_pte_offset, BTFIXUPCALL_NORM);
2191 BTFIXUPSET_CALL(free_pte_fast, srmmu_free_pte_fast, BTFIXUPCALL_NORM);
2192 BTFIXUPSET_CALL(pte_free, srmmu_pte_free, BTFIXUPCALL_NORM);
2193 BTFIXUPSET_CALL(pte_alloc_one_kernel, srmmu_pte_alloc_one_kernel, BTFIXUPCALL_NORM);
2194 BTFIXUPSET_CALL(pte_alloc_one, srmmu_pte_alloc_one, BTFIXUPCALL_NORM);
2195 BTFIXUPSET_CALL(free_pmd_fast, srmmu_pmd_free, BTFIXUPCALL_NORM);
2196 BTFIXUPSET_CALL(pmd_alloc_one, srmmu_pmd_alloc_one, BTFIXUPCALL_NORM);
2197 BTFIXUPSET_CALL(free_pgd_fast, srmmu_free_pgd_fast, BTFIXUPCALL_NORM);
2198 BTFIXUPSET_CALL(get_pgd_fast, srmmu_get_pgd_fast, BTFIXUPCALL_NORM);
2200 BTFIXUPSET_HALF(pte_writei, SRMMU_WRITE);
2201 BTFIXUPSET_HALF(pte_dirtyi, SRMMU_DIRTY);
2202 BTFIXUPSET_HALF(pte_youngi, SRMMU_REF);
2203 BTFIXUPSET_HALF(pte_filei, SRMMU_FILE);
2204 BTFIXUPSET_HALF(pte_wrprotecti, SRMMU_WRITE);
2205 BTFIXUPSET_HALF(pte_mkcleani, SRMMU_DIRTY);
2206 BTFIXUPSET_HALF(pte_mkoldi, SRMMU_REF);
2207 BTFIXUPSET_CALL(pte_mkwrite, srmmu_pte_mkwrite, BTFIXUPCALL_ORINT(SRMMU_WRITE));
2208 BTFIXUPSET_CALL(pte_mkdirty, srmmu_pte_mkdirty, BTFIXUPCALL_ORINT(SRMMU_DIRTY));
2209 BTFIXUPSET_CALL(pte_mkyoung, srmmu_pte_mkyoung, BTFIXUPCALL_ORINT(SRMMU_REF));
2210 BTFIXUPSET_CALL(update_mmu_cache, srmmu_update_mmu_cache, BTFIXUPCALL_NOP);
2211 BTFIXUPSET_CALL(destroy_context, srmmu_destroy_context, BTFIXUPCALL_NORM);
2213 BTFIXUPSET_CALL(sparc_mapiorange, srmmu_mapiorange, BTFIXUPCALL_NORM);
2214 BTFIXUPSET_CALL(sparc_unmapiorange, srmmu_unmapiorange, BTFIXUPCALL_NORM);
2216 BTFIXUPSET_CALL(__swp_type, srmmu_swp_type, BTFIXUPCALL_NORM);
2217 BTFIXUPSET_CALL(__swp_offset, srmmu_swp_offset, BTFIXUPCALL_NORM);
2218 BTFIXUPSET_CALL(__swp_entry, srmmu_swp_entry, BTFIXUPCALL_NORM);
2220 BTFIXUPSET_CALL(mmu_info, srmmu_mmu_info, BTFIXUPCALL_NORM);
2222 BTFIXUPSET_CALL(alloc_thread_info, srmmu_alloc_thread_info, BTFIXUPCALL_NORM);
2223 BTFIXUPSET_CALL(free_thread_info, srmmu_free_thread_info, BTFIXUPCALL_NORM);
2225 BTFIXUPSET_CALL(pte_to_pgoff, srmmu_pte_to_pgoff, BTFIXUPCALL_NORM);
2226 BTFIXUPSET_CALL(pgoff_to_pte, srmmu_pgoff_to_pte, BTFIXUPCALL_NORM);
2229 patch_window_trap_handlers();
2232 /* El switcheroo... */
2234 BTFIXUPCOPY_CALL(local_flush_cache_all, flush_cache_all);
2235 BTFIXUPCOPY_CALL(local_flush_cache_mm, flush_cache_mm);
2236 BTFIXUPCOPY_CALL(local_flush_cache_range, flush_cache_range);
2237 BTFIXUPCOPY_CALL(local_flush_cache_page, flush_cache_page);
2238 BTFIXUPCOPY_CALL(local_flush_tlb_all, flush_tlb_all);
2239 BTFIXUPCOPY_CALL(local_flush_tlb_mm, flush_tlb_mm);
2240 BTFIXUPCOPY_CALL(local_flush_tlb_range, flush_tlb_range);
2241 BTFIXUPCOPY_CALL(local_flush_tlb_page, flush_tlb_page);
2242 BTFIXUPCOPY_CALL(local_flush_page_to_ram, __flush_page_to_ram);
2243 BTFIXUPCOPY_CALL(local_flush_sig_insns, flush_sig_insns);
2244 BTFIXUPCOPY_CALL(local_flush_page_for_dma, flush_page_for_dma);
2246 BTFIXUPSET_CALL(flush_cache_all, smp_flush_cache_all, BTFIXUPCALL_NORM);
2247 BTFIXUPSET_CALL(flush_cache_mm, smp_flush_cache_mm, BTFIXUPCALL_NORM);
2248 BTFIXUPSET_CALL(flush_cache_range, smp_flush_cache_range, BTFIXUPCALL_NORM);
2249 BTFIXUPSET_CALL(flush_cache_page, smp_flush_cache_page, BTFIXUPCALL_NORM);
2250 if (sparc_cpu_model != sun4d) {
2251 BTFIXUPSET_CALL(flush_tlb_all, smp_flush_tlb_all, BTFIXUPCALL_NORM);
2252 BTFIXUPSET_CALL(flush_tlb_mm, smp_flush_tlb_mm, BTFIXUPCALL_NORM);
2253 BTFIXUPSET_CALL(flush_tlb_range, smp_flush_tlb_range, BTFIXUPCALL_NORM);
2254 BTFIXUPSET_CALL(flush_tlb_page, smp_flush_tlb_page, BTFIXUPCALL_NORM);
2256 BTFIXUPSET_CALL(__flush_page_to_ram, smp_flush_page_to_ram, BTFIXUPCALL_NORM);
2257 BTFIXUPSET_CALL(flush_sig_insns, smp_flush_sig_insns, BTFIXUPCALL_NORM);
2258 BTFIXUPSET_CALL(flush_page_for_dma, smp_flush_page_for_dma, BTFIXUPCALL_NORM);
2261 if (sparc_cpu_model == sun4d)
2266 if (sparc_cpu_model == sun4d)