1 /* $Id: etrap.S,v 1.46 2002/02/09 19:49:30 davem Exp $
2 * etrap.S: Preparing for entry into the kernel on Sparc V9.
4 * Copyright (C) 1996, 1997 David S. Miller (davem@caip.rutgers.edu)
5 * Copyright (C) 1997, 1998, 1999 Jakub Jelinek (jj@ultra.linux.cz)
8 #include <linux/config.h>
11 #include <asm/pstate.h>
12 #include <asm/ptrace.h>
14 #include <asm/spitfire.h>
16 #include <asm/processor.h>
18 #define TASK_REGOFF (THREAD_SIZE-TRACEREG_SZ-STACKFRAME_SZ)
19 #define ETRAP_PSTATE1 (PSTATE_RMO | PSTATE_PRIV)
20 #define ETRAP_PSTATE2 (PSTATE_RMO | PSTATE_PEF | PSTATE_PRIV | PSTATE_IE)
23 * On entry, %g7 is return address - 0x4.
24 * %g4 and %g5 will be preserved %l4 and %l5 respectively.
29 .globl etrap, etrap_irq, etraptl1
30 etrap: rdpr %pil, %g2 ! Single Group
32 rdpr %tstate, %g1 ! Single Group
33 sllx %g2, 20, %g3 ! IEU0 Group
34 andcc %g1, TSTATE_PRIV, %g0 ! IEU1
35 or %g1, %g3, %g1 ! IEU0 Group
37 sub %sp, STACKFRAME_SZ+TRACEREG_SZ-STACK_BIAS, %g2 ! IEU1
38 wrpr %g0, 7, %cleanwin ! Single Group+4bubbles
40 sethi %hi(TASK_REGOFF), %g2 ! IEU0 Group
41 sethi %hi(TSTATE_PEF), %g3 ! IEU1
42 or %g2, %lo(TASK_REGOFF), %g2 ! IEU0 Group
43 and %g1, %g3, %g3 ! IEU1
44 brnz,pn %g3, 1f ! CTI+IEU1 Group
45 add %g6, %g2, %g2 ! IEU0
46 wr %g0, 0, %fprs ! Single Group+4bubbles
47 1: rdpr %tpc, %g3 ! Single Group
49 stx %g1, [%g2 + STACKFRAME_SZ + PT_V9_TSTATE] ! Store Group
50 rdpr %tnpc, %g1 ! Single Group
51 stx %g3, [%g2 + STACKFRAME_SZ + PT_V9_TPC] ! Store Group
52 rd %y, %g3 ! Single Group+4bubbles
53 stx %g1, [%g2 + STACKFRAME_SZ + PT_V9_TNPC] ! Store Group
54 st %g3, [%g2 + STACKFRAME_SZ + PT_V9_Y] ! Store Group
55 save %g2, -STACK_BIAS, %sp ! Ordering here is critical ! Single Group
56 mov %g6, %l6 ! IEU0 Group
59 mov PRIMARY_CONTEXT, %l4 ! IEU1
60 rdpr %canrestore, %g3 ! Single Group+4bubbles
61 rdpr %wstate, %g2 ! Single Group+4bubbles
62 wrpr %g0, 0, %canrestore ! Single Group+4bubbles
63 sll %g2, 3, %g2 ! IEU0 Group
65 stb %l5, [%l6 + TI_FPDEPTH] ! Store
67 wrpr %g3, 0, %otherwin ! Single Group+4bubbles
68 wrpr %g2, 0, %wstate ! Single Group+4bubbles
69 stxa %g0, [%l4] ASI_DMMU ! Store Group
70 flush %l6 ! Single Group+9bubbles
71 wr %g0, ASI_AIUS, %asi ! Single Group+4bubbles
72 2: wrpr %g0, 0x0, %tl ! Single Group+4bubbles
74 mov %g5, %l5 ! IEU0 Group
77 wrpr %g0, ETRAP_PSTATE1, %pstate ! Single Group+4bubbles
78 stx %g1, [%sp + PTREGS_OFF + PT_V9_G1] ! Store Group
79 stx %g2, [%sp + PTREGS_OFF + PT_V9_G2] ! Store Group
80 stx %g3, [%sp + PTREGS_OFF + PT_V9_G3] ! Store Group
81 stx %g4, [%sp + PTREGS_OFF + PT_V9_G4] ! Store Group
82 stx %g5, [%sp + PTREGS_OFF + PT_V9_G5] ! Store Group
83 stx %g6, [%sp + PTREGS_OFF + PT_V9_G6] ! Store Group
85 stx %g7, [%sp + PTREGS_OFF + PT_V9_G7] ! Store Group
86 stx %i0, [%sp + PTREGS_OFF + PT_V9_I0] ! Store Group
87 stx %i1, [%sp + PTREGS_OFF + PT_V9_I1] ! Store Group
88 stx %i2, [%sp + PTREGS_OFF + PT_V9_I2] ! Store Group
89 stx %i3, [%sp + PTREGS_OFF + PT_V9_I3] ! Store Group
90 stx %i4, [%sp + PTREGS_OFF + PT_V9_I4] ! Store Group
91 stx %i5, [%sp + PTREGS_OFF + PT_V9_I5] ! Store Group
93 stx %i6, [%sp + PTREGS_OFF + PT_V9_I6] ! Store Group
94 stx %i7, [%sp + PTREGS_OFF + PT_V9_I7] ! Store Group
95 wrpr %g0, ETRAP_PSTATE2, %pstate ! Single Group+4bubbles
97 jmpl %l2 + 0x4, %g0 ! CTI Group
98 ldx [%g6 + TI_TASK], %g4 ! Load
103 3: ldub [%l6 + TI_FPDEPTH], %l5 ! Load Group
104 add %l6, TI_FPSAVED + 1, %l4 ! IEU0
105 srl %l5, 1, %l3 ! IEU0 Group
106 add %l5, 2, %l5 ! IEU1
107 stb %l5, [%l6 + TI_FPDEPTH] ! Store
109 stb %g0, [%l4 + %l3] ! Store Group
112 etraptl1: /* Save tstate/tpc/tnpc of TL 1-->4 and the tl register itself.
113 * We place this right after pt_regs on the trap stack. The layout
123 sub %sp, ((4 * 8) * 4) + 8, %g2
128 stx %g3, [%g2 + STACK_BIAS + 0x00]
130 stx %g3, [%g2 + STACK_BIAS + 0x08]
132 stx %g3, [%g2 + STACK_BIAS + 0x10]
134 stx %g3, [%g2 + STACK_BIAS + 0x18]
138 stx %g3, [%g2 + STACK_BIAS + 0x20]
140 stx %g3, [%g2 + STACK_BIAS + 0x28]
142 stx %g3, [%g2 + STACK_BIAS + 0x30]
144 stx %g3, [%g2 + STACK_BIAS + 0x38]
148 stx %g3, [%g2 + STACK_BIAS + 0x40]
150 stx %g3, [%g2 + STACK_BIAS + 0x48]
152 stx %g3, [%g2 + STACK_BIAS + 0x50]
154 stx %g3, [%g2 + STACK_BIAS + 0x58]
158 stx %g3, [%g2 + STACK_BIAS + 0x60]
160 stx %g3, [%g2 + STACK_BIAS + 0x68]
162 stx %g3, [%g2 + STACK_BIAS + 0x70]
164 stx %g3, [%g2 + STACK_BIAS + 0x78]
167 stx %g1, [%g2 + STACK_BIAS + 0x80]
169 rdpr %tstate, %g1 ! Single Group+4bubbles
170 sub %g2, STACKFRAME_SZ + TRACEREG_SZ - STACK_BIAS, %g2 ! IEU1
171 ba,pt %xcc, 1b ! CTI Group
172 andcc %g1, TSTATE_PRIV, %g0 ! IEU0
176 scetrap: rdpr %pil, %g2 ! Single Group
177 rdpr %tstate, %g1 ! Single Group
178 sllx %g2, 20, %g3 ! IEU0 Group
179 andcc %g1, TSTATE_PRIV, %g0 ! IEU1
180 or %g1, %g3, %g1 ! IEU0 Group
181 bne,pn %xcc, 1f ! CTI
182 sub %sp, (STACKFRAME_SZ+TRACEREG_SZ-STACK_BIAS), %g2 ! IEU1
183 wrpr %g0, 7, %cleanwin ! Single Group+4bubbles
185 sllx %g1, 51, %g3 ! IEU0 Group
186 sethi %hi(TASK_REGOFF), %g2 ! IEU1
187 or %g2, %lo(TASK_REGOFF), %g2 ! IEU0 Group
188 brlz,pn %g3, 1f ! CTI+IEU1
189 add %g6, %g2, %g2 ! IEU0 Group
190 wr %g0, 0, %fprs ! Single Group+4bubbles
191 1: rdpr %tpc, %g3 ! Single Group
192 stx %g1, [%g2 + STACKFRAME_SZ + PT_V9_TSTATE] ! Store Group
194 rdpr %tnpc, %g1 ! Single Group
195 stx %g3, [%g2 + STACKFRAME_SZ + PT_V9_TPC] ! Store Group
196 stx %g1, [%g2 + STACKFRAME_SZ + PT_V9_TNPC] ! Store Group
197 save %g2, -STACK_BIAS, %sp ! Ordering here is critical ! Single Group
198 mov %g6, %l6 ! IEU0 Group
199 bne,pn %xcc, 2f ! CTI
200 mov ASI_P, %l7 ! IEU1
201 rdpr %canrestore, %g3 ! Single Group+4bubbles
203 rdpr %wstate, %g2 ! Single Group+4bubbles
204 wrpr %g0, 0, %canrestore ! Single Group+4bubbles
205 sll %g2, 3, %g2 ! IEU0 Group
206 mov PRIMARY_CONTEXT, %l4 ! IEU1
207 wrpr %g3, 0, %otherwin ! Single Group+4bubbles
208 wrpr %g2, 0, %wstate ! Single Group+4bubbles
209 stxa %g0, [%l4] ASI_DMMU ! Store
210 flush %l6 ! Single Group+9bubbles
212 mov ASI_AIUS, %l7 ! IEU0 Group
213 2: mov %g4, %l4 ! IEU1
214 mov %g5, %l5 ! IEU0 Group
215 add %g7, 0x4, %l2 ! IEU1
216 wrpr %g0, ETRAP_PSTATE1, %pstate ! Single Group+4bubbles
217 stx %g1, [%sp + PTREGS_OFF + PT_V9_G1] ! Store Group
218 stx %g2, [%sp + PTREGS_OFF + PT_V9_G2] ! Store Group
219 sllx %l7, 24, %l7 ! IEU0
221 stx %g3, [%sp + PTREGS_OFF + PT_V9_G3] ! Store Group
222 rdpr %cwp, %l0 ! Single Group
223 stx %g4, [%sp + PTREGS_OFF + PT_V9_G4] ! Store Group
224 stx %g5, [%sp + PTREGS_OFF + PT_V9_G5] ! Store Group
225 stx %g6, [%sp + PTREGS_OFF + PT_V9_G6] ! Store Group
226 stx %g7, [%sp + PTREGS_OFF + PT_V9_G7] ! Store Group
227 or %l7, %l0, %l7 ! IEU0
228 sethi %hi(TSTATE_RMO | TSTATE_PEF), %l0 ! IEU1
230 or %l7, %l0, %l7 ! IEU0 Group
231 wrpr %l2, %tnpc ! Single Group+4bubbles
232 wrpr %l7, (TSTATE_PRIV | TSTATE_IE), %tstate ! Single Group+4bubbles
233 stx %i0, [%sp + PTREGS_OFF + PT_V9_I0] ! Store Group
234 stx %i1, [%sp + PTREGS_OFF + PT_V9_I1] ! Store Group
235 stx %i2, [%sp + PTREGS_OFF + PT_V9_I2] ! Store Group
236 stx %i3, [%sp + PTREGS_OFF + PT_V9_I3] ! Store Group
237 stx %i4, [%sp + PTREGS_OFF + PT_V9_I4] ! Store Group
239 stx %i5, [%sp + PTREGS_OFF + PT_V9_I5] ! Store Group
240 stx %i6, [%sp + PTREGS_OFF + PT_V9_I6] ! Store Group
242 stx %i7, [%sp + PTREGS_OFF + PT_V9_I7] ! Store Group
243 ldx [%g6 + TI_TASK], %g4 ! Load Group