1 /* $Id: etrap.S,v 1.46 2002/02/09 19:49:30 davem Exp $
2 * etrap.S: Preparing for entry into the kernel on Sparc V9.
4 * Copyright (C) 1996, 1997 David S. Miller (davem@caip.rutgers.edu)
5 * Copyright (C) 1997, 1998, 1999 Jakub Jelinek (jj@ultra.linux.cz)
8 #include <linux/config.h>
11 #include <asm/pstate.h>
12 #include <asm/ptrace.h>
14 #include <asm/spitfire.h>
16 #include <asm/processor.h>
18 #define TASK_REGOFF (THREAD_SIZE-TRACEREG_SZ-STACKFRAME_SZ)
19 #define ETRAP_PSTATE1 (PSTATE_RMO | PSTATE_PRIV)
20 #define ETRAP_PSTATE2 \
21 (PSTATE_RMO | PSTATE_PEF | PSTATE_PRIV | PSTATE_IE)
24 * On entry, %g7 is return address - 0x4.
25 * %g4 and %g5 will be preserved %l4 and %l5 respectively.
30 .globl etrap, etrap_irq, etraptl1
35 andcc %g1, TSTATE_PRIV, %g0
38 sub %sp, STACKFRAME_SZ+TRACEREG_SZ-STACK_BIAS, %g2
39 wrpr %g0, 7, %cleanwin
41 sethi %hi(TASK_REGOFF), %g2
42 sethi %hi(TSTATE_PEF), %g3
43 or %g2, %lo(TASK_REGOFF), %g2
50 stx %g1, [%g2 + STACKFRAME_SZ + PT_V9_TSTATE]
52 stx %g3, [%g2 + STACKFRAME_SZ + PT_V9_TPC]
54 stx %g1, [%g2 + STACKFRAME_SZ + PT_V9_TNPC]
55 st %g3, [%g2 + STACKFRAME_SZ + PT_V9_Y]
56 save %g2, -STACK_BIAS, %sp ! Ordering here is critical
60 mov PRIMARY_CONTEXT, %l4
63 wrpr %g0, 0, %canrestore
66 stb %l5, [%l6 + TI_FPDEPTH]
68 wrpr %g3, 0, %otherwin
70 stxa %g0, [%l4] ASI_DMMU
72 wr %g0, ASI_AIUS, %asi
78 wrpr %g0, ETRAP_PSTATE1, %pstate
79 stx %g1, [%sp + PTREGS_OFF + PT_V9_G1]
80 stx %g2, [%sp + PTREGS_OFF + PT_V9_G2]
81 stx %g3, [%sp + PTREGS_OFF + PT_V9_G3]
82 stx %g4, [%sp + PTREGS_OFF + PT_V9_G4]
83 stx %g5, [%sp + PTREGS_OFF + PT_V9_G5]
84 stx %g6, [%sp + PTREGS_OFF + PT_V9_G6]
86 stx %g7, [%sp + PTREGS_OFF + PT_V9_G7]
87 stx %i0, [%sp + PTREGS_OFF + PT_V9_I0]
88 stx %i1, [%sp + PTREGS_OFF + PT_V9_I1]
89 stx %i2, [%sp + PTREGS_OFF + PT_V9_I2]
90 stx %i3, [%sp + PTREGS_OFF + PT_V9_I3]
91 stx %i4, [%sp + PTREGS_OFF + PT_V9_I4]
92 stx %i5, [%sp + PTREGS_OFF + PT_V9_I5]
94 stx %i6, [%sp + PTREGS_OFF + PT_V9_I6]
95 stx %i7, [%sp + PTREGS_OFF + PT_V9_I7]
96 wrpr %g0, ETRAP_PSTATE2, %pstate
99 ldx [%g6 + TI_TASK], %g4
104 3: ldub [%l6 + TI_FPDEPTH], %l5
105 add %l6, TI_FPSAVED + 1, %l4
108 stb %l5, [%l6 + TI_FPDEPTH]
113 etraptl1: /* Save tstate/tpc/tnpc of TL 1-->4 and the tl register itself.
114 * We place this right after pt_regs on the trap stack.
124 sub %sp, ((4 * 8) * 4) + 8, %g2
129 stx %g3, [%g2 + STACK_BIAS + 0x00]
131 stx %g3, [%g2 + STACK_BIAS + 0x08]
133 stx %g3, [%g2 + STACK_BIAS + 0x10]
135 stx %g3, [%g2 + STACK_BIAS + 0x18]
139 stx %g3, [%g2 + STACK_BIAS + 0x20]
141 stx %g3, [%g2 + STACK_BIAS + 0x28]
143 stx %g3, [%g2 + STACK_BIAS + 0x30]
145 stx %g3, [%g2 + STACK_BIAS + 0x38]
149 stx %g3, [%g2 + STACK_BIAS + 0x40]
151 stx %g3, [%g2 + STACK_BIAS + 0x48]
153 stx %g3, [%g2 + STACK_BIAS + 0x50]
155 stx %g3, [%g2 + STACK_BIAS + 0x58]
159 stx %g3, [%g2 + STACK_BIAS + 0x60]
161 stx %g3, [%g2 + STACK_BIAS + 0x68]
163 stx %g3, [%g2 + STACK_BIAS + 0x70]
165 stx %g3, [%g2 + STACK_BIAS + 0x78]
168 stx %g1, [%g2 + STACK_BIAS + 0x80]
171 sub %g2, STACKFRAME_SZ + TRACEREG_SZ - STACK_BIAS, %g2
173 andcc %g1, TSTATE_PRIV, %g0
177 scetrap: rdpr %pil, %g2
180 andcc %g1, TSTATE_PRIV, %g0
183 sub %sp, (STACKFRAME_SZ+TRACEREG_SZ-STACK_BIAS), %g2
184 wrpr %g0, 7, %cleanwin
187 sethi %hi(TASK_REGOFF), %g2
188 or %g2, %lo(TASK_REGOFF), %g2
193 stx %g1, [%g2 + STACKFRAME_SZ + PT_V9_TSTATE]
196 stx %g3, [%g2 + STACKFRAME_SZ + PT_V9_TPC]
197 stx %g1, [%g2 + STACKFRAME_SZ + PT_V9_TNPC]
198 save %g2, -STACK_BIAS, %sp ! Ordering here is critical
202 rdpr %canrestore, %g3
205 wrpr %g0, 0, %canrestore
207 mov PRIMARY_CONTEXT, %l4
208 wrpr %g3, 0, %otherwin
210 stxa %g0, [%l4] ASI_DMMU
217 wrpr %g0, ETRAP_PSTATE1, %pstate
218 stx %g1, [%sp + PTREGS_OFF + PT_V9_G1]
219 stx %g2, [%sp + PTREGS_OFF + PT_V9_G2]
222 stx %g3, [%sp + PTREGS_OFF + PT_V9_G3]
224 stx %g4, [%sp + PTREGS_OFF + PT_V9_G4]
225 stx %g5, [%sp + PTREGS_OFF + PT_V9_G5]
226 stx %g6, [%sp + PTREGS_OFF + PT_V9_G6]
227 stx %g7, [%sp + PTREGS_OFF + PT_V9_G7]
229 sethi %hi(TSTATE_RMO | TSTATE_PEF), %l0
233 wrpr %l7, (TSTATE_PRIV | TSTATE_IE), %tstate
234 stx %i0, [%sp + PTREGS_OFF + PT_V9_I0]
235 stx %i1, [%sp + PTREGS_OFF + PT_V9_I1]
236 stx %i2, [%sp + PTREGS_OFF + PT_V9_I2]
237 stx %i3, [%sp + PTREGS_OFF + PT_V9_I3]
238 stx %i4, [%sp + PTREGS_OFF + PT_V9_I4]
240 stx %i5, [%sp + PTREGS_OFF + PT_V9_I5]
241 stx %i6, [%sp + PTREGS_OFF + PT_V9_I6]
243 stx %i7, [%sp + PTREGS_OFF + PT_V9_I7]
244 ldx [%g6 + TI_TASK], %g4