1 /* $Id: head.S,v 1.87 2002/02/09 19:49:31 davem Exp $
2 * head.S: Initial boot code for the Sparc64 port of Linux.
4 * Copyright (C) 1996,1997 David S. Miller (davem@caip.rutgers.edu)
5 * Copyright (C) 1996 David Sitsky (David.Sitsky@anu.edu.au)
6 * Copyright (C) 1997,1998 Jakub Jelinek (jj@sunsite.mff.cuni.cz)
7 * Copyright (C) 1997 Miguel de Icaza (miguel@nuclecu.unam.mx)
10 #include <linux/config.h>
11 #include <linux/version.h>
12 #include <linux/errno.h>
13 #include <asm/thread_info.h>
15 #include <asm/pstate.h>
16 #include <asm/ptrace.h>
17 #include <asm/spitfire.h>
19 #include <asm/pgtable.h>
20 #include <asm/errno.h>
21 #include <asm/signal.h>
22 #include <asm/processor.h>
27 #include <asm/ttable.h>
29 /* This section from from _start to sparc64_boot_end should fit into
30 * 0x0000.0000.0040.4000 to 0x0000.0000.0040.8000 and will be sharing space
31 * with bootup_user_stack, which is from 0x0000.0000.0040.4000 to
32 * 0x0000.0000.0040.6000 and empty_bad_page, which is from
33 * 0x0000.0000.0040.6000 to 0x0000.0000.0040.8000.
37 .globl start, _start, stext, _stext
45 flushw /* Flush register file. */
47 /* This stuff has to be in sync with SILO and other potential boot loaders
48 * Fields should be kept upward compatible and whenever any change is made,
49 * HdrS version should be incremented.
51 .global root_flags, ram_flags, root_dev
52 .global sparc_ramdisk_image, sparc_ramdisk_size
53 .global sparc_ramdisk_image64
56 .word LINUX_VERSION_CODE
60 * 0x0300 : Supports being located at other than 0x4000
61 * 0x0202 : Supports kernel params string
62 * 0x0201 : Supports reboot_command
64 .half 0x0301 /* HdrS version */
78 sparc_ramdisk_image64:
82 /* We must be careful, 32-bit OpenBOOT will get confused if it
83 * tries to save away a register window to a 64-bit kernel
84 * stack address. Flush all windows, disable interrupts,
85 * remap if necessary, jump onto kernel trap table, then kernel
86 * stack, or else we die.
88 * PROM entry point is on %o4
91 BRANCH_IF_CHEETAH_BASE(g1,g5,cheetah_boot)
92 BRANCH_IF_CHEETAH_PLUS_OR_FOLLOWON(g1,g5,cheetah_plus_boot)
93 ba,pt %xcc, spitfire_boot
97 /* Preserve OBP chosen DCU and DCR register settings. */
98 ba,pt %xcc, cheetah_generic_boot
102 mov DCR_BPE | DCR_RPE | DCR_SI | DCR_IFPOE | DCR_MS, %g1
105 sethi %uhi(DCU_ME|DCU_RE|DCU_HPE|DCU_SPE|DCU_SL|DCU_WE), %g5
106 or %g5, %ulo(DCU_ME|DCU_RE|DCU_HPE|DCU_SPE|DCU_SL|DCU_WE), %g5
108 or %g5, DCU_DM | DCU_IM | DCU_DC | DCU_IC, %g5
109 stxa %g5, [%g0] ASI_DCU_CONTROL_REG
112 cheetah_generic_boot:
113 mov TSB_EXTENSION_P, %g3
114 stxa %g0, [%g3] ASI_DMMU
115 stxa %g0, [%g3] ASI_IMMU
118 mov TSB_EXTENSION_S, %g3
119 stxa %g0, [%g3] ASI_DMMU
122 mov TSB_EXTENSION_N, %g3
123 stxa %g0, [%g3] ASI_DMMU
124 stxa %g0, [%g3] ASI_IMMU
127 wrpr %g0, (PSTATE_PRIV|PSTATE_PEF|PSTATE_IE), %pstate
130 /* Just like for Spitfire, we probe itlb-2 for a mapping which
131 * matches our current %pc. We take the physical address in
132 * that mapping and use it to make our own.
135 /* %g5 holds the tlb data */
136 sethi %uhi(_PAGE_VALID | _PAGE_SZ4MB), %g5
138 or %g5, (_PAGE_CP | _PAGE_CV | _PAGE_P | _PAGE_L | _PAGE_W | _PAGE_G), %g5
140 /* Put PADDR tlb data mask into %g3. */
141 sethi %uhi(_PAGE_PADDR), %g3
142 or %g3, %ulo(_PAGE_PADDR), %g3
144 sethi %hi(_PAGE_PADDR), %g7
145 or %g7, %lo(_PAGE_PADDR), %g7
148 set 2 << 16, %l0 /* TLB entry walker. */
149 set 0x1fff, %l2 /* Page mask. */
151 andn %l3, %l2, %g2 /* vaddr comparator */
153 1: ldxa [%l0] ASI_ITLB_TAG_READ, %g1
157 be,pn %xcc, cheetah_got_tlbentry
159 and %l0, (127 << 3), %g1
162 add %l0, (1 << 3), %l0
164 /* Search the small TLB. OBP never maps us like that but
169 1: ldxa [%l0] ASI_ITLB_TAG_READ, %g1
173 be,pn %xcc, cheetah_got_tlbentry
177 add %l0, (1 << 3), %l0
179 /* BUG() if we get here... */
182 cheetah_got_tlbentry:
183 ldxa [%l0] ASI_ITLB_DATA_ACCESS, %g0
184 ldxa [%l0] ASI_ITLB_DATA_ACCESS, %g1
191 /* Clear out any KERNBASE area entries. */
193 sethi %hi(KERNBASE), %g3
194 sethi %hi(KERNBASE<<1), %g7
195 mov TLB_TAG_ACCESS, %l7
197 /* First, check ITLB */
198 1: ldxa [%l0] ASI_ITLB_TAG_READ, %g1
206 stxa %g0, [%l7] ASI_IMMU
208 stxa %g0, [%l0] ASI_ITLB_DATA_ACCESS
211 2: and %l0, (127 << 3), %g1
214 add %l0, (1 << 3), %l0
216 /* Next, check DTLB */
218 1: ldxa [%l0] ASI_DTLB_TAG_READ, %g1
226 stxa %g0, [%l7] ASI_DMMU
228 stxa %g0, [%l0] ASI_DTLB_DATA_ACCESS
231 2: and %l0, (511 << 3), %g1
234 add %l0, (1 << 3), %l0
236 /* On Cheetah+, have to check second DTLB. */
237 BRANCH_IF_CHEETAH_PLUS_OR_FOLLOWON(g1,l0,2f)
242 1: ldxa [%l0] ASI_DTLB_TAG_READ, %g1
250 stxa %g0, [%l7] ASI_DMMU
252 stxa %g0, [%l0] ASI_DTLB_DATA_ACCESS
255 2: and %l0, (511 << 3), %g1
258 add %l0, (1 << 3), %l0
262 /* Now lock the TTE we created into ITLB-0 and DTLB-0,
263 * entry 15 (and maybe 14 too).
265 sethi %hi(KERNBASE), %g3
266 set (0 << 16) | (15 << 3), %g7
267 stxa %g3, [%l7] ASI_DMMU
269 stxa %g5, [%g7] ASI_DTLB_DATA_ACCESS
271 stxa %g3, [%l7] ASI_IMMU
273 stxa %g5, [%g7] ASI_ITLB_DATA_ACCESS
277 sethi %hi(_end), %g3 /* Check for bigkernel case */
278 or %g3, %lo(_end), %g3
279 srl %g3, 23, %g3 /* Check if _end > 8M */
281 sethi %hi(KERNBASE), %g3 /* Restore for fixup code below */
282 sethi %hi(0x400000), %g3
283 or %g3, %lo(0x400000), %g3
284 add %g5, %g3, %g5 /* New tte data */
285 andn %g5, (_PAGE_G), %g5
286 sethi %hi(KERNBASE+0x400000), %g3
287 or %g3, %lo(KERNBASE+0x400000), %g3
288 set (0 << 16) | (14 << 3), %g7
289 stxa %g3, [%l7] ASI_DMMU
291 stxa %g5, [%g7] ASI_DTLB_DATA_ACCESS
293 stxa %g3, [%l7] ASI_IMMU
295 stxa %g5, [%g7] ASI_ITLB_DATA_ACCESS
299 sethi %hi(KERNBASE), %g3 /* Restore for fixup code below */
303 1: set sun4u_init, %g2
308 /* Typically PROM has already enabled both MMU's and both on-chip
309 * caches, but we do it here anyway just to be paranoid.
311 mov (LSU_CONTROL_IC|LSU_CONTROL_DC|LSU_CONTROL_IM|LSU_CONTROL_DM), %g1
312 stxa %g1, [%g0] ASI_LSU_CONTROL
316 * Make sure we are in privileged mode, have address masking,
317 * using the ordinary globals and have enabled floating
320 * Again, typically PROM has left %pil at 13 or similar, and
321 * (PSTATE_PRIV | PSTATE_PEF | PSTATE_IE) in %pstate.
323 wrpr %g0, (PSTATE_PRIV|PSTATE_PEF|PSTATE_IE), %pstate
326 spitfire_create_mappings:
327 /* %g5 holds the tlb data */
328 sethi %uhi(_PAGE_VALID | _PAGE_SZ4MB), %g5
330 or %g5, (_PAGE_CP | _PAGE_CV | _PAGE_P | _PAGE_L | _PAGE_W | _PAGE_G), %g5
332 /* Base of physical memory cannot reliably be assumed to be
333 * at 0x0! Figure out where it happens to be. -DaveM
336 /* Put PADDR tlb data mask into %g3. */
337 sethi %uhi(_PAGE_PADDR_SF), %g3
338 or %g3, %ulo(_PAGE_PADDR_SF), %g3
340 sethi %hi(_PAGE_PADDR_SF), %g7
341 or %g7, %lo(_PAGE_PADDR_SF), %g7
344 /* Walk through entire ITLB, looking for entry which maps
345 * our %pc currently, stick PADDR from there into %g5 tlb data.
347 clr %l0 /* TLB entry walker. */
348 set 0x1fff, %l2 /* Page mask. */
350 andn %l3, %l2, %g2 /* vaddr comparator */
352 /* Yes, the nops seem to be necessary for now, don't ask me why. -DaveM */
353 ldxa [%l0] ASI_ITLB_TAG_READ, %g1
357 andn %g1, %l2, %g1 /* Get vaddr */
359 be,a,pn %xcc, spitfire_got_tlbentry
360 ldxa [%l0] ASI_ITLB_DATA_ACCESS, %g1
363 add %l0, (1 << 3), %l0
365 /* BUG() if we get here... */
368 spitfire_got_tlbentry:
369 /* Nops here again, perhaps Cheetah/Blackbird are better behaved... */
373 and %g1, %g3, %g1 /* Mask to just get paddr bits. */
374 set 0x5fff, %l3 /* Mask offset to get phys base. */
377 /* NOTE: We hold on to %g1 paddr base as we need it below to lock
378 * NOTE: the PROM cif code into the TLB.
381 or %g5, %g1, %g5 /* Or it into TAG being built. */
383 clr %l0 /* TLB entry walker. */
384 sethi %hi(KERNBASE), %g3 /* 4M lower limit */
385 sethi %hi(KERNBASE<<1), %g7 /* 8M upper limit */
386 mov TLB_TAG_ACCESS, %l7
388 /* Yes, the nops seem to be necessary for now, don't ask me why. -DaveM */
389 ldxa [%l0] ASI_ITLB_TAG_READ, %g1
393 andn %g1, %l2, %g1 /* Get vaddr */
399 stxa %g0, [%l7] ASI_IMMU
400 stxa %g0, [%l0] ASI_ITLB_DATA_ACCESS
405 add %l0, (1 << 3), %l0
409 clr %l0 /* TLB entry walker. */
411 /* Yes, the nops seem to be necessary for now, don't ask me why. -DaveM */
412 ldxa [%l0] ASI_DTLB_TAG_READ, %g1
416 andn %g1, %l2, %g1 /* Get vaddr */
422 stxa %g0, [%l7] ASI_DMMU
423 stxa %g0, [%l0] ASI_DTLB_DATA_ACCESS
428 add %l0, (1 << 3), %l0
433 /* PROM never puts any TLB entries into the MMU with the lock bit
434 * set. So we gladly use tlb entry 63 for KERNBASE. And maybe 62 too.
437 sethi %hi(KERNBASE), %g3
439 stxa %g3, [%l7] ASI_DMMU /* KERNBASE into TLB TAG */
440 stxa %g5, [%g7] ASI_DTLB_DATA_ACCESS /* TTE into TLB DATA */
442 stxa %g3, [%l7] ASI_IMMU /* KERNBASE into TLB TAG */
443 stxa %g5, [%g7] ASI_ITLB_DATA_ACCESS /* TTE into TLB DATA */
447 sethi %hi(_end), %g3 /* Check for bigkernel case */
448 or %g3, %lo(_end), %g3
449 srl %g3, 23, %g3 /* Check if _end > 8M */
451 sethi %hi(KERNBASE), %g3 /* Restore for fixup code below */
452 sethi %hi(0x400000), %g3
453 or %g3, %lo(0x400000), %g3
454 add %g5, %g3, %g5 /* New tte data */
455 andn %g5, (_PAGE_G), %g5
456 sethi %hi(KERNBASE+0x400000), %g3
457 or %g3, %lo(KERNBASE+0x400000), %g3
459 stxa %g3, [%l7] ASI_DMMU
460 stxa %g5, [%g7] ASI_DTLB_DATA_ACCESS
462 stxa %g3, [%l7] ASI_IMMU
463 stxa %g5, [%g7] ASI_ITLB_DATA_ACCESS
467 sethi %hi(KERNBASE), %g3 /* Restore for fixup code below */
477 mov PRIMARY_CONTEXT, %g7
478 stxa %g0, [%g7] ASI_DMMU
481 mov SECONDARY_CONTEXT, %g7
482 stxa %g0, [%g7] ASI_DMMU
485 /* We are now safely (we hope) in Nucleus context (0), rewrite
486 * the KERNBASE TTE's so they no longer have the global bit set.
487 * Don't forget to setup TAG_ACCESS first 8-)
489 mov TLB_TAG_ACCESS, %g2
490 stxa %g3, [%g2] ASI_IMMU
491 stxa %g3, [%g2] ASI_DMMU
494 BRANCH_IF_ANY_CHEETAH(g1,g5,cheetah_tlb_fixup)
496 ba,pt %xcc, spitfire_tlb_fixup
500 set (0 << 16) | (15 << 3), %g7
501 ldxa [%g7] ASI_ITLB_DATA_ACCESS, %g0
502 ldxa [%g7] ASI_ITLB_DATA_ACCESS, %g1
503 andn %g1, (_PAGE_G), %g1
504 stxa %g1, [%g7] ASI_ITLB_DATA_ACCESS
507 ldxa [%g7] ASI_DTLB_DATA_ACCESS, %g0
508 ldxa [%g7] ASI_DTLB_DATA_ACCESS, %g1
509 andn %g1, (_PAGE_G), %g1
510 stxa %g1, [%g7] ASI_DTLB_DATA_ACCESS
513 /* Kill instruction prefetch queues. */
517 mov 2, %g2 /* Set TLB type to cheetah+. */
518 BRANCH_IF_CHEETAH_PLUS_OR_FOLLOWON(g5,g7,1f)
520 mov 1, %g2 /* Set TLB type to cheetah. */
522 1: sethi %hi(tlb_type), %g5
523 stw %g2, [%g5 + %lo(tlb_type)]
525 /* Patch copy/page operations to cheetah optimized versions. */
526 call cheetah_patch_copyops
528 call cheetah_patch_cachetlbops
531 ba,pt %xcc, tlb_fixup_done
536 ldxa [%g7] ASI_ITLB_DATA_ACCESS, %g1
537 andn %g1, (_PAGE_G), %g1
538 stxa %g1, [%g7] ASI_ITLB_DATA_ACCESS
541 ldxa [%g7] ASI_DTLB_DATA_ACCESS, %g1
542 andn %g1, (_PAGE_G), %g1
543 stxa %g1, [%g7] ASI_DTLB_DATA_ACCESS
546 /* Kill instruction prefetch queues. */
550 /* Set TLB type to spitfire. */
552 sethi %hi(tlb_type), %g5
553 stw %g2, [%g5 + %lo(tlb_type)]
556 sethi %hi(init_thread_union), %g6
557 or %g6, %lo(init_thread_union), %g6
558 ldx [%g6 + TI_TASK], %g4
562 #if 0 /* We don't do it like this anymore, but for historical hack value
563 * I leave this snippet here to show how crazy we can be sometimes. 8-)
566 /* Setup "Linux Current Register", thanks Sun 8-) */
569 /* Blackbird errata workaround. See commentary in
570 * smp.c:smp_percpu_timer_interrupt() for more
576 99: wr %g6, %g0, %pic
582 sllx %g5, THREAD_SHIFT, %g5
583 sub %g5, (STACKFRAME_SZ + STACK_BIAS), %g5
591 sethi %hi(__bss_start), %o0
592 or %o0, %lo(__bss_start), %o0
594 or %o1, %lo(_end), %o1
598 mov %l6, %o1 ! OpenPROM stack
600 mov %l7, %o0 ! OpenPROM cif handler
607 /* IMPORTANT NOTE: Whenever making changes here, check
608 * trampoline.S as well. -jj */
610 setup_tba: /* i0 = is_starfire */
614 sethi %hi(prom_tba), %o1
615 or %o1, %lo(prom_tba), %o1
618 /* Setup "Linux" globals 8-) */
621 wrpr %o1, (PSTATE_AG|PSTATE_IE), %pstate
622 sethi %hi(sparc64_ttable_tl0), %g5
626 /* Set up MMU globals */
627 wrpr %o1, (PSTATE_MG|PSTATE_IE), %pstate
629 /* Set fixed globals used by dTLB miss handler. */
630 #define KERN_HIGHBITS ((_PAGE_VALID|_PAGE_SZ4MB)^0xfffff80000000000)
631 #define KERN_LOWBITS (_PAGE_CP | _PAGE_CV | _PAGE_P | _PAGE_W)
634 stxa %g0, [%g1] ASI_DMMU
637 sethi %uhi(KERN_HIGHBITS), %g2
638 or %g2, %ulo(KERN_HIGHBITS), %g2
640 or %g2, KERN_LOWBITS, %g2
642 BRANCH_IF_ANY_CHEETAH(g3,g7,cheetah_vpte_base)
643 ba,pt %xcc, spitfire_vpte_base
647 sethi %uhi(VPTE_BASE_CHEETAH), %g3
648 or %g3, %ulo(VPTE_BASE_CHEETAH), %g3
653 sethi %uhi(VPTE_BASE_SPITFIRE), %g3
654 or %g3, %ulo(VPTE_BASE_SPITFIRE), %g3
662 /* Kill PROM timer */
663 sethi %hi(0x80000000), %o2
665 wr %o2, 0, %tick_cmpr
667 BRANCH_IF_ANY_CHEETAH(o2,o3,1f)
672 /* Disable STICK_INT interrupts. */
674 sethi %hi(0x80000000), %o2
678 /* Ok, we're done setting up all the state our trap mechanims needs,
679 * now get back into normal globals and let the PROM know what is up.
682 wrpr %g0, %g0, %wstate
683 wrpr %o1, PSTATE_IE, %pstate
685 call init_irqwork_curcpu
688 sethi %hi(sparc64_ttable_tl0), %g5
689 call prom_set_trap_table
693 or %o1, PSTATE_IE, %o1
700 * The following skips make sure the trap table in ttable.S is aligned
701 * on a 32K boundary as required by the v9 specs for TBA register.
704 .skip 0x2000 + _start - sparc64_boot_end
705 bootup_user_stack_end:
709 /* This is just a hack to fool make depend config.h discovering
710 strategy: As the .S files below need config.h, but
711 make depend does not find it for them, we include config.h
721 .globl swapper_pg_dir
727 #include "winfixup.S"
730 /* This is just anal retentiveness on my part... */
735 .globl prom_tba, tlb_type
737 tlb_type: .word 0 /* Must NOT end up in BSS */
738 .section ".fixup",#alloc,#execinstr
742 restore %g0, -EFAULT, %o0