1 /* $Id: pci_schizo.c,v 1.24 2002/01/23 11:27:32 davem Exp $
2 * pci_schizo.c: SCHIZO/TOMATILLO specific PCI controller support.
4 * Copyright (C) 2001, 2002, 2003 David S. Miller (davem@redhat.com)
7 #include <linux/kernel.h>
8 #include <linux/types.h>
10 #include <linux/init.h>
11 #include <linux/slab.h>
12 #include <linux/interrupt.h>
15 #include <asm/iommu.h>
20 #include "iommu_common.h"
22 /* All SCHIZO registers are 64-bits. The following accessor
23 * routines are how they are accessed. The REG parameter
24 * is a physical address.
26 #define schizo_read(__reg) \
28 __asm__ __volatile__("ldxa [%1] %2, %0" \
30 : "r" (__reg), "i" (ASI_PHYS_BYPASS_EC_E) \
34 #define schizo_write(__reg, __val) \
35 __asm__ __volatile__("stxa %0, [%1] %2" \
37 : "r" (__val), "r" (__reg), \
38 "i" (ASI_PHYS_BYPASS_EC_E) \
41 /* This is a convention that at least Excalibur and Merlin
42 * follow. I suppose the SCHIZO used in Starcat and friends
45 * The only way I could see this changing is if the newlink
46 * block requires more space in Schizo's address space than
47 * they predicted, thus requiring an address space reorg when
48 * the newer Schizo is taped out.
51 /* Streaming buffer control register. */
52 #define SCHIZO_STRBUF_CTRL_LPTR 0x00000000000000f0UL /* LRU Lock Pointer */
53 #define SCHIZO_STRBUF_CTRL_LENAB 0x0000000000000008UL /* LRU Lock Enable */
54 #define SCHIZO_STRBUF_CTRL_RRDIS 0x0000000000000004UL /* Rerun Disable */
55 #define SCHIZO_STRBUF_CTRL_DENAB 0x0000000000000002UL /* Diagnostic Mode Enable */
56 #define SCHIZO_STRBUF_CTRL_ENAB 0x0000000000000001UL /* Streaming Buffer Enable */
58 /* IOMMU control register. */
59 #define SCHIZO_IOMMU_CTRL_RESV 0xfffffffff9000000UL /* Reserved */
60 #define SCHIZO_IOMMU_CTRL_XLTESTAT 0x0000000006000000UL /* Translation Error Status */
61 #define SCHIZO_IOMMU_CTRL_XLTEERR 0x0000000001000000UL /* Translation Error encountered */
62 #define SCHIZO_IOMMU_CTRL_LCKEN 0x0000000000800000UL /* Enable translation locking */
63 #define SCHIZO_IOMMU_CTRL_LCKPTR 0x0000000000780000UL /* Translation lock pointer */
64 #define SCHIZO_IOMMU_CTRL_TSBSZ 0x0000000000070000UL /* TSB Size */
65 #define SCHIZO_IOMMU_TSBSZ_1K 0x0000000000000000UL /* TSB Table 1024 8-byte entries */
66 #define SCHIZO_IOMMU_TSBSZ_2K 0x0000000000010000UL /* TSB Table 2048 8-byte entries */
67 #define SCHIZO_IOMMU_TSBSZ_4K 0x0000000000020000UL /* TSB Table 4096 8-byte entries */
68 #define SCHIZO_IOMMU_TSBSZ_8K 0x0000000000030000UL /* TSB Table 8192 8-byte entries */
69 #define SCHIZO_IOMMU_TSBSZ_16K 0x0000000000040000UL /* TSB Table 16k 8-byte entries */
70 #define SCHIZO_IOMMU_TSBSZ_32K 0x0000000000050000UL /* TSB Table 32k 8-byte entries */
71 #define SCHIZO_IOMMU_TSBSZ_64K 0x0000000000060000UL /* TSB Table 64k 8-byte entries */
72 #define SCHIZO_IOMMU_TSBSZ_128K 0x0000000000070000UL /* TSB Table 128k 8-byte entries */
73 #define SCHIZO_IOMMU_CTRL_RESV2 0x000000000000fff8UL /* Reserved */
74 #define SCHIZO_IOMMU_CTRL_TBWSZ 0x0000000000000004UL /* Assumed page size, 0=8k 1=64k */
75 #define SCHIZO_IOMMU_CTRL_DENAB 0x0000000000000002UL /* Diagnostic mode enable */
76 #define SCHIZO_IOMMU_CTRL_ENAB 0x0000000000000001UL /* IOMMU Enable */
78 /* Schizo config space address format is nearly identical to
81 * 32 24 23 16 15 11 10 8 7 2 1 0
82 * ---------------------------------------------------------
83 * |0 0 0 0 0 0 0 0 0| bus | device | function | reg | 0 0 |
84 * ---------------------------------------------------------
86 #define SCHIZO_CONFIG_BASE(PBM) ((PBM)->config_space)
87 #define SCHIZO_CONFIG_ENCODE(BUS, DEVFN, REG) \
88 (((unsigned long)(BUS) << 16) | \
89 ((unsigned long)(DEVFN) << 8) | \
90 ((unsigned long)(REG)))
92 static void *schizo_pci_config_mkaddr(struct pci_pbm_info *pbm,
99 bus -= pbm->pci_first_busno;
101 (SCHIZO_CONFIG_BASE(pbm) |
102 SCHIZO_CONFIG_ENCODE(bus, devfn, where));
105 /* Just make sure the bus number is in range. */
106 static int schizo_out_of_range(struct pci_pbm_info *pbm,
110 if (bus < pbm->pci_first_busno ||
111 bus > pbm->pci_last_busno)
116 /* SCHIZO PCI configuration space accessors. */
118 static int schizo_read_pci_cfg(struct pci_bus *bus_dev, unsigned int devfn,
119 int where, int size, u32 *value)
121 struct pci_pbm_info *pbm = bus_dev->sysdata;
122 unsigned char bus = bus_dev->number;
139 addr = schizo_pci_config_mkaddr(pbm, bus, devfn, where);
141 return PCIBIOS_SUCCESSFUL;
143 if (schizo_out_of_range(pbm, bus, devfn))
144 return PCIBIOS_SUCCESSFUL;
147 pci_config_read8((u8 *)addr, &tmp8);
153 printk("pci_read_config_word: misaligned reg [%x]\n",
155 return PCIBIOS_SUCCESSFUL;
157 pci_config_read16((u16 *)addr, &tmp16);
163 printk("pci_read_config_dword: misaligned reg [%x]\n",
165 return PCIBIOS_SUCCESSFUL;
167 pci_config_read32(addr, value);
170 return PCIBIOS_SUCCESSFUL;
173 static int schizo_write_pci_cfg(struct pci_bus *bus_dev, unsigned int devfn,
174 int where, int size, u32 value)
176 struct pci_pbm_info *pbm = bus_dev->sysdata;
177 unsigned char bus = bus_dev->number;
180 addr = schizo_pci_config_mkaddr(pbm, bus, devfn, where);
182 return PCIBIOS_SUCCESSFUL;
184 if (schizo_out_of_range(pbm, bus, devfn))
185 return PCIBIOS_SUCCESSFUL;
189 pci_config_write8((u8 *)addr, value);
194 printk("pci_write_config_word: misaligned reg [%x]\n",
196 return PCIBIOS_SUCCESSFUL;
198 pci_config_write16((u16 *)addr, value);
203 printk("pci_write_config_dword: misaligned reg [%x]\n",
205 return PCIBIOS_SUCCESSFUL;
208 pci_config_write32(addr, value);
210 return PCIBIOS_SUCCESSFUL;
213 static struct pci_ops schizo_ops = {
214 .read = schizo_read_pci_cfg,
215 .write = schizo_write_pci_cfg,
218 /* SCHIZO interrupt mapping support. Unlike Psycho, for this controller the
219 * imap/iclr registers are per-PBM.
221 #define SCHIZO_IMAP_BASE 0x1000UL
222 #define SCHIZO_ICLR_BASE 0x1400UL
224 static unsigned long schizo_imap_offset(unsigned long ino)
226 return SCHIZO_IMAP_BASE + (ino * 8UL);
229 static unsigned long schizo_iclr_offset(unsigned long ino)
231 return SCHIZO_ICLR_BASE + (ino * 8UL);
234 /* PCI SCHIZO INO number to Sparc PIL level. This table only matters for
235 * INOs which will not have an associated PCI device struct, ie. onboard
236 * EBUS devices and PCI controller internal error interrupts.
238 static unsigned char schizo_pil_table[] = {
239 /*0x00*/0, 0, 0, 0, /* PCI slot 0 Int A, B, C, D */
240 /*0x04*/0, 0, 0, 0, /* PCI slot 1 Int A, B, C, D */
241 /*0x08*/0, 0, 0, 0, /* PCI slot 2 Int A, B, C, D */
242 /*0x0c*/0, 0, 0, 0, /* PCI slot 3 Int A, B, C, D */
243 /*0x10*/0, 0, 0, 0, /* PCI slot 4 Int A, B, C, D */
244 /*0x14*/0, 0, 0, 0, /* PCI slot 5 Int A, B, C, D */
245 /*0x18*/4, /* SCSI */
246 /*0x19*/4, /* second SCSI */
247 /*0x1a*/0, /* UNKNOWN */
248 /*0x1b*/0, /* UNKNOWN */
249 /*0x1c*/8, /* Parallel */
250 /*0x1d*/5, /* Ethernet */
251 /*0x1e*/8, /* Firewire-1394 */
253 /*0x20*/13, /* Audio Record */
254 /*0x21*/14, /* Audio Playback */
255 /*0x22*/12, /* Serial */
256 /*0x23*/4, /* EBUS I2C */
257 /*0x24*/10, /* RTC Clock */
258 /*0x25*/11, /* Floppy */
259 /*0x26*/0, /* UNKNOWN */
260 /*0x27*/0, /* UNKNOWN */
261 /*0x28*/0, /* UNKNOWN */
262 /*0x29*/0, /* UNKNOWN */
263 /*0x2a*/10, /* UPA 1 */
264 /*0x2b*/10, /* UPA 2 */
265 /*0x2c*/0, /* UNKNOWN */
266 /*0x2d*/0, /* UNKNOWN */
267 /*0x2e*/0, /* UNKNOWN */
268 /*0x2f*/0, /* UNKNOWN */
269 /*0x30*/15, /* Uncorrectable ECC */
270 /*0x31*/15, /* Correctable ECC */
271 /*0x32*/15, /* PCI Bus A Error */
272 /*0x33*/15, /* PCI Bus B Error */
273 /*0x34*/15, /* Safari Bus Error */
274 /*0x35*/0, /* Reserved */
275 /*0x36*/0, /* Reserved */
276 /*0x37*/0, /* Reserved */
277 /*0x38*/0, /* Reserved for NewLink */
278 /*0x39*/0, /* Reserved for NewLink */
279 /*0x3a*/0, /* Reserved for NewLink */
280 /*0x3b*/0, /* Reserved for NewLink */
281 /*0x3c*/0, /* Reserved for NewLink */
282 /*0x3d*/0, /* Reserved for NewLink */
283 /*0x3e*/0, /* Reserved for NewLink */
284 /*0x3f*/0, /* Reserved for NewLink */
287 static int __init schizo_ino_to_pil(struct pci_dev *pdev, unsigned int ino)
292 pdev->vendor == PCI_VENDOR_ID_SUN &&
293 pdev->device == PCI_DEVICE_ID_SUN_RIO_USB)
296 ret = schizo_pil_table[ino];
297 if (ret == 0 && pdev == NULL) {
299 } else if (ret == 0) {
300 switch ((pdev->class >> 16) & 0xff) {
301 case PCI_BASE_CLASS_STORAGE:
305 case PCI_BASE_CLASS_NETWORK:
309 case PCI_BASE_CLASS_DISPLAY:
313 case PCI_BASE_CLASS_MULTIMEDIA:
314 case PCI_BASE_CLASS_MEMORY:
315 case PCI_BASE_CLASS_BRIDGE:
316 case PCI_BASE_CLASS_SERIAL:
329 static unsigned int __init schizo_irq_build(struct pci_pbm_info *pbm,
330 struct pci_dev *pdev,
333 struct ino_bucket *bucket;
334 unsigned long imap, iclr;
335 unsigned long imap_off, iclr_off;
339 imap_off = schizo_imap_offset(ino);
341 /* Now build the IRQ bucket. */
342 pil = schizo_ino_to_pil(pdev, ino);
344 if (PIL_RESERVED(pil))
347 imap = pbm->pbm_regs + imap_off;
350 iclr_off = schizo_iclr_offset(ino);
351 iclr = pbm->pbm_regs + iclr_off;
354 /* On Schizo, no inofixup occurs. This is because each
355 * INO has it's own IMAP register. On Psycho and Sabre
356 * there is only one IMAP register for each PCI slot even
357 * though four different INOs can be generated by each
360 * But, for JBUS variants (essentially, Tomatillo), we have
361 * to fixup the lowest bit of the interrupt group number.
364 if (pbm->chip_type == PBM_CHIP_TYPE_TOMATILLO) {
366 ign_fixup = (1 << 6);
369 bucket = __bucket(build_irq(pil, ign_fixup, iclr, imap));
370 bucket->flags |= IBF_PCI;
372 return __irq(bucket);
375 /* SCHIZO error handling support. */
376 enum schizo_error_type {
377 UE_ERR, CE_ERR, PCI_ERR, SAFARI_ERR
380 static DEFINE_SPINLOCK(stc_buf_lock);
381 static unsigned long stc_error_buf[128];
382 static unsigned long stc_tag_buf[16];
383 static unsigned long stc_line_buf[16];
385 /* These offsets look weird because I keep in pbm->controller_regs
386 * the second PROM register property minus 0x10000 which is the
387 * base of the Safari and UPA64S registers of SCHIZO.
389 #define SCHIZO_PBM_A_REGS_OFF (0x600000UL - 0x400000UL)
390 #define SCHIZO_PBM_B_REGS_OFF (0x700000UL - 0x400000UL)
392 static void schizo_clear_other_err_intr(int irq)
394 struct ino_bucket *bucket = __bucket(irq);
395 unsigned long iclr = bucket->iclr;
397 iclr += (SCHIZO_PBM_B_REGS_OFF - SCHIZO_PBM_A_REGS_OFF);
398 upa_writel(ICLR_IDLE, iclr);
401 #define SCHIZO_STC_ERR 0xb800UL /* --> 0xba00 */
402 #define SCHIZO_STC_TAG 0xba00UL /* --> 0xba80 */
403 #define SCHIZO_STC_LINE 0xbb00UL /* --> 0xbb80 */
405 #define SCHIZO_STCERR_WRITE 0x2UL
406 #define SCHIZO_STCERR_READ 0x1UL
408 #define SCHIZO_STCTAG_PPN 0x3fffffff00000000UL
409 #define SCHIZO_STCTAG_VPN 0x00000000ffffe000UL
410 #define SCHIZO_STCTAG_VALID 0x8000000000000000UL
411 #define SCHIZO_STCTAG_READ 0x4000000000000000UL
413 #define SCHIZO_STCLINE_LINDX 0x0000000007800000UL
414 #define SCHIZO_STCLINE_SPTR 0x000000000007e000UL
415 #define SCHIZO_STCLINE_LADDR 0x0000000000001fc0UL
416 #define SCHIZO_STCLINE_EPTR 0x000000000000003fUL
417 #define SCHIZO_STCLINE_VALID 0x0000000000600000UL
418 #define SCHIZO_STCLINE_FOFN 0x0000000000180000UL
420 static void __schizo_check_stc_error_pbm(struct pci_pbm_info *pbm,
421 enum schizo_error_type type)
423 struct pci_strbuf *strbuf = &pbm->stc;
424 unsigned long regbase = pbm->pbm_regs;
425 unsigned long err_base, tag_base, line_base;
429 err_base = regbase + SCHIZO_STC_ERR;
430 tag_base = regbase + SCHIZO_STC_TAG;
431 line_base = regbase + SCHIZO_STC_LINE;
433 spin_lock(&stc_buf_lock);
435 /* This is __REALLY__ dangerous. When we put the
436 * streaming buffer into diagnostic mode to probe
437 * it's tags and error status, we _must_ clear all
438 * of the line tag valid bits before re-enabling
439 * the streaming buffer. If any dirty data lives
440 * in the STC when we do this, we will end up
441 * invalidating it before it has a chance to reach
444 control = schizo_read(strbuf->strbuf_control);
445 schizo_write(strbuf->strbuf_control,
446 (control | SCHIZO_STRBUF_CTRL_DENAB));
447 for (i = 0; i < 128; i++) {
450 val = schizo_read(err_base + (i * 8UL));
451 schizo_write(err_base + (i * 8UL), 0UL);
452 stc_error_buf[i] = val;
454 for (i = 0; i < 16; i++) {
455 stc_tag_buf[i] = schizo_read(tag_base + (i * 8UL));
456 stc_line_buf[i] = schizo_read(line_base + (i * 8UL));
457 schizo_write(tag_base + (i * 8UL), 0UL);
458 schizo_write(line_base + (i * 8UL), 0UL);
461 /* OK, state is logged, exit diagnostic mode. */
462 schizo_write(strbuf->strbuf_control, control);
464 for (i = 0; i < 16; i++) {
465 int j, saw_error, first, last;
470 for (j = first; j < last; j++) {
471 unsigned long errval = stc_error_buf[j];
474 printk("%s: STC_ERR(%d)[wr(%d)rd(%d)]\n",
477 (errval & SCHIZO_STCERR_WRITE) ? 1 : 0,
478 (errval & SCHIZO_STCERR_READ) ? 1 : 0);
481 if (saw_error != 0) {
482 unsigned long tagval = stc_tag_buf[i];
483 unsigned long lineval = stc_line_buf[i];
484 printk("%s: STC_TAG(%d)[PA(%016lx)VA(%08lx)V(%d)R(%d)]\n",
487 ((tagval & SCHIZO_STCTAG_PPN) >> 19UL),
488 (tagval & SCHIZO_STCTAG_VPN),
489 ((tagval & SCHIZO_STCTAG_VALID) ? 1 : 0),
490 ((tagval & SCHIZO_STCTAG_READ) ? 1 : 0));
492 /* XXX Should spit out per-bank error information... -DaveM */
493 printk("%s: STC_LINE(%d)[LIDX(%lx)SP(%lx)LADDR(%lx)EP(%lx)"
497 ((lineval & SCHIZO_STCLINE_LINDX) >> 23UL),
498 ((lineval & SCHIZO_STCLINE_SPTR) >> 13UL),
499 ((lineval & SCHIZO_STCLINE_LADDR) >> 6UL),
500 ((lineval & SCHIZO_STCLINE_EPTR) >> 0UL),
501 ((lineval & SCHIZO_STCLINE_VALID) ? 1 : 0),
502 ((lineval & SCHIZO_STCLINE_FOFN) ? 1 : 0));
506 spin_unlock(&stc_buf_lock);
509 /* IOMMU is per-PBM in Schizo, so interrogate both for anonymous
510 * controller level errors.
513 #define SCHIZO_IOMMU_TAG 0xa580UL
514 #define SCHIZO_IOMMU_DATA 0xa600UL
516 #define SCHIZO_IOMMU_TAG_CTXT 0x0000001ffe000000UL
517 #define SCHIZO_IOMMU_TAG_ERRSTS 0x0000000001800000UL
518 #define SCHIZO_IOMMU_TAG_ERR 0x0000000000400000UL
519 #define SCHIZO_IOMMU_TAG_WRITE 0x0000000000200000UL
520 #define SCHIZO_IOMMU_TAG_STREAM 0x0000000000100000UL
521 #define SCHIZO_IOMMU_TAG_SIZE 0x0000000000080000UL
522 #define SCHIZO_IOMMU_TAG_VPAGE 0x000000000007ffffUL
524 #define SCHIZO_IOMMU_DATA_VALID 0x0000000100000000UL
525 #define SCHIZO_IOMMU_DATA_CACHE 0x0000000040000000UL
526 #define SCHIZO_IOMMU_DATA_PPAGE 0x000000003fffffffUL
528 static void schizo_check_iommu_error_pbm(struct pci_pbm_info *pbm,
529 enum schizo_error_type type)
531 struct pci_iommu *iommu = pbm->iommu;
532 unsigned long iommu_tag[16];
533 unsigned long iommu_data[16];
538 spin_lock_irqsave(&iommu->lock, flags);
539 control = schizo_read(iommu->iommu_control);
540 if (control & SCHIZO_IOMMU_CTRL_XLTEERR) {
544 /* Clear the error encountered bit. */
545 control &= ~SCHIZO_IOMMU_CTRL_XLTEERR;
546 schizo_write(iommu->iommu_control, control);
548 switch((control & SCHIZO_IOMMU_CTRL_XLTESTAT) >> 25UL) {
550 type_string = "Protection Error";
553 type_string = "Invalid Error";
556 type_string = "TimeOut Error";
560 type_string = "ECC Error";
563 printk("%s: IOMMU Error, type[%s]\n",
564 pbm->name, type_string);
566 /* Put the IOMMU into diagnostic mode and probe
567 * it's TLB for entries with error status.
569 * It is very possible for another DVMA to occur
570 * while we do this probe, and corrupt the system
571 * further. But we are so screwed at this point
572 * that we are likely to crash hard anyways, so
573 * get as much diagnostic information to the
576 schizo_write(iommu->iommu_control,
577 control | SCHIZO_IOMMU_CTRL_DENAB);
579 base = pbm->pbm_regs;
581 for (i = 0; i < 16; i++) {
583 schizo_read(base + SCHIZO_IOMMU_TAG + (i * 8UL));
585 schizo_read(base + SCHIZO_IOMMU_DATA + (i * 8UL));
587 /* Now clear out the entry. */
588 schizo_write(base + SCHIZO_IOMMU_TAG + (i * 8UL), 0);
589 schizo_write(base + SCHIZO_IOMMU_DATA + (i * 8UL), 0);
592 /* Leave diagnostic mode. */
593 schizo_write(iommu->iommu_control, control);
595 for (i = 0; i < 16; i++) {
596 unsigned long tag, data;
599 if (!(tag & SCHIZO_IOMMU_TAG_ERR))
602 data = iommu_data[i];
603 switch((tag & SCHIZO_IOMMU_TAG_ERRSTS) >> 23UL) {
605 type_string = "Protection Error";
608 type_string = "Invalid Error";
611 type_string = "TimeOut Error";
615 type_string = "ECC Error";
618 printk("%s: IOMMU TAG(%d)[error(%s) ctx(%x) wr(%d) str(%d) "
619 "sz(%dK) vpg(%08lx)]\n",
620 pbm->name, i, type_string,
621 (int)((tag & SCHIZO_IOMMU_TAG_CTXT) >> 25UL),
622 ((tag & SCHIZO_IOMMU_TAG_WRITE) ? 1 : 0),
623 ((tag & SCHIZO_IOMMU_TAG_STREAM) ? 1 : 0),
624 ((tag & SCHIZO_IOMMU_TAG_SIZE) ? 64 : 8),
625 (tag & SCHIZO_IOMMU_TAG_VPAGE) << IOMMU_PAGE_SHIFT);
626 printk("%s: IOMMU DATA(%d)[valid(%d) cache(%d) ppg(%016lx)]\n",
628 ((data & SCHIZO_IOMMU_DATA_VALID) ? 1 : 0),
629 ((data & SCHIZO_IOMMU_DATA_CACHE) ? 1 : 0),
630 (data & SCHIZO_IOMMU_DATA_PPAGE) << IOMMU_PAGE_SHIFT);
633 if (pbm->stc.strbuf_enabled)
634 __schizo_check_stc_error_pbm(pbm, type);
635 spin_unlock_irqrestore(&iommu->lock, flags);
638 static void schizo_check_iommu_error(struct pci_controller_info *p,
639 enum schizo_error_type type)
641 schizo_check_iommu_error_pbm(&p->pbm_A, type);
642 schizo_check_iommu_error_pbm(&p->pbm_B, type);
645 /* Uncorrectable ECC error status gathering. */
646 #define SCHIZO_UE_AFSR 0x10030UL
647 #define SCHIZO_UE_AFAR 0x10038UL
649 #define SCHIZO_UEAFSR_PPIO 0x8000000000000000UL /* Safari */
650 #define SCHIZO_UEAFSR_PDRD 0x4000000000000000UL /* Safari/Tomatillo */
651 #define SCHIZO_UEAFSR_PDWR 0x2000000000000000UL /* Safari */
652 #define SCHIZO_UEAFSR_SPIO 0x1000000000000000UL /* Safari */
653 #define SCHIZO_UEAFSR_SDMA 0x0800000000000000UL /* Safari/Tomatillo */
654 #define SCHIZO_UEAFSR_ERRPNDG 0x0300000000000000UL /* Safari */
655 #define SCHIZO_UEAFSR_BMSK 0x000003ff00000000UL /* Safari */
656 #define SCHIZO_UEAFSR_QOFF 0x00000000c0000000UL /* Safari/Tomatillo */
657 #define SCHIZO_UEAFSR_AID 0x000000001f000000UL /* Safari/Tomatillo */
658 #define SCHIZO_UEAFSR_PARTIAL 0x0000000000800000UL /* Safari */
659 #define SCHIZO_UEAFSR_OWNEDIN 0x0000000000400000UL /* Safari */
660 #define SCHIZO_UEAFSR_MTAGSYND 0x00000000000f0000UL /* Safari */
661 #define SCHIZO_UEAFSR_MTAG 0x000000000000e000UL /* Safari */
662 #define SCHIZO_UEAFSR_ECCSYND 0x00000000000001ffUL /* Safari */
664 static irqreturn_t schizo_ue_intr(int irq, void *dev_id, struct pt_regs *regs)
666 struct pci_controller_info *p = dev_id;
667 unsigned long afsr_reg = p->pbm_B.controller_regs + SCHIZO_UE_AFSR;
668 unsigned long afar_reg = p->pbm_B.controller_regs + SCHIZO_UE_AFAR;
669 unsigned long afsr, afar, error_bits;
672 /* Latch uncorrectable error status. */
673 afar = schizo_read(afar_reg);
675 /* If either of the error pending bits are set in the
676 * AFSR, the error status is being actively updated by
677 * the hardware and we must re-read to get a clean value.
681 afsr = schizo_read(afsr_reg);
682 } while ((afsr & SCHIZO_UEAFSR_ERRPNDG) != 0 && --limit);
684 /* Clear the primary/secondary error status bits. */
686 (SCHIZO_UEAFSR_PPIO | SCHIZO_UEAFSR_PDRD | SCHIZO_UEAFSR_PDWR |
687 SCHIZO_UEAFSR_SPIO | SCHIZO_UEAFSR_SDMA);
690 schizo_write(afsr_reg, error_bits);
693 printk("PCI%d: Uncorrectable Error, primary error type[%s]\n",
695 (((error_bits & SCHIZO_UEAFSR_PPIO) ?
697 ((error_bits & SCHIZO_UEAFSR_PDRD) ?
699 ((error_bits & SCHIZO_UEAFSR_PDWR) ?
700 "DMA Write" : "???")))));
701 printk("PCI%d: bytemask[%04lx] qword_offset[%lx] SAFARI_AID[%02lx]\n",
703 (afsr & SCHIZO_UEAFSR_BMSK) >> 32UL,
704 (afsr & SCHIZO_UEAFSR_QOFF) >> 30UL,
705 (afsr & SCHIZO_UEAFSR_AID) >> 24UL);
706 printk("PCI%d: partial[%d] owned_in[%d] mtag[%lx] mtag_synd[%lx] ecc_sync[%lx]\n",
708 (afsr & SCHIZO_UEAFSR_PARTIAL) ? 1 : 0,
709 (afsr & SCHIZO_UEAFSR_OWNEDIN) ? 1 : 0,
710 (afsr & SCHIZO_UEAFSR_MTAG) >> 13UL,
711 (afsr & SCHIZO_UEAFSR_MTAGSYND) >> 16UL,
712 (afsr & SCHIZO_UEAFSR_ECCSYND) >> 0UL);
713 printk("PCI%d: UE AFAR [%016lx]\n", p->index, afar);
714 printk("PCI%d: UE Secondary errors [", p->index);
716 if (afsr & SCHIZO_UEAFSR_SPIO) {
720 if (afsr & SCHIZO_UEAFSR_SDMA) {
728 /* Interrogate IOMMU for error status. */
729 schizo_check_iommu_error(p, UE_ERR);
731 schizo_clear_other_err_intr(irq);
736 #define SCHIZO_CE_AFSR 0x10040UL
737 #define SCHIZO_CE_AFAR 0x10048UL
739 #define SCHIZO_CEAFSR_PPIO 0x8000000000000000UL
740 #define SCHIZO_CEAFSR_PDRD 0x4000000000000000UL
741 #define SCHIZO_CEAFSR_PDWR 0x2000000000000000UL
742 #define SCHIZO_CEAFSR_SPIO 0x1000000000000000UL
743 #define SCHIZO_CEAFSR_SDMA 0x0800000000000000UL
744 #define SCHIZO_CEAFSR_ERRPNDG 0x0300000000000000UL
745 #define SCHIZO_CEAFSR_BMSK 0x000003ff00000000UL
746 #define SCHIZO_CEAFSR_QOFF 0x00000000c0000000UL
747 #define SCHIZO_CEAFSR_AID 0x000000001f000000UL
748 #define SCHIZO_CEAFSR_PARTIAL 0x0000000000800000UL
749 #define SCHIZO_CEAFSR_OWNEDIN 0x0000000000400000UL
750 #define SCHIZO_CEAFSR_MTAGSYND 0x00000000000f0000UL
751 #define SCHIZO_CEAFSR_MTAG 0x000000000000e000UL
752 #define SCHIZO_CEAFSR_ECCSYND 0x00000000000001ffUL
754 static irqreturn_t schizo_ce_intr(int irq, void *dev_id, struct pt_regs *regs)
756 struct pci_controller_info *p = dev_id;
757 unsigned long afsr_reg = p->pbm_B.controller_regs + SCHIZO_CE_AFSR;
758 unsigned long afar_reg = p->pbm_B.controller_regs + SCHIZO_CE_AFAR;
759 unsigned long afsr, afar, error_bits;
762 /* Latch error status. */
763 afar = schizo_read(afar_reg);
765 /* If either of the error pending bits are set in the
766 * AFSR, the error status is being actively updated by
767 * the hardware and we must re-read to get a clean value.
771 afsr = schizo_read(afsr_reg);
772 } while ((afsr & SCHIZO_UEAFSR_ERRPNDG) != 0 && --limit);
774 /* Clear primary/secondary error status bits. */
776 (SCHIZO_CEAFSR_PPIO | SCHIZO_CEAFSR_PDRD | SCHIZO_CEAFSR_PDWR |
777 SCHIZO_CEAFSR_SPIO | SCHIZO_CEAFSR_SDMA);
780 schizo_write(afsr_reg, error_bits);
783 printk("PCI%d: Correctable Error, primary error type[%s]\n",
785 (((error_bits & SCHIZO_CEAFSR_PPIO) ?
787 ((error_bits & SCHIZO_CEAFSR_PDRD) ?
789 ((error_bits & SCHIZO_CEAFSR_PDWR) ?
790 "DMA Write" : "???")))));
792 /* XXX Use syndrome and afar to print out module string just like
793 * XXX UDB CE trap handler does... -DaveM
795 printk("PCI%d: bytemask[%04lx] qword_offset[%lx] SAFARI_AID[%02lx]\n",
797 (afsr & SCHIZO_UEAFSR_BMSK) >> 32UL,
798 (afsr & SCHIZO_UEAFSR_QOFF) >> 30UL,
799 (afsr & SCHIZO_UEAFSR_AID) >> 24UL);
800 printk("PCI%d: partial[%d] owned_in[%d] mtag[%lx] mtag_synd[%lx] ecc_sync[%lx]\n",
802 (afsr & SCHIZO_UEAFSR_PARTIAL) ? 1 : 0,
803 (afsr & SCHIZO_UEAFSR_OWNEDIN) ? 1 : 0,
804 (afsr & SCHIZO_UEAFSR_MTAG) >> 13UL,
805 (afsr & SCHIZO_UEAFSR_MTAGSYND) >> 16UL,
806 (afsr & SCHIZO_UEAFSR_ECCSYND) >> 0UL);
807 printk("PCI%d: CE AFAR [%016lx]\n", p->index, afar);
808 printk("PCI%d: CE Secondary errors [", p->index);
810 if (afsr & SCHIZO_CEAFSR_SPIO) {
814 if (afsr & SCHIZO_CEAFSR_SDMA) {
822 schizo_clear_other_err_intr(irq);
827 #define SCHIZO_PCI_AFSR 0x2010UL
828 #define SCHIZO_PCI_AFAR 0x2018UL
830 #define SCHIZO_PCIAFSR_PMA 0x8000000000000000UL /* Schizo/Tomatillo */
831 #define SCHIZO_PCIAFSR_PTA 0x4000000000000000UL /* Schizo/Tomatillo */
832 #define SCHIZO_PCIAFSR_PRTRY 0x2000000000000000UL /* Schizo/Tomatillo */
833 #define SCHIZO_PCIAFSR_PPERR 0x1000000000000000UL /* Schizo/Tomatillo */
834 #define SCHIZO_PCIAFSR_PTTO 0x0800000000000000UL /* Schizo/Tomatillo */
835 #define SCHIZO_PCIAFSR_PUNUS 0x0400000000000000UL /* Schizo */
836 #define SCHIZO_PCIAFSR_SMA 0x0200000000000000UL /* Schizo/Tomatillo */
837 #define SCHIZO_PCIAFSR_STA 0x0100000000000000UL /* Schizo/Tomatillo */
838 #define SCHIZO_PCIAFSR_SRTRY 0x0080000000000000UL /* Schizo/Tomatillo */
839 #define SCHIZO_PCIAFSR_SPERR 0x0040000000000000UL /* Schizo/Tomatillo */
840 #define SCHIZO_PCIAFSR_STTO 0x0020000000000000UL /* Schizo/Tomatillo */
841 #define SCHIZO_PCIAFSR_SUNUS 0x0010000000000000UL /* Schizo */
842 #define SCHIZO_PCIAFSR_BMSK 0x000003ff00000000UL /* Schizo/Tomatillo */
843 #define SCHIZO_PCIAFSR_BLK 0x0000000080000000UL /* Schizo/Tomatillo */
844 #define SCHIZO_PCIAFSR_CFG 0x0000000040000000UL /* Schizo/Tomatillo */
845 #define SCHIZO_PCIAFSR_MEM 0x0000000020000000UL /* Schizo/Tomatillo */
846 #define SCHIZO_PCIAFSR_IO 0x0000000010000000UL /* Schizo/Tomatillo */
848 #define SCHIZO_PCI_CTRL (0x2000UL)
849 #define SCHIZO_PCICTRL_BUS_UNUS (1UL << 63UL) /* Safari */
850 #define SCHIZO_PCICTRL_ARB_PRIO (0x1ff << 52UL) /* Tomatillo */
851 #define SCHIZO_PCICTRL_ESLCK (1UL << 51UL) /* Safari */
852 #define SCHIZO_PCICTRL_ERRSLOT (7UL << 48UL) /* Safari */
853 #define SCHIZO_PCICTRL_TTO_ERR (1UL << 38UL) /* Safari/Tomatillo */
854 #define SCHIZO_PCICTRL_RTRY_ERR (1UL << 37UL) /* Safari/Tomatillo */
855 #define SCHIZO_PCICTRL_DTO_ERR (1UL << 36UL) /* Safari/Tomatillo */
856 #define SCHIZO_PCICTRL_SBH_ERR (1UL << 35UL) /* Safari */
857 #define SCHIZO_PCICTRL_SERR (1UL << 34UL) /* Safari/Tomatillo */
858 #define SCHIZO_PCICTRL_PCISPD (1UL << 33UL) /* Safari */
859 #define SCHIZO_PCICTRL_MRM_PREF (1UL << 28UL) /* Tomatillo */
860 #define SCHIZO_PCICTRL_RDO_PREF (1UL << 27UL) /* Tomatillo */
861 #define SCHIZO_PCICTRL_RDL_PREF (1UL << 26UL) /* Tomatillo */
862 #define SCHIZO_PCICTRL_PTO (3UL << 24UL) /* Safari/Tomatillo */
863 #define SCHIZO_PCICTRL_PTO_SHIFT 24UL
864 #define SCHIZO_PCICTRL_TRWSW (7UL << 21UL) /* Tomatillo */
865 #define SCHIZO_PCICTRL_F_TGT_A (1UL << 20UL) /* Tomatillo */
866 #define SCHIZO_PCICTRL_S_DTO_INT (1UL << 19UL) /* Safari */
867 #define SCHIZO_PCICTRL_F_TGT_RT (1UL << 19UL) /* Tomatillo */
868 #define SCHIZO_PCICTRL_SBH_INT (1UL << 18UL) /* Safari */
869 #define SCHIZO_PCICTRL_T_DTO_INT (1UL << 18UL) /* Tomatillo */
870 #define SCHIZO_PCICTRL_EEN (1UL << 17UL) /* Safari/Tomatillo */
871 #define SCHIZO_PCICTRL_PARK (1UL << 16UL) /* Safari/Tomatillo */
872 #define SCHIZO_PCICTRL_PCIRST (1UL << 8UL) /* Safari */
873 #define SCHIZO_PCICTRL_ARB_S (0x3fUL << 0UL) /* Safari */
874 #define SCHIZO_PCICTRL_ARB_T (0xffUL << 0UL) /* Tomatillo */
876 static irqreturn_t schizo_pcierr_intr_other(struct pci_pbm_info *pbm)
878 unsigned long csr_reg, csr, csr_error_bits;
879 irqreturn_t ret = IRQ_NONE;
882 csr_reg = pbm->pbm_regs + SCHIZO_PCI_CTRL;
883 csr = schizo_read(csr_reg);
885 csr & (SCHIZO_PCICTRL_BUS_UNUS |
886 SCHIZO_PCICTRL_TTO_ERR |
887 SCHIZO_PCICTRL_RTRY_ERR |
888 SCHIZO_PCICTRL_DTO_ERR |
889 SCHIZO_PCICTRL_SBH_ERR |
890 SCHIZO_PCICTRL_SERR);
891 if (csr_error_bits) {
892 /* Clear the errors. */
893 schizo_write(csr_reg, csr);
896 if (csr_error_bits & SCHIZO_PCICTRL_BUS_UNUS)
897 printk("%s: Bus unusable error asserted.\n",
899 if (csr_error_bits & SCHIZO_PCICTRL_TTO_ERR)
900 printk("%s: PCI TRDY# timeout error asserted.\n",
902 if (csr_error_bits & SCHIZO_PCICTRL_RTRY_ERR)
903 printk("%s: PCI excessive retry error asserted.\n",
905 if (csr_error_bits & SCHIZO_PCICTRL_DTO_ERR)
906 printk("%s: PCI discard timeout error asserted.\n",
908 if (csr_error_bits & SCHIZO_PCICTRL_SBH_ERR)
909 printk("%s: PCI streaming byte hole error asserted.\n",
911 if (csr_error_bits & SCHIZO_PCICTRL_SERR)
912 printk("%s: PCI SERR signal asserted.\n",
916 pci_read_config_word(pbm->pci_bus->self, PCI_STATUS, &stat);
917 if (stat & (PCI_STATUS_PARITY |
918 PCI_STATUS_SIG_TARGET_ABORT |
919 PCI_STATUS_REC_TARGET_ABORT |
920 PCI_STATUS_REC_MASTER_ABORT |
921 PCI_STATUS_SIG_SYSTEM_ERROR)) {
922 printk("%s: PCI bus error, PCI_STATUS[%04x]\n",
924 pci_write_config_word(pbm->pci_bus->self, PCI_STATUS, 0xffff);
930 static irqreturn_t schizo_pcierr_intr(int irq, void *dev_id, struct pt_regs *regs)
932 struct pci_pbm_info *pbm = dev_id;
933 struct pci_controller_info *p = pbm->parent;
934 unsigned long afsr_reg, afar_reg, base;
935 unsigned long afsr, afar, error_bits;
938 base = pbm->pbm_regs;
940 afsr_reg = base + SCHIZO_PCI_AFSR;
941 afar_reg = base + SCHIZO_PCI_AFAR;
943 /* Latch error status. */
944 afar = schizo_read(afar_reg);
945 afsr = schizo_read(afsr_reg);
947 /* Clear primary/secondary error status bits. */
949 (SCHIZO_PCIAFSR_PMA | SCHIZO_PCIAFSR_PTA |
950 SCHIZO_PCIAFSR_PRTRY | SCHIZO_PCIAFSR_PPERR |
951 SCHIZO_PCIAFSR_PTTO | SCHIZO_PCIAFSR_PUNUS |
952 SCHIZO_PCIAFSR_SMA | SCHIZO_PCIAFSR_STA |
953 SCHIZO_PCIAFSR_SRTRY | SCHIZO_PCIAFSR_SPERR |
954 SCHIZO_PCIAFSR_STTO | SCHIZO_PCIAFSR_SUNUS);
956 return schizo_pcierr_intr_other(pbm);
957 schizo_write(afsr_reg, error_bits);
960 printk("%s: PCI Error, primary error type[%s]\n",
962 (((error_bits & SCHIZO_PCIAFSR_PMA) ?
964 ((error_bits & SCHIZO_PCIAFSR_PTA) ?
966 ((error_bits & SCHIZO_PCIAFSR_PRTRY) ?
967 "Excessive Retries" :
968 ((error_bits & SCHIZO_PCIAFSR_PPERR) ?
970 ((error_bits & SCHIZO_PCIAFSR_PTTO) ?
972 ((error_bits & SCHIZO_PCIAFSR_PUNUS) ?
973 "Bus Unusable" : "???"))))))));
974 printk("%s: bytemask[%04lx] was_block(%d) space(%s)\n",
976 (afsr & SCHIZO_PCIAFSR_BMSK) >> 32UL,
977 (afsr & SCHIZO_PCIAFSR_BLK) ? 1 : 0,
978 ((afsr & SCHIZO_PCIAFSR_CFG) ?
980 ((afsr & SCHIZO_PCIAFSR_MEM) ?
982 ((afsr & SCHIZO_PCIAFSR_IO) ?
984 printk("%s: PCI AFAR [%016lx]\n",
986 printk("%s: PCI Secondary errors [",
989 if (afsr & SCHIZO_PCIAFSR_SMA) {
991 printk("(Master Abort)");
993 if (afsr & SCHIZO_PCIAFSR_STA) {
995 printk("(Target Abort)");
997 if (afsr & SCHIZO_PCIAFSR_SRTRY) {
999 printk("(Excessive Retries)");
1001 if (afsr & SCHIZO_PCIAFSR_SPERR) {
1003 printk("(Parity Error)");
1005 if (afsr & SCHIZO_PCIAFSR_STTO) {
1007 printk("(Timeout)");
1009 if (afsr & SCHIZO_PCIAFSR_SUNUS) {
1011 printk("(Bus Unusable)");
1017 /* For the error types shown, scan PBM's PCI bus for devices
1018 * which have logged that error type.
1021 /* If we see a Target Abort, this could be the result of an
1022 * IOMMU translation error of some sort. It is extremely
1023 * useful to log this information as usually it indicates
1024 * a bug in the IOMMU support code or a PCI device driver.
1026 if (error_bits & (SCHIZO_PCIAFSR_PTA | SCHIZO_PCIAFSR_STA)) {
1027 schizo_check_iommu_error(p, PCI_ERR);
1028 pci_scan_for_target_abort(p, pbm, pbm->pci_bus);
1030 if (error_bits & (SCHIZO_PCIAFSR_PMA | SCHIZO_PCIAFSR_SMA))
1031 pci_scan_for_master_abort(p, pbm, pbm->pci_bus);
1033 /* For excessive retries, PSYCHO/PBM will abort the device
1034 * and there is no way to specifically check for excessive
1035 * retries in the config space status registers. So what
1036 * we hope is that we'll catch it via the master/target
1040 if (error_bits & (SCHIZO_PCIAFSR_PPERR | SCHIZO_PCIAFSR_SPERR))
1041 pci_scan_for_parity_error(p, pbm, pbm->pci_bus);
1043 schizo_clear_other_err_intr(irq);
1048 #define SCHIZO_SAFARI_ERRLOG 0x10018UL
1050 #define SAFARI_ERRLOG_ERROUT 0x8000000000000000UL
1052 #define BUS_ERROR_BADCMD 0x4000000000000000UL /* Schizo/Tomatillo */
1053 #define BUS_ERROR_SSMDIS 0x2000000000000000UL /* Safari */
1054 #define BUS_ERROR_BADMA 0x1000000000000000UL /* Safari */
1055 #define BUS_ERROR_BADMB 0x0800000000000000UL /* Safari */
1056 #define BUS_ERROR_BADMC 0x0400000000000000UL /* Safari */
1057 #define BUS_ERROR_SNOOP_GR 0x0000000000200000UL /* Tomatillo */
1058 #define BUS_ERROR_SNOOP_PCI 0x0000000000100000UL /* Tomatillo */
1059 #define BUS_ERROR_SNOOP_RD 0x0000000000080000UL /* Tomatillo */
1060 #define BUS_ERROR_SNOOP_RDS 0x0000000000020000UL /* Tomatillo */
1061 #define BUS_ERROR_SNOOP_RDSA 0x0000000000010000UL /* Tomatillo */
1062 #define BUS_ERROR_SNOOP_OWN 0x0000000000008000UL /* Tomatillo */
1063 #define BUS_ERROR_SNOOP_RDO 0x0000000000004000UL /* Tomatillo */
1064 #define BUS_ERROR_CPU1PS 0x0000000000002000UL /* Safari */
1065 #define BUS_ERROR_WDATA_PERR 0x0000000000002000UL /* Tomatillo */
1066 #define BUS_ERROR_CPU1PB 0x0000000000001000UL /* Safari */
1067 #define BUS_ERROR_CTRL_PERR 0x0000000000001000UL /* Tomatillo */
1068 #define BUS_ERROR_CPU0PS 0x0000000000000800UL /* Safari */
1069 #define BUS_ERROR_SNOOP_ERR 0x0000000000000800UL /* Tomatillo */
1070 #define BUS_ERROR_CPU0PB 0x0000000000000400UL /* Safari */
1071 #define BUS_ERROR_JBUS_ILL_B 0x0000000000000400UL /* Tomatillo */
1072 #define BUS_ERROR_CIQTO 0x0000000000000200UL /* Safari */
1073 #define BUS_ERROR_LPQTO 0x0000000000000100UL /* Safari */
1074 #define BUS_ERROR_JBUS_ILL_C 0x0000000000000100UL /* Tomatillo */
1075 #define BUS_ERROR_SFPQTO 0x0000000000000080UL /* Safari */
1076 #define BUS_ERROR_UFPQTO 0x0000000000000040UL /* Safari */
1077 #define BUS_ERROR_RD_PERR 0x0000000000000040UL /* Tomatillo */
1078 #define BUS_ERROR_APERR 0x0000000000000020UL /* Safari/Tomatillo */
1079 #define BUS_ERROR_UNMAP 0x0000000000000010UL /* Safari/Tomatillo */
1080 #define BUS_ERROR_BUSERR 0x0000000000000004UL /* Safari/Tomatillo */
1081 #define BUS_ERROR_TIMEOUT 0x0000000000000002UL /* Safari/Tomatillo */
1082 #define BUS_ERROR_ILL 0x0000000000000001UL /* Safari */
1084 /* We only expect UNMAP errors here. The rest of the Safari errors
1085 * are marked fatal and thus cause a system reset.
1087 static irqreturn_t schizo_safarierr_intr(int irq, void *dev_id, struct pt_regs *regs)
1089 struct pci_controller_info *p = dev_id;
1092 errlog = schizo_read(p->pbm_B.controller_regs + SCHIZO_SAFARI_ERRLOG);
1093 schizo_write(p->pbm_B.controller_regs + SCHIZO_SAFARI_ERRLOG,
1094 errlog & ~(SAFARI_ERRLOG_ERROUT));
1096 if (!(errlog & BUS_ERROR_UNMAP)) {
1097 printk("PCI%d: Unexpected Safari/JBUS error interrupt, errlog[%016lx]\n",
1100 schizo_clear_other_err_intr(irq);
1104 printk("PCI%d: Safari/JBUS interrupt, UNMAPPED error, interrogating IOMMUs.\n",
1106 schizo_check_iommu_error(p, SAFARI_ERR);
1108 schizo_clear_other_err_intr(irq);
1112 /* Nearly identical to PSYCHO equivalents... */
1113 #define SCHIZO_ECC_CTRL 0x10020UL
1114 #define SCHIZO_ECCCTRL_EE 0x8000000000000000UL /* Enable ECC Checking */
1115 #define SCHIZO_ECCCTRL_UE 0x4000000000000000UL /* Enable UE Interrupts */
1116 #define SCHIZO_ECCCTRL_CE 0x2000000000000000UL /* Enable CE INterrupts */
1118 #define SCHIZO_SAFARI_ERRCTRL 0x10008UL
1119 #define SCHIZO_SAFERRCTRL_EN 0x8000000000000000UL
1120 #define SCHIZO_SAFARI_IRQCTRL 0x10010UL
1121 #define SCHIZO_SAFIRQCTRL_EN 0x8000000000000000UL
1123 #define SCHIZO_UE_INO 0x30 /* Uncorrectable ECC error */
1124 #define SCHIZO_CE_INO 0x31 /* Correctable ECC error */
1125 #define SCHIZO_PCIERR_A_INO 0x32 /* PBM A PCI bus error */
1126 #define SCHIZO_PCIERR_B_INO 0x33 /* PBM B PCI bus error */
1127 #define SCHIZO_SERR_INO 0x34 /* Safari interface error */
1129 struct pci_pbm_info *pbm_for_ino(struct pci_controller_info *p, u32 ino)
1132 if (p->pbm_A.ino_bitmap & (1UL << ino))
1134 if (p->pbm_B.ino_bitmap & (1UL << ino))
1136 prom_printf("TOMATILLO%d: No entry in ino bitmap for %d\n",
1143 /* How the Tomatillo IRQs are routed around is pure guesswork here.
1145 * All the Tomatillo devices I see in prtconf dumps seem to have only
1146 * a single PCI bus unit attached to it. It would seem they are seperate
1147 * devices because their PortID (ie. JBUS ID) values are all different
1148 * and thus the registers are mapped to totally different locations.
1150 * However, two Tomatillo's look "similar" in that the only difference
1151 * in their PortID is the lowest bit.
1153 * So if we were to ignore this lower bit, it certainly looks like two
1154 * PCI bus units of the same Tomatillo. I still have not really
1155 * figured this out...
1157 static void __init tomatillo_register_error_handlers(struct pci_controller_info *p)
1159 struct pci_pbm_info *pbm;
1161 struct ino_bucket *bucket;
1162 u64 tmp, err_mask, err_no_mask;
1164 /* Build IRQs and register handlers. */
1165 pbm = pbm_for_ino(p, SCHIZO_UE_INO);
1166 irq = schizo_irq_build(pbm, NULL, (pbm->portid << 6) | SCHIZO_UE_INO);
1167 if (request_irq(irq, schizo_ue_intr,
1168 SA_SHIRQ, "TOMATILLO UE", p) < 0) {
1169 prom_printf("%s: Cannot register UE interrupt.\n",
1173 bucket = __bucket(irq);
1174 tmp = upa_readl(bucket->imap);
1175 upa_writel(tmp, (pbm->pbm_regs +
1176 schizo_imap_offset(SCHIZO_UE_INO) + 4));
1178 pbm = pbm_for_ino(p, SCHIZO_CE_INO);
1179 irq = schizo_irq_build(pbm, NULL, (pbm->portid << 6) | SCHIZO_CE_INO);
1180 if (request_irq(irq, schizo_ce_intr,
1181 SA_SHIRQ, "TOMATILLO CE", p) < 0) {
1182 prom_printf("%s: Cannot register CE interrupt.\n",
1186 bucket = __bucket(irq);
1187 tmp = upa_readl(bucket->imap);
1188 upa_writel(tmp, (pbm->pbm_regs +
1189 schizo_imap_offset(SCHIZO_CE_INO) + 4));
1191 pbm = pbm_for_ino(p, SCHIZO_PCIERR_A_INO);
1192 irq = schizo_irq_build(pbm, NULL, ((pbm->portid << 6) |
1193 SCHIZO_PCIERR_A_INO));
1194 if (request_irq(irq, schizo_pcierr_intr,
1195 SA_SHIRQ, "TOMATILLO PCIERR", pbm) < 0) {
1196 prom_printf("%s: Cannot register PBM A PciERR interrupt.\n",
1200 bucket = __bucket(irq);
1201 tmp = upa_readl(bucket->imap);
1202 upa_writel(tmp, (pbm->pbm_regs +
1203 schizo_imap_offset(SCHIZO_PCIERR_A_INO) + 4));
1205 pbm = pbm_for_ino(p, SCHIZO_PCIERR_B_INO);
1206 irq = schizo_irq_build(pbm, NULL, ((pbm->portid << 6) |
1207 SCHIZO_PCIERR_B_INO));
1208 if (request_irq(irq, schizo_pcierr_intr,
1209 SA_SHIRQ, "TOMATILLO PCIERR", pbm) < 0) {
1210 prom_printf("%s: Cannot register PBM B PciERR interrupt.\n",
1214 bucket = __bucket(irq);
1215 tmp = upa_readl(bucket->imap);
1216 upa_writel(tmp, (pbm->pbm_regs +
1217 schizo_imap_offset(SCHIZO_PCIERR_B_INO) + 4));
1219 pbm = pbm_for_ino(p, SCHIZO_SERR_INO);
1220 irq = schizo_irq_build(pbm, NULL, (pbm->portid << 6) | SCHIZO_SERR_INO);
1221 if (request_irq(irq, schizo_safarierr_intr,
1222 SA_SHIRQ, "TOMATILLO SERR", p) < 0) {
1223 prom_printf("%s: Cannot register SafariERR interrupt.\n",
1227 bucket = __bucket(irq);
1228 tmp = upa_readl(bucket->imap);
1229 upa_writel(tmp, (pbm->pbm_regs +
1230 schizo_imap_offset(SCHIZO_SERR_INO) + 4));
1232 /* Enable UE and CE interrupts for controller. */
1233 schizo_write(p->pbm_A.controller_regs + SCHIZO_ECC_CTRL,
1234 (SCHIZO_ECCCTRL_EE |
1236 SCHIZO_ECCCTRL_CE));
1238 schizo_write(p->pbm_B.controller_regs + SCHIZO_ECC_CTRL,
1239 (SCHIZO_ECCCTRL_EE |
1241 SCHIZO_ECCCTRL_CE));
1243 /* Enable PCI Error interrupts and clear error
1246 err_mask = (SCHIZO_PCICTRL_BUS_UNUS |
1247 SCHIZO_PCICTRL_TTO_ERR |
1248 SCHIZO_PCICTRL_RTRY_ERR |
1249 SCHIZO_PCICTRL_SERR |
1250 SCHIZO_PCICTRL_EEN);
1252 err_no_mask = SCHIZO_PCICTRL_DTO_ERR;
1254 tmp = schizo_read(p->pbm_A.pbm_regs + SCHIZO_PCI_CTRL);
1256 tmp &= ~err_no_mask;
1257 schizo_write(p->pbm_A.pbm_regs + SCHIZO_PCI_CTRL, tmp);
1259 tmp = schizo_read(p->pbm_B.pbm_regs + SCHIZO_PCI_CTRL);
1261 tmp &= ~err_no_mask;
1262 schizo_write(p->pbm_B.pbm_regs + SCHIZO_PCI_CTRL, tmp);
1264 err_mask = (SCHIZO_PCIAFSR_PMA | SCHIZO_PCIAFSR_PTA |
1265 SCHIZO_PCIAFSR_PRTRY | SCHIZO_PCIAFSR_PPERR |
1266 SCHIZO_PCIAFSR_PTTO |
1267 SCHIZO_PCIAFSR_SMA | SCHIZO_PCIAFSR_STA |
1268 SCHIZO_PCIAFSR_SRTRY | SCHIZO_PCIAFSR_SPERR |
1269 SCHIZO_PCIAFSR_STTO);
1271 schizo_write(p->pbm_A.pbm_regs + SCHIZO_PCI_AFSR, err_mask);
1272 schizo_write(p->pbm_B.pbm_regs + SCHIZO_PCI_AFSR, err_mask);
1274 err_mask = (BUS_ERROR_BADCMD | BUS_ERROR_SNOOP_GR |
1275 BUS_ERROR_SNOOP_PCI | BUS_ERROR_SNOOP_RD |
1276 BUS_ERROR_SNOOP_RDS | BUS_ERROR_SNOOP_RDSA |
1277 BUS_ERROR_SNOOP_OWN | BUS_ERROR_SNOOP_RDO |
1278 BUS_ERROR_WDATA_PERR | BUS_ERROR_CTRL_PERR |
1279 BUS_ERROR_SNOOP_ERR | BUS_ERROR_JBUS_ILL_B |
1280 BUS_ERROR_JBUS_ILL_C | BUS_ERROR_RD_PERR |
1281 BUS_ERROR_APERR | BUS_ERROR_UNMAP |
1282 BUS_ERROR_BUSERR | BUS_ERROR_TIMEOUT);
1284 schizo_write(p->pbm_A.controller_regs + SCHIZO_SAFARI_ERRCTRL,
1285 (SCHIZO_SAFERRCTRL_EN | err_mask));
1286 schizo_write(p->pbm_B.controller_regs + SCHIZO_SAFARI_ERRCTRL,
1287 (SCHIZO_SAFERRCTRL_EN | err_mask));
1289 schizo_write(p->pbm_A.controller_regs + SCHIZO_SAFARI_IRQCTRL,
1290 (SCHIZO_SAFIRQCTRL_EN | (BUS_ERROR_UNMAP)));
1291 schizo_write(p->pbm_B.controller_regs + SCHIZO_SAFARI_IRQCTRL,
1292 (SCHIZO_SAFIRQCTRL_EN | (BUS_ERROR_UNMAP)));
1295 static void __init schizo_register_error_handlers(struct pci_controller_info *p)
1297 struct pci_pbm_info *pbm;
1299 struct ino_bucket *bucket;
1300 u64 tmp, err_mask, err_no_mask;
1302 /* Build IRQs and register handlers. */
1303 pbm = pbm_for_ino(p, SCHIZO_UE_INO);
1304 irq = schizo_irq_build(pbm, NULL, (pbm->portid << 6) | SCHIZO_UE_INO);
1305 if (request_irq(irq, schizo_ue_intr,
1306 SA_SHIRQ, "SCHIZO UE", p) < 0) {
1307 prom_printf("%s: Cannot register UE interrupt.\n",
1311 bucket = __bucket(irq);
1312 tmp = upa_readl(bucket->imap);
1313 upa_writel(tmp, (pbm->pbm_regs + schizo_imap_offset(SCHIZO_UE_INO) + 4));
1315 pbm = pbm_for_ino(p, SCHIZO_CE_INO);
1316 irq = schizo_irq_build(pbm, NULL, (pbm->portid << 6) | SCHIZO_CE_INO);
1317 if (request_irq(irq, schizo_ce_intr,
1318 SA_SHIRQ, "SCHIZO CE", p) < 0) {
1319 prom_printf("%s: Cannot register CE interrupt.\n",
1323 bucket = __bucket(irq);
1324 tmp = upa_readl(bucket->imap);
1325 upa_writel(tmp, (pbm->pbm_regs + schizo_imap_offset(SCHIZO_CE_INO) + 4));
1327 pbm = pbm_for_ino(p, SCHIZO_PCIERR_A_INO);
1328 irq = schizo_irq_build(pbm, NULL, (pbm->portid << 6) | SCHIZO_PCIERR_A_INO);
1329 if (request_irq(irq, schizo_pcierr_intr,
1330 SA_SHIRQ, "SCHIZO PCIERR", pbm) < 0) {
1331 prom_printf("%s: Cannot register PBM A PciERR interrupt.\n",
1335 bucket = __bucket(irq);
1336 tmp = upa_readl(bucket->imap);
1337 upa_writel(tmp, (pbm->pbm_regs + schizo_imap_offset(SCHIZO_PCIERR_A_INO) + 4));
1339 pbm = pbm_for_ino(p, SCHIZO_PCIERR_B_INO);
1340 irq = schizo_irq_build(pbm, NULL, (pbm->portid << 6) | SCHIZO_PCIERR_B_INO);
1341 if (request_irq(irq, schizo_pcierr_intr,
1342 SA_SHIRQ, "SCHIZO PCIERR", &p->pbm_B) < 0) {
1343 prom_printf("%s: Cannot register PBM B PciERR interrupt.\n",
1347 bucket = __bucket(irq);
1348 tmp = upa_readl(bucket->imap);
1349 upa_writel(tmp, (pbm->pbm_regs + schizo_imap_offset(SCHIZO_PCIERR_B_INO) + 4));
1351 pbm = pbm_for_ino(p, SCHIZO_SERR_INO);
1352 irq = schizo_irq_build(pbm, NULL, (pbm->portid << 6) | SCHIZO_SERR_INO);
1353 if (request_irq(irq, schizo_safarierr_intr,
1354 SA_SHIRQ, "SCHIZO SERR", p) < 0) {
1355 prom_printf("%s: Cannot register SafariERR interrupt.\n",
1359 bucket = __bucket(irq);
1360 tmp = upa_readl(bucket->imap);
1361 upa_writel(tmp, (pbm->pbm_regs + schizo_imap_offset(SCHIZO_SERR_INO) + 4));
1363 /* Enable UE and CE interrupts for controller. */
1364 schizo_write(p->pbm_A.controller_regs + SCHIZO_ECC_CTRL,
1365 (SCHIZO_ECCCTRL_EE |
1367 SCHIZO_ECCCTRL_CE));
1369 err_mask = (SCHIZO_PCICTRL_BUS_UNUS |
1370 SCHIZO_PCICTRL_ESLCK |
1371 SCHIZO_PCICTRL_TTO_ERR |
1372 SCHIZO_PCICTRL_RTRY_ERR |
1373 SCHIZO_PCICTRL_SBH_ERR |
1374 SCHIZO_PCICTRL_SERR |
1375 SCHIZO_PCICTRL_EEN);
1377 err_no_mask = (SCHIZO_PCICTRL_DTO_ERR |
1378 SCHIZO_PCICTRL_SBH_INT);
1380 /* Enable PCI Error interrupts and clear error
1381 * bits for each PBM.
1383 tmp = schizo_read(p->pbm_A.pbm_regs + SCHIZO_PCI_CTRL);
1385 tmp &= ~err_no_mask;
1386 schizo_write(p->pbm_A.pbm_regs + SCHIZO_PCI_CTRL, tmp);
1388 schizo_write(p->pbm_A.pbm_regs + SCHIZO_PCI_AFSR,
1389 (SCHIZO_PCIAFSR_PMA | SCHIZO_PCIAFSR_PTA |
1390 SCHIZO_PCIAFSR_PRTRY | SCHIZO_PCIAFSR_PPERR |
1391 SCHIZO_PCIAFSR_PTTO | SCHIZO_PCIAFSR_PUNUS |
1392 SCHIZO_PCIAFSR_SMA | SCHIZO_PCIAFSR_STA |
1393 SCHIZO_PCIAFSR_SRTRY | SCHIZO_PCIAFSR_SPERR |
1394 SCHIZO_PCIAFSR_STTO | SCHIZO_PCIAFSR_SUNUS));
1396 tmp = schizo_read(p->pbm_B.pbm_regs + SCHIZO_PCI_CTRL);
1398 tmp &= ~err_no_mask;
1399 schizo_write(p->pbm_B.pbm_regs + SCHIZO_PCI_CTRL, tmp);
1401 schizo_write(p->pbm_B.pbm_regs + SCHIZO_PCI_AFSR,
1402 (SCHIZO_PCIAFSR_PMA | SCHIZO_PCIAFSR_PTA |
1403 SCHIZO_PCIAFSR_PRTRY | SCHIZO_PCIAFSR_PPERR |
1404 SCHIZO_PCIAFSR_PTTO | SCHIZO_PCIAFSR_PUNUS |
1405 SCHIZO_PCIAFSR_SMA | SCHIZO_PCIAFSR_STA |
1406 SCHIZO_PCIAFSR_SRTRY | SCHIZO_PCIAFSR_SPERR |
1407 SCHIZO_PCIAFSR_STTO | SCHIZO_PCIAFSR_SUNUS));
1409 /* Make all Safari error conditions fatal except unmapped
1410 * errors which we make generate interrupts.
1412 err_mask = (BUS_ERROR_BADCMD | BUS_ERROR_SSMDIS |
1413 BUS_ERROR_BADMA | BUS_ERROR_BADMB |
1415 BUS_ERROR_CPU1PS | BUS_ERROR_CPU1PB |
1416 BUS_ERROR_CPU0PS | BUS_ERROR_CPU0PB |
1418 BUS_ERROR_LPQTO | BUS_ERROR_SFPQTO |
1419 BUS_ERROR_UFPQTO | BUS_ERROR_APERR |
1420 BUS_ERROR_BUSERR | BUS_ERROR_TIMEOUT |
1423 /* XXX Something wrong with some Excalibur systems
1424 * XXX Sun is shipping. The behavior on a 2-cpu
1425 * XXX machine is that both CPU1 parity error bits
1426 * XXX are set and are immediately set again when
1427 * XXX their error status bits are cleared. Just
1428 * XXX ignore them for now. -DaveM
1430 err_mask &= ~(BUS_ERROR_CPU1PS | BUS_ERROR_CPU1PB |
1431 BUS_ERROR_CPU0PS | BUS_ERROR_CPU0PB);
1434 schizo_write(p->pbm_A.controller_regs + SCHIZO_SAFARI_ERRCTRL,
1435 (SCHIZO_SAFERRCTRL_EN | err_mask));
1437 schizo_write(p->pbm_A.controller_regs + SCHIZO_SAFARI_IRQCTRL,
1438 (SCHIZO_SAFIRQCTRL_EN | (BUS_ERROR_UNMAP)));
1441 static void __init pbm_config_busmastering(struct pci_pbm_info *pbm)
1445 /* Set cache-line size to 64 bytes, this is actually
1446 * a nop but I do it for completeness.
1448 addr = schizo_pci_config_mkaddr(pbm, pbm->pci_first_busno,
1449 0, PCI_CACHE_LINE_SIZE);
1450 pci_config_write8(addr, 64 / sizeof(u32));
1452 /* Set PBM latency timer to 64 PCI clocks. */
1453 addr = schizo_pci_config_mkaddr(pbm, pbm->pci_first_busno,
1454 0, PCI_LATENCY_TIMER);
1455 pci_config_write8(addr, 64);
1458 static void __init pbm_scan_bus(struct pci_controller_info *p,
1459 struct pci_pbm_info *pbm)
1461 struct pcidev_cookie *cookie = kmalloc(sizeof(*cookie), GFP_KERNEL);
1464 prom_printf("%s: Critical allocation failure.\n", pbm->name);
1468 /* All we care about is the PBM. */
1469 memset(cookie, 0, sizeof(*cookie));
1472 pbm->pci_bus = pci_scan_bus(pbm->pci_first_busno,
1475 pci_fixup_host_bridge_self(pbm->pci_bus);
1476 pbm->pci_bus->self->sysdata = cookie;
1478 pci_fill_in_pbm_cookies(pbm->pci_bus, pbm, pbm->prom_node);
1479 pci_record_assignments(pbm, pbm->pci_bus);
1480 pci_assign_unassigned(pbm, pbm->pci_bus);
1481 pci_fixup_irq(pbm, pbm->pci_bus);
1482 pci_determine_66mhz_disposition(pbm, pbm->pci_bus);
1483 pci_setup_busmastering(pbm, pbm->pci_bus);
1486 static void __init __schizo_scan_bus(struct pci_controller_info *p,
1489 if (!p->pbm_B.prom_node || !p->pbm_A.prom_node) {
1490 printk("PCI: Only one PCI bus module of controller found.\n");
1491 printk("PCI: Ignoring entire controller.\n");
1495 pbm_config_busmastering(&p->pbm_B);
1496 p->pbm_B.is_66mhz_capable =
1497 prom_getbool(p->pbm_B.prom_node, "66mhz-capable");
1498 pbm_config_busmastering(&p->pbm_A);
1499 p->pbm_A.is_66mhz_capable =
1500 prom_getbool(p->pbm_A.prom_node, "66mhz-capable");
1501 pbm_scan_bus(p, &p->pbm_B);
1502 pbm_scan_bus(p, &p->pbm_A);
1504 /* After the PCI bus scan is complete, we can register
1505 * the error interrupt handlers.
1507 if (chip_type == PBM_CHIP_TYPE_TOMATILLO)
1508 tomatillo_register_error_handlers(p);
1510 schizo_register_error_handlers(p);
1513 static void __init schizo_scan_bus(struct pci_controller_info *p)
1515 __schizo_scan_bus(p, PBM_CHIP_TYPE_SCHIZO);
1518 static void __init tomatillo_scan_bus(struct pci_controller_info *p)
1520 __schizo_scan_bus(p, PBM_CHIP_TYPE_TOMATILLO);
1523 static void __init schizo_base_address_update(struct pci_dev *pdev, int resource)
1525 struct pcidev_cookie *pcp = pdev->sysdata;
1526 struct pci_pbm_info *pbm = pcp->pbm;
1527 struct resource *res, *root;
1529 int where, size, is_64bit;
1531 res = &pdev->resource[resource];
1533 where = PCI_BASE_ADDRESS_0 + (resource * 4);
1534 } else if (resource == PCI_ROM_RESOURCE) {
1535 where = pdev->rom_base_reg;
1537 /* Somebody might have asked allocation of a non-standard resource */
1542 if (res->flags & IORESOURCE_IO)
1543 root = &pbm->io_space;
1545 root = &pbm->mem_space;
1546 if ((res->flags & PCI_BASE_ADDRESS_MEM_TYPE_MASK)
1547 == PCI_BASE_ADDRESS_MEM_TYPE_64)
1551 size = res->end - res->start;
1552 pci_read_config_dword(pdev, where, ®);
1553 reg = ((reg & size) |
1554 (((u32)(res->start - root->start)) & ~size));
1555 if (resource == PCI_ROM_RESOURCE) {
1556 reg |= PCI_ROM_ADDRESS_ENABLE;
1557 res->flags |= PCI_ROM_ADDRESS_ENABLE;
1559 pci_write_config_dword(pdev, where, reg);
1561 /* This knows that the upper 32-bits of the address
1562 * must be zero. Our PCI common layer enforces this.
1565 pci_write_config_dword(pdev, where + 4, 0);
1568 static void __init schizo_resource_adjust(struct pci_dev *pdev,
1569 struct resource *res,
1570 struct resource *root)
1572 res->start += root->start;
1573 res->end += root->start;
1576 /* Use ranges property to determine where PCI MEM, I/O, and Config
1577 * space are for this PCI bus module.
1579 static void schizo_determine_mem_io_space(struct pci_pbm_info *pbm)
1581 int i, saw_cfg, saw_mem, saw_io;
1583 saw_cfg = saw_mem = saw_io = 0;
1584 for (i = 0; i < pbm->num_pbm_ranges; i++) {
1585 struct linux_prom_pci_ranges *pr = &pbm->pbm_ranges[i];
1589 type = (pr->child_phys_hi >> 24) & 0x3;
1590 a = (((unsigned long)pr->parent_phys_hi << 32UL) |
1591 ((unsigned long)pr->parent_phys_lo << 0UL));
1595 /* PCI config space, 16MB */
1596 pbm->config_space = a;
1601 /* 16-bit IO space, 16MB */
1602 pbm->io_space.start = a;
1603 pbm->io_space.end = a + ((16UL*1024UL*1024UL) - 1UL);
1604 pbm->io_space.flags = IORESOURCE_IO;
1609 /* 32-bit MEM space, 2GB */
1610 pbm->mem_space.start = a;
1611 pbm->mem_space.end = a + (0x80000000UL - 1UL);
1612 pbm->mem_space.flags = IORESOURCE_MEM;
1621 if (!saw_cfg || !saw_io || !saw_mem) {
1622 prom_printf("%s: Fatal error, missing %s PBM range.\n",
1631 printk("%s: PCI CFG[%lx] IO[%lx] MEM[%lx]\n",
1634 pbm->io_space.start,
1635 pbm->mem_space.start);
1638 static void __init pbm_register_toplevel_resources(struct pci_controller_info *p,
1639 struct pci_pbm_info *pbm)
1641 pbm->io_space.name = pbm->mem_space.name = pbm->name;
1643 request_resource(&ioport_resource, &pbm->io_space);
1644 request_resource(&iomem_resource, &pbm->mem_space);
1645 pci_register_legacy_regions(&pbm->io_space,
1649 #define SCHIZO_STRBUF_CONTROL (0x02800UL)
1650 #define SCHIZO_STRBUF_FLUSH (0x02808UL)
1651 #define SCHIZO_STRBUF_FSYNC (0x02810UL)
1652 #define SCHIZO_STRBUF_CTXFLUSH (0x02818UL)
1653 #define SCHIZO_STRBUF_CTXMATCH (0x10000UL)
1655 static void schizo_pbm_strbuf_init(struct pci_pbm_info *pbm)
1657 unsigned long base = pbm->pbm_regs;
1660 if (pbm->chip_type == PBM_CHIP_TYPE_TOMATILLO) {
1661 /* TOMATILLO lacks streaming cache. */
1665 /* SCHIZO has context flushing. */
1666 pbm->stc.strbuf_control = base + SCHIZO_STRBUF_CONTROL;
1667 pbm->stc.strbuf_pflush = base + SCHIZO_STRBUF_FLUSH;
1668 pbm->stc.strbuf_fsync = base + SCHIZO_STRBUF_FSYNC;
1669 pbm->stc.strbuf_ctxflush = base + SCHIZO_STRBUF_CTXFLUSH;
1670 pbm->stc.strbuf_ctxmatch_base = base + SCHIZO_STRBUF_CTXMATCH;
1672 pbm->stc.strbuf_flushflag = (volatile unsigned long *)
1673 ((((unsigned long)&pbm->stc.__flushflag_buf[0])
1676 pbm->stc.strbuf_flushflag_pa = (unsigned long)
1677 __pa(pbm->stc.strbuf_flushflag);
1679 /* Turn off LRU locking and diag mode, enable the
1680 * streaming buffer and leave the rerun-disable
1681 * setting however OBP set it.
1683 control = schizo_read(pbm->stc.strbuf_control);
1684 control &= ~(SCHIZO_STRBUF_CTRL_LPTR |
1685 SCHIZO_STRBUF_CTRL_LENAB |
1686 SCHIZO_STRBUF_CTRL_DENAB);
1687 control |= SCHIZO_STRBUF_CTRL_ENAB;
1688 schizo_write(pbm->stc.strbuf_control, control);
1690 pbm->stc.strbuf_enabled = 1;
1693 #define SCHIZO_IOMMU_CONTROL (0x00200UL)
1694 #define SCHIZO_IOMMU_TSBBASE (0x00208UL)
1695 #define SCHIZO_IOMMU_FLUSH (0x00210UL)
1696 #define SCHIZO_IOMMU_CTXFLUSH (0x00218UL)
1698 static void schizo_pbm_iommu_init(struct pci_pbm_info *pbm)
1700 struct pci_iommu *iommu = pbm->iommu;
1701 unsigned long tsbbase, i, tagbase, database, order;
1702 u32 vdma[2], dma_mask;
1706 err = prom_getproperty(pbm->prom_node, "virtual-dma",
1707 (char *)&vdma[0], sizeof(vdma));
1708 if (err == 0 || err == -1) {
1709 /* No property, use default values. */
1710 vdma[0] = 0xc0000000;
1711 vdma[1] = 0x40000000;
1717 dma_mask |= 0x1fffffff;
1722 dma_mask |= 0x3fffffff;
1727 dma_mask |= 0x7fffffff;
1732 prom_printf("SCHIZO: strange virtual-dma size.\n");
1736 /* Setup initial software IOMMU state. */
1737 spin_lock_init(&iommu->lock);
1738 iommu->iommu_cur_ctx = 0;
1740 /* Register addresses, SCHIZO has iommu ctx flushing. */
1741 iommu->iommu_control = pbm->pbm_regs + SCHIZO_IOMMU_CONTROL;
1742 iommu->iommu_tsbbase = pbm->pbm_regs + SCHIZO_IOMMU_TSBBASE;
1743 iommu->iommu_flush = pbm->pbm_regs + SCHIZO_IOMMU_FLUSH;
1744 iommu->iommu_ctxflush = pbm->pbm_regs + SCHIZO_IOMMU_CTXFLUSH;
1746 /* We use the main control/status register of SCHIZO as the write
1747 * completion register.
1749 iommu->write_complete_reg = pbm->controller_regs + 0x10000UL;
1752 * Invalidate TLB Entries.
1754 control = schizo_read(iommu->iommu_control);
1755 control |= SCHIZO_IOMMU_CTRL_DENAB;
1756 schizo_write(iommu->iommu_control, control);
1758 tagbase = SCHIZO_IOMMU_TAG, database = SCHIZO_IOMMU_DATA;
1760 for(i = 0; i < 16; i++) {
1761 schizo_write(pbm->pbm_regs + tagbase + (i * 8UL), 0);
1762 schizo_write(pbm->pbm_regs + database + (i * 8UL), 0);
1765 /* Leave diag mode enabled for full-flushing done
1769 iommu->dummy_page = __get_free_pages(GFP_KERNEL, 0);
1770 if (!iommu->dummy_page) {
1771 prom_printf("PSYCHO_IOMMU: Error, gfp(dummy_page) failed.\n");
1774 memset((void *)iommu->dummy_page, 0, PAGE_SIZE);
1775 iommu->dummy_page_pa = (unsigned long) __pa(iommu->dummy_page);
1777 /* Using assumed page size 8K with 128K entries we need 1MB iommu page
1778 * table (128K ioptes * 8 bytes per iopte). This is
1779 * page order 7 on UltraSparc.
1781 order = get_order(tsbsize * 8 * 1024);
1782 tsbbase = __get_free_pages(GFP_KERNEL, order);
1784 prom_printf("%s: Error, gfp(tsb) failed.\n", pbm->name);
1788 iommu->page_table = (iopte_t *)tsbbase;
1789 iommu->page_table_map_base = vdma[0];
1790 iommu->dma_addr_mask = dma_mask;
1791 pci_iommu_table_init(iommu, PAGE_SIZE << order);
1795 iommu->page_table_sz_bits = 16;
1799 iommu->page_table_sz_bits = 17;
1803 prom_printf("iommu_init: Illegal TSB size %d\n", tsbsize);
1808 /* We start with no consistent mappings. */
1809 iommu->lowest_consistent_map =
1810 1 << (iommu->page_table_sz_bits - PBM_LOGCLUSTERS);
1812 for (i = 0; i < PBM_NCLUSTERS; i++) {
1813 iommu->alloc_info[i].flush = 0;
1814 iommu->alloc_info[i].next = 0;
1817 schizo_write(iommu->iommu_tsbbase, __pa(tsbbase));
1819 control = schizo_read(iommu->iommu_control);
1820 control &= ~(SCHIZO_IOMMU_CTRL_TSBSZ | SCHIZO_IOMMU_CTRL_TBWSZ);
1823 control |= SCHIZO_IOMMU_TSBSZ_64K;
1826 control |= SCHIZO_IOMMU_TSBSZ_128K;
1830 control |= SCHIZO_IOMMU_CTRL_ENAB;
1831 schizo_write(iommu->iommu_control, control);
1834 #define SCHIZO_PCI_IRQ_RETRY (0x1a00UL)
1835 #define SCHIZO_IRQ_RETRY_INF 0xffUL
1837 #define SCHIZO_PCI_DIAG (0x2020UL)
1838 #define SCHIZO_PCIDIAG_D_BADECC (1UL << 10UL) /* Disable BAD ECC errors (Schizo) */
1839 #define SCHIZO_PCIDIAG_D_BYPASS (1UL << 9UL) /* Disable MMU bypass mode (Schizo/Tomatillo) */
1840 #define SCHIZO_PCIDIAG_D_TTO (1UL << 8UL) /* Disable TTO errors (Schizo/Tomatillo) */
1841 #define SCHIZO_PCIDIAG_D_RTRYARB (1UL << 7UL) /* Disable retry arbitration (Schizo) */
1842 #define SCHIZO_PCIDIAG_D_RETRY (1UL << 6UL) /* Disable retry limit (Schizo/Tomatillo) */
1843 #define SCHIZO_PCIDIAG_D_INTSYNC (1UL << 5UL) /* Disable interrupt/DMA synch (Schizo/Tomatillo) */
1844 #define SCHIZO_PCIDIAG_I_DMA_PARITY (1UL << 3UL) /* Invert DMA parity (Schizo/Tomatillo) */
1845 #define SCHIZO_PCIDIAG_I_PIOD_PARITY (1UL << 2UL) /* Invert PIO data parity (Schizo/Tomatillo) */
1846 #define SCHIZO_PCIDIAG_I_PIOA_PARITY (1UL << 1UL) /* Invert PIO address parity (Schizo/Tomatillo) */
1848 #define TOMATILLO_PCI_IOC_CSR (0x2248UL)
1849 #define TOMATILLO_IOC_PART_WPENAB 0x0000000000080000UL
1850 #define TOMATILLO_IOC_RDMULT_PENAB 0x0000000000040000UL
1851 #define TOMATILLO_IOC_RDONE_PENAB 0x0000000000020000UL
1852 #define TOMATILLO_IOC_RDLINE_PENAB 0x0000000000010000UL
1853 #define TOMATILLO_IOC_RDMULT_PLEN 0x000000000000c000UL
1854 #define TOMATILLO_IOC_RDMULT_PLEN_SHIFT 14UL
1855 #define TOMATILLO_IOC_RDONE_PLEN 0x0000000000003000UL
1856 #define TOMATILLO_IOC_RDONE_PLEN_SHIFT 12UL
1857 #define TOMATILLO_IOC_RDLINE_PLEN 0x0000000000000c00UL
1858 #define TOMATILLO_IOC_RDLINE_PLEN_SHIFT 10UL
1859 #define TOMATILLO_IOC_PREF_OFF 0x00000000000003f8UL
1860 #define TOMATILLO_IOC_PREF_OFF_SHIFT 3UL
1861 #define TOMATILLO_IOC_RDMULT_CPENAB 0x0000000000000004UL
1862 #define TOMATILLO_IOC_RDONE_CPENAB 0x0000000000000002UL
1863 #define TOMATILLO_IOC_RDLINE_CPENAB 0x0000000000000001UL
1865 #define TOMATILLO_PCI_IOC_TDIAG (0x2250UL)
1866 #define TOMATILLO_PCI_IOC_DDIAG (0x2290UL)
1868 static void __init schizo_pbm_hw_init(struct pci_pbm_info *pbm)
1872 /* Set IRQ retry to infinity. */
1873 schizo_write(pbm->pbm_regs + SCHIZO_PCI_IRQ_RETRY,
1874 SCHIZO_IRQ_RETRY_INF);
1876 /* Enable arbiter for all PCI slots. Also, disable PCI interval
1877 * timer so that DTO (Discard TimeOuts) are not reported because
1878 * some Schizo revisions report them erroneously.
1880 tmp = schizo_read(pbm->pbm_regs + SCHIZO_PCI_CTRL);
1881 if (pbm->chip_type == PBM_CHIP_TYPE_SCHIZO_PLUS &&
1882 pbm->chip_version == 0x5 &&
1883 pbm->chip_revision == 0x1)
1888 tmp &= ~SCHIZO_PCICTRL_PTO;
1889 if (pbm->chip_type == PBM_CHIP_TYPE_TOMATILLO &&
1890 pbm->chip_version == 0x2)
1891 tmp |= 0x3UL << SCHIZO_PCICTRL_PTO_SHIFT;
1893 tmp |= 0x1UL << SCHIZO_PCICTRL_PTO_SHIFT;
1895 if (!prom_getbool(pbm->prom_node, "no-bus-parking"))
1896 tmp |= SCHIZO_PCICTRL_PARK;
1898 if (pbm->chip_type == PBM_CHIP_TYPE_TOMATILLO)
1899 tmp |= SCHIZO_PCICTRL_MRM_PREF;
1901 schizo_write(pbm->pbm_regs + SCHIZO_PCI_CTRL, tmp);
1903 tmp = schizo_read(pbm->pbm_regs + SCHIZO_PCI_DIAG);
1904 tmp &= ~(SCHIZO_PCIDIAG_D_RTRYARB |
1905 SCHIZO_PCIDIAG_D_RETRY |
1906 SCHIZO_PCIDIAG_D_INTSYNC);
1907 schizo_write(pbm->pbm_regs + SCHIZO_PCI_DIAG, tmp);
1909 if (pbm->chip_type == PBM_CHIP_TYPE_TOMATILLO) {
1910 /* Clear prefetch lengths to workaround a bug in
1913 tmp = (TOMATILLO_IOC_PART_WPENAB |
1914 (1 << TOMATILLO_IOC_PREF_OFF_SHIFT) |
1915 TOMATILLO_IOC_RDMULT_CPENAB |
1916 TOMATILLO_IOC_RDONE_CPENAB |
1917 TOMATILLO_IOC_RDLINE_CPENAB);
1919 schizo_write(pbm->pbm_regs + TOMATILLO_PCI_IOC_CSR,
1924 static void __init schizo_pbm_init(struct pci_controller_info *p,
1925 int prom_node, u32 portid,
1928 struct linux_prom64_registers pr_regs[4];
1929 unsigned int busrange[2];
1930 struct pci_pbm_info *pbm;
1931 const char *chipset_name;
1936 switch (chip_type) {
1937 case PBM_CHIP_TYPE_TOMATILLO:
1938 chipset_name = "TOMATILLO";
1941 case PBM_CHIP_TYPE_SCHIZO_PLUS:
1942 chipset_name = "SCHIZO+";
1945 case PBM_CHIP_TYPE_SCHIZO:
1947 chipset_name = "SCHIZO";
1951 /* For SCHIZO, three OBP regs:
1952 * 1) PBM controller regs
1953 * 2) Schizo front-end controller regs (same for both PBMs)
1954 * 3) PBM PCI config space
1956 * For TOMATILLO, four OBP regs:
1957 * 1) PBM controller regs
1958 * 2) Tomatillo front-end controller regs
1959 * 3) PBM PCI config space
1962 err = prom_getproperty(prom_node, "reg",
1963 (char *)&pr_regs[0],
1965 if (err == 0 || err == -1) {
1966 prom_printf("%s: Fatal error, no reg property.\n",
1971 is_pbm_a = ((pr_regs[0].phys_addr & 0x00700000) == 0x00600000);
1978 pbm->portid = portid;
1980 pbm->prom_node = prom_node;
1981 pbm->pci_first_slot = 1;
1983 pbm->chip_type = chip_type;
1985 prom_getintdefault(prom_node, "version#", 0);
1986 pbm->chip_revision =
1987 prom_getintdefault(prom_node, "module-revision#", 0);
1989 pbm->pbm_regs = pr_regs[0].phys_addr;
1990 pbm->controller_regs = pr_regs[1].phys_addr - 0x10000UL;
1993 (chip_type == PBM_CHIP_TYPE_TOMATILLO ?
1994 "TOMATILLO%d PBM%c" :
1997 (pbm == &p->pbm_A ? 'A' : 'B'));
1999 printk("%s: ver[%x:%x], portid %x, "
2000 "cregs[%lx] pregs[%lx]\n",
2002 pbm->chip_version, pbm->chip_revision,
2004 pbm->controller_regs,
2007 schizo_pbm_hw_init(pbm);
2009 prom_getstring(prom_node, "name",
2011 sizeof(pbm->prom_name));
2013 err = prom_getproperty(prom_node, "ranges",
2014 (char *) pbm->pbm_ranges,
2015 sizeof(pbm->pbm_ranges));
2016 if (err == 0 || err == -1) {
2017 prom_printf("%s: Fatal error, no ranges property.\n",
2022 pbm->num_pbm_ranges =
2023 (err / sizeof(struct linux_prom_pci_ranges));
2025 schizo_determine_mem_io_space(pbm);
2026 pbm_register_toplevel_resources(p, pbm);
2028 err = prom_getproperty(prom_node, "interrupt-map",
2029 (char *)pbm->pbm_intmap,
2030 sizeof(pbm->pbm_intmap));
2032 pbm->num_pbm_intmap = (err / sizeof(struct linux_prom_pci_intmap));
2033 err = prom_getproperty(prom_node, "interrupt-map-mask",
2034 (char *)&pbm->pbm_intmask,
2035 sizeof(pbm->pbm_intmask));
2037 prom_printf("%s: Fatal error, no "
2038 "interrupt-map-mask.\n", pbm->name);
2042 pbm->num_pbm_intmap = 0;
2043 memset(&pbm->pbm_intmask, 0, sizeof(pbm->pbm_intmask));
2046 err = prom_getproperty(prom_node, "ino-bitmap",
2047 (char *) &ino_bitmap[0],
2048 sizeof(ino_bitmap));
2049 if (err == 0 || err == -1) {
2050 prom_printf("%s: Fatal error, no ino-bitmap.\n", pbm->name);
2053 pbm->ino_bitmap = (((u64)ino_bitmap[1] << 32UL) |
2054 ((u64)ino_bitmap[0] << 0UL));
2056 err = prom_getproperty(prom_node, "bus-range",
2057 (char *)&busrange[0],
2059 if (err == 0 || err == -1) {
2060 prom_printf("%s: Fatal error, no bus-range.\n", pbm->name);
2063 pbm->pci_first_busno = busrange[0];
2064 pbm->pci_last_busno = busrange[1];
2066 schizo_pbm_iommu_init(pbm);
2067 schizo_pbm_strbuf_init(pbm);
2070 static inline int portid_compare(u32 x, u32 y, int chip_type)
2072 if (chip_type == PBM_CHIP_TYPE_TOMATILLO) {
2080 static void __init __schizo_init(int node, char *model_name, int chip_type)
2082 struct pci_controller_info *p;
2083 struct pci_iommu *iommu;
2087 portid = prom_getintdefault(node, "portid", 0xff);
2089 for(p = pci_controller_root; p; p = p->next) {
2090 struct pci_pbm_info *pbm;
2092 if (p->pbm_A.prom_node && p->pbm_B.prom_node)
2095 pbm = (p->pbm_A.prom_node ?
2099 if (portid_compare(pbm->portid, portid, chip_type)) {
2100 is_pbm_a = (p->pbm_A.prom_node == 0);
2101 schizo_pbm_init(p, node, portid, chip_type);
2106 p = kmalloc(sizeof(struct pci_controller_info), GFP_ATOMIC);
2108 prom_printf("SCHIZO: Fatal memory allocation error.\n");
2111 memset(p, 0, sizeof(*p));
2113 iommu = kmalloc(sizeof(struct pci_iommu), GFP_ATOMIC);
2115 prom_printf("SCHIZO: Fatal memory allocation error.\n");
2118 memset(iommu, 0, sizeof(*iommu));
2119 p->pbm_A.iommu = iommu;
2121 iommu = kmalloc(sizeof(struct pci_iommu), GFP_ATOMIC);
2123 prom_printf("SCHIZO: Fatal memory allocation error.\n");
2126 memset(iommu, 0, sizeof(*iommu));
2127 p->pbm_B.iommu = iommu;
2129 p->next = pci_controller_root;
2130 pci_controller_root = p;
2132 p->index = pci_num_controllers++;
2133 p->pbms_same_domain = 0;
2134 p->scan_bus = (chip_type == PBM_CHIP_TYPE_TOMATILLO ?
2135 tomatillo_scan_bus :
2137 p->irq_build = schizo_irq_build;
2138 p->base_address_update = schizo_base_address_update;
2139 p->resource_adjust = schizo_resource_adjust;
2140 p->pci_ops = &schizo_ops;
2142 /* Like PSYCHO we have a 2GB aligned area for memory space. */
2143 pci_memspace_mask = 0x7fffffffUL;
2145 schizo_pbm_init(p, node, portid, chip_type);
2148 void __init schizo_init(int node, char *model_name)
2150 __schizo_init(node, model_name, PBM_CHIP_TYPE_SCHIZO);
2153 void __init schizo_plus_init(int node, char *model_name)
2155 __schizo_init(node, model_name, PBM_CHIP_TYPE_SCHIZO_PLUS);
2158 void __init tomatillo_init(int node, char *model_name)
2160 __schizo_init(node, model_name, PBM_CHIP_TYPE_TOMATILLO);