1 /* smp.c: Sparc64 SMP support.
3 * Copyright (C) 1997 David S. Miller (davem@caip.rutgers.edu)
6 #include <linux/kernel.h>
7 #include <linux/sched.h>
9 #include <linux/pagemap.h>
10 #include <linux/threads.h>
11 #include <linux/smp.h>
12 #include <linux/smp_lock.h>
13 #include <linux/interrupt.h>
14 #include <linux/kernel_stat.h>
15 #include <linux/delay.h>
16 #include <linux/init.h>
17 #include <linux/spinlock.h>
19 #include <linux/seq_file.h>
20 #include <linux/cache.h>
21 #include <linux/jiffies.h>
22 #include <linux/profile.h>
25 #include <asm/ptrace.h>
26 #include <asm/atomic.h>
27 #include <asm/tlbflush.h>
28 #include <asm/mmu_context.h>
29 #include <asm/cpudata.h>
33 #include <asm/pgtable.h>
34 #include <asm/oplib.h>
35 #include <asm/uaccess.h>
36 #include <asm/timer.h>
37 #include <asm/starfire.h>
40 extern int linux_num_cpus;
41 extern void calibrate_delay(void);
43 /* Please don't make this stuff initdata!!! --DaveM */
44 static unsigned char boot_cpu_id;
46 cpumask_t cpu_online_map = CPU_MASK_NONE;
47 cpumask_t phys_cpu_present_map = CPU_MASK_NONE;
48 static cpumask_t smp_commenced_mask;
49 static cpumask_t cpu_callout_map;
51 void smp_info(struct seq_file *m)
55 seq_printf(m, "State:\n");
56 for (i = 0; i < NR_CPUS; i++) {
59 "CPU%d:\t\tonline\n", i);
63 void smp_bogo(struct seq_file *m)
67 for (i = 0; i < NR_CPUS; i++)
70 "Cpu%dBogo\t: %lu.%02lu\n"
71 "Cpu%dClkTck\t: %016lx\n",
72 i, cpu_data(i).udelay_val / (500000/HZ),
73 (cpu_data(i).udelay_val / (5000/HZ)) % 100,
74 i, cpu_data(i).clock_tick);
77 void __init smp_store_cpu_info(int id)
81 /* multiplier and counter set by
82 smp_setup_percpu_timer() */
83 cpu_data(id).udelay_val = loops_per_jiffy;
85 cpu_find_by_mid(id, &cpu_node);
86 cpu_data(id).clock_tick = prom_getintdefault(cpu_node,
87 "clock-frequency", 0);
89 cpu_data(id).pgcache_size = 0;
90 cpu_data(id).pte_cache[0] = NULL;
91 cpu_data(id).pte_cache[1] = NULL;
92 cpu_data(id).pgdcache_size = 0;
93 cpu_data(id).pgd_cache = NULL;
94 cpu_data(id).idle_volume = 1;
97 static void smp_setup_percpu_timer(void);
99 static volatile unsigned long callin_flag = 0;
101 extern void inherit_locked_prom_mappings(int save_p);
103 void __init smp_callin(void)
105 int cpuid = hard_smp_processor_id();
107 inherit_locked_prom_mappings(0);
111 smp_setup_percpu_timer();
116 smp_store_cpu_info(cpuid);
118 __asm__ __volatile__("membar #Sync\n\t"
119 "flush %%g6" : : : "memory");
121 /* Clear this or we will die instantly when we
122 * schedule back to this idler...
124 clear_thread_flag(TIF_NEWCHILD);
126 /* Attach to the address space of init_task. */
127 atomic_inc(&init_mm.mm_count);
128 current->active_mm = &init_mm;
130 while (!cpu_isset(cpuid, smp_commenced_mask))
133 cpu_set(cpuid, cpu_online_map);
138 printk("CPU[%d]: Returns from cpu_idle!\n", smp_processor_id());
139 panic("SMP bolixed\n");
142 static unsigned long current_tick_offset;
144 /* This tick register synchronization scheme is taken entirely from
145 * the ia64 port, see arch/ia64/kernel/smpboot.c for details and credit.
147 * The only change I've made is to rework it so that the master
148 * initiates the synchonization instead of the slave. -DaveM
152 #define SLAVE (SMP_CACHE_BYTES/sizeof(unsigned long))
154 #define NUM_ROUNDS 64 /* magic value */
155 #define NUM_ITERS 5 /* likewise */
157 static spinlock_t itc_sync_lock = SPIN_LOCK_UNLOCKED;
158 static unsigned long go[SLAVE + 1];
160 #define DEBUG_TICK_SYNC 0
162 static inline long get_delta (long *rt, long *master)
164 unsigned long best_t0 = 0, best_t1 = ~0UL, best_tm = 0;
165 unsigned long tcenter, t0, t1, tm;
168 for (i = 0; i < NUM_ITERS; i++) {
169 t0 = tick_ops->get_tick();
171 membar("#StoreLoad");
172 while (!(tm = go[SLAVE]))
175 membar("#StoreStore");
176 t1 = tick_ops->get_tick();
178 if (t1 - t0 < best_t1 - best_t0)
179 best_t0 = t0, best_t1 = t1, best_tm = tm;
182 *rt = best_t1 - best_t0;
183 *master = best_tm - best_t0;
185 /* average best_t0 and best_t1 without overflow: */
186 tcenter = (best_t0/2 + best_t1/2);
187 if (best_t0 % 2 + best_t1 % 2 == 2)
189 return tcenter - best_tm;
192 void smp_synchronize_tick_client(void)
194 long i, delta, adj, adjust_latency = 0, done = 0;
195 unsigned long flags, rt, master_time_stamp, bound;
198 long rt; /* roundtrip time */
199 long master; /* master's timestamp */
200 long diff; /* difference between midpoint and master's timestamp */
201 long lat; /* estimate of itc adjustment latency */
210 local_irq_save(flags);
212 for (i = 0; i < NUM_ROUNDS; i++) {
213 delta = get_delta(&rt, &master_time_stamp);
215 done = 1; /* let's lock on to this... */
221 adjust_latency += -delta;
222 adj = -delta + adjust_latency/4;
226 tick_ops->add_tick(adj, current_tick_offset);
230 t[i].master = master_time_stamp;
232 t[i].lat = adjust_latency/4;
236 local_irq_restore(flags);
239 for (i = 0; i < NUM_ROUNDS; i++)
240 printk("rt=%5ld master=%5ld diff=%5ld adjlat=%5ld\n",
241 t[i].rt, t[i].master, t[i].diff, t[i].lat);
244 printk(KERN_INFO "CPU %d: synchronized TICK with master CPU (last diff %ld cycles,"
245 "maxerr %lu cycles)\n", smp_processor_id(), delta, rt);
248 static void smp_start_sync_tick_client(int cpu);
250 static void smp_synchronize_one_tick(int cpu)
252 unsigned long flags, i;
256 smp_start_sync_tick_client(cpu);
258 /* wait for client to be ready */
262 /* now let the client proceed into his loop */
264 membar("#StoreLoad");
266 spin_lock_irqsave(&itc_sync_lock, flags);
268 for (i = 0; i < NUM_ROUNDS*NUM_ITERS; i++) {
272 membar("#StoreStore");
273 go[SLAVE] = tick_ops->get_tick();
274 membar("#StoreLoad");
277 spin_unlock_irqrestore(&itc_sync_lock, flags);
280 extern unsigned long sparc64_cpu_startup;
282 /* The OBP cpu startup callback truncates the 3rd arg cookie to
283 * 32-bits (I think) so to be safe we have it read the pointer
284 * contained here so we work on >4GB machines. -DaveM
286 static struct thread_info *cpu_new_thread = NULL;
288 static int __devinit smp_boot_one_cpu(unsigned int cpu)
290 unsigned long entry =
291 (unsigned long)(&sparc64_cpu_startup);
292 unsigned long cookie =
293 (unsigned long)(&cpu_new_thread);
294 struct task_struct *p;
295 int timeout, ret, cpu_node;
299 cpu_new_thread = p->thread_info;
300 cpu_set(cpu, cpu_callout_map);
302 cpu_find_by_mid(cpu, &cpu_node);
303 prom_startcpu(cpu_node, entry, cookie);
305 for (timeout = 0; timeout < 5000000; timeout++) {
313 printk("Processor %d is stuck.\n", cpu);
314 cpu_clear(cpu, cpu_callout_map);
317 cpu_new_thread = NULL;
322 static void spitfire_xcall_helper(u64 data0, u64 data1, u64 data2, u64 pstate, unsigned long cpu)
327 if (this_is_starfire) {
328 /* map to real upaid */
329 cpu = (((cpu & 0x3c) << 1) |
330 ((cpu & 0x40) >> 4) |
334 target = (cpu << 14) | 0x70;
336 /* Ok, this is the real Spitfire Errata #54.
337 * One must read back from a UDB internal register
338 * after writes to the UDB interrupt dispatch, but
339 * before the membar Sync for that write.
340 * So we use the high UDB control register (ASI 0x7f,
341 * ADDR 0x20) for the dummy read. -DaveM
344 __asm__ __volatile__(
345 "wrpr %1, %2, %%pstate\n\t"
346 "stxa %4, [%0] %3\n\t"
347 "stxa %5, [%0+%8] %3\n\t"
349 "stxa %6, [%0+%8] %3\n\t"
351 "stxa %%g0, [%7] %3\n\t"
354 "ldxa [%%g1] 0x7f, %%g0\n\t"
357 : "r" (pstate), "i" (PSTATE_IE), "i" (ASI_INTR_W),
358 "r" (data0), "r" (data1), "r" (data2), "r" (target),
359 "r" (0x10), "0" (tmp)
362 /* NOTE: PSTATE_IE is still clear. */
365 __asm__ __volatile__("ldxa [%%g0] %1, %0"
367 : "i" (ASI_INTR_DISPATCH_STAT));
369 __asm__ __volatile__("wrpr %0, 0x0, %%pstate"
376 } while (result & 0x1);
377 __asm__ __volatile__("wrpr %0, 0x0, %%pstate"
380 printk("CPU[%d]: mondo stuckage result[%016lx]\n",
381 smp_processor_id(), result);
388 static __inline__ void spitfire_xcall_deliver(u64 data0, u64 data1, u64 data2, cpumask_t mask)
393 __asm__ __volatile__("rdpr %%pstate, %0" : "=r" (pstate));
394 for_each_cpu_mask(i, mask)
395 spitfire_xcall_helper(data0, data1, data2, pstate, i);
398 /* Cheetah now allows to send the whole 64-bytes of data in the interrupt
399 * packet, but we have no use for that. However we do take advantage of
400 * the new pipelining feature (ie. dispatch to multiple cpus simultaneously).
402 static void cheetah_xcall_deliver(u64 data0, u64 data1, u64 data2, cpumask_t mask)
405 int nack_busy_id, is_jalapeno;
407 if (cpus_empty(mask))
410 /* Unfortunately, someone at Sun had the brilliant idea to make the
411 * busy/nack fields hard-coded by ITID number for this Ultra-III
412 * derivative processor.
414 __asm__ ("rdpr %%ver, %0" : "=r" (ver));
415 is_jalapeno = ((ver >> 32) == 0x003e0016);
417 __asm__ __volatile__("rdpr %%pstate, %0" : "=r" (pstate));
420 __asm__ __volatile__("wrpr %0, %1, %%pstate\n\t"
421 : : "r" (pstate), "i" (PSTATE_IE));
423 /* Setup the dispatch data registers. */
424 __asm__ __volatile__("stxa %0, [%3] %6\n\t"
425 "stxa %1, [%4] %6\n\t"
426 "stxa %2, [%5] %6\n\t"
429 : "r" (data0), "r" (data1), "r" (data2),
430 "r" (0x40), "r" (0x50), "r" (0x60),
437 for_each_cpu_mask(i, mask) {
438 u64 target = (i << 14) | 0x70;
441 target |= (nack_busy_id << 24);
442 __asm__ __volatile__(
443 "stxa %%g0, [%0] %1\n\t"
446 : "r" (target), "i" (ASI_INTR_W));
451 /* Now, poll for completion. */
456 stuck = 100000 * nack_busy_id;
458 __asm__ __volatile__("ldxa [%%g0] %1, %0"
459 : "=r" (dispatch_stat)
460 : "i" (ASI_INTR_DISPATCH_STAT));
461 if (dispatch_stat == 0UL) {
462 __asm__ __volatile__("wrpr %0, 0x0, %%pstate"
468 } while (dispatch_stat & 0x5555555555555555UL);
470 __asm__ __volatile__("wrpr %0, 0x0, %%pstate"
473 if ((dispatch_stat & ~(0x5555555555555555UL)) == 0) {
474 /* Busy bits will not clear, continue instead
475 * of freezing up on this cpu.
477 printk("CPU[%d]: mondo stuckage result[%016lx]\n",
478 smp_processor_id(), dispatch_stat);
480 int i, this_busy_nack = 0;
482 /* Delay some random time with interrupts enabled
483 * to prevent deadlock.
485 udelay(2 * nack_busy_id);
487 /* Clear out the mask bits for cpus which did not
490 for_each_cpu_mask(i, mask) {
494 check_mask = (0x2UL << (2*i));
496 check_mask = (0x2UL <<
498 if ((dispatch_stat & check_mask) == 0)
508 /* Send cross call to all processors mentioned in MASK
511 static void smp_cross_call_masked(unsigned long *func, u32 ctx, u64 data1, u64 data2, cpumask_t mask)
513 u64 data0 = (((u64)ctx)<<32 | (((u64)func) & 0xffffffff));
514 int this_cpu = get_cpu();
516 cpus_and(mask, mask, cpu_online_map);
517 cpu_clear(this_cpu, mask);
519 if (tlb_type == spitfire)
520 spitfire_xcall_deliver(data0, data1, data2, mask);
522 cheetah_xcall_deliver(data0, data1, data2, mask);
523 /* NOTE: Caller runs local copy on master. */
528 extern unsigned long xcall_sync_tick;
530 static void smp_start_sync_tick_client(int cpu)
532 cpumask_t mask = cpumask_of_cpu(cpu);
534 smp_cross_call_masked(&xcall_sync_tick,
538 /* Send cross call to all processors except self. */
539 #define smp_cross_call(func, ctx, data1, data2) \
540 smp_cross_call_masked(func, ctx, data1, data2, cpu_online_map)
542 struct call_data_struct {
543 void (*func) (void *info);
549 static spinlock_t call_lock = SPIN_LOCK_UNLOCKED;
550 static struct call_data_struct *call_data;
552 extern unsigned long xcall_call_function;
555 * You must not call this function with disabled interrupts or from a
556 * hardware interrupt handler or from a bottom half handler.
558 int smp_call_function(void (*func)(void *info), void *info,
559 int nonatomic, int wait)
561 struct call_data_struct data;
562 int cpus = num_online_cpus() - 1;
568 /* Can deadlock when called with interrupts disabled */
569 WARN_ON(irqs_disabled());
573 atomic_set(&data.finished, 0);
576 spin_lock(&call_lock);
580 smp_cross_call(&xcall_call_function, 0, 0, 0);
583 * Wait for other cpus to complete function or at
584 * least snap the call data.
587 while (atomic_read(&data.finished) != cpus) {
594 spin_unlock(&call_lock);
599 spin_unlock(&call_lock);
600 printk("XCALL: Remote cpus not responding, ncpus=%ld finished=%ld\n",
601 (long) num_online_cpus() - 1L,
602 (long) atomic_read(&data.finished));
606 void smp_call_function_client(int irq, struct pt_regs *regs)
608 void (*func) (void *info) = call_data->func;
609 void *info = call_data->info;
611 clear_softint(1 << irq);
612 if (call_data->wait) {
613 /* let initiator proceed only after completion */
615 atomic_inc(&call_data->finished);
617 /* let initiator proceed after getting data */
618 atomic_inc(&call_data->finished);
623 extern unsigned long xcall_flush_tlb_mm;
624 extern unsigned long xcall_flush_tlb_pending;
625 extern unsigned long xcall_flush_tlb_kernel_range;
626 extern unsigned long xcall_flush_tlb_all_spitfire;
627 extern unsigned long xcall_flush_tlb_all_cheetah;
628 extern unsigned long xcall_report_regs;
629 extern unsigned long xcall_receive_signal;
630 extern unsigned long xcall_flush_dcache_page_cheetah;
631 extern unsigned long xcall_flush_dcache_page_spitfire;
633 #ifdef CONFIG_DEBUG_DCFLUSH
634 extern atomic_t dcpage_flushes;
635 extern atomic_t dcpage_flushes_xcall;
638 static __inline__ void __local_flush_dcache_page(struct page *page)
640 #if (L1DCACHE_SIZE > PAGE_SIZE)
641 __flush_dcache_page(page_address(page),
642 ((tlb_type == spitfire) &&
643 page_mapping(page) != NULL));
645 if (page_mapping(page) != NULL &&
646 tlb_type == spitfire)
647 __flush_icache_page(__pa(page_address(page)));
651 void smp_flush_dcache_page_impl(struct page *page, int cpu)
653 cpumask_t mask = cpumask_of_cpu(cpu);
654 int this_cpu = get_cpu();
656 #ifdef CONFIG_DEBUG_DCFLUSH
657 atomic_inc(&dcpage_flushes);
659 if (cpu == this_cpu) {
660 __local_flush_dcache_page(page);
661 } else if (cpu_online(cpu)) {
662 void *pg_addr = page_address(page);
665 if (tlb_type == spitfire) {
667 ((u64)&xcall_flush_dcache_page_spitfire);
668 if (page_mapping(page) != NULL)
669 data0 |= ((u64)1 << 32);
670 spitfire_xcall_deliver(data0,
676 ((u64)&xcall_flush_dcache_page_cheetah);
677 cheetah_xcall_deliver(data0,
681 #ifdef CONFIG_DEBUG_DCFLUSH
682 atomic_inc(&dcpage_flushes_xcall);
689 void flush_dcache_page_all(struct mm_struct *mm, struct page *page)
691 void *pg_addr = page_address(page);
692 cpumask_t mask = cpu_online_map;
694 int this_cpu = get_cpu();
696 cpu_clear(this_cpu, mask);
698 #ifdef CONFIG_DEBUG_DCFLUSH
699 atomic_inc(&dcpage_flushes);
701 if (cpus_empty(mask))
703 if (tlb_type == spitfire) {
704 data0 = ((u64)&xcall_flush_dcache_page_spitfire);
705 if (page_mapping(page) != NULL)
706 data0 |= ((u64)1 << 32);
707 spitfire_xcall_deliver(data0,
712 data0 = ((u64)&xcall_flush_dcache_page_cheetah);
713 cheetah_xcall_deliver(data0,
717 #ifdef CONFIG_DEBUG_DCFLUSH
718 atomic_inc(&dcpage_flushes_xcall);
721 __local_flush_dcache_page(page);
726 void smp_receive_signal(int cpu)
728 cpumask_t mask = cpumask_of_cpu(cpu);
730 if (cpu_online(cpu)) {
731 u64 data0 = (((u64)&xcall_receive_signal) & 0xffffffff);
733 if (tlb_type == spitfire)
734 spitfire_xcall_deliver(data0, 0, 0, mask);
736 cheetah_xcall_deliver(data0, 0, 0, mask);
740 void smp_receive_signal_client(int irq, struct pt_regs *regs)
742 /* Just return, rtrap takes care of the rest. */
743 clear_softint(1 << irq);
746 void smp_report_regs(void)
748 smp_cross_call(&xcall_report_regs, 0, 0, 0);
751 void smp_flush_tlb_all(void)
753 if (tlb_type == spitfire)
754 smp_cross_call(&xcall_flush_tlb_all_spitfire, 0, 0, 0);
756 smp_cross_call(&xcall_flush_tlb_all_cheetah, 0, 0, 0);
760 /* We know that the window frames of the user have been flushed
761 * to the stack before we get here because all callers of us
762 * are flush_tlb_*() routines, and these run after flush_cache_*()
763 * which performs the flushw.
765 * The SMP TLB coherency scheme we use works as follows:
767 * 1) mm->cpu_vm_mask is a bit mask of which cpus an address
768 * space has (potentially) executed on, this is the heuristic
769 * we use to avoid doing cross calls.
771 * Also, for flushing from kswapd and also for clones, we
772 * use cpu_vm_mask as the list of cpus to make run the TLB.
774 * 2) TLB context numbers are shared globally across all processors
775 * in the system, this allows us to play several games to avoid
778 * One invariant is that when a cpu switches to a process, and
779 * that processes tsk->active_mm->cpu_vm_mask does not have the
780 * current cpu's bit set, that tlb context is flushed locally.
782 * If the address space is non-shared (ie. mm->count == 1) we avoid
783 * cross calls when we want to flush the currently running process's
784 * tlb state. This is done by clearing all cpu bits except the current
785 * processor's in current->active_mm->cpu_vm_mask and performing the
786 * flush locally only. This will force any subsequent cpus which run
787 * this task to flush the context from the local tlb if the process
788 * migrates to another cpu (again).
790 * 3) For shared address spaces (threads) and swapping we bite the
791 * bullet for most cases and perform the cross call (but only to
792 * the cpus listed in cpu_vm_mask).
794 * The performance gain from "optimizing" away the cross call for threads is
795 * questionable (in theory the big win for threads is the massive sharing of
796 * address space state across processors).
798 void smp_flush_tlb_mm(struct mm_struct *mm)
801 * This code is called from two places, dup_mmap and exit_mmap. In the
802 * former case, we really need a flush. In the later case, the callers
803 * are single threaded exec_mmap (really need a flush), multithreaded
804 * exec_mmap case (do not need to flush, since the caller gets a new
805 * context via activate_mm), and all other callers of mmput() whence
806 * the flush can be optimized since the associated threads are dead and
807 * the mm is being torn down (__exit_mm and other mmput callers) or the
808 * owning thread is dissociating itself from the mm. The
809 * (atomic_read(&mm->mm_users) == 0) check ensures real work is done
810 * for single thread exec and dup_mmap cases. An alternate check might
811 * have been (current->mm != mm).
814 if (atomic_read(&mm->mm_users) == 0)
818 u32 ctx = CTX_HWBITS(mm->context);
821 if (atomic_read(&mm->mm_users) == 1) {
822 mm->cpu_vm_mask = cpumask_of_cpu(cpu);
823 goto local_flush_and_out;
826 smp_cross_call_masked(&xcall_flush_tlb_mm,
831 __flush_tlb_mm(ctx, SECONDARY_CONTEXT);
837 void smp_flush_tlb_pending(struct mm_struct *mm, unsigned long nr, unsigned long *vaddrs)
839 u32 ctx = CTX_HWBITS(mm->context);
842 if (mm == current->active_mm && atomic_read(&mm->mm_users) == 1) {
843 mm->cpu_vm_mask = cpumask_of_cpu(cpu);
844 goto local_flush_and_out;
846 /* This optimization is not valid. Normally
847 * we will be holding the page_table_lock, but
848 * there is an exception which is copy_page_range()
849 * when forking. The lock is held during the individual
850 * page table updates in the parent, but not at the
851 * top level, which is where we are invoked.
854 cpumask_t this_cpu_mask = cpumask_of_cpu(cpu);
856 /* By virtue of running under the mm->page_table_lock,
857 * and mmu_context.h:switch_mm doing the same, the
858 * following operation is safe.
860 if (cpus_equal(mm->cpu_vm_mask, this_cpu_mask))
861 goto local_flush_and_out;
865 smp_cross_call_masked(&xcall_flush_tlb_pending,
866 ctx, nr, (unsigned long) vaddrs,
870 __flush_tlb_pending(ctx, nr, vaddrs);
875 void smp_flush_tlb_kernel_range(unsigned long start, unsigned long end)
878 end = PAGE_ALIGN(end);
880 smp_cross_call(&xcall_flush_tlb_kernel_range,
883 __flush_tlb_kernel_range(start, end);
888 /* #define CAPTURE_DEBUG */
889 extern unsigned long xcall_capture;
891 static atomic_t smp_capture_depth = ATOMIC_INIT(0);
892 static atomic_t smp_capture_registry = ATOMIC_INIT(0);
893 static unsigned long penguins_are_doing_time;
895 void smp_capture(void)
897 int result = __atomic_add(1, &smp_capture_depth);
899 membar("#StoreStore | #LoadStore");
901 int ncpus = num_online_cpus();
904 printk("CPU[%d]: Sending penguins to jail...",
907 penguins_are_doing_time = 1;
908 membar("#StoreStore | #LoadStore");
909 atomic_inc(&smp_capture_registry);
910 smp_cross_call(&xcall_capture, 0, 0, 0);
911 while (atomic_read(&smp_capture_registry) != ncpus)
919 void smp_release(void)
921 if (atomic_dec_and_test(&smp_capture_depth)) {
923 printk("CPU[%d]: Giving pardon to "
924 "imprisoned penguins\n",
927 penguins_are_doing_time = 0;
928 membar("#StoreStore | #StoreLoad");
929 atomic_dec(&smp_capture_registry);
933 /* Imprisoned penguins run with %pil == 15, but PSTATE_IE set, so they
934 * can service tlb flush xcalls...
936 extern void prom_world(int);
937 extern void save_alternate_globals(unsigned long *);
938 extern void restore_alternate_globals(unsigned long *);
939 void smp_penguin_jailcell(int irq, struct pt_regs *regs)
941 unsigned long global_save[24];
943 clear_softint(1 << irq);
947 __asm__ __volatile__("flushw");
948 save_alternate_globals(global_save);
950 atomic_inc(&smp_capture_registry);
951 membar("#StoreLoad | #StoreStore");
952 while (penguins_are_doing_time)
954 restore_alternate_globals(global_save);
955 atomic_dec(&smp_capture_registry);
961 extern unsigned long xcall_promstop;
963 void smp_promstop_others(void)
965 smp_cross_call(&xcall_promstop, 0, 0, 0);
968 #define prof_multiplier(__cpu) cpu_data(__cpu).multiplier
969 #define prof_counter(__cpu) cpu_data(__cpu).counter
971 void smp_percpu_timer_interrupt(struct pt_regs *regs)
973 unsigned long compare, tick, pstate;
974 int cpu = smp_processor_id();
975 int user = user_mode(regs);
978 * Check for level 14 softint.
981 unsigned long tick_mask = tick_ops->softint_mask;
983 if (!(get_softint() & tick_mask)) {
984 extern void handler_irq(int, struct pt_regs *);
986 handler_irq(14, regs);
989 clear_softint(tick_mask);
993 profile_tick(CPU_PROFILING, regs);
994 if (!--prof_counter(cpu)) {
997 if (cpu == boot_cpu_id) {
998 kstat_this_cpu.irqs[0]++;
999 timer_tick_interrupt(regs);
1002 update_process_times(user);
1006 prof_counter(cpu) = prof_multiplier(cpu);
1009 /* Guarantee that the following sequences execute
1012 __asm__ __volatile__("rdpr %%pstate, %0\n\t"
1013 "wrpr %0, %1, %%pstate"
1017 compare = tick_ops->add_compare(current_tick_offset);
1018 tick = tick_ops->get_tick();
1020 /* Restore PSTATE_IE. */
1021 __asm__ __volatile__("wrpr %0, 0x0, %%pstate"
1024 } while (time_after_eq(tick, compare));
1027 static void __init smp_setup_percpu_timer(void)
1029 int cpu = smp_processor_id();
1030 unsigned long pstate;
1032 prof_counter(cpu) = prof_multiplier(cpu) = 1;
1034 /* Guarantee that the following sequences execute
1037 __asm__ __volatile__("rdpr %%pstate, %0\n\t"
1038 "wrpr %0, %1, %%pstate"
1042 tick_ops->init_tick(current_tick_offset);
1044 /* Restore PSTATE_IE. */
1045 __asm__ __volatile__("wrpr %0, 0x0, %%pstate"
1050 void __init smp_tick_init(void)
1052 boot_cpu_id = hard_smp_processor_id();
1053 current_tick_offset = timer_tick_offset;
1055 cpu_set(boot_cpu_id, cpu_online_map);
1056 prof_counter(boot_cpu_id) = prof_multiplier(boot_cpu_id) = 1;
1059 cycles_t cacheflush_time;
1060 unsigned long cache_decay_ticks;
1062 extern unsigned long cheetah_tune_scheduling(void);
1064 static void __init smp_tune_scheduling(void)
1066 unsigned long orig_flush_base, flush_base, flags, *p;
1067 unsigned int ecache_size, order;
1068 cycles_t tick1, tick2, raw;
1071 /* Approximate heuristic for SMP scheduling. It is an
1072 * estimation of the time it takes to flush the L2 cache
1073 * on the local processor.
1075 * The ia32 chooses to use the L1 cache flush time instead,
1076 * and I consider this complete nonsense. The Ultra can service
1077 * a miss to the L1 with a hit to the L2 in 7 or 8 cycles, and
1078 * L2 misses are what create extra bus traffic (ie. the "cost"
1079 * of moving a process from one cpu to another).
1081 printk("SMP: Calibrating ecache flush... ");
1082 if (tlb_type == cheetah || tlb_type == cheetah_plus) {
1083 cacheflush_time = cheetah_tune_scheduling();
1087 cpu_find_by_instance(0, &cpu_node, NULL);
1088 ecache_size = prom_getintdefault(cpu_node,
1089 "ecache-size", (512 * 1024));
1090 if (ecache_size > (4 * 1024 * 1024))
1091 ecache_size = (4 * 1024 * 1024);
1092 orig_flush_base = flush_base =
1093 __get_free_pages(GFP_KERNEL, order = get_order(ecache_size));
1095 if (flush_base != 0UL) {
1096 local_irq_save(flags);
1098 /* Scan twice the size once just to get the TLB entries
1099 * loaded and make sure the second scan measures pure misses.
1101 for (p = (unsigned long *)flush_base;
1102 ((unsigned long)p) < (flush_base + (ecache_size<<1));
1103 p += (64 / sizeof(unsigned long)))
1104 *((volatile unsigned long *)p);
1106 tick1 = tick_ops->get_tick();
1108 __asm__ __volatile__("1:\n\t"
1109 "ldx [%0 + 0x000], %%g1\n\t"
1110 "ldx [%0 + 0x040], %%g2\n\t"
1111 "ldx [%0 + 0x080], %%g3\n\t"
1112 "ldx [%0 + 0x0c0], %%g5\n\t"
1113 "add %0, 0x100, %0\n\t"
1115 "bne,pt %%xcc, 1b\n\t"
1117 : "=&r" (flush_base)
1119 "r" (flush_base + ecache_size)
1120 : "g1", "g2", "g3", "g5");
1122 tick2 = tick_ops->get_tick();
1124 local_irq_restore(flags);
1126 raw = (tick2 - tick1);
1128 /* Dampen it a little, considering two processes
1129 * sharing the cache and fitting.
1131 cacheflush_time = (raw - (raw >> 2));
1133 free_pages(orig_flush_base, order);
1135 cacheflush_time = ((ecache_size << 2) +
1136 (ecache_size << 1));
1139 /* Convert ticks/sticks to jiffies. */
1140 cache_decay_ticks = cacheflush_time / timer_tick_offset;
1141 if (cache_decay_ticks < 1)
1142 cache_decay_ticks = 1;
1144 printk("Using heuristic of %ld cycles, %ld ticks.\n",
1145 cacheflush_time, cache_decay_ticks);
1148 /* /proc/profile writes can call this, don't __init it please. */
1149 static spinlock_t prof_setup_lock = SPIN_LOCK_UNLOCKED;
1151 int setup_profiling_timer(unsigned int multiplier)
1153 unsigned long flags;
1156 if ((!multiplier) || (timer_tick_offset / multiplier) < 1000)
1159 spin_lock_irqsave(&prof_setup_lock, flags);
1160 for (i = 0; i < NR_CPUS; i++)
1161 prof_multiplier(i) = multiplier;
1162 current_tick_offset = (timer_tick_offset / multiplier);
1163 spin_unlock_irqrestore(&prof_setup_lock, flags);
1168 void __init smp_prepare_cpus(unsigned int max_cpus)
1173 while (!cpu_find_by_instance(instance, NULL, &mid)) {
1175 cpu_set(mid, phys_cpu_present_map);
1179 if (num_possible_cpus() > max_cpus) {
1181 while (!cpu_find_by_instance(instance, NULL, &mid)) {
1182 if (mid != boot_cpu_id) {
1183 cpu_clear(mid, phys_cpu_present_map);
1184 if (num_possible_cpus() <= max_cpus)
1191 smp_store_cpu_info(boot_cpu_id);
1194 void __devinit smp_prepare_boot_cpu(void)
1196 if (hard_smp_processor_id() >= NR_CPUS) {
1197 prom_printf("Serious problem, boot cpu id >= NR_CPUS\n");
1201 current_thread_info()->cpu = hard_smp_processor_id();
1202 cpu_set(smp_processor_id(), cpu_online_map);
1203 cpu_set(smp_processor_id(), phys_cpu_present_map);
1206 int __devinit __cpu_up(unsigned int cpu)
1208 int ret = smp_boot_one_cpu(cpu);
1211 cpu_set(cpu, smp_commenced_mask);
1212 while (!cpu_isset(cpu, cpu_online_map))
1214 if (!cpu_isset(cpu, cpu_online_map)) {
1217 smp_synchronize_one_tick(cpu);
1223 void __init smp_cpus_done(unsigned int max_cpus)
1225 unsigned long bogosum = 0;
1228 for (i = 0; i < NR_CPUS; i++) {
1230 bogosum += cpu_data(i).udelay_val;
1232 printk("Total of %ld processors activated "
1233 "(%lu.%02lu BogoMIPS).\n",
1234 (long) num_online_cpus(),
1235 bogosum/(500000/HZ),
1236 (bogosum/(5000/HZ))%100);
1238 /* We want to run this with all the other cpus spinning
1241 smp_tune_scheduling();
1244 /* This needn't do anything as we do not sleep the cpu
1245 * inside of the idler task, so an interrupt is not needed
1246 * to get a clean fast response.
1248 * XXX Reverify this assumption... -DaveM
1250 * Addendum: We do want it to do something for the signal
1251 * delivery case, we detect that by just seeing
1252 * if we are trying to send this to an idler or not.
1254 void smp_send_reschedule(int cpu)
1256 if (cpu_data(cpu).idle_volume == 0)
1257 smp_receive_signal(cpu);
1260 /* This is a nop because we capture all other cpus
1261 * anyways when making the PROM active.
1263 void smp_send_stop(void)