1 /* $Id: trampoline.S,v 1.26 2002/02/09 19:49:30 davem Exp $
2 * trampoline.S: Jump start slave processors on sparc64.
4 * Copyright (C) 1997 David S. Miller (davem@caip.rutgers.edu)
12 #include <asm/pstate.h>
14 #include <asm/pgtable.h>
15 #include <asm/spitfire.h>
16 #include <asm/processor.h>
17 #include <asm/thread_info.h>
25 .asciz "SUNW,itlb-load"
28 .asciz "SUNW,dtlb-load"
32 .globl sparc64_cpu_startup, sparc64_cpu_startup_end
36 BRANCH_IF_CHEETAH_BASE(g1,g5,cheetah_startup)
37 BRANCH_IF_CHEETAH_PLUS_OR_FOLLOWON(g1,g5,cheetah_plus_startup)
39 ba,pt %xcc, spitfire_startup
43 /* Preserve OBP chosen DCU and DCR register settings. */
44 ba,pt %xcc, cheetah_generic_startup
48 mov DCR_BPE | DCR_RPE | DCR_SI | DCR_IFPOE | DCR_MS, %g1
51 sethi %uhi(DCU_ME|DCU_RE|DCU_HPE|DCU_SPE|DCU_SL|DCU_WE), %g5
52 or %g5, %ulo(DCU_ME|DCU_RE|DCU_HPE|DCU_SPE|DCU_SL|DCU_WE), %g5
54 or %g5, DCU_DM | DCU_IM | DCU_DC | DCU_IC, %g5
55 stxa %g5, [%g0] ASI_DCU_CONTROL_REG
58 cheetah_generic_startup:
59 mov TSB_EXTENSION_P, %g3
60 stxa %g0, [%g3] ASI_DMMU
61 stxa %g0, [%g3] ASI_IMMU
64 mov TSB_EXTENSION_S, %g3
65 stxa %g0, [%g3] ASI_DMMU
68 mov TSB_EXTENSION_N, %g3
69 stxa %g0, [%g3] ASI_DMMU
70 stxa %g0, [%g3] ASI_IMMU
73 /* Disable STICK_INT interrupts. */
74 sethi %hi(0x80000000), %g5
78 ba,pt %xcc, startup_continue
82 mov (LSU_CONTROL_IC | LSU_CONTROL_DC | LSU_CONTROL_IM | LSU_CONTROL_DM), %g1
83 stxa %g1, [%g0] ASI_LSU_CONTROL
89 sethi %hi(0x80000000), %g2
93 /* Call OBP by hand to lock KERNBASE into i/d tlbs. */
96 sethi %hi(prom_entry_lock), %g2
97 1: ldstub [%g2 + %lo(prom_entry_lock)], %g1
99 membar #StoreLoad | #StoreStore
101 sethi %hi(p1275buf), %g2
102 or %g2, %lo(p1275buf), %g2
103 ldx [%g2 + 0x10], %l2
105 add %l2, -(192 + 128), %sp
108 sethi %hi(call_method), %g2
109 or %g2, %lo(call_method), %g2
110 stx %g2, [%sp + 2047 + 128 + 0x00]
112 stx %g2, [%sp + 2047 + 128 + 0x08]
114 stx %g2, [%sp + 2047 + 128 + 0x10]
115 sethi %hi(itlb_load), %g2
116 or %g2, %lo(itlb_load), %g2
117 stx %g2, [%sp + 2047 + 128 + 0x18]
118 sethi %hi(mmu_ihandle_cache), %g2
119 lduw [%g2 + %lo(mmu_ihandle_cache)], %g2
120 stx %g2, [%sp + 2047 + 128 + 0x20]
121 sethi %hi(KERNBASE), %g2
122 stx %g2, [%sp + 2047 + 128 + 0x28]
123 sethi %hi(kern_locked_tte_data), %g2
124 ldx [%g2 + %lo(kern_locked_tte_data)], %g2
125 stx %g2, [%sp + 2047 + 128 + 0x30]
128 BRANCH_IF_ANY_CHEETAH(g1,g5,1f)
132 stx %g2, [%sp + 2047 + 128 + 0x38]
133 sethi %hi(p1275buf), %g2
134 or %g2, %lo(p1275buf), %g2
135 ldx [%g2 + 0x08], %o1
137 add %sp, (2047 + 128), %o0
139 sethi %hi(call_method), %g2
140 or %g2, %lo(call_method), %g2
141 stx %g2, [%sp + 2047 + 128 + 0x00]
143 stx %g2, [%sp + 2047 + 128 + 0x08]
145 stx %g2, [%sp + 2047 + 128 + 0x10]
146 sethi %hi(dtlb_load), %g2
147 or %g2, %lo(dtlb_load), %g2
148 stx %g2, [%sp + 2047 + 128 + 0x18]
149 sethi %hi(mmu_ihandle_cache), %g2
150 lduw [%g2 + %lo(mmu_ihandle_cache)], %g2
151 stx %g2, [%sp + 2047 + 128 + 0x20]
152 sethi %hi(KERNBASE), %g2
153 stx %g2, [%sp + 2047 + 128 + 0x28]
154 sethi %hi(kern_locked_tte_data), %g2
155 ldx [%g2 + %lo(kern_locked_tte_data)], %g2
156 stx %g2, [%sp + 2047 + 128 + 0x30]
159 BRANCH_IF_ANY_CHEETAH(g1,g5,1f)
164 stx %g2, [%sp + 2047 + 128 + 0x38]
165 sethi %hi(p1275buf), %g2
166 or %g2, %lo(p1275buf), %g2
167 ldx [%g2 + 0x08], %o1
169 add %sp, (2047 + 128), %o0
171 sethi %hi(prom_entry_lock), %g2
172 stb %g0, [%g2 + %lo(prom_entry_lock)]
173 membar #StoreStore | #StoreLoad
180 wrpr %g0, (PSTATE_PRIV | PSTATE_PEF), %pstate
183 /* XXX Buggy PROM... */
189 mov PRIMARY_CONTEXT, %g7
190 stxa %g0, [%g7] ASI_DMMU
192 mov SECONDARY_CONTEXT, %g7
193 stxa %g0, [%g7] ASI_DMMU
197 sllx %g5, THREAD_SHIFT, %g5
198 sub %g5, (STACKFRAME_SZ + STACK_BIAS), %g5
205 /* Setup the trap globals, then we can resurface. */
208 wrpr %o1, PSTATE_AG, %pstate
209 sethi %hi(sparc64_ttable_tl0), %g5
213 wrpr %o1, PSTATE_MG, %pstate
214 #define KERN_HIGHBITS ((_PAGE_VALID|_PAGE_SZ4MB)^0xfffff80000000000)
215 #define KERN_LOWBITS (_PAGE_CP | _PAGE_CV | _PAGE_P | _PAGE_W)
218 stxa %g0, [%g1] ASI_DMMU
221 sethi %uhi(KERN_HIGHBITS), %g2
222 or %g2, %ulo(KERN_HIGHBITS), %g2
224 or %g2, KERN_LOWBITS, %g2
226 BRANCH_IF_ANY_CHEETAH(g3,g7,9f)
232 sethi %uhi(VPTE_BASE_CHEETAH), %g3
233 or %g3, %ulo(VPTE_BASE_CHEETAH), %g3
237 sethi %uhi(VPTE_BASE_SPITFIRE), %g3
238 or %g3, %ulo(VPTE_BASE_SPITFIRE), %g3
246 wrpr %o1, 0x0, %pstate
247 ldx [%g6 + TI_TASK], %g4
251 call init_irqwork_curcpu
255 or %o1, PSTATE_IE, %o1
258 call prom_set_trap_table
259 sethi %hi(sparc64_ttable_tl0), %o0
270 sparc64_cpu_startup_end: