1 /* $Id: ultra.S,v 1.72 2002/02/09 19:49:31 davem Exp $
2 * ultra.S: Don't expand these all over the place...
4 * Copyright (C) 1997, 2000 David S. Miller (davem@redhat.com)
7 #include <linux/config.h>
9 #include <asm/pgtable.h>
11 #include <asm/spitfire.h>
12 #include <asm/mmu_context.h>
15 #include <asm/thread_info.h>
17 /* Basically, most of the Spitfire vs. Cheetah madness
18 * has to do with the fact that Cheetah does not support
19 * IMMU flushes out of the secondary context. Someone needs
20 * to throw a south lake birthday party for the folks
21 * in Microelectronics who refused to fix this shit.
24 /* This file is meant to be read efficiently by the CPU, not humans.
25 * Staraj sie tego nikomu nie pierdolnac...
29 .globl __flush_tlb_page, __flush_tlb_mm, __flush_tlb_range
30 __flush_tlb_page: /* %o0=(ctx & TAG_CONTEXT_BITS), %o1=page&PAGE_MASK, %o2=SECONDARY_CONTEXT */
31 ldxa [%o2] ASI_DMMU, %g2
33 bne,pn %icc, __spitfire_flush_tlb_page_slow
35 stxa %g0, [%g3] ASI_DMMU_DEMAP
36 stxa %g0, [%g3] ASI_IMMU_DEMAP
48 __flush_tlb_mm: /* %o0=(ctx & TAG_CONTEXT_BITS), %o1=SECONDARY_CONTEXT */
49 ldxa [%o1] ASI_DMMU, %g2
51 bne,pn %icc, __spitfire_flush_tlb_mm_slow
53 stxa %g0, [%g3] ASI_DMMU_DEMAP
54 stxa %g0, [%g3] ASI_IMMU_DEMAP
66 __flush_tlb_range: /* %o0=(ctx&TAG_CONTEXT_BITS), %o1=start&PAGE_MASK, %o2=SECONDARY_CONTEXT,
67 * %o3=end&PAGE_MASK, %o4=PAGE_SIZE, %o5=(end - start)
69 #define TLB_MAGIC 207 /* Students, do you know how I calculated this? -DaveM */
71 bleu,pt %xcc, __flush_tlb_page
72 srlx %o5, PAGE_SHIFT, %g5
74 bgeu,pn %icc, __spitfire_flush_tlb_range_constant_time
76 ldxa [%o2] ASI_DMMU, %g2
78 __spitfire_flush_tlb_range_page_by_page:
79 bne,pn %icc, __spitfire_flush_tlb_range_pbp_slow
81 1: stxa %g0, [%g5 + %o5] ASI_DMMU_DEMAP
82 stxa %g0, [%g5 + %o5] ASI_IMMU_DEMAP
87 __spitfire_flush_tlb_range_constant_time: /* %o0=ctx, %o1=start, %o3=end */
89 wrpr %g1, PSTATE_IE, %pstate
90 mov TLB_TAG_ACCESS, %g3
91 mov ((SPITFIRE_HIGHEST_LOCKED_TLBENT-1) << 3), %g2
93 /* Spitfire Errata #32 workaround. */
95 stxa %g0, [%o4] ASI_DMMU
98 1: ldxa [%g2] ASI_ITLB_TAG_READ, %o4
99 and %o4, TAG_CONTEXT_BITS, %o5
102 andn %o4, TAG_CONTEXT_BITS, %o4
107 2: ldxa [%g2] ASI_DTLB_TAG_READ, %o4
108 and %o4, TAG_CONTEXT_BITS, %o5
110 andn %o4, TAG_CONTEXT_BITS, %o4
118 sub %g2, (1 << 3), %g2
120 wrpr %g1, 0x0, %pstate
121 4: stxa %g0, [%g3] ASI_IMMU
122 stxa %g0, [%g2] ASI_ITLB_DATA_ACCESS
125 /* Spitfire Errata #32 workaround. */
127 stxa %g0, [%o4] ASI_DMMU
133 5: stxa %g0, [%g3] ASI_DMMU
134 stxa %g0, [%g2] ASI_DTLB_DATA_ACCESS
137 /* Spitfire Errata #32 workaround. */
139 stxa %g0, [%o4] ASI_DMMU
146 .globl __flush_tlb_kernel_range
147 __flush_tlb_kernel_range: /* %o0=start, %o1=end */
150 sethi %hi(PAGE_SIZE), %o4
153 or %o0, 0x20, %o0 ! Nucleus
154 1: stxa %g0, [%o0 + %o3] ASI_DMMU_DEMAP
155 stxa %g0, [%o0 + %o3] ASI_IMMU_DEMAP
162 __spitfire_flush_tlb_mm_slow:
164 wrpr %g1, PSTATE_IE, %pstate
165 stxa %o0, [%o1] ASI_DMMU
166 stxa %g0, [%g3] ASI_DMMU_DEMAP
167 stxa %g0, [%g3] ASI_IMMU_DEMAP
169 stxa %g2, [%o1] ASI_DMMU
174 __spitfire_flush_tlb_page_slow:
176 wrpr %g1, PSTATE_IE, %pstate
177 stxa %o0, [%o2] ASI_DMMU
178 stxa %g0, [%g3] ASI_DMMU_DEMAP
179 stxa %g0, [%g3] ASI_IMMU_DEMAP
181 stxa %g2, [%o2] ASI_DMMU
186 __spitfire_flush_tlb_range_pbp_slow:
188 wrpr %g1, PSTATE_IE, %pstate
189 stxa %o0, [%o2] ASI_DMMU
191 2: stxa %g0, [%g5 + %o5] ASI_DMMU_DEMAP
192 stxa %g0, [%g5 + %o5] ASI_IMMU_DEMAP
196 stxa %g2, [%o2] ASI_DMMU
199 wrpr %g1, 0x0, %pstate
202 * The following code flushes one page_size worth.
204 #if (PAGE_SHIFT == 13)
205 #define ITAG_MASK 0xfe
206 #elif (PAGE_SHIFT == 16)
207 #define ITAG_MASK 0x7fe
209 #error unsupported PAGE_SIZE
212 .globl __flush_icache_page
213 __flush_icache_page: /* %o0 = phys_page */
214 sethi %hi(1 << 13), %o2 ! IC_set bit
219 ldda [%o1] ASI_IC_TAG, %o4
221 or %o0, %g1, %o0 ! VALID+phys-addr comparitor
224 andn %g2, ITAG_MASK, %g2 ! IC_tag mask
232 1: addx %g0, %g0, %g0
233 ldda [%o1 + %o2] ASI_IC_TAG, %g4
238 ldda [%o1] ASI_IC_TAG, %o4
251 ldx [%g6 + TI_TASK], %g4
253 iflush1:sub %o1, 0x20, %g3
254 stxa %g0, [%g3] ASI_IC_TAG
257 iflush2:sub %o1, 0x20, %g3
258 stxa %g0, [%o1 + %o2] ASI_IC_TAG
262 #if (PAGE_SHIFT == 13)
263 #define DTAG_MASK 0x3
264 #elif (PAGE_SHIFT == 16)
265 #define DTAG_MASK 0x1f
266 #elif (PAGE_SHIFT == 19)
267 #define DTAG_MASK 0xff
268 #elif (PAGE_SHIFT == 22)
269 #define DTAG_MASK 0x3ff
273 .globl __flush_dcache_page
274 __flush_dcache_page: /* %o0=kaddr, %o1=flush_icache */
275 sethi %uhi(PAGE_OFFSET), %g1
280 sethi %hi(1 << 14), %o2
281 1: ldxa [%o4] ASI_DCACHE_TAG, %o3 ! LSU Group
282 add %o4, (1 << 5), %o4 ! IEU0
283 ldxa [%o4] ASI_DCACHE_TAG, %g1 ! LSU Group
284 add %o4, (1 << 5), %o4 ! IEU0
285 ldxa [%o4] ASI_DCACHE_TAG, %g2 ! LSU Group o3 available
286 add %o4, (1 << 5), %o4 ! IEU0
287 andn %o3, DTAG_MASK, %o3 ! IEU1
288 ldxa [%o4] ASI_DCACHE_TAG, %g3 ! LSU Group
289 add %o4, (1 << 5), %o4 ! IEU0
290 andn %g1, DTAG_MASK, %g1 ! IEU1
291 cmp %o0, %o3 ! IEU1 Group
292 be,a,pn %xcc, dflush1 ! CTI
293 sub %o4, (4 << 5), %o4 ! IEU0 (Group)
294 cmp %o0, %g1 ! IEU1 Group
295 andn %g2, DTAG_MASK, %g2 ! IEU0
296 be,a,pn %xcc, dflush2 ! CTI
297 sub %o4, (3 << 5), %o4 ! IEU0 (Group)
298 cmp %o0, %g2 ! IEU1 Group
299 andn %g3, DTAG_MASK, %g3 ! IEU0
300 be,a,pn %xcc, dflush3 ! CTI
301 sub %o4, (2 << 5), %o4 ! IEU0 (Group)
302 cmp %o0, %g3 ! IEU1 Group
303 be,a,pn %xcc, dflush4 ! CTI
304 sub %o4, (1 << 5), %o4 ! IEU0
305 2: cmp %o4, %o2 ! IEU1 Group
306 bne,pt %xcc, 1b ! CTI
309 /* The I-cache does not snoop local stores so we
310 * better flush that too when necessary.
312 brnz,pt %o1, __flush_icache_page
317 dflush1:stxa %g0, [%o4] ASI_DCACHE_TAG
318 add %o4, (1 << 5), %o4
319 dflush2:stxa %g0, [%o4] ASI_DCACHE_TAG
320 add %o4, (1 << 5), %o4
321 dflush3:stxa %g0, [%o4] ASI_DCACHE_TAG
322 add %o4, (1 << 5), %o4
323 dflush4:stxa %g0, [%o4] ASI_DCACHE_TAG
324 add %o4, (1 << 5), %o4
332 wrpr %g7, PSTATE_IE, %pstate
333 mov TLB_TAG_ACCESS, %g1
334 stxa %o5, [%g1] ASI_DMMU
335 stxa %o2, [%g0] ASI_DTLB_DATA_IN
341 wrpr %g7, PSTATE_IE, %pstate
342 mov TLB_TAG_ACCESS, %g1
343 stxa %o5, [%g1] ASI_IMMU
344 stxa %o2, [%g0] ASI_ITLB_DATA_IN
349 .globl __update_mmu_cache
350 __update_mmu_cache: /* %o0=hw_context, %o1=address, %o2=pte, %o3=fault_code */
351 srlx %o1, PAGE_SHIFT, %o1
352 andcc %o3, FAULT_CODE_DTLB, %g0
353 sllx %o1, PAGE_SHIFT, %o5
354 bne,pt %xcc, __prefill_dtlb
356 ba,a,pt %xcc, __prefill_itlb
358 /* Cheetah specific versions, patched at boot time. */
359 __cheetah_flush_tlb_page: /* 14 insns */
361 andn %g5, PSTATE_IE, %g2
362 wrpr %g2, 0x0, %pstate
364 mov PRIMARY_CONTEXT, %o2
365 ldxa [%o2] ASI_DMMU, %g2
366 stxa %o0, [%o2] ASI_DMMU
367 stxa %g0, [%o1] ASI_DMMU_DEMAP
368 stxa %g0, [%o1] ASI_IMMU_DEMAP
369 stxa %g2, [%o2] ASI_DMMU
373 wrpr %g5, 0x0, %pstate
375 __cheetah_flush_tlb_mm: /* 15 insns */
377 andn %g5, PSTATE_IE, %g2
378 wrpr %g2, 0x0, %pstate
380 mov PRIMARY_CONTEXT, %o2
382 ldxa [%o2] ASI_DMMU, %g2
383 stxa %o0, [%o2] ASI_DMMU
384 stxa %g0, [%g3] ASI_DMMU_DEMAP
385 stxa %g0, [%g3] ASI_IMMU_DEMAP
386 stxa %g2, [%o2] ASI_DMMU
390 wrpr %g5, 0x0, %pstate
392 __cheetah_flush_tlb_range: /* 20 insns */
396 andn %g5, PSTATE_IE, %g2
397 wrpr %g2, 0x0, %pstate
399 mov PRIMARY_CONTEXT, %o2
401 ldxa [%o2] ASI_DMMU, %g2
402 stxa %o0, [%o2] ASI_DMMU
403 1: stxa %g0, [%o1 + %o5] ASI_DMMU_DEMAP
404 stxa %g0, [%o1 + %o5] ASI_IMMU_DEMAP
408 stxa %g2, [%o2] ASI_DMMU
412 wrpr %g5, 0x0, %pstate
414 flush_dcpage_cheetah: /* 11 insns */
415 sethi %uhi(PAGE_OFFSET), %g1
418 sethi %hi(PAGE_SIZE), %o4
419 1: subcc %o4, (1 << 5), %o4
420 stxa %g0, [%o0 + %o4] ASI_DCACHE_INVALIDATE
424 retl /* I-cache flush never needed on Cheetah, see callers. */
438 .globl cheetah_patch_cachetlbops
439 cheetah_patch_cachetlbops:
442 sethi %hi(__flush_tlb_page), %o0
443 or %o0, %lo(__flush_tlb_page), %o0
444 sethi %hi(__cheetah_flush_tlb_page), %o1
445 or %o1, %lo(__cheetah_flush_tlb_page), %o1
446 call cheetah_patch_one
449 sethi %hi(__flush_tlb_mm), %o0
450 or %o0, %lo(__flush_tlb_mm), %o0
451 sethi %hi(__cheetah_flush_tlb_mm), %o1
452 or %o1, %lo(__cheetah_flush_tlb_mm), %o1
453 call cheetah_patch_one
456 sethi %hi(__flush_tlb_range), %o0
457 or %o0, %lo(__flush_tlb_range), %o0
458 sethi %hi(__cheetah_flush_tlb_range), %o1
459 or %o1, %lo(__cheetah_flush_tlb_range), %o1
460 call cheetah_patch_one
463 sethi %hi(__flush_dcache_page), %o0
464 or %o0, %lo(__flush_dcache_page), %o0
465 sethi %hi(flush_dcpage_cheetah), %o1
466 or %o1, %lo(flush_dcpage_cheetah), %o1
467 call cheetah_patch_one
474 /* These are all called by the slaves of a cross call, at
475 * trap level 1, with interrupts fully disabled.
478 * %g5 mm->context (all tlb flushes)
479 * %g1 address arg 1 (tlb page and range flushes)
480 * %g7 address arg 2 (tlb range flush only)
482 * %g6 ivector table, don't touch
487 * TODO: Make xcall TLB range flushes use the tricks above... -DaveM
490 .globl xcall_flush_tlb_page, xcall_flush_tlb_mm, xcall_flush_tlb_range
491 xcall_flush_tlb_page:
492 mov PRIMARY_CONTEXT, %g2
493 ldxa [%g2] ASI_DMMU, %g3
494 stxa %g5, [%g2] ASI_DMMU
495 stxa %g0, [%g1] ASI_DMMU_DEMAP
496 stxa %g0, [%g1] ASI_IMMU_DEMAP
497 stxa %g3, [%g2] ASI_DMMU
502 mov PRIMARY_CONTEXT, %g2
504 ldxa [%g2] ASI_DMMU, %g3
505 stxa %g5, [%g2] ASI_DMMU
506 stxa %g0, [%g4] ASI_DMMU_DEMAP
507 stxa %g0, [%g4] ASI_IMMU_DEMAP
508 stxa %g3, [%g2] ASI_DMMU
511 xcall_flush_tlb_range:
512 sethi %hi(PAGE_SIZE - 1), %g2
513 or %g2, %lo(PAGE_SIZE - 1), %g2
518 srlx %g3, PAGE_SHIFT, %g4
521 bgu,pn %icc, xcall_flush_tlb_mm
522 mov PRIMARY_CONTEXT, %g4
523 ldxa [%g4] ASI_DMMU, %g7
525 stxa %g5, [%g4] ASI_DMMU
530 1: stxa %g0, [%g1 + %g3] ASI_DMMU_DEMAP
531 stxa %g0, [%g1 + %g3] ASI_IMMU_DEMAP
535 stxa %g7, [%g4] ASI_DMMU
540 .globl xcall_flush_tlb_kernel_range
541 xcall_flush_tlb_kernel_range:
542 sethi %hi(PAGE_SIZE - 1), %g2
543 or %g2, %lo(PAGE_SIZE - 1), %g2
549 or %g1, 0x20, %g1 ! Nucleus
550 1: stxa %g0, [%g1 + %g3] ASI_DMMU_DEMAP
551 stxa %g0, [%g1 + %g3] ASI_IMMU_DEMAP
560 /* This runs in a very controlled environment, so we do
561 * not need to worry about BH races etc.
563 .globl xcall_sync_tick
566 wrpr %g2, PSTATE_IG | PSTATE_AG, %pstate
571 109: or %g7, %lo(109b), %g7
572 call smp_synchronize_tick_client
576 ldx [%sp + PTREGS_OFF + PT_V9_TSTATE], %l1
578 /* NOTE: This is SPECIAL!! We do etrap/rtrap however
579 * we choose to deal with the "BH's run with
580 * %pil==15" problem (described in asm/pil.h)
581 * by just invoking rtrap directly past where
582 * BH's are checked for.
584 * We do it like this because we do not want %pil==15
585 * lockups to prevent regs being reported.
587 .globl xcall_report_regs
590 wrpr %g2, PSTATE_IG | PSTATE_AG, %pstate
595 109: or %g7, %lo(109b), %g7
597 add %sp, PTREGS_OFF, %o0
599 /* Has to be a non-v9 branch due to the large distance. */
601 ldx [%sp + PTREGS_OFF + PT_V9_TSTATE], %l1
604 .globl xcall_flush_dcache_page_cheetah
605 xcall_flush_dcache_page_cheetah: /* %g1 == physical page address */
606 sethi %hi(PAGE_SIZE), %g3
607 1: subcc %g3, (1 << 5), %g3
608 stxa %g0, [%g1 + %g3] ASI_DCACHE_INVALIDATE
615 .globl xcall_flush_dcache_page_spitfire
616 xcall_flush_dcache_page_spitfire: /* %g1 == physical page address
617 %g7 == kernel page virtual address
618 %g5 == (page->mapping != NULL) */
619 #if (L1DCACHE_SIZE > PAGE_SIZE)
620 srlx %g1, (13 - 2), %g1 ! Form tag comparitor
621 sethi %hi(L1DCACHE_SIZE), %g3 ! D$ size == 16K
622 sub %g3, (1 << 5), %g3 ! D$ linesize == 32
623 1: ldxa [%g3] ASI_DCACHE_TAG, %g2
631 stxa %g0, [%g3] ASI_DCACHE_TAG
635 sub %g3, (1 << 5), %g3
638 #endif /* L1DCACHE_SIZE > PAGE_SIZE */
639 sethi %hi(PAGE_SIZE), %g3
642 subcc %g3, (1 << 5), %g3
644 add %g7, (1 << 5), %g7
650 .globl xcall_promstop
653 wrpr %g2, PSTATE_IG | PSTATE_AG, %pstate
658 109: or %g7, %lo(109b), %g7
662 /* We should not return, just spin if we do... */
673 /* These two are not performance critical... */
674 .globl xcall_flush_tlb_all_spitfire
675 xcall_flush_tlb_all_spitfire:
676 /* Spitfire Errata #32 workaround. */
677 sethi %hi(errata32_hwbug), %g4
678 stx %g0, [%g4 + %lo(errata32_hwbug)]
682 1: ldxa [%g3] ASI_DTLB_DATA_ACCESS, %g4
683 and %g4, _PAGE_L, %g5
685 mov TLB_TAG_ACCESS, %g7
687 stxa %g0, [%g7] ASI_DMMU
689 stxa %g0, [%g3] ASI_DTLB_DATA_ACCESS
692 /* Spitfire Errata #32 workaround. */
693 sethi %hi(errata32_hwbug), %g4
694 stx %g0, [%g4 + %lo(errata32_hwbug)]
696 2: ldxa [%g3] ASI_ITLB_DATA_ACCESS, %g4
697 and %g4, _PAGE_L, %g5
699 mov TLB_TAG_ACCESS, %g7
701 stxa %g0, [%g7] ASI_IMMU
703 stxa %g0, [%g3] ASI_ITLB_DATA_ACCESS
706 /* Spitfire Errata #32 workaround. */
707 sethi %hi(errata32_hwbug), %g4
708 stx %g0, [%g4 + %lo(errata32_hwbug)]
711 cmp %g2, SPITFIRE_HIGHEST_LOCKED_TLBENT
717 .globl xcall_flush_tlb_all_cheetah
718 xcall_flush_tlb_all_cheetah:
720 stxa %g0, [%g2] ASI_DMMU_DEMAP
721 stxa %g0, [%g2] ASI_IMMU_DEMAP
724 /* These just get rescheduled to PIL vectors. */
725 .globl xcall_call_function
727 wr %g0, (1 << PIL_SMP_CALL_FUNC), %set_softint
730 .globl xcall_receive_signal
731 xcall_receive_signal:
732 wr %g0, (1 << PIL_SMP_RECEIVE_SIGNAL), %set_softint
737 wr %g0, (1 << PIL_SMP_CAPTURE), %set_softint
740 #endif /* CONFIG_SMP */