2 * Local APIC handling, local APIC timers
4 * (c) 1999, 2000 Ingo Molnar <mingo@redhat.com>
7 * Maciej W. Rozycki : Bits for genuine 82489DX APICs;
8 * thanks to Eric Gilmore
10 * for testing these extensively.
11 * Maciej W. Rozycki : Various updates and fixes.
12 * Mikael Pettersson : Power Management for UP-APIC.
14 * Mikael Pettersson : PM converted to driver model.
17 #include <linux/config.h>
18 #include <linux/init.h>
21 #include <linux/irq.h>
22 #include <linux/delay.h>
23 #include <linux/bootmem.h>
24 #include <linux/smp_lock.h>
25 #include <linux/interrupt.h>
26 #include <linux/mc146818rtc.h>
27 #include <linux/kernel_stat.h>
28 #include <linux/sysdev.h>
30 #include <asm/atomic.h>
33 #include <asm/mpspec.h>
34 #include <asm/pgalloc.h>
36 int disable_apic_timer __initdata;
38 /* Using APIC to generate smp_local_timer_interrupt? */
39 int using_apic_timer = 0;
41 static DEFINE_PER_CPU(int, prof_multiplier) = 1;
42 static DEFINE_PER_CPU(int, prof_old_multiplier) = 1;
43 static DEFINE_PER_CPU(int, prof_counter) = 1;
45 static void apic_pm_activate(void);
47 void enable_NMI_through_LVT0 (void * dummy)
51 ver = apic_read(APIC_LVR);
52 ver = GET_APIC_VERSION(ver);
53 v = APIC_DM_NMI; /* unmask and set to NMI */
54 apic_write_around(APIC_LVT0, v);
59 unsigned int v, ver, maxlvt;
61 v = apic_read(APIC_LVR);
62 ver = GET_APIC_VERSION(v);
63 maxlvt = GET_APIC_MAXLVT(v);
67 void clear_local_APIC(void)
72 maxlvt = get_maxlvt();
75 * Masking an LVT entry on a P6 can trigger a local APIC error
76 * if the vector is zero. Mask LVTERR first to prevent this.
79 v = ERROR_APIC_VECTOR; /* any non-zero vector will do */
80 apic_write_around(APIC_LVTERR, v | APIC_LVT_MASKED);
83 * Careful: we have to set masks only first to deassert
84 * any level-triggered sources.
86 v = apic_read(APIC_LVTT);
87 apic_write_around(APIC_LVTT, v | APIC_LVT_MASKED);
88 v = apic_read(APIC_LVT0);
89 apic_write_around(APIC_LVT0, v | APIC_LVT_MASKED);
90 v = apic_read(APIC_LVT1);
91 apic_write_around(APIC_LVT1, v | APIC_LVT_MASKED);
93 v = apic_read(APIC_LVTPC);
94 apic_write_around(APIC_LVTPC, v | APIC_LVT_MASKED);
98 * Clean APIC state for other OSs:
100 apic_write_around(APIC_LVTT, APIC_LVT_MASKED);
101 apic_write_around(APIC_LVT0, APIC_LVT_MASKED);
102 apic_write_around(APIC_LVT1, APIC_LVT_MASKED);
104 apic_write_around(APIC_LVTERR, APIC_LVT_MASKED);
106 apic_write_around(APIC_LVTPC, APIC_LVT_MASKED);
107 v = GET_APIC_VERSION(apic_read(APIC_LVR));
108 if (APIC_INTEGRATED(v)) { /* !82489DX */
109 if (maxlvt > 3) /* Due to Pentium errata 3AP and 11AP. */
110 apic_write(APIC_ESR, 0);
115 void __init connect_bsp_APIC(void)
119 * Do not trust the local APIC being empty at bootup.
123 * PIC mode, enable APIC mode in the IMCR, i.e.
124 * connect BSP's local APIC to INT and NMI lines.
126 printk(KERN_INFO "leaving PIC mode, enabling APIC mode.\n");
132 void disconnect_bsp_APIC(void)
136 * Put the board back into PIC mode (has an effect
137 * only on certain older boards). Note that APIC
138 * interrupts, including IPIs, won't work beyond
139 * this point! The only exception are INIT IPIs.
141 printk(KERN_INFO "disabling APIC mode, entering PIC mode.\n");
147 void disable_local_APIC(void)
154 * Disable APIC (implies clearing of registers
157 value = apic_read(APIC_SPIV);
158 value &= ~APIC_SPIV_APIC_ENABLED;
159 apic_write_around(APIC_SPIV, value);
163 * This is to verify that we're looking at a real local APIC.
164 * Check these against your board if the CPUs aren't getting
165 * started for no apparent reason.
167 int __init verify_local_APIC(void)
169 unsigned int reg0, reg1;
172 * The version register is read-only in a real APIC.
174 reg0 = apic_read(APIC_LVR);
175 Dprintk("Getting VERSION: %x\n", reg0);
176 apic_write(APIC_LVR, reg0 ^ APIC_LVR_MASK);
177 reg1 = apic_read(APIC_LVR);
178 Dprintk("Getting VERSION: %x\n", reg1);
181 * The two version reads above should print the same
182 * numbers. If the second one is different, then we
183 * poke at a non-APIC.
189 * Check if the version looks reasonably.
191 reg1 = GET_APIC_VERSION(reg0);
192 if (reg1 == 0x00 || reg1 == 0xff)
195 if (reg1 < 0x02 || reg1 == 0xff)
199 * The ID register is read/write in a real APIC.
201 reg0 = apic_read(APIC_ID);
202 Dprintk("Getting ID: %x\n", reg0);
203 apic_write(APIC_ID, reg0 ^ APIC_ID_MASK);
204 reg1 = apic_read(APIC_ID);
205 Dprintk("Getting ID: %x\n", reg1);
206 apic_write(APIC_ID, reg0);
207 if (reg1 != (reg0 ^ APIC_ID_MASK))
211 * The next two are just to see if we have sane values.
212 * They're only really relevant if we're in Virtual Wire
213 * compatibility mode, but most boxes are anymore.
215 reg0 = apic_read(APIC_LVT0);
216 Dprintk("Getting LVT0: %x\n", reg0);
217 reg1 = apic_read(APIC_LVT1);
218 Dprintk("Getting LVT1: %x\n", reg1);
223 void __init sync_Arb_IDs(void)
228 apic_wait_icr_idle();
230 Dprintk("Synchronizing Arb IDs.\n");
231 apic_write_around(APIC_ICR, APIC_DEST_ALLINC | APIC_INT_LEVELTRIG
235 extern void __error_in_apic_c (void);
238 * An initial setup of the virtual wire mode.
240 void __init init_bsp_APIC(void)
242 unsigned int value, ver;
245 * Don't do the setup now if we have a SMP BIOS as the
246 * through-I/O-APIC virtual wire mode might be active.
248 if (smp_found_config || !cpu_has_apic)
251 value = apic_read(APIC_LVR);
252 ver = GET_APIC_VERSION(value);
255 * Do not trust the local APIC being empty at bootup.
262 value = apic_read(APIC_SPIV);
263 value &= ~APIC_VECTOR_MASK;
264 value |= APIC_SPIV_APIC_ENABLED;
265 value |= APIC_SPIV_FOCUS_DISABLED;
266 value |= SPURIOUS_APIC_VECTOR;
267 apic_write_around(APIC_SPIV, value);
270 * Set up the virtual wire mode.
272 apic_write_around(APIC_LVT0, APIC_DM_EXTINT);
274 if (!APIC_INTEGRATED(ver)) /* 82489DX */
275 value |= APIC_LVT_LEVEL_TRIGGER;
276 apic_write_around(APIC_LVT1, value);
279 void __init setup_local_APIC (void)
281 unsigned int value, ver, maxlvt;
283 /* Pound the ESR really hard over the head with a big hammer - mbligh */
285 apic_write(APIC_ESR, 0);
286 apic_write(APIC_ESR, 0);
287 apic_write(APIC_ESR, 0);
288 apic_write(APIC_ESR, 0);
291 value = apic_read(APIC_LVR);
292 ver = GET_APIC_VERSION(value);
294 if ((SPURIOUS_APIC_VECTOR & 0x0f) != 0x0f)
298 * Double-check whether this APIC is really registered.
299 * This is meaningless in clustered apic mode, so we skip it.
301 if (!clustered_apic_mode &&
302 !physid_isset(GET_APIC_ID(apic_read(APIC_ID)), phys_cpu_present_map))
306 * Intel recommends to set DFR, LDR and TPR before enabling
307 * an APIC. See e.g. "AP-388 82489DX User's Manual" (Intel
308 * document number 292116). So here it goes...
311 if (!clustered_apic_mode) {
313 * In clustered apic mode, the firmware does this for us
314 * Put the APIC into flat delivery mode.
315 * Must be "all ones" explicitly for 82489DX.
317 apic_write_around(APIC_DFR, 0xffffffff);
320 * Set up the logical destination ID.
322 value = apic_read(APIC_LDR);
323 value &= ~APIC_LDR_MASK;
324 value |= (1<<(smp_processor_id()+24));
325 apic_write_around(APIC_LDR, value);
329 * Set Task Priority to 'accept all'. We never change this
332 value = apic_read(APIC_TASKPRI);
333 value &= ~APIC_TPRI_MASK;
334 apic_write_around(APIC_TASKPRI, value);
337 * Now that we are all set up, enable the APIC
339 value = apic_read(APIC_SPIV);
340 value &= ~APIC_VECTOR_MASK;
344 value |= APIC_SPIV_APIC_ENABLED;
347 * Some unknown Intel IO/APIC (or APIC) errata is biting us with
348 * certain networking cards. If high frequency interrupts are
349 * happening on a particular IOAPIC pin, plus the IOAPIC routing
350 * entry is masked/unmasked at a high rate as well then sooner or
351 * later IOAPIC line gets 'stuck', no more interrupts are received
352 * from the device. If focus CPU is disabled then the hang goes
355 * [ This bug can be reproduced easily with a level-triggered
356 * PCI Ne2000 networking cards and PII/PIII processors, dual
360 * Actually disabling the focus CPU check just makes the hang less
361 * frequent as it makes the interrupt distributon model be more
362 * like LRU than MRU (the short-term load is more even across CPUs).
363 * See also the comment in end_level_ioapic_irq(). --macro
366 /* Enable focus processor (bit==0) */
367 value &= ~APIC_SPIV_FOCUS_DISABLED;
369 /* Disable focus processor (bit==1) */
370 value |= APIC_SPIV_FOCUS_DISABLED;
373 * Set spurious IRQ vector
375 value |= SPURIOUS_APIC_VECTOR;
376 apic_write_around(APIC_SPIV, value);
381 * set up through-local-APIC on the BP's LINT0. This is not
382 * strictly necessary in pure symmetric-IO mode, but sometimes
383 * we delegate interrupts to the 8259A.
386 * TODO: set up through-local-APIC from through-I/O-APIC? --macro
388 value = apic_read(APIC_LVT0) & APIC_LVT_MASKED;
389 if (!smp_processor_id() && (pic_mode || !value)) {
390 value = APIC_DM_EXTINT;
391 Dprintk(KERN_INFO "enabled ExtINT on CPU#%d\n", smp_processor_id());
393 value = APIC_DM_EXTINT | APIC_LVT_MASKED;
394 Dprintk(KERN_INFO "masked ExtINT on CPU#%d\n", smp_processor_id());
396 apic_write_around(APIC_LVT0, value);
399 * only the BP should see the LINT1 NMI signal, obviously.
401 if (!smp_processor_id())
404 value = APIC_DM_NMI | APIC_LVT_MASKED;
405 if (!APIC_INTEGRATED(ver)) /* 82489DX */
406 value |= APIC_LVT_LEVEL_TRIGGER;
407 apic_write_around(APIC_LVT1, value);
409 if (APIC_INTEGRATED(ver) && !esr_disable) { /* !82489DX */
410 maxlvt = get_maxlvt();
411 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */
412 apic_write(APIC_ESR, 0);
413 value = apic_read(APIC_ESR);
414 Dprintk("ESR value before enabling vector: %08x\n", value);
416 value = ERROR_APIC_VECTOR; // enables sending errors
417 apic_write_around(APIC_LVTERR, value);
419 * spec says clear errors after enabling vector.
422 apic_write(APIC_ESR, 0);
423 value = apic_read(APIC_ESR);
424 Dprintk("ESR value after enabling vector: %08x\n", value);
428 * Something untraceble is creating bad interrupts on
429 * secondary quads ... for the moment, just leave the
430 * ESR disabled - we can't do anything useful with the
431 * errors anyway - mbligh
433 printk("Leaving ESR disabled.\n");
435 printk("No ESR for 82489DX.\n");
438 nmi_watchdog_default();
439 if (nmi_watchdog == NMI_LOCAL_APIC)
440 setup_apic_nmi_watchdog();
447 /* 'active' is true if the local APIC was enabled by us and
448 not the BIOS; this signifies that we are also responsible
449 for disabling it before entering apm/acpi suspend */
451 /* r/w apic fields */
452 unsigned int apic_id;
453 unsigned int apic_taskpri;
454 unsigned int apic_ldr;
455 unsigned int apic_dfr;
456 unsigned int apic_spiv;
457 unsigned int apic_lvtt;
458 unsigned int apic_lvtpc;
459 unsigned int apic_lvt0;
460 unsigned int apic_lvt1;
461 unsigned int apic_lvterr;
462 unsigned int apic_tmict;
463 unsigned int apic_tdcr;
464 unsigned int apic_thmr;
467 static int lapic_suspend(struct sys_device *dev, u32 state)
471 if (!apic_pm_state.active)
474 apic_pm_state.apic_id = apic_read(APIC_ID);
475 apic_pm_state.apic_taskpri = apic_read(APIC_TASKPRI);
476 apic_pm_state.apic_ldr = apic_read(APIC_LDR);
477 apic_pm_state.apic_dfr = apic_read(APIC_DFR);
478 apic_pm_state.apic_spiv = apic_read(APIC_SPIV);
479 apic_pm_state.apic_lvtt = apic_read(APIC_LVTT);
480 apic_pm_state.apic_lvtpc = apic_read(APIC_LVTPC);
481 apic_pm_state.apic_lvt0 = apic_read(APIC_LVT0);
482 apic_pm_state.apic_lvt1 = apic_read(APIC_LVT1);
483 apic_pm_state.apic_lvterr = apic_read(APIC_LVTERR);
484 apic_pm_state.apic_tmict = apic_read(APIC_TMICT);
485 apic_pm_state.apic_tdcr = apic_read(APIC_TDCR);
486 apic_pm_state.apic_thmr = apic_read(APIC_LVTTHMR);
487 local_save_flags(flags);
489 disable_local_APIC();
490 local_irq_restore(flags);
494 static int lapic_resume(struct sys_device *dev)
499 if (!apic_pm_state.active)
502 /* XXX: Pavel needs this for S3 resume, but can't explain why */
503 set_fixmap_nocache(FIX_APIC_BASE, APIC_DEFAULT_PHYS_BASE);
505 local_irq_save(flags);
506 rdmsr(MSR_IA32_APICBASE, l, h);
507 l &= ~MSR_IA32_APICBASE_BASE;
508 l |= MSR_IA32_APICBASE_ENABLE | APIC_DEFAULT_PHYS_BASE;
509 wrmsr(MSR_IA32_APICBASE, l, h);
510 apic_write(APIC_LVTERR, ERROR_APIC_VECTOR | APIC_LVT_MASKED);
511 apic_write(APIC_ID, apic_pm_state.apic_id);
512 apic_write(APIC_DFR, apic_pm_state.apic_dfr);
513 apic_write(APIC_LDR, apic_pm_state.apic_ldr);
514 apic_write(APIC_TASKPRI, apic_pm_state.apic_taskpri);
515 apic_write(APIC_SPIV, apic_pm_state.apic_spiv);
516 apic_write(APIC_LVT0, apic_pm_state.apic_lvt0);
517 apic_write(APIC_LVT1, apic_pm_state.apic_lvt1);
518 apic_write(APIC_LVTTHMR, apic_pm_state.apic_thmr);
519 apic_write(APIC_LVTPC, apic_pm_state.apic_lvtpc);
520 apic_write(APIC_LVTT, apic_pm_state.apic_lvtt);
521 apic_write(APIC_TDCR, apic_pm_state.apic_tdcr);
522 apic_write(APIC_TMICT, apic_pm_state.apic_tmict);
523 apic_write(APIC_ESR, 0);
525 apic_write(APIC_LVTERR, apic_pm_state.apic_lvterr);
526 apic_write(APIC_ESR, 0);
528 local_irq_restore(flags);
532 static struct sysdev_class lapic_sysclass = {
533 set_kset_name("lapic"),
534 .resume = lapic_resume,
535 .suspend = lapic_suspend,
538 static struct sys_device device_lapic = {
540 .cls = &lapic_sysclass,
543 static void __init apic_pm_activate(void)
545 apic_pm_state.active = 1;
548 static int __init init_lapic_sysfs(void)
553 /* XXX: remove suspend/resume procs if !apic_pm_state.active? */
554 error = sysdev_class_register(&lapic_sysclass);
556 error = sysdev_register(&device_lapic);
559 device_initcall(init_lapic_sysfs);
561 #else /* CONFIG_PM */
563 static void apic_pm_activate(void) { }
565 #endif /* CONFIG_PM */
568 * Detect and enable local APICs on non-SMP boards.
569 * Original code written by Keir Fraser.
570 * On AMD64 we trust the BIOS - if it says no APIC it is likely
571 * not correctly set up (usually the APIC timer won't work etc.)
574 static int __init detect_init_APIC (void)
577 printk(KERN_INFO "No local APIC present\n");
581 mp_lapic_addr = APIC_DEFAULT_PHYS_BASE;
586 void __init init_apic_mappings(void)
588 unsigned long apic_phys;
591 * If no local APIC can be found then set up a fake all
592 * zeroes page to simulate the local APIC and another
593 * one for the IO-APIC.
595 if (!smp_found_config && detect_init_APIC()) {
596 apic_phys = (unsigned long) alloc_bootmem_pages(PAGE_SIZE);
597 apic_phys = __pa(apic_phys);
599 apic_phys = mp_lapic_addr;
601 set_fixmap_nocache(FIX_APIC_BASE, apic_phys);
602 Dprintk("mapped APIC to %16lx (%16lx)\n", APIC_BASE, apic_phys);
605 * Fetch the APIC ID of the BSP in case we have a
606 * default configuration (or the MP table is broken).
608 if (boot_cpu_id == -1U)
609 boot_cpu_id = GET_APIC_ID(apic_read(APIC_ID));
611 #ifdef CONFIG_X86_IO_APIC
613 unsigned long ioapic_phys, idx = FIX_IO_APIC_BASE_0;
616 for (i = 0; i < nr_ioapics; i++) {
617 if (smp_found_config) {
618 ioapic_phys = mp_ioapics[i].mpc_apicaddr;
620 ioapic_phys = (unsigned long) alloc_bootmem_pages(PAGE_SIZE);
621 ioapic_phys = __pa(ioapic_phys);
623 set_fixmap_nocache(idx, ioapic_phys);
624 Dprintk("mapped IOAPIC to %016lx (%016lx)\n",
625 __fix_to_virt(idx), ioapic_phys);
633 * This function sets up the local APIC timer, with a timeout of
634 * 'clocks' APIC bus clock. During calibration we actually call
635 * this function twice on the boot CPU, once with a bogus timeout
636 * value, second time for real. The other (noncalibrating) CPUs
637 * call this function only once, with the real, calibrated value.
639 * We do reads before writes even if unnecessary, to get around the
640 * P5 APIC double write bug.
643 #define APIC_DIVISOR 16
645 void __setup_APIC_LVTT(unsigned int clocks)
647 unsigned int lvtt_value, tmp_value, ver;
649 ver = GET_APIC_VERSION(apic_read(APIC_LVR));
650 lvtt_value = APIC_LVT_TIMER_PERIODIC | LOCAL_TIMER_VECTOR;
651 if (!APIC_INTEGRATED(ver))
652 lvtt_value |= SET_APIC_TIMER_BASE(APIC_TIMER_BASE_DIV);
653 apic_write_around(APIC_LVTT, lvtt_value);
658 tmp_value = apic_read(APIC_TDCR);
659 apic_write_around(APIC_TDCR, (tmp_value
660 & ~(APIC_TDR_DIV_1 | APIC_TDR_DIV_TMBASE))
663 apic_write_around(APIC_TMICT, clocks/APIC_DIVISOR);
666 static void setup_APIC_timer(unsigned int clocks)
670 local_irq_save(flags);
672 /* For some reasons this doesn't work on Simics, so fake it for now */
673 if (!strstr(boot_cpu_data.x86_model_id, "Screwdriver")) {
674 __setup_APIC_LVTT(clocks);
678 /* wait for irq slice */
679 if (vxtime.hpet_address) {
680 int trigger = hpet_readl(HPET_T0_CMP);
681 while (hpet_readl(HPET_COUNTER) >= trigger)
683 while (hpet_readl(HPET_COUNTER) < trigger)
689 c2 |= inb_p(0x40) << 8;
694 c2 |= inb_p(0x40) << 8;
695 } while (c2 - c1 < 300);
698 __setup_APIC_LVTT(clocks);
700 local_irq_restore(flags);
704 * In this function we calibrate APIC bus clocks to the external
705 * timer. Unfortunately we cannot use jiffies and the timer irq
706 * to calibrate, since some later bootup code depends on getting
707 * the first irq? Ugh.
709 * We want to do the calibration only once since we
710 * want to have local timer irqs syncron. CPUs connected
711 * by the same APIC bus have the very same bus frequency.
712 * And we want to have irqs off anyways, no accidental
716 #define TICK_COUNT 100000000
718 int __init calibrate_APIC_clock(void)
720 int apic, apic_start, tsc, tsc_start;
723 * Put whatever arbitrary (but long enough) timeout
724 * value into the APIC clock, we just want to get the
725 * counter running for calibration.
727 __setup_APIC_LVTT(1000000000);
729 apic_start = apic_read(APIC_TMCCT);
733 apic = apic_read(APIC_TMCCT);
735 } while ((tsc - tsc_start) < TICK_COUNT && (apic - apic_start) < TICK_COUNT);
737 result = (apic_start - apic) * 1000L * cpu_khz / (tsc - tsc_start);
739 printk(KERN_INFO "Detected %d.%03d MHz APIC timer.\n",
740 result / 1000 / 1000, result / 1000 % 1000);
742 return result * APIC_DIVISOR / HZ;
745 static unsigned int calibration_result;
747 void __init setup_boot_APIC_clock (void)
749 if (disable_apic_timer) {
750 printk(KERN_INFO "Disabling APIC timer\n");
754 printk(KERN_INFO "Using local APIC timer interrupts.\n");
755 using_apic_timer = 1;
759 calibration_result = calibrate_APIC_clock();
761 * Now set up the timer for real.
763 setup_APIC_timer(calibration_result);
768 void __init setup_secondary_APIC_clock(void)
770 local_irq_disable(); /* FIXME: Do we need this? --RR */
771 setup_APIC_timer(calibration_result);
775 void __init disable_APIC_timer(void)
777 if (using_apic_timer) {
780 v = apic_read(APIC_LVTT);
781 apic_write_around(APIC_LVTT, v | APIC_LVT_MASKED);
785 void enable_APIC_timer(void)
787 if (using_apic_timer) {
790 v = apic_read(APIC_LVTT);
791 apic_write_around(APIC_LVTT, v & ~APIC_LVT_MASKED);
796 * the frequency of the profiling timer can be changed
797 * by writing a multiplier value into /proc/profile.
799 int setup_profiling_timer(unsigned int multiplier)
804 * Sanity check. [at least 500 APIC cycles should be
805 * between APIC interrupts as a rule of thumb, to avoid
808 if ( (!multiplier) || (calibration_result/multiplier < 500))
812 * Set the new multiplier for each CPU. CPUs don't start using the
813 * new values until the next timer interrupt in which they do process
814 * accounting. At that time they also adjust their APIC timers
817 for (i = 0; i < NR_CPUS; ++i)
818 per_cpu(prof_multiplier, i) = multiplier;
826 * Local timer interrupt handler. It does both profiling and
827 * process statistics/rescheduling.
829 * We do profiling in every local tick, statistics/rescheduling
830 * happen only every 'profiling multiplier' ticks. The default
831 * multiplier is 1 and it can be changed by writing the new multiplier
832 * value into /proc/profile.
835 void smp_local_timer_interrupt(struct pt_regs *regs)
837 int cpu = smp_processor_id();
839 x86_do_profile(regs);
841 if (--per_cpu(prof_counter, cpu) <= 0) {
843 * The multiplier may have changed since the last time we got
844 * to this point as a result of the user writing to
845 * /proc/profile. In this case we need to adjust the APIC
848 * Interrupts are already masked off at this point.
850 per_cpu(prof_counter, cpu) = per_cpu(prof_multiplier, cpu);
851 if (per_cpu(prof_counter, cpu) !=
852 per_cpu(prof_old_multiplier, cpu)) {
853 __setup_APIC_LVTT(calibration_result/
854 per_cpu(prof_counter, cpu));
855 per_cpu(prof_old_multiplier, cpu) =
856 per_cpu(prof_counter, cpu);
860 update_process_times(user_mode(regs));
865 * We take the 'long' return path, and there every subsystem
866 * grabs the appropriate locks (kernel lock/ irq lock).
868 * we might want to decouple profiling from the 'long path',
869 * and do the profiling totally in assembly.
871 * Currently this isn't too much of an issue (performance wise),
872 * we can take more than 100K local irqs per second on a 100 MHz P5.
877 * Local APIC timer interrupt. This is the most natural way for doing
878 * local interrupts, but local timer interrupts can be emulated by
879 * broadcast interrupts too. [in case the hw doesn't support APIC timers]
881 * [ if a single-CPU system runs an SMP kernel then we call the local
882 * interrupt as well. Thus we cannot inline the local irq ... ]
884 void smp_apic_timer_interrupt(struct pt_regs *regs)
887 * the NMI deadlock-detector uses this.
889 add_pda(apic_timer_irqs, 1);
892 * NOTE! We'd better ACK the irq immediately,
893 * because timer handling can be slow.
897 * update_process_times() expects us to have done irq_enter().
898 * Besides, if we don't timer interrupts ignore the global
899 * interrupt lock, which is the WrongThing (tm) to do.
902 smp_local_timer_interrupt(regs);
907 * This interrupt should _never_ happen with our APIC/SMP architecture
909 asmlinkage void smp_spurious_interrupt(void)
914 * Check if this really is a spurious interrupt and ACK it
915 * if it is a vectored one. Just in case...
916 * Spurious interrupts should not be ACKed.
918 v = apic_read(APIC_ISR + ((SPURIOUS_APIC_VECTOR & ~0x1f) >> 1));
919 if (v & (1 << (SPURIOUS_APIC_VECTOR & 0x1f)))
923 static unsigned long last_warning;
924 static unsigned long skipped;
926 /* see sw-dev-man vol 3, chapter 7.4.13.5 */
927 if (time_before(last_warning+30*HZ,jiffies)) {
928 printk(KERN_INFO "spurious APIC interrupt on CPU#%d, %ld skipped.\n",
929 smp_processor_id(), skipped);
930 last_warning = jiffies;
940 * This interrupt should never happen with our APIC/SMP architecture
943 asmlinkage void smp_error_interrupt(void)
948 /* First tickle the hardware, only then report what went on. -- REW */
949 v = apic_read(APIC_ESR);
950 apic_write(APIC_ESR, 0);
951 v1 = apic_read(APIC_ESR);
953 atomic_inc(&irq_err_count);
955 /* Here is what the APIC error bits mean:
959 3: Receive accept error
961 5: Send illegal vector
962 6: Received illegal vector
963 7: Illegal register address
965 printk (KERN_INFO "APIC error on CPU%d: %02x(%02x)\n",
966 smp_processor_id(), v , v1);
973 * This initializes the IO-APIC and APIC hardware if this is
976 int __init APIC_init_uniprocessor (void)
979 printk(KERN_INFO "Apic disabled\n");
984 printk(KERN_INFO "Apic disabled by BIOS\n");
992 phys_cpu_present_map = physid_mask_of_physid(0);
993 apic_write_around(APIC_ID, boot_cpu_id);
997 #ifdef CONFIG_X86_IO_APIC
998 if (smp_found_config && !skip_ioapic_setup && nr_ioapics)
1003 setup_boot_APIC_clock();
1008 static __init int setup_disableapic(char *str)
1014 static __init int setup_nolapic(char *str)
1020 static __init int setup_noapictimer(char *str)
1022 disable_apic_timer = 1;
1026 /* dummy parsing: see setup.c */
1028 __setup("disableapic", setup_disableapic);
1029 __setup("nolapic", setup_nolapic); /* same as disableapic, for compatibility */
1031 __setup("noapictimer", setup_noapictimer);
1033 /* no "lapic" flag - we only use the lapic when the BIOS tells us so. */