2 * Local APIC handling, local APIC timers
4 * (c) 1999, 2000 Ingo Molnar <mingo@redhat.com>
7 * Maciej W. Rozycki : Bits for genuine 82489DX APICs;
8 * thanks to Eric Gilmore
10 * for testing these extensively.
11 * Maciej W. Rozycki : Various updates and fixes.
12 * Mikael Pettersson : Power Management for UP-APIC.
14 * Mikael Pettersson : PM converted to driver model.
17 #include <linux/config.h>
18 #include <linux/init.h>
21 #include <linux/irq.h>
22 #include <linux/delay.h>
23 #include <linux/bootmem.h>
24 #include <linux/smp_lock.h>
25 #include <linux/interrupt.h>
26 #include <linux/mc146818rtc.h>
27 #include <linux/kernel_stat.h>
28 #include <linux/sysdev.h>
30 #include <asm/atomic.h>
33 #include <asm/mpspec.h>
34 #include <asm/pgalloc.h>
35 #include <asm/mach_apic.h>
39 int disable_apic_timer __initdata;
41 /* Using APIC to generate smp_local_timer_interrupt? */
42 int using_apic_timer = 0;
44 static DEFINE_PER_CPU(int, prof_multiplier) = 1;
45 static DEFINE_PER_CPU(int, prof_old_multiplier) = 1;
46 static DEFINE_PER_CPU(int, prof_counter) = 1;
48 static void apic_pm_activate(void);
50 void enable_NMI_through_LVT0 (void * dummy)
54 ver = apic_read(APIC_LVR);
55 ver = GET_APIC_VERSION(ver);
56 v = APIC_DM_NMI; /* unmask and set to NMI */
57 apic_write_around(APIC_LVT0, v);
62 unsigned int v, ver, maxlvt;
64 v = apic_read(APIC_LVR);
65 ver = GET_APIC_VERSION(v);
66 maxlvt = GET_APIC_MAXLVT(v);
70 void clear_local_APIC(void)
75 maxlvt = get_maxlvt();
78 * Masking an LVT entry on a P6 can trigger a local APIC error
79 * if the vector is zero. Mask LVTERR first to prevent this.
82 v = ERROR_APIC_VECTOR; /* any non-zero vector will do */
83 apic_write_around(APIC_LVTERR, v | APIC_LVT_MASKED);
86 * Careful: we have to set masks only first to deassert
87 * any level-triggered sources.
89 v = apic_read(APIC_LVTT);
90 apic_write_around(APIC_LVTT, v | APIC_LVT_MASKED);
91 v = apic_read(APIC_LVT0);
92 apic_write_around(APIC_LVT0, v | APIC_LVT_MASKED);
93 v = apic_read(APIC_LVT1);
94 apic_write_around(APIC_LVT1, v | APIC_LVT_MASKED);
96 v = apic_read(APIC_LVTPC);
97 apic_write_around(APIC_LVTPC, v | APIC_LVT_MASKED);
101 * Clean APIC state for other OSs:
103 apic_write_around(APIC_LVTT, APIC_LVT_MASKED);
104 apic_write_around(APIC_LVT0, APIC_LVT_MASKED);
105 apic_write_around(APIC_LVT1, APIC_LVT_MASKED);
107 apic_write_around(APIC_LVTERR, APIC_LVT_MASKED);
109 apic_write_around(APIC_LVTPC, APIC_LVT_MASKED);
110 v = GET_APIC_VERSION(apic_read(APIC_LVR));
111 if (APIC_INTEGRATED(v)) { /* !82489DX */
112 if (maxlvt > 3) /* Due to Pentium errata 3AP and 11AP. */
113 apic_write(APIC_ESR, 0);
118 void __init connect_bsp_APIC(void)
122 * Do not trust the local APIC being empty at bootup.
126 * PIC mode, enable APIC mode in the IMCR, i.e.
127 * connect BSP's local APIC to INT and NMI lines.
129 apic_printk(APIC_VERBOSE, "leaving PIC mode, enabling APIC mode.\n");
135 void disconnect_bsp_APIC(void)
139 * Put the board back into PIC mode (has an effect
140 * only on certain older boards). Note that APIC
141 * interrupts, including IPIs, won't work beyond
142 * this point! The only exception are INIT IPIs.
144 apic_printk(APIC_QUIET, "disabling APIC mode, entering PIC mode.\n");
150 void disable_local_APIC(void)
157 * Disable APIC (implies clearing of registers
160 value = apic_read(APIC_SPIV);
161 value &= ~APIC_SPIV_APIC_ENABLED;
162 apic_write_around(APIC_SPIV, value);
166 * This is to verify that we're looking at a real local APIC.
167 * Check these against your board if the CPUs aren't getting
168 * started for no apparent reason.
170 int __init verify_local_APIC(void)
172 unsigned int reg0, reg1;
175 * The version register is read-only in a real APIC.
177 reg0 = apic_read(APIC_LVR);
178 apic_printk(APIC_DEBUG, "Getting VERSION: %x\n", reg0);
179 apic_write(APIC_LVR, reg0 ^ APIC_LVR_MASK);
180 reg1 = apic_read(APIC_LVR);
181 apic_printk(APIC_DEBUG, "Getting VERSION: %x\n", reg1);
184 * The two version reads above should print the same
185 * numbers. If the second one is different, then we
186 * poke at a non-APIC.
192 * Check if the version looks reasonably.
194 reg1 = GET_APIC_VERSION(reg0);
195 if (reg1 == 0x00 || reg1 == 0xff)
198 if (reg1 < 0x02 || reg1 == 0xff)
202 * The ID register is read/write in a real APIC.
204 reg0 = apic_read(APIC_ID);
205 apic_printk(APIC_DEBUG, "Getting ID: %x\n", reg0);
206 apic_write(APIC_ID, reg0 ^ APIC_ID_MASK);
207 reg1 = apic_read(APIC_ID);
208 apic_printk(APIC_DEBUG, "Getting ID: %x\n", reg1);
209 apic_write(APIC_ID, reg0);
210 if (reg1 != (reg0 ^ APIC_ID_MASK))
214 * The next two are just to see if we have sane values.
215 * They're only really relevant if we're in Virtual Wire
216 * compatibility mode, but most boxes are anymore.
218 reg0 = apic_read(APIC_LVT0);
219 apic_printk(APIC_DEBUG,"Getting LVT0: %x\n", reg0);
220 reg1 = apic_read(APIC_LVT1);
221 apic_printk(APIC_DEBUG, "Getting LVT1: %x\n", reg1);
226 void __init sync_Arb_IDs(void)
231 apic_wait_icr_idle();
233 apic_printk(APIC_DEBUG, "Synchronizing Arb IDs.\n");
234 apic_write_around(APIC_ICR, APIC_DEST_ALLINC | APIC_INT_LEVELTRIG
238 extern void __error_in_apic_c (void);
241 * An initial setup of the virtual wire mode.
243 void __init init_bsp_APIC(void)
245 unsigned int value, ver;
248 * Don't do the setup now if we have a SMP BIOS as the
249 * through-I/O-APIC virtual wire mode might be active.
251 if (smp_found_config || !cpu_has_apic)
254 value = apic_read(APIC_LVR);
255 ver = GET_APIC_VERSION(value);
258 * Do not trust the local APIC being empty at bootup.
265 value = apic_read(APIC_SPIV);
266 value &= ~APIC_VECTOR_MASK;
267 value |= APIC_SPIV_APIC_ENABLED;
268 value |= APIC_SPIV_FOCUS_DISABLED;
269 value |= SPURIOUS_APIC_VECTOR;
270 apic_write_around(APIC_SPIV, value);
273 * Set up the virtual wire mode.
275 apic_write_around(APIC_LVT0, APIC_DM_EXTINT);
277 if (!APIC_INTEGRATED(ver)) /* 82489DX */
278 value |= APIC_LVT_LEVEL_TRIGGER;
279 apic_write_around(APIC_LVT1, value);
282 void __init setup_local_APIC (void)
284 unsigned int value, ver, maxlvt;
286 /* Pound the ESR really hard over the head with a big hammer - mbligh */
288 apic_write(APIC_ESR, 0);
289 apic_write(APIC_ESR, 0);
290 apic_write(APIC_ESR, 0);
291 apic_write(APIC_ESR, 0);
294 value = apic_read(APIC_LVR);
295 ver = GET_APIC_VERSION(value);
297 if ((SPURIOUS_APIC_VECTOR & 0x0f) != 0x0f)
301 * Double-check whether this APIC is really registered.
302 * This is meaningless in clustered apic mode, so we skip it.
304 if (!apic_id_registered())
308 * Intel recommends to set DFR, LDR and TPR before enabling
309 * an APIC. See e.g. "AP-388 82489DX User's Manual" (Intel
310 * document number 292116). So here it goes...
315 * Set Task Priority to 'accept all'. We never change this
318 value = apic_read(APIC_TASKPRI);
319 value &= ~APIC_TPRI_MASK;
320 apic_write_around(APIC_TASKPRI, value);
323 * Now that we are all set up, enable the APIC
325 value = apic_read(APIC_SPIV);
326 value &= ~APIC_VECTOR_MASK;
330 value |= APIC_SPIV_APIC_ENABLED;
333 * Some unknown Intel IO/APIC (or APIC) errata is biting us with
334 * certain networking cards. If high frequency interrupts are
335 * happening on a particular IOAPIC pin, plus the IOAPIC routing
336 * entry is masked/unmasked at a high rate as well then sooner or
337 * later IOAPIC line gets 'stuck', no more interrupts are received
338 * from the device. If focus CPU is disabled then the hang goes
341 * [ This bug can be reproduced easily with a level-triggered
342 * PCI Ne2000 networking cards and PII/PIII processors, dual
346 * Actually disabling the focus CPU check just makes the hang less
347 * frequent as it makes the interrupt distributon model be more
348 * like LRU than MRU (the short-term load is more even across CPUs).
349 * See also the comment in end_level_ioapic_irq(). --macro
352 /* Enable focus processor (bit==0) */
353 value &= ~APIC_SPIV_FOCUS_DISABLED;
355 /* Disable focus processor (bit==1) */
356 value |= APIC_SPIV_FOCUS_DISABLED;
359 * Set spurious IRQ vector
361 value |= SPURIOUS_APIC_VECTOR;
362 apic_write_around(APIC_SPIV, value);
367 * set up through-local-APIC on the BP's LINT0. This is not
368 * strictly necessary in pure symmetric-IO mode, but sometimes
369 * we delegate interrupts to the 8259A.
372 * TODO: set up through-local-APIC from through-I/O-APIC? --macro
374 value = apic_read(APIC_LVT0) & APIC_LVT_MASKED;
375 if (!smp_processor_id() && (pic_mode || !value)) {
376 value = APIC_DM_EXTINT;
377 apic_printk(APIC_VERBOSE, "enabled ExtINT on CPU#%d\n", smp_processor_id());
379 value = APIC_DM_EXTINT | APIC_LVT_MASKED;
380 apic_printk(APIC_VERBOSE, "masked ExtINT on CPU#%d\n", smp_processor_id());
382 apic_write_around(APIC_LVT0, value);
385 * only the BP should see the LINT1 NMI signal, obviously.
387 if (!smp_processor_id())
390 value = APIC_DM_NMI | APIC_LVT_MASKED;
391 if (!APIC_INTEGRATED(ver)) /* 82489DX */
392 value |= APIC_LVT_LEVEL_TRIGGER;
393 apic_write_around(APIC_LVT1, value);
395 if (APIC_INTEGRATED(ver) && !esr_disable) { /* !82489DX */
397 maxlvt = get_maxlvt();
398 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */
399 apic_write(APIC_ESR, 0);
400 oldvalue = apic_read(APIC_ESR);
401 value = ERROR_APIC_VECTOR; // enables sending errors
402 apic_write_around(APIC_LVTERR, value);
404 * spec says clear errors after enabling vector.
407 apic_write(APIC_ESR, 0);
408 value = apic_read(APIC_ESR);
409 if (value != oldvalue)
410 apic_printk(APIC_VERBOSE,
411 "ESR value after enabling vector: %08x, after %08x\n",
416 * Something untraceble is creating bad interrupts on
417 * secondary quads ... for the moment, just leave the
418 * ESR disabled - we can't do anything useful with the
419 * errors anyway - mbligh
421 apic_printk(APIC_DEBUG, "Leaving ESR disabled.\n");
423 apic_printk(APIC_DEBUG, "No ESR for 82489DX.\n");
426 nmi_watchdog_default();
427 if (nmi_watchdog == NMI_LOCAL_APIC)
428 setup_apic_nmi_watchdog();
435 /* 'active' is true if the local APIC was enabled by us and
436 not the BIOS; this signifies that we are also responsible
437 for disabling it before entering apm/acpi suspend */
439 /* r/w apic fields */
440 unsigned int apic_id;
441 unsigned int apic_taskpri;
442 unsigned int apic_ldr;
443 unsigned int apic_dfr;
444 unsigned int apic_spiv;
445 unsigned int apic_lvtt;
446 unsigned int apic_lvtpc;
447 unsigned int apic_lvt0;
448 unsigned int apic_lvt1;
449 unsigned int apic_lvterr;
450 unsigned int apic_tmict;
451 unsigned int apic_tdcr;
452 unsigned int apic_thmr;
455 static int lapic_suspend(struct sys_device *dev, u32 state)
459 if (!apic_pm_state.active)
462 apic_pm_state.apic_id = apic_read(APIC_ID);
463 apic_pm_state.apic_taskpri = apic_read(APIC_TASKPRI);
464 apic_pm_state.apic_ldr = apic_read(APIC_LDR);
465 apic_pm_state.apic_dfr = apic_read(APIC_DFR);
466 apic_pm_state.apic_spiv = apic_read(APIC_SPIV);
467 apic_pm_state.apic_lvtt = apic_read(APIC_LVTT);
468 apic_pm_state.apic_lvtpc = apic_read(APIC_LVTPC);
469 apic_pm_state.apic_lvt0 = apic_read(APIC_LVT0);
470 apic_pm_state.apic_lvt1 = apic_read(APIC_LVT1);
471 apic_pm_state.apic_lvterr = apic_read(APIC_LVTERR);
472 apic_pm_state.apic_tmict = apic_read(APIC_TMICT);
473 apic_pm_state.apic_tdcr = apic_read(APIC_TDCR);
474 apic_pm_state.apic_thmr = apic_read(APIC_LVTTHMR);
475 local_save_flags(flags);
477 disable_local_APIC();
478 local_irq_restore(flags);
482 static int lapic_resume(struct sys_device *dev)
487 if (!apic_pm_state.active)
490 /* XXX: Pavel needs this for S3 resume, but can't explain why */
491 set_fixmap_nocache(FIX_APIC_BASE, APIC_DEFAULT_PHYS_BASE);
493 local_irq_save(flags);
494 rdmsr(MSR_IA32_APICBASE, l, h);
495 l &= ~MSR_IA32_APICBASE_BASE;
496 l |= MSR_IA32_APICBASE_ENABLE | APIC_DEFAULT_PHYS_BASE;
497 wrmsr(MSR_IA32_APICBASE, l, h);
498 apic_write(APIC_LVTERR, ERROR_APIC_VECTOR | APIC_LVT_MASKED);
499 apic_write(APIC_ID, apic_pm_state.apic_id);
500 apic_write(APIC_DFR, apic_pm_state.apic_dfr);
501 apic_write(APIC_LDR, apic_pm_state.apic_ldr);
502 apic_write(APIC_TASKPRI, apic_pm_state.apic_taskpri);
503 apic_write(APIC_SPIV, apic_pm_state.apic_spiv);
504 apic_write(APIC_LVT0, apic_pm_state.apic_lvt0);
505 apic_write(APIC_LVT1, apic_pm_state.apic_lvt1);
506 apic_write(APIC_LVTTHMR, apic_pm_state.apic_thmr);
507 apic_write(APIC_LVTPC, apic_pm_state.apic_lvtpc);
508 apic_write(APIC_LVTT, apic_pm_state.apic_lvtt);
509 apic_write(APIC_TDCR, apic_pm_state.apic_tdcr);
510 apic_write(APIC_TMICT, apic_pm_state.apic_tmict);
511 apic_write(APIC_ESR, 0);
513 apic_write(APIC_LVTERR, apic_pm_state.apic_lvterr);
514 apic_write(APIC_ESR, 0);
516 local_irq_restore(flags);
520 static struct sysdev_class lapic_sysclass = {
521 set_kset_name("lapic"),
522 .resume = lapic_resume,
523 .suspend = lapic_suspend,
526 static struct sys_device device_lapic = {
528 .cls = &lapic_sysclass,
531 static void __init apic_pm_activate(void)
533 apic_pm_state.active = 1;
536 static int __init init_lapic_sysfs(void)
541 /* XXX: remove suspend/resume procs if !apic_pm_state.active? */
542 error = sysdev_class_register(&lapic_sysclass);
544 error = sysdev_register(&device_lapic);
547 device_initcall(init_lapic_sysfs);
549 #else /* CONFIG_PM */
551 static void apic_pm_activate(void) { }
553 #endif /* CONFIG_PM */
555 static int __init apic_set_verbosity(char *str)
557 if (strcmp("debug", str) == 0)
558 apic_verbosity = APIC_DEBUG;
559 else if (strcmp("verbose", str) == 0)
560 apic_verbosity = APIC_VERBOSE;
562 printk(KERN_WARNING "APIC Verbosity level %s not recognised"
563 " use apic=verbose or apic=debug", str);
568 __setup("apic=", apic_set_verbosity);
571 * Detect and enable local APICs on non-SMP boards.
572 * Original code written by Keir Fraser.
573 * On AMD64 we trust the BIOS - if it says no APIC it is likely
574 * not correctly set up (usually the APIC timer won't work etc.)
577 static int __init detect_init_APIC (void)
580 printk(KERN_INFO "No local APIC present\n");
584 mp_lapic_addr = APIC_DEFAULT_PHYS_BASE;
589 void __init init_apic_mappings(void)
591 unsigned long apic_phys;
594 * If no local APIC can be found then set up a fake all
595 * zeroes page to simulate the local APIC and another
596 * one for the IO-APIC.
598 if (!smp_found_config && detect_init_APIC()) {
599 apic_phys = (unsigned long) alloc_bootmem_pages(PAGE_SIZE);
600 apic_phys = __pa(apic_phys);
602 apic_phys = mp_lapic_addr;
604 set_fixmap_nocache(FIX_APIC_BASE, apic_phys);
605 apic_printk(APIC_VERBOSE,"mapped APIC to %16lx (%16lx)\n", APIC_BASE, apic_phys);
608 * Fetch the APIC ID of the BSP in case we have a
609 * default configuration (or the MP table is broken).
611 if (boot_cpu_id == -1U)
612 boot_cpu_id = GET_APIC_ID(apic_read(APIC_ID));
614 #ifdef CONFIG_X86_IO_APIC
616 unsigned long ioapic_phys, idx = FIX_IO_APIC_BASE_0;
619 for (i = 0; i < nr_ioapics; i++) {
620 if (smp_found_config) {
621 ioapic_phys = mp_ioapics[i].mpc_apicaddr;
623 ioapic_phys = (unsigned long) alloc_bootmem_pages(PAGE_SIZE);
624 ioapic_phys = __pa(ioapic_phys);
626 set_fixmap_nocache(idx, ioapic_phys);
627 apic_printk(APIC_VERBOSE,"mapped IOAPIC to %016lx (%016lx)\n",
628 __fix_to_virt(idx), ioapic_phys);
636 * This function sets up the local APIC timer, with a timeout of
637 * 'clocks' APIC bus clock. During calibration we actually call
638 * this function twice on the boot CPU, once with a bogus timeout
639 * value, second time for real. The other (noncalibrating) CPUs
640 * call this function only once, with the real, calibrated value.
642 * We do reads before writes even if unnecessary, to get around the
643 * P5 APIC double write bug.
646 #define APIC_DIVISOR 16
648 void __setup_APIC_LVTT(unsigned int clocks)
650 unsigned int lvtt_value, tmp_value, ver;
652 ver = GET_APIC_VERSION(apic_read(APIC_LVR));
653 lvtt_value = APIC_LVT_TIMER_PERIODIC | LOCAL_TIMER_VECTOR;
654 if (!APIC_INTEGRATED(ver))
655 lvtt_value |= SET_APIC_TIMER_BASE(APIC_TIMER_BASE_DIV);
656 apic_write_around(APIC_LVTT, lvtt_value);
661 tmp_value = apic_read(APIC_TDCR);
662 apic_write_around(APIC_TDCR, (tmp_value
663 & ~(APIC_TDR_DIV_1 | APIC_TDR_DIV_TMBASE))
666 apic_write_around(APIC_TMICT, clocks/APIC_DIVISOR);
669 static void setup_APIC_timer(unsigned int clocks)
673 local_irq_save(flags);
675 /* For some reasons this doesn't work on Simics, so fake it for now */
676 if (!strstr(boot_cpu_data.x86_model_id, "Screwdriver")) {
677 __setup_APIC_LVTT(clocks);
681 /* wait for irq slice */
682 if (vxtime.hpet_address) {
683 int trigger = hpet_readl(HPET_T0_CMP);
684 while (hpet_readl(HPET_COUNTER) >= trigger)
686 while (hpet_readl(HPET_COUNTER) < trigger)
692 c2 |= inb_p(0x40) << 8;
697 c2 |= inb_p(0x40) << 8;
698 } while (c2 - c1 < 300);
701 __setup_APIC_LVTT(clocks);
703 local_irq_restore(flags);
707 * In this function we calibrate APIC bus clocks to the external
708 * timer. Unfortunately we cannot use jiffies and the timer irq
709 * to calibrate, since some later bootup code depends on getting
710 * the first irq? Ugh.
712 * We want to do the calibration only once since we
713 * want to have local timer irqs syncron. CPUs connected
714 * by the same APIC bus have the very same bus frequency.
715 * And we want to have irqs off anyways, no accidental
719 #define TICK_COUNT 100000000
721 int __init calibrate_APIC_clock(void)
723 int apic, apic_start, tsc, tsc_start;
726 * Put whatever arbitrary (but long enough) timeout
727 * value into the APIC clock, we just want to get the
728 * counter running for calibration.
730 __setup_APIC_LVTT(1000000000);
732 apic_start = apic_read(APIC_TMCCT);
736 apic = apic_read(APIC_TMCCT);
738 } while ((tsc - tsc_start) < TICK_COUNT && (apic - apic_start) < TICK_COUNT);
740 result = (apic_start - apic) * 1000L * cpu_khz / (tsc - tsc_start);
742 printk(KERN_INFO "Detected %d.%03d MHz APIC timer.\n",
743 result / 1000 / 1000, result / 1000 % 1000);
745 return result * APIC_DIVISOR / HZ;
748 static unsigned int calibration_result;
750 void __init setup_boot_APIC_clock (void)
752 if (disable_apic_timer) {
753 printk(KERN_INFO "Disabling APIC timer\n");
757 printk(KERN_INFO "Using local APIC timer interrupts.\n");
758 using_apic_timer = 1;
762 calibration_result = calibrate_APIC_clock();
764 * Now set up the timer for real.
766 setup_APIC_timer(calibration_result);
771 void __init setup_secondary_APIC_clock(void)
773 local_irq_disable(); /* FIXME: Do we need this? --RR */
774 setup_APIC_timer(calibration_result);
778 void __init disable_APIC_timer(void)
780 if (using_apic_timer) {
783 v = apic_read(APIC_LVTT);
784 apic_write_around(APIC_LVTT, v | APIC_LVT_MASKED);
788 void enable_APIC_timer(void)
790 if (using_apic_timer) {
793 v = apic_read(APIC_LVTT);
794 apic_write_around(APIC_LVTT, v & ~APIC_LVT_MASKED);
799 * the frequency of the profiling timer can be changed
800 * by writing a multiplier value into /proc/profile.
802 int setup_profiling_timer(unsigned int multiplier)
807 * Sanity check. [at least 500 APIC cycles should be
808 * between APIC interrupts as a rule of thumb, to avoid
811 if ( (!multiplier) || (calibration_result/multiplier < 500))
815 * Set the new multiplier for each CPU. CPUs don't start using the
816 * new values until the next timer interrupt in which they do process
817 * accounting. At that time they also adjust their APIC timers
820 for (i = 0; i < NR_CPUS; ++i)
821 per_cpu(prof_multiplier, i) = multiplier;
829 * Local timer interrupt handler. It does both profiling and
830 * process statistics/rescheduling.
832 * We do profiling in every local tick, statistics/rescheduling
833 * happen only every 'profiling multiplier' ticks. The default
834 * multiplier is 1 and it can be changed by writing the new multiplier
835 * value into /proc/profile.
838 void smp_local_timer_interrupt(struct pt_regs *regs)
840 int cpu = smp_processor_id();
842 profile_tick(CPU_PROFILING, regs);
843 if (--per_cpu(prof_counter, cpu) <= 0) {
845 * The multiplier may have changed since the last time we got
846 * to this point as a result of the user writing to
847 * /proc/profile. In this case we need to adjust the APIC
850 * Interrupts are already masked off at this point.
852 per_cpu(prof_counter, cpu) = per_cpu(prof_multiplier, cpu);
853 if (per_cpu(prof_counter, cpu) !=
854 per_cpu(prof_old_multiplier, cpu)) {
855 __setup_APIC_LVTT(calibration_result/
856 per_cpu(prof_counter, cpu));
857 per_cpu(prof_old_multiplier, cpu) =
858 per_cpu(prof_counter, cpu);
862 update_process_times(user_mode(regs));
867 * We take the 'long' return path, and there every subsystem
868 * grabs the appropriate locks (kernel lock/ irq lock).
870 * we might want to decouple profiling from the 'long path',
871 * and do the profiling totally in assembly.
873 * Currently this isn't too much of an issue (performance wise),
874 * we can take more than 100K local irqs per second on a 100 MHz P5.
879 * Local APIC timer interrupt. This is the most natural way for doing
880 * local interrupts, but local timer interrupts can be emulated by
881 * broadcast interrupts too. [in case the hw doesn't support APIC timers]
883 * [ if a single-CPU system runs an SMP kernel then we call the local
884 * interrupt as well. Thus we cannot inline the local irq ... ]
886 void smp_apic_timer_interrupt(struct pt_regs *regs)
889 * the NMI deadlock-detector uses this.
891 add_pda(apic_timer_irqs, 1);
894 * NOTE! We'd better ACK the irq immediately,
895 * because timer handling can be slow.
899 * update_process_times() expects us to have done irq_enter().
900 * Besides, if we don't timer interrupts ignore the global
901 * interrupt lock, which is the WrongThing (tm) to do.
904 smp_local_timer_interrupt(regs);
909 * oem_force_hpet_timer -- force HPET mode for some boxes.
911 * Thus far, the major user of this is IBM's Summit2 series:
913 * Clustered boxes may have unsynced TSC problems if they are
914 * multi-chassis. Use available data to take a good guess.
915 * If in doubt, go HPET.
917 __init int oem_force_hpet_timer(void)
919 int i, clusters, zeros;
921 DECLARE_BITMAP(clustermap, NUM_APIC_CLUSTERS);
923 bitmap_empty(clustermap, NUM_APIC_CLUSTERS);
925 for (i = 0; i < NR_CPUS; i++) {
926 id = bios_cpu_apicid[i];
927 if (id != BAD_APICID)
928 __set_bit(APIC_CLUSTERID(id), clustermap);
931 /* Problem: Partially populated chassis may not have CPUs in some of
932 * the APIC clusters they have been allocated. Only present CPUs have
933 * bios_cpu_apicid entries, thus causing zeroes in the bitmap. Since
934 * clusters are allocated sequentially, count zeros only if they are
939 for (i = 0; i < NUM_APIC_CLUSTERS; i++) {
940 if (test_bit(i, clustermap)) {
941 clusters += 1 + zeros;
948 * If clusters > 2, then should be multi-chassis. Return 1 for HPET.
949 * Else return 0 to use TSC.
950 * May have to revisit this when multi-core + hyperthreaded CPUs come
951 * out, but AFAIK this will work even for them.
953 return (clusters > 2);
957 * This interrupt should _never_ happen with our APIC/SMP architecture
959 asmlinkage void smp_spurious_interrupt(void)
964 * Check if this really is a spurious interrupt and ACK it
965 * if it is a vectored one. Just in case...
966 * Spurious interrupts should not be ACKed.
968 v = apic_read(APIC_ISR + ((SPURIOUS_APIC_VECTOR & ~0x1f) >> 1));
969 if (v & (1 << (SPURIOUS_APIC_VECTOR & 0x1f)))
973 static unsigned long last_warning;
974 static unsigned long skipped;
976 /* see sw-dev-man vol 3, chapter 7.4.13.5 */
977 if (time_before(last_warning+30*HZ,jiffies)) {
978 printk(KERN_INFO "spurious APIC interrupt on CPU#%d, %ld skipped.\n",
979 smp_processor_id(), skipped);
980 last_warning = jiffies;
990 * This interrupt should never happen with our APIC/SMP architecture
993 asmlinkage void smp_error_interrupt(void)
998 /* First tickle the hardware, only then report what went on. -- REW */
999 v = apic_read(APIC_ESR);
1000 apic_write(APIC_ESR, 0);
1001 v1 = apic_read(APIC_ESR);
1003 atomic_inc(&irq_err_count);
1005 /* Here is what the APIC error bits mean:
1008 2: Send accept error
1009 3: Receive accept error
1011 5: Send illegal vector
1012 6: Received illegal vector
1013 7: Illegal register address
1015 printk (KERN_DEBUG "APIC error on CPU%d: %02x(%02x)\n",
1016 smp_processor_id(), v , v1);
1023 * This initializes the IO-APIC and APIC hardware if this is
1026 int __init APIC_init_uniprocessor (void)
1029 printk(KERN_INFO "Apic disabled\n");
1032 if (!cpu_has_apic) {
1034 printk(KERN_INFO "Apic disabled by BIOS\n");
1038 verify_local_APIC();
1042 phys_cpu_present_map = physid_mask_of_physid(0);
1043 apic_write_around(APIC_ID, boot_cpu_id);
1047 #ifdef CONFIG_X86_IO_APIC
1048 if (smp_found_config && !skip_ioapic_setup && nr_ioapics)
1053 setup_boot_APIC_clock();
1058 static __init int setup_disableapic(char *str)
1064 static __init int setup_nolapic(char *str)
1070 static __init int setup_noapictimer(char *str)
1072 disable_apic_timer = 1;
1076 /* dummy parsing: see setup.c */
1078 __setup("disableapic", setup_disableapic);
1079 __setup("nolapic", setup_nolapic); /* same as disableapic, for compatibility */
1081 __setup("noapictimer", setup_noapictimer);
1083 /* no "lapic" flag - we only use the lapic when the BIOS tells us so. */