2 * Intel IO-APIC support for multi-Pentium hosts.
4 * Copyright (C) 1997, 1998, 1999, 2000 Ingo Molnar, Hajnalka Szabo
6 * Many thanks to Stig Venaas for trying out countless experimental
7 * patches and reporting/debugging problems patiently!
9 * (c) 1999, Multiple IO-APIC support, developed by
10 * Ken-ichi Yaku <yaku@css1.kbnes.nec.co.jp> and
11 * Hidemi Kishimoto <kisimoto@css1.kbnes.nec.co.jp>,
12 * further tested and cleaned up by Zach Brown <zab@redhat.com>
13 * and Ingo Molnar <mingo@redhat.com>
16 * Maciej W. Rozycki : Bits for genuine 82489DX APICs;
17 * thanks to Eric Gilmore
19 * for testing these extensively
20 * Paul Diefenbaugh : Added full ACPI support
24 #include <linux/irq.h>
25 #include <linux/interrupt.h>
26 #include <linux/init.h>
27 #include <linux/delay.h>
28 #include <linux/sched.h>
29 #include <linux/config.h>
30 #include <linux/smp_lock.h>
31 #include <linux/mc146818rtc.h>
32 #include <linux/acpi.h>
33 #include <linux/sysdev.h>
38 #include <asm/proto.h>
39 #include <asm/mach_apic.h>
41 #define __apicdebuginit __init
43 int sis_apic_bug; /* not actually supported, dummy for compile */
45 static DEFINE_SPINLOCK(ioapic_lock);
48 * # of IRQ routing registers
50 int nr_ioapic_registers[MAX_IO_APICS];
53 * Rough estimation of how many shared IRQs there are, can
56 #define MAX_PLUS_SHARED_IRQS NR_IRQS
57 #define PIN_MAP_SIZE (MAX_PLUS_SHARED_IRQS + NR_IRQS)
60 * This is performance-critical, we want to do it O(1)
62 * the indexing order of this array favors 1:1 mappings
63 * between pins and IRQs.
66 static struct irq_pin_list {
67 short apic, pin, next;
68 } irq_2_pin[PIN_MAP_SIZE];
70 int vector_irq[NR_VECTORS] = { [0 ... NR_VECTORS - 1] = -1};
72 #define vector_to_irq(vector) \
73 (platform_legacy_irq(vector) ? vector : vector_irq[vector])
75 #define vector_to_irq(vector) (vector)
79 * The common case is 1:1 IRQ<->pin mappings. Sometimes there are
80 * shared ISA-space IRQs, so we have to support them. We are super
81 * fast in the common case, and fast for shared ISA-space IRQs.
83 static void add_pin_to_irq(unsigned int irq, int apic, int pin)
85 static int first_free_entry = NR_IRQS;
86 struct irq_pin_list *entry = irq_2_pin + irq;
89 entry = irq_2_pin + entry->next;
91 if (entry->pin != -1) {
92 entry->next = first_free_entry;
93 entry = irq_2_pin + entry->next;
94 if (++first_free_entry >= PIN_MAP_SIZE)
95 panic("io_apic.c: whoops");
101 #define __DO_ACTION(R, ACTION, FINAL) \
105 struct irq_pin_list *entry = irq_2_pin + irq; \
112 reg = io_apic_read(entry->apic, 0x10 + R + pin*2); \
114 io_apic_modify(entry->apic, reg); \
117 entry = irq_2_pin + entry->next; \
122 #define DO_ACTION(name,R,ACTION, FINAL) \
124 static void name##_IO_APIC_irq (unsigned int irq) \
125 __DO_ACTION(R, ACTION, FINAL)
127 DO_ACTION( __mask, 0, |= 0x00010000, io_apic_sync(entry->apic) )
129 DO_ACTION( __unmask, 0, &= 0xfffeffff, )
132 static void mask_IO_APIC_irq (unsigned int irq)
136 spin_lock_irqsave(&ioapic_lock, flags);
137 __mask_IO_APIC_irq(irq);
138 spin_unlock_irqrestore(&ioapic_lock, flags);
141 static void unmask_IO_APIC_irq (unsigned int irq)
145 spin_lock_irqsave(&ioapic_lock, flags);
146 __unmask_IO_APIC_irq(irq);
147 spin_unlock_irqrestore(&ioapic_lock, flags);
150 void clear_IO_APIC_pin(unsigned int apic, unsigned int pin)
152 struct IO_APIC_route_entry entry;
155 /* Check delivery_mode to be sure we're not clearing an SMI pin */
156 spin_lock_irqsave(&ioapic_lock, flags);
157 *(((int*)&entry) + 0) = io_apic_read(apic, 0x10 + 2 * pin);
158 *(((int*)&entry) + 1) = io_apic_read(apic, 0x11 + 2 * pin);
159 spin_unlock_irqrestore(&ioapic_lock, flags);
160 if (entry.delivery_mode == dest_SMI)
163 * Disable it in the IO-APIC irq-routing table:
165 memset(&entry, 0, sizeof(entry));
167 spin_lock_irqsave(&ioapic_lock, flags);
168 io_apic_write(apic, 0x10 + 2 * pin, *(((int *)&entry) + 0));
169 io_apic_write(apic, 0x11 + 2 * pin, *(((int *)&entry) + 1));
170 spin_unlock_irqrestore(&ioapic_lock, flags);
173 static void clear_IO_APIC (void)
177 for (apic = 0; apic < nr_ioapics; apic++)
178 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++)
179 clear_IO_APIC_pin(apic, pin);
183 * support for broken MP BIOSs, enables hand-redirection of PIRQ0-7 to
184 * specific CPU-side IRQs.
188 int pirq_entries [MAX_PIRQS];
190 int skip_ioapic_setup;
193 /* dummy parsing: see setup.c */
195 static int __init disable_ioapic_setup(char *str)
197 skip_ioapic_setup = 1;
201 static int __init enable_ioapic_setup(char *str)
204 skip_ioapic_setup = 0;
208 __setup("noapic", disable_ioapic_setup);
209 __setup("apic", enable_ioapic_setup);
211 #include <asm/pci-direct.h>
212 #include <linux/pci_ids.h>
213 #include <linux/pci.h>
215 /* Temporary Hack. Nvidia and VIA boards currently only work with IO-APIC
216 off. Check for an Nvidia or VIA PCI bridge and turn it off.
217 Use pci direct infrastructure because this runs before the PCI subsystem.
219 Can be overwritten with "apic"
221 And another hack to disable the IOMMU on VIA chipsets.
224 void __init check_ioapic(void)
230 /* Poor man's PCI discovery */
231 for (num = 0; num < 32; num++) {
232 for (slot = 0; slot < 32; slot++) {
233 for (func = 0; func < 8; func++) {
237 class = read_pci_config(num,slot,func,
239 if (class == 0xffffffff)
242 if ((class >> 16) != PCI_CLASS_BRIDGE_PCI)
245 vendor = read_pci_config(num, slot, func,
249 case PCI_VENDOR_ID_VIA:
250 #ifdef CONFIG_GART_IOMMU
251 if ((end_pfn >= (0xffffffff>>PAGE_SHIFT) ||
253 !iommu_aperture_allowed) {
255 "Looks like a VIA chipset. Disabling IOMMU. Overwrite with \"iommu=allowed\"\n");
256 iommu_aperture_disabled = 1;
260 case PCI_VENDOR_ID_NVIDIA:
262 /* All timer overrides on Nvidia
263 seem to be wrong. Skip them. */
264 acpi_skip_timer_override = 1;
266 "Nvidia board detected. Ignoring ACPI timer override.\n");
268 /* RED-PEN skip them on mptables too? */
272 /* No multi-function device? */
273 type = read_pci_config_byte(num,slot,func,
282 static int __init ioapic_pirq_setup(char *str)
285 int ints[MAX_PIRQS+1];
287 get_options(str, ARRAY_SIZE(ints), ints);
289 for (i = 0; i < MAX_PIRQS; i++)
290 pirq_entries[i] = -1;
293 apic_printk(APIC_VERBOSE, "PIRQ redirection, working around broken MP-BIOS.\n");
295 if (ints[0] < MAX_PIRQS)
298 for (i = 0; i < max; i++) {
299 apic_printk(APIC_VERBOSE, "... PIRQ%d -> IRQ %d\n", i, ints[i+1]);
301 * PIRQs are mapped upside down, usually.
303 pirq_entries[MAX_PIRQS-i-1] = ints[i+1];
308 __setup("pirq=", ioapic_pirq_setup);
311 * Find the IRQ entry number of a certain pin.
313 static int find_irq_entry(int apic, int pin, int type)
317 for (i = 0; i < mp_irq_entries; i++)
318 if (mp_irqs[i].mpc_irqtype == type &&
319 (mp_irqs[i].mpc_dstapic == mp_ioapics[apic].mpc_apicid ||
320 mp_irqs[i].mpc_dstapic == MP_APIC_ALL) &&
321 mp_irqs[i].mpc_dstirq == pin)
328 * Find the pin to which IRQ[irq] (ISA) is connected
330 static int __init find_isa_irq_pin(int irq, int type)
334 for (i = 0; i < mp_irq_entries; i++) {
335 int lbus = mp_irqs[i].mpc_srcbus;
337 if ((mp_bus_id_to_type[lbus] == MP_BUS_ISA ||
338 mp_bus_id_to_type[lbus] == MP_BUS_EISA ||
339 mp_bus_id_to_type[lbus] == MP_BUS_MCA) &&
340 (mp_irqs[i].mpc_irqtype == type) &&
341 (mp_irqs[i].mpc_srcbusirq == irq))
343 return mp_irqs[i].mpc_dstirq;
349 * Find a specific PCI IRQ entry.
350 * Not an __init, possibly needed by modules
352 static int pin_2_irq(int idx, int apic, int pin);
354 int IO_APIC_get_PCI_irq_vector(int bus, int slot, int pin)
356 int apic, i, best_guess = -1;
358 apic_printk(APIC_DEBUG, "querying PCI -> IRQ mapping bus:%d, slot:%d, pin:%d.\n",
360 if (mp_bus_id_to_pci_bus[bus] == -1) {
361 apic_printk(APIC_VERBOSE, "PCI BIOS passed nonexistent PCI bus %d!\n", bus);
364 for (i = 0; i < mp_irq_entries; i++) {
365 int lbus = mp_irqs[i].mpc_srcbus;
367 for (apic = 0; apic < nr_ioapics; apic++)
368 if (mp_ioapics[apic].mpc_apicid == mp_irqs[i].mpc_dstapic ||
369 mp_irqs[i].mpc_dstapic == MP_APIC_ALL)
372 if ((mp_bus_id_to_type[lbus] == MP_BUS_PCI) &&
373 !mp_irqs[i].mpc_irqtype &&
375 (slot == ((mp_irqs[i].mpc_srcbusirq >> 2) & 0x1f))) {
376 int irq = pin_2_irq(i,apic,mp_irqs[i].mpc_dstirq);
378 if (!(apic || IO_APIC_IRQ(irq)))
381 if (pin == (mp_irqs[i].mpc_srcbusirq & 3))
384 * Use the first all-but-pin matching entry as a
385 * best-guess fuzzy result for broken mptables.
395 * EISA Edge/Level control register, ELCR
397 static int EISA_ELCR(unsigned int irq)
400 unsigned int port = 0x4d0 + (irq >> 3);
401 return (inb(port) >> (irq & 7)) & 1;
403 apic_printk(APIC_VERBOSE, "Broken MPtable reports ISA irq %d\n", irq);
407 /* EISA interrupts are always polarity zero and can be edge or level
408 * trigger depending on the ELCR value. If an interrupt is listed as
409 * EISA conforming in the MP table, that means its trigger type must
410 * be read in from the ELCR */
412 #define default_EISA_trigger(idx) (EISA_ELCR(mp_irqs[idx].mpc_srcbusirq))
413 #define default_EISA_polarity(idx) (0)
415 /* ISA interrupts are always polarity zero edge triggered,
416 * when listed as conforming in the MP table. */
418 #define default_ISA_trigger(idx) (0)
419 #define default_ISA_polarity(idx) (0)
421 /* PCI interrupts are always polarity one level triggered,
422 * when listed as conforming in the MP table. */
424 #define default_PCI_trigger(idx) (1)
425 #define default_PCI_polarity(idx) (1)
427 /* MCA interrupts are always polarity zero level triggered,
428 * when listed as conforming in the MP table. */
430 #define default_MCA_trigger(idx) (1)
431 #define default_MCA_polarity(idx) (0)
433 static int __init MPBIOS_polarity(int idx)
435 int bus = mp_irqs[idx].mpc_srcbus;
439 * Determine IRQ line polarity (high active or low active):
441 switch (mp_irqs[idx].mpc_irqflag & 3)
443 case 0: /* conforms, ie. bus-type dependent polarity */
445 switch (mp_bus_id_to_type[bus])
447 case MP_BUS_ISA: /* ISA pin */
449 polarity = default_ISA_polarity(idx);
452 case MP_BUS_EISA: /* EISA pin */
454 polarity = default_EISA_polarity(idx);
457 case MP_BUS_PCI: /* PCI pin */
459 polarity = default_PCI_polarity(idx);
462 case MP_BUS_MCA: /* MCA pin */
464 polarity = default_MCA_polarity(idx);
469 printk(KERN_WARNING "broken BIOS!!\n");
476 case 1: /* high active */
481 case 2: /* reserved */
483 printk(KERN_WARNING "broken BIOS!!\n");
487 case 3: /* low active */
492 default: /* invalid */
494 printk(KERN_WARNING "broken BIOS!!\n");
502 static int MPBIOS_trigger(int idx)
504 int bus = mp_irqs[idx].mpc_srcbus;
508 * Determine IRQ trigger mode (edge or level sensitive):
510 switch ((mp_irqs[idx].mpc_irqflag>>2) & 3)
512 case 0: /* conforms, ie. bus-type dependent */
514 switch (mp_bus_id_to_type[bus])
516 case MP_BUS_ISA: /* ISA pin */
518 trigger = default_ISA_trigger(idx);
521 case MP_BUS_EISA: /* EISA pin */
523 trigger = default_EISA_trigger(idx);
526 case MP_BUS_PCI: /* PCI pin */
528 trigger = default_PCI_trigger(idx);
531 case MP_BUS_MCA: /* MCA pin */
533 trigger = default_MCA_trigger(idx);
538 printk(KERN_WARNING "broken BIOS!!\n");
550 case 2: /* reserved */
552 printk(KERN_WARNING "broken BIOS!!\n");
561 default: /* invalid */
563 printk(KERN_WARNING "broken BIOS!!\n");
571 static inline int irq_polarity(int idx)
573 return MPBIOS_polarity(idx);
576 static inline int irq_trigger(int idx)
578 return MPBIOS_trigger(idx);
581 static int pin_2_irq(int idx, int apic, int pin)
584 int bus = mp_irqs[idx].mpc_srcbus;
587 * Debugging check, we are in big trouble if this message pops up!
589 if (mp_irqs[idx].mpc_dstirq != pin)
590 printk(KERN_ERR "broken BIOS or MPTABLE parser, ayiee!!\n");
592 switch (mp_bus_id_to_type[bus])
594 case MP_BUS_ISA: /* ISA pin */
598 irq = mp_irqs[idx].mpc_srcbusirq;
601 case MP_BUS_PCI: /* PCI pin */
604 * PCI IRQs are mapped in order
608 irq += nr_ioapic_registers[i++];
614 printk(KERN_ERR "unknown bus type %d.\n",bus);
621 * PCI IRQ command line redirection. Yes, limits are hardcoded.
623 if ((pin >= 16) && (pin <= 23)) {
624 if (pirq_entries[pin-16] != -1) {
625 if (!pirq_entries[pin-16]) {
626 apic_printk(APIC_VERBOSE, "disabling PIRQ%d\n", pin-16);
628 irq = pirq_entries[pin-16];
629 apic_printk(APIC_VERBOSE, "using PIRQ%d -> IRQ %d\n",
637 static inline int IO_APIC_irq_trigger(int irq)
641 for (apic = 0; apic < nr_ioapics; apic++) {
642 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
643 idx = find_irq_entry(apic,pin,mp_INT);
644 if ((idx != -1) && (irq == pin_2_irq(idx,apic,pin)))
645 return irq_trigger(idx);
649 * nonexistent IRQs are edge default
654 /* irq_vectors is indexed by the sum of all RTEs in all I/O APICs. */
655 u8 irq_vector[NR_IRQ_VECTORS] = { FIRST_DEVICE_VECTOR , 0 };
657 int assign_irq_vector(int irq)
659 static int current_vector = FIRST_DEVICE_VECTOR, offset = 0;
661 BUG_ON(irq >= NR_IRQ_VECTORS);
662 if (IO_APIC_VECTOR(irq) > 0)
663 return IO_APIC_VECTOR(irq);
666 if (current_vector == IA32_SYSCALL_VECTOR)
669 if (current_vector >= FIRST_SYSTEM_VECTOR) {
673 current_vector = FIRST_DEVICE_VECTOR + offset;
676 vector_irq[current_vector] = irq;
677 if (irq != AUTO_ASSIGN)
678 IO_APIC_VECTOR(irq) = current_vector;
680 return current_vector;
683 extern void (*interrupt[NR_IRQS])(void);
684 static struct hw_interrupt_type ioapic_level_type;
685 static struct hw_interrupt_type ioapic_edge_type;
687 #define IOAPIC_AUTO -1
688 #define IOAPIC_EDGE 0
689 #define IOAPIC_LEVEL 1
691 static inline void ioapic_register_intr(int irq, int vector, unsigned long trigger)
693 if (use_pci_vector() && !platform_legacy_irq(irq)) {
694 if ((trigger == IOAPIC_AUTO && IO_APIC_irq_trigger(irq)) ||
695 trigger == IOAPIC_LEVEL)
696 irq_desc[vector].handler = &ioapic_level_type;
698 irq_desc[vector].handler = &ioapic_edge_type;
699 set_intr_gate(vector, interrupt[vector]);
701 if ((trigger == IOAPIC_AUTO && IO_APIC_irq_trigger(irq)) ||
702 trigger == IOAPIC_LEVEL)
703 irq_desc[irq].handler = &ioapic_level_type;
705 irq_desc[irq].handler = &ioapic_edge_type;
706 set_intr_gate(vector, interrupt[irq]);
710 void __init setup_IO_APIC_irqs(void)
712 struct IO_APIC_route_entry entry;
713 int apic, pin, idx, irq, first_notcon = 1, vector;
716 apic_printk(APIC_VERBOSE, KERN_DEBUG "init IO_APIC IRQs\n");
718 for (apic = 0; apic < nr_ioapics; apic++) {
719 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
722 * add it to the IO-APIC irq-routing table:
724 memset(&entry,0,sizeof(entry));
726 entry.delivery_mode = INT_DELIVERY_MODE;
727 entry.dest_mode = INT_DEST_MODE;
728 entry.mask = 0; /* enable IRQ */
729 entry.dest.logical.logical_dest = cpu_mask_to_apicid(TARGET_CPUS);
731 idx = find_irq_entry(apic,pin,mp_INT);
734 apic_printk(APIC_VERBOSE, KERN_DEBUG " IO-APIC (apicid-pin) %d-%d", mp_ioapics[apic].mpc_apicid, pin);
737 apic_printk(APIC_VERBOSE, ", %d-%d", mp_ioapics[apic].mpc_apicid, pin);
741 entry.trigger = irq_trigger(idx);
742 entry.polarity = irq_polarity(idx);
744 if (irq_trigger(idx)) {
747 entry.dest.logical.logical_dest = cpu_mask_to_apicid(TARGET_CPUS);
750 irq = pin_2_irq(idx, apic, pin);
751 add_pin_to_irq(irq, apic, pin);
753 if (!apic && !IO_APIC_IRQ(irq))
756 if (IO_APIC_IRQ(irq)) {
757 vector = assign_irq_vector(irq);
758 entry.vector = vector;
760 ioapic_register_intr(irq, vector, IOAPIC_AUTO);
761 if (!apic && (irq < 16))
762 disable_8259A_irq(irq);
764 spin_lock_irqsave(&ioapic_lock, flags);
765 io_apic_write(apic, 0x11+2*pin, *(((int *)&entry)+1));
766 io_apic_write(apic, 0x10+2*pin, *(((int *)&entry)+0));
767 spin_unlock_irqrestore(&ioapic_lock, flags);
772 apic_printk(APIC_VERBOSE," not connected.\n");
776 * Set up the 8259A-master output pin as broadcast to all
779 void __init setup_ExtINT_IRQ0_pin(unsigned int pin, int vector)
781 struct IO_APIC_route_entry entry;
784 memset(&entry,0,sizeof(entry));
786 disable_8259A_irq(0);
789 apic_write_around(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT);
792 * We use logical delivery to get the timer IRQ
795 entry.dest_mode = INT_DEST_MODE;
796 entry.mask = 0; /* unmask IRQ now */
797 entry.dest.logical.logical_dest = cpu_mask_to_apicid(TARGET_CPUS);
798 entry.delivery_mode = INT_DELIVERY_MODE;
801 entry.vector = vector;
804 * The timer IRQ doesn't have to know that behind the
805 * scene we have a 8259A-master in AEOI mode ...
807 irq_desc[0].handler = &ioapic_edge_type;
810 * Add it to the IO-APIC irq-routing table:
812 spin_lock_irqsave(&ioapic_lock, flags);
813 io_apic_write(0, 0x11+2*pin, *(((int *)&entry)+1));
814 io_apic_write(0, 0x10+2*pin, *(((int *)&entry)+0));
815 spin_unlock_irqrestore(&ioapic_lock, flags);
820 void __init UNEXPECTED_IO_APIC(void)
824 void __apicdebuginit print_IO_APIC(void)
827 union IO_APIC_reg_00 reg_00;
828 union IO_APIC_reg_01 reg_01;
829 union IO_APIC_reg_02 reg_02;
832 if (apic_verbosity == APIC_QUIET)
835 printk(KERN_DEBUG "number of MP IRQ sources: %d.\n", mp_irq_entries);
836 for (i = 0; i < nr_ioapics; i++)
837 printk(KERN_DEBUG "number of IO-APIC #%d registers: %d.\n",
838 mp_ioapics[i].mpc_apicid, nr_ioapic_registers[i]);
841 * We are a bit conservative about what we expect. We have to
842 * know about every hardware change ASAP.
844 printk(KERN_INFO "testing the IO APIC.......................\n");
846 for (apic = 0; apic < nr_ioapics; apic++) {
848 spin_lock_irqsave(&ioapic_lock, flags);
849 reg_00.raw = io_apic_read(apic, 0);
850 reg_01.raw = io_apic_read(apic, 1);
851 if (reg_01.bits.version >= 0x10)
852 reg_02.raw = io_apic_read(apic, 2);
853 spin_unlock_irqrestore(&ioapic_lock, flags);
856 printk(KERN_DEBUG "IO APIC #%d......\n", mp_ioapics[apic].mpc_apicid);
857 printk(KERN_DEBUG ".... register #00: %08X\n", reg_00.raw);
858 printk(KERN_DEBUG "....... : physical APIC id: %02X\n", reg_00.bits.ID);
859 if (reg_00.bits.__reserved_1 || reg_00.bits.__reserved_2)
860 UNEXPECTED_IO_APIC();
862 printk(KERN_DEBUG ".... register #01: %08X\n", *(int *)®_01);
863 printk(KERN_DEBUG "....... : max redirection entries: %04X\n", reg_01.bits.entries);
864 if ( (reg_01.bits.entries != 0x0f) && /* older (Neptune) boards */
865 (reg_01.bits.entries != 0x17) && /* typical ISA+PCI boards */
866 (reg_01.bits.entries != 0x1b) && /* Compaq Proliant boards */
867 (reg_01.bits.entries != 0x1f) && /* dual Xeon boards */
868 (reg_01.bits.entries != 0x22) && /* bigger Xeon boards */
869 (reg_01.bits.entries != 0x2E) &&
870 (reg_01.bits.entries != 0x3F) &&
871 (reg_01.bits.entries != 0x03)
873 UNEXPECTED_IO_APIC();
875 printk(KERN_DEBUG "....... : PRQ implemented: %X\n", reg_01.bits.PRQ);
876 printk(KERN_DEBUG "....... : IO APIC version: %04X\n", reg_01.bits.version);
877 if ( (reg_01.bits.version != 0x01) && /* 82489DX IO-APICs */
878 (reg_01.bits.version != 0x02) && /* 82801BA IO-APICs (ICH2) */
879 (reg_01.bits.version != 0x10) && /* oldest IO-APICs */
880 (reg_01.bits.version != 0x11) && /* Pentium/Pro IO-APICs */
881 (reg_01.bits.version != 0x13) && /* Xeon IO-APICs */
882 (reg_01.bits.version != 0x20) /* Intel P64H (82806 AA) */
884 UNEXPECTED_IO_APIC();
885 if (reg_01.bits.__reserved_1 || reg_01.bits.__reserved_2)
886 UNEXPECTED_IO_APIC();
888 if (reg_01.bits.version >= 0x10) {
889 printk(KERN_DEBUG ".... register #02: %08X\n", reg_02.raw);
890 printk(KERN_DEBUG "....... : arbitration: %02X\n", reg_02.bits.arbitration);
891 if (reg_02.bits.__reserved_1 || reg_02.bits.__reserved_2)
892 UNEXPECTED_IO_APIC();
895 printk(KERN_DEBUG ".... IRQ redirection table:\n");
897 printk(KERN_DEBUG " NR Log Phy Mask Trig IRR Pol"
898 " Stat Dest Deli Vect: \n");
900 for (i = 0; i <= reg_01.bits.entries; i++) {
901 struct IO_APIC_route_entry entry;
903 spin_lock_irqsave(&ioapic_lock, flags);
904 *(((int *)&entry)+0) = io_apic_read(apic, 0x10+i*2);
905 *(((int *)&entry)+1) = io_apic_read(apic, 0x11+i*2);
906 spin_unlock_irqrestore(&ioapic_lock, flags);
908 printk(KERN_DEBUG " %02x %03X %02X ",
910 entry.dest.logical.logical_dest,
911 entry.dest.physical.physical_dest
914 printk("%1d %1d %1d %1d %1d %1d %1d %02X\n",
919 entry.delivery_status,
926 if (use_pci_vector())
927 printk(KERN_INFO "Using vector-based indexing\n");
928 printk(KERN_DEBUG "IRQ to pin mappings:\n");
929 for (i = 0; i < NR_IRQS; i++) {
930 struct irq_pin_list *entry = irq_2_pin + i;
933 if (use_pci_vector() && !platform_legacy_irq(i))
934 printk(KERN_DEBUG "IRQ%d ", IO_APIC_VECTOR(i));
936 printk(KERN_DEBUG "IRQ%d ", i);
938 printk("-> %d:%d", entry->apic, entry->pin);
941 entry = irq_2_pin + entry->next;
946 printk(KERN_INFO ".................................... done.\n");
951 static __apicdebuginit void print_APIC_bitfield (int base)
956 if (apic_verbosity == APIC_QUIET)
959 printk(KERN_DEBUG "0123456789abcdef0123456789abcdef\n" KERN_DEBUG);
960 for (i = 0; i < 8; i++) {
961 v = apic_read(base + i*0x10);
962 for (j = 0; j < 32; j++) {
972 void __apicdebuginit print_local_APIC(void * dummy)
974 unsigned int v, ver, maxlvt;
976 if (apic_verbosity == APIC_QUIET)
979 printk("\n" KERN_DEBUG "printing local APIC contents on CPU#%d/%d:\n",
980 smp_processor_id(), hard_smp_processor_id());
981 v = apic_read(APIC_ID);
982 printk(KERN_INFO "... APIC ID: %08x (%01x)\n", v, GET_APIC_ID(v));
983 v = apic_read(APIC_LVR);
984 printk(KERN_INFO "... APIC VERSION: %08x\n", v);
985 ver = GET_APIC_VERSION(v);
986 maxlvt = get_maxlvt();
988 v = apic_read(APIC_TASKPRI);
989 printk(KERN_DEBUG "... APIC TASKPRI: %08x (%02x)\n", v, v & APIC_TPRI_MASK);
991 if (APIC_INTEGRATED(ver)) { /* !82489DX */
992 v = apic_read(APIC_ARBPRI);
993 printk(KERN_DEBUG "... APIC ARBPRI: %08x (%02x)\n", v,
994 v & APIC_ARBPRI_MASK);
995 v = apic_read(APIC_PROCPRI);
996 printk(KERN_DEBUG "... APIC PROCPRI: %08x\n", v);
999 v = apic_read(APIC_EOI);
1000 printk(KERN_DEBUG "... APIC EOI: %08x\n", v);
1001 v = apic_read(APIC_RRR);
1002 printk(KERN_DEBUG "... APIC RRR: %08x\n", v);
1003 v = apic_read(APIC_LDR);
1004 printk(KERN_DEBUG "... APIC LDR: %08x\n", v);
1005 v = apic_read(APIC_DFR);
1006 printk(KERN_DEBUG "... APIC DFR: %08x\n", v);
1007 v = apic_read(APIC_SPIV);
1008 printk(KERN_DEBUG "... APIC SPIV: %08x\n", v);
1010 printk(KERN_DEBUG "... APIC ISR field:\n");
1011 print_APIC_bitfield(APIC_ISR);
1012 printk(KERN_DEBUG "... APIC TMR field:\n");
1013 print_APIC_bitfield(APIC_TMR);
1014 printk(KERN_DEBUG "... APIC IRR field:\n");
1015 print_APIC_bitfield(APIC_IRR);
1017 if (APIC_INTEGRATED(ver)) { /* !82489DX */
1018 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */
1019 apic_write(APIC_ESR, 0);
1020 v = apic_read(APIC_ESR);
1021 printk(KERN_DEBUG "... APIC ESR: %08x\n", v);
1024 v = apic_read(APIC_ICR);
1025 printk(KERN_DEBUG "... APIC ICR: %08x\n", v);
1026 v = apic_read(APIC_ICR2);
1027 printk(KERN_DEBUG "... APIC ICR2: %08x\n", v);
1029 v = apic_read(APIC_LVTT);
1030 printk(KERN_DEBUG "... APIC LVTT: %08x\n", v);
1032 if (maxlvt > 3) { /* PC is LVT#4. */
1033 v = apic_read(APIC_LVTPC);
1034 printk(KERN_DEBUG "... APIC LVTPC: %08x\n", v);
1036 v = apic_read(APIC_LVT0);
1037 printk(KERN_DEBUG "... APIC LVT0: %08x\n", v);
1038 v = apic_read(APIC_LVT1);
1039 printk(KERN_DEBUG "... APIC LVT1: %08x\n", v);
1041 if (maxlvt > 2) { /* ERR is LVT#3. */
1042 v = apic_read(APIC_LVTERR);
1043 printk(KERN_DEBUG "... APIC LVTERR: %08x\n", v);
1046 v = apic_read(APIC_TMICT);
1047 printk(KERN_DEBUG "... APIC TMICT: %08x\n", v);
1048 v = apic_read(APIC_TMCCT);
1049 printk(KERN_DEBUG "... APIC TMCCT: %08x\n", v);
1050 v = apic_read(APIC_TDCR);
1051 printk(KERN_DEBUG "... APIC TDCR: %08x\n", v);
1055 void print_all_local_APICs (void)
1057 on_each_cpu(print_local_APIC, NULL, 1, 1);
1060 void __apicdebuginit print_PIC(void)
1062 extern spinlock_t i8259A_lock;
1064 unsigned long flags;
1066 if (apic_verbosity == APIC_QUIET)
1069 printk(KERN_DEBUG "\nprinting PIC contents\n");
1071 spin_lock_irqsave(&i8259A_lock, flags);
1073 v = inb(0xa1) << 8 | inb(0x21);
1074 printk(KERN_DEBUG "... PIC IMR: %04x\n", v);
1076 v = inb(0xa0) << 8 | inb(0x20);
1077 printk(KERN_DEBUG "... PIC IRR: %04x\n", v);
1081 v = inb(0xa0) << 8 | inb(0x20);
1085 spin_unlock_irqrestore(&i8259A_lock, flags);
1087 printk(KERN_DEBUG "... PIC ISR: %04x\n", v);
1089 v = inb(0x4d1) << 8 | inb(0x4d0);
1090 printk(KERN_DEBUG "... PIC ELCR: %04x\n", v);
1093 static void __init enable_IO_APIC(void)
1095 union IO_APIC_reg_01 reg_01;
1097 unsigned long flags;
1099 for (i = 0; i < PIN_MAP_SIZE; i++) {
1100 irq_2_pin[i].pin = -1;
1101 irq_2_pin[i].next = 0;
1104 for (i = 0; i < MAX_PIRQS; i++)
1105 pirq_entries[i] = -1;
1108 * The number of IO-APIC IRQ registers (== #pins):
1110 for (i = 0; i < nr_ioapics; i++) {
1111 spin_lock_irqsave(&ioapic_lock, flags);
1112 reg_01.raw = io_apic_read(i, 1);
1113 spin_unlock_irqrestore(&ioapic_lock, flags);
1114 nr_ioapic_registers[i] = reg_01.bits.entries+1;
1118 * Do not trust the IO-APIC being empty at bootup
1124 * Not an __init, needed by the reboot code
1126 void disable_IO_APIC(void)
1129 * Clear the IO-APIC before rebooting:
1133 disconnect_bsp_APIC();
1137 * function to set the IO-APIC physical IDs based on the
1138 * values stored in the MPC table.
1140 * by Matt Domsch <Matt_Domsch@dell.com> Tue Dec 21 12:25:05 CST 1999
1143 static void __init setup_ioapic_ids_from_mpc (void)
1145 union IO_APIC_reg_00 reg_00;
1148 unsigned char old_id;
1149 unsigned long flags;
1152 * Set the IOAPIC ID to the value stored in the MPC table.
1154 for (apic = 0; apic < nr_ioapics; apic++) {
1156 /* Read the register 0 value */
1157 spin_lock_irqsave(&ioapic_lock, flags);
1158 reg_00.raw = io_apic_read(apic, 0);
1159 spin_unlock_irqrestore(&ioapic_lock, flags);
1161 old_id = mp_ioapics[apic].mpc_apicid;
1164 printk(KERN_INFO "Using IO-APIC %d\n", mp_ioapics[apic].mpc_apicid);
1168 * We need to adjust the IRQ routing table
1169 * if the ID changed.
1171 if (old_id != mp_ioapics[apic].mpc_apicid)
1172 for (i = 0; i < mp_irq_entries; i++)
1173 if (mp_irqs[i].mpc_dstapic == old_id)
1174 mp_irqs[i].mpc_dstapic
1175 = mp_ioapics[apic].mpc_apicid;
1178 * Read the right value from the MPC table and
1179 * write it into the ID register.
1181 apic_printk(APIC_VERBOSE,KERN_INFO "...changing IO-APIC physical APIC ID to %d ...",
1182 mp_ioapics[apic].mpc_apicid);
1184 reg_00.bits.ID = mp_ioapics[apic].mpc_apicid;
1185 spin_lock_irqsave(&ioapic_lock, flags);
1186 io_apic_write(apic, 0, reg_00.raw);
1187 spin_unlock_irqrestore(&ioapic_lock, flags);
1192 spin_lock_irqsave(&ioapic_lock, flags);
1193 reg_00.raw = io_apic_read(apic, 0);
1194 spin_unlock_irqrestore(&ioapic_lock, flags);
1195 if (reg_00.bits.ID != mp_ioapics[apic].mpc_apicid)
1196 printk("could not set ID!\n");
1198 apic_printk(APIC_VERBOSE," ok.\n");
1203 * There is a nasty bug in some older SMP boards, their mptable lies
1204 * about the timer IRQ. We do the following to work around the situation:
1206 * - timer IRQ defaults to IO-APIC IRQ
1207 * - if this function detects that timer IRQs are defunct, then we fall
1208 * back to ISA timer IRQs
1210 static int __init timer_irq_works(void)
1212 unsigned long t1 = jiffies;
1215 /* Let ten ticks pass... */
1216 mdelay((10 * 1000) / HZ);
1219 * Expect a few ticks at least, to be sure some possible
1220 * glue logic does not lock up after one or two first
1221 * ticks in a non-ExtINT mode. Also the local APIC
1222 * might have cached one ExtINT interrupt. Finally, at
1223 * least one tick may be lost due to delays.
1227 if (jiffies - t1 > 4)
1233 * In the SMP+IOAPIC case it might happen that there are an unspecified
1234 * number of pending IRQ events unhandled. These cases are very rare,
1235 * so we 'resend' these IRQs via IPIs, to the same CPU. It's much
1236 * better to do it this way as thus we do not have to be aware of
1237 * 'pending' interrupts in the IRQ path, except at this point.
1240 * Edge triggered needs to resend any interrupt
1241 * that was delayed but this is now handled in the device
1246 * Starting up a edge-triggered IO-APIC interrupt is
1247 * nasty - we need to make sure that we get the edge.
1248 * If it is already asserted for some reason, we need
1249 * return 1 to indicate that is was pending.
1251 * This is not complete - we should be able to fake
1252 * an edge even if it isn't on the 8259A...
1255 static unsigned int startup_edge_ioapic_irq(unsigned int irq)
1257 int was_pending = 0;
1258 unsigned long flags;
1260 spin_lock_irqsave(&ioapic_lock, flags);
1262 disable_8259A_irq(irq);
1263 if (i8259A_irq_pending(irq))
1266 __unmask_IO_APIC_irq(irq);
1267 spin_unlock_irqrestore(&ioapic_lock, flags);
1273 * Once we have recorded IRQ_PENDING already, we can mask the
1274 * interrupt for real. This prevents IRQ storms from unhandled
1277 static void ack_edge_ioapic_irq(unsigned int irq)
1279 if ((irq_desc[irq].status & (IRQ_PENDING | IRQ_DISABLED))
1280 == (IRQ_PENDING | IRQ_DISABLED))
1281 mask_IO_APIC_irq(irq);
1286 * Level triggered interrupts can just be masked,
1287 * and shutting down and starting up the interrupt
1288 * is the same as enabling and disabling them -- except
1289 * with a startup need to return a "was pending" value.
1291 * Level triggered interrupts are special because we
1292 * do not touch any IO-APIC register while handling
1293 * them. We ack the APIC in the end-IRQ handler, not
1294 * in the start-IRQ-handler. Protection against reentrance
1295 * from the same interrupt is still provided, both by the
1296 * generic IRQ layer and by the fact that an unacked local
1297 * APIC does not accept IRQs.
1299 static unsigned int startup_level_ioapic_irq (unsigned int irq)
1301 unmask_IO_APIC_irq(irq);
1303 return 0; /* don't check for pending */
1306 static void end_level_ioapic_irq (unsigned int irq)
1311 static void set_ioapic_affinity_irq(unsigned int irq, cpumask_t mask)
1313 unsigned long flags;
1316 dest = cpu_mask_to_apicid(mask);
1319 * Only the high 8 bits are valid.
1321 dest = SET_APIC_LOGICAL_ID(dest);
1323 spin_lock_irqsave(&ioapic_lock, flags);
1324 __DO_ACTION(1, = dest, )
1325 spin_unlock_irqrestore(&ioapic_lock, flags);
1328 #ifdef CONFIG_PCI_MSI
1329 static unsigned int startup_edge_ioapic_vector(unsigned int vector)
1331 int irq = vector_to_irq(vector);
1333 return startup_edge_ioapic_irq(irq);
1336 static void ack_edge_ioapic_vector(unsigned int vector)
1338 int irq = vector_to_irq(vector);
1340 ack_edge_ioapic_irq(irq);
1343 static unsigned int startup_level_ioapic_vector (unsigned int vector)
1345 int irq = vector_to_irq(vector);
1347 return startup_level_ioapic_irq (irq);
1350 static void end_level_ioapic_vector (unsigned int vector)
1352 int irq = vector_to_irq(vector);
1354 end_level_ioapic_irq(irq);
1357 static void mask_IO_APIC_vector (unsigned int vector)
1359 int irq = vector_to_irq(vector);
1361 mask_IO_APIC_irq(irq);
1364 static void unmask_IO_APIC_vector (unsigned int vector)
1366 int irq = vector_to_irq(vector);
1368 unmask_IO_APIC_irq(irq);
1371 static void set_ioapic_affinity_vector (unsigned int vector,
1374 int irq = vector_to_irq(vector);
1376 set_ioapic_affinity_irq(irq, cpu_mask);
1381 * Level and edge triggered IO-APIC interrupts need different handling,
1382 * so we use two separate IRQ descriptors. Edge triggered IRQs can be
1383 * handled with the level-triggered descriptor, but that one has slightly
1384 * more overhead. Level-triggered interrupts cannot be handled with the
1385 * edge-triggered handler, without risking IRQ storms and other ugly
1389 static struct hw_interrupt_type ioapic_edge_type = {
1390 .typename = "IO-APIC-edge",
1391 .startup = startup_edge_ioapic,
1392 .shutdown = shutdown_edge_ioapic,
1393 .enable = enable_edge_ioapic,
1394 .disable = disable_edge_ioapic,
1395 .ack = ack_edge_ioapic,
1396 .end = end_edge_ioapic,
1397 .set_affinity = set_ioapic_affinity,
1400 static struct hw_interrupt_type ioapic_level_type = {
1401 .typename = "IO-APIC-level",
1402 .startup = startup_level_ioapic,
1403 .shutdown = shutdown_level_ioapic,
1404 .enable = enable_level_ioapic,
1405 .disable = disable_level_ioapic,
1406 .ack = mask_and_ack_level_ioapic,
1407 .end = end_level_ioapic,
1408 .set_affinity = set_ioapic_affinity,
1411 static inline void init_IO_APIC_traps(void)
1416 * NOTE! The local APIC isn't very good at handling
1417 * multiple interrupts at the same interrupt level.
1418 * As the interrupt level is determined by taking the
1419 * vector number and shifting that right by 4, we
1420 * want to spread these out a bit so that they don't
1421 * all fall in the same interrupt level.
1423 * Also, we've got to be careful not to trash gate
1424 * 0x80, because int 0x80 is hm, kind of importantish. ;)
1426 for (irq = 0; irq < NR_IRQS ; irq++) {
1428 if (use_pci_vector()) {
1429 if (!platform_legacy_irq(tmp))
1430 if ((tmp = vector_to_irq(tmp)) == -1)
1433 if (IO_APIC_IRQ(tmp) && !IO_APIC_VECTOR(tmp)) {
1435 * Hmm.. We don't have an entry for this,
1436 * so default to an old-fashioned 8259
1437 * interrupt if we can..
1440 make_8259A_irq(irq);
1442 /* Strange. Oh, well.. */
1443 irq_desc[irq].handler = &no_irq_type;
1448 static void enable_lapic_irq (unsigned int irq)
1452 v = apic_read(APIC_LVT0);
1453 apic_write_around(APIC_LVT0, v & ~APIC_LVT_MASKED);
1456 static void disable_lapic_irq (unsigned int irq)
1460 v = apic_read(APIC_LVT0);
1461 apic_write_around(APIC_LVT0, v | APIC_LVT_MASKED);
1464 static void ack_lapic_irq (unsigned int irq)
1469 static void end_lapic_irq (unsigned int i) { /* nothing */ }
1471 static struct hw_interrupt_type lapic_irq_type = {
1472 .typename = "local-APIC-edge",
1473 .startup = NULL, /* startup_irq() not used for IRQ0 */
1474 .shutdown = NULL, /* shutdown_irq() not used for IRQ0 */
1475 .enable = enable_lapic_irq,
1476 .disable = disable_lapic_irq,
1477 .ack = ack_lapic_irq,
1478 .end = end_lapic_irq,
1481 static void setup_nmi (void)
1484 * Dirty trick to enable the NMI watchdog ...
1485 * We put the 8259A master into AEOI mode and
1486 * unmask on all local APICs LVT0 as NMI.
1488 * The idea to use the 8259A in AEOI mode ('8259A Virtual Wire')
1489 * is from Maciej W. Rozycki - so we do not have to EOI from
1490 * the NMI handler or the timer interrupt.
1492 printk(KERN_INFO "activating NMI Watchdog ...");
1494 enable_NMI_through_LVT0(NULL);
1500 * This looks a bit hackish but it's about the only one way of sending
1501 * a few INTA cycles to 8259As and any associated glue logic. ICR does
1502 * not support the ExtINT mode, unfortunately. We need to send these
1503 * cycles as some i82489DX-based boards have glue logic that keeps the
1504 * 8259A interrupt line asserted until INTA. --macro
1506 static inline void unlock_ExtINT_logic(void)
1509 struct IO_APIC_route_entry entry0, entry1;
1510 unsigned char save_control, save_freq_select;
1511 unsigned long flags;
1513 pin = find_isa_irq_pin(8, mp_INT);
1517 spin_lock_irqsave(&ioapic_lock, flags);
1518 *(((int *)&entry0) + 1) = io_apic_read(0, 0x11 + 2 * pin);
1519 *(((int *)&entry0) + 0) = io_apic_read(0, 0x10 + 2 * pin);
1520 spin_unlock_irqrestore(&ioapic_lock, flags);
1521 clear_IO_APIC_pin(0, pin);
1523 memset(&entry1, 0, sizeof(entry1));
1525 entry1.dest_mode = 0; /* physical delivery */
1526 entry1.mask = 0; /* unmask IRQ now */
1527 entry1.dest.physical.physical_dest = hard_smp_processor_id();
1528 entry1.delivery_mode = dest_ExtINT;
1529 entry1.polarity = entry0.polarity;
1533 spin_lock_irqsave(&ioapic_lock, flags);
1534 io_apic_write(0, 0x11 + 2 * pin, *(((int *)&entry1) + 1));
1535 io_apic_write(0, 0x10 + 2 * pin, *(((int *)&entry1) + 0));
1536 spin_unlock_irqrestore(&ioapic_lock, flags);
1538 save_control = CMOS_READ(RTC_CONTROL);
1539 save_freq_select = CMOS_READ(RTC_FREQ_SELECT);
1540 CMOS_WRITE((save_freq_select & ~RTC_RATE_SELECT) | 0x6,
1542 CMOS_WRITE(save_control | RTC_PIE, RTC_CONTROL);
1547 if ((CMOS_READ(RTC_INTR_FLAGS) & RTC_PF) == RTC_PF)
1551 CMOS_WRITE(save_control, RTC_CONTROL);
1552 CMOS_WRITE(save_freq_select, RTC_FREQ_SELECT);
1553 clear_IO_APIC_pin(0, pin);
1555 spin_lock_irqsave(&ioapic_lock, flags);
1556 io_apic_write(0, 0x11 + 2 * pin, *(((int *)&entry0) + 1));
1557 io_apic_write(0, 0x10 + 2 * pin, *(((int *)&entry0) + 0));
1558 spin_unlock_irqrestore(&ioapic_lock, flags);
1562 * This code may look a bit paranoid, but it's supposed to cooperate with
1563 * a wide range of boards and BIOS bugs. Fortunately only the timer IRQ
1564 * is so screwy. Thanks to Brian Perkins for testing/hacking this beast
1565 * fanatically on his truly buggy board.
1567 static inline void check_timer(void)
1573 * get/set the timer IRQ vector:
1575 disable_8259A_irq(0);
1576 vector = assign_irq_vector(0);
1577 set_intr_gate(vector, interrupt[0]);
1580 * Subtle, code in do_timer_interrupt() expects an AEOI
1581 * mode for the 8259A whenever interrupts are routed
1582 * through I/O APICs. Also IRQ0 has to be enabled in
1583 * the 8259A which implies the virtual wire has to be
1584 * disabled in the local APIC.
1586 apic_write_around(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT);
1588 enable_8259A_irq(0);
1590 pin1 = find_isa_irq_pin(0, mp_INT);
1591 pin2 = find_isa_irq_pin(0, mp_ExtINT);
1593 apic_printk(APIC_VERBOSE,KERN_INFO "..TIMER: vector=0x%02X pin1=%d pin2=%d\n", vector, pin1, pin2);
1597 * Ok, does IRQ0 through the IOAPIC work?
1599 unmask_IO_APIC_irq(0);
1600 if (timer_irq_works()) {
1601 nmi_watchdog_default();
1602 if (nmi_watchdog == NMI_IO_APIC) {
1603 disable_8259A_irq(0);
1605 enable_8259A_irq(0);
1606 check_nmi_watchdog();
1610 clear_IO_APIC_pin(0, pin1);
1611 apic_printk(APIC_QUIET,KERN_ERR "..MP-BIOS bug: 8254 timer not connected to IO-APIC\n");
1614 apic_printk(APIC_VERBOSE,KERN_INFO "...trying to set up timer (IRQ0) through the 8259A ... ");
1616 apic_printk(APIC_VERBOSE,"\n..... (found pin %d) ...", pin2);
1618 * legacy devices should be connected to IO APIC #0
1620 setup_ExtINT_IRQ0_pin(pin2, vector);
1621 if (timer_irq_works()) {
1623 nmi_watchdog_default();
1624 if (nmi_watchdog == NMI_IO_APIC) {
1626 check_nmi_watchdog();
1631 * Cleanup, just in case ...
1633 clear_IO_APIC_pin(0, pin2);
1635 printk(" failed.\n");
1638 printk(KERN_WARNING "timer doesn't work through the IO-APIC - disabling NMI Watchdog!\n");
1642 apic_printk(APIC_VERBOSE, KERN_INFO "...trying to set up timer as Virtual Wire IRQ...");
1644 disable_8259A_irq(0);
1645 irq_desc[0].handler = &lapic_irq_type;
1646 apic_write_around(APIC_LVT0, APIC_DM_FIXED | vector); /* Fixed mode */
1647 enable_8259A_irq(0);
1649 if (timer_irq_works()) {
1650 apic_printk(APIC_QUIET, " works.\n");
1653 apic_write_around(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_FIXED | vector);
1654 apic_printk(APIC_VERBOSE," failed.\n");
1656 apic_printk(APIC_VERBOSE, KERN_INFO "...trying to set up timer as ExtINT IRQ...");
1660 apic_write_around(APIC_LVT0, APIC_DM_EXTINT);
1662 unlock_ExtINT_logic();
1664 if (timer_irq_works()) {
1665 apic_printk(APIC_VERBOSE," works.\n");
1668 apic_printk(APIC_VERBOSE," failed :(.\n");
1669 panic("IO-APIC + timer doesn't work! Try using the 'noapic' kernel parameter\n");
1674 * IRQ's that are handled by the PIC in the MPS IOAPIC case.
1675 * - IRQ2 is the cascade IRQ, and cannot be a io-apic IRQ.
1676 * Linux doesn't really care, as it's not actually used
1677 * for any interrupt handling anyway.
1679 #define PIC_IRQS (1<<2)
1681 void __init setup_IO_APIC(void)
1686 io_apic_irqs = ~0; /* all IRQs go through IOAPIC */
1688 io_apic_irqs = ~PIC_IRQS;
1690 apic_printk(APIC_VERBOSE, "ENABLING IO-APIC IRQs\n");
1693 * Set up the IO-APIC IRQ routing table.
1696 setup_ioapic_ids_from_mpc();
1698 setup_IO_APIC_irqs();
1699 init_IO_APIC_traps();
1705 struct sysfs_ioapic_data {
1706 struct sys_device dev;
1707 struct IO_APIC_route_entry entry[0];
1709 static struct sysfs_ioapic_data * mp_ioapic_data[MAX_IO_APICS];
1711 static int ioapic_suspend(struct sys_device *dev, u32 state)
1713 struct IO_APIC_route_entry *entry;
1714 struct sysfs_ioapic_data *data;
1715 unsigned long flags;
1718 data = container_of(dev, struct sysfs_ioapic_data, dev);
1719 entry = data->entry;
1720 spin_lock_irqsave(&ioapic_lock, flags);
1721 for (i = 0; i < nr_ioapic_registers[dev->id]; i ++, entry ++ ) {
1722 *(((int *)entry) + 1) = io_apic_read(dev->id, 0x11 + 2 * i);
1723 *(((int *)entry) + 0) = io_apic_read(dev->id, 0x10 + 2 * i);
1725 spin_unlock_irqrestore(&ioapic_lock, flags);
1730 static int ioapic_resume(struct sys_device *dev)
1732 struct IO_APIC_route_entry *entry;
1733 struct sysfs_ioapic_data *data;
1734 unsigned long flags;
1735 union IO_APIC_reg_00 reg_00;
1738 data = container_of(dev, struct sysfs_ioapic_data, dev);
1739 entry = data->entry;
1741 spin_lock_irqsave(&ioapic_lock, flags);
1742 reg_00.raw = io_apic_read(dev->id, 0);
1743 if (reg_00.bits.ID != mp_ioapics[dev->id].mpc_apicid) {
1744 reg_00.bits.ID = mp_ioapics[dev->id].mpc_apicid;
1745 io_apic_write(dev->id, 0, reg_00.raw);
1747 for (i = 0; i < nr_ioapic_registers[dev->id]; i ++, entry ++ ) {
1748 io_apic_write(dev->id, 0x11+2*i, *(((int *)entry)+1));
1749 io_apic_write(dev->id, 0x10+2*i, *(((int *)entry)+0));
1751 spin_unlock_irqrestore(&ioapic_lock, flags);
1756 static struct sysdev_class ioapic_sysdev_class = {
1757 set_kset_name("ioapic"),
1758 .suspend = ioapic_suspend,
1759 .resume = ioapic_resume,
1762 static int __init ioapic_init_sysfs(void)
1764 struct sys_device * dev;
1765 int i, size, error = 0;
1767 error = sysdev_class_register(&ioapic_sysdev_class);
1771 for (i = 0; i < nr_ioapics; i++ ) {
1772 size = sizeof(struct sys_device) + nr_ioapic_registers[i]
1773 * sizeof(struct IO_APIC_route_entry);
1774 mp_ioapic_data[i] = kmalloc(size, GFP_KERNEL);
1775 if (!mp_ioapic_data[i]) {
1776 printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i);
1779 memset(mp_ioapic_data[i], 0, size);
1780 dev = &mp_ioapic_data[i]->dev;
1782 dev->cls = &ioapic_sysdev_class;
1783 error = sysdev_register(dev);
1785 kfree(mp_ioapic_data[i]);
1786 mp_ioapic_data[i] = NULL;
1787 printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i);
1795 device_initcall(ioapic_init_sysfs);
1797 /* --------------------------------------------------------------------------
1798 ACPI-based IOAPIC Configuration
1799 -------------------------------------------------------------------------- */
1801 #ifdef CONFIG_ACPI_BOOT
1803 #define IO_APIC_MAX_ID 0xFE
1805 int __init io_apic_get_unique_id (int ioapic, int apic_id)
1807 union IO_APIC_reg_00 reg_00;
1808 static physid_mask_t apic_id_map;
1809 unsigned long flags;
1813 * The P4 platform supports up to 256 APIC IDs on two separate APIC
1814 * buses (one for LAPICs, one for IOAPICs), where predecessors only
1815 * supports up to 16 on one shared APIC bus.
1817 * TBD: Expand LAPIC/IOAPIC support on P4-class systems to take full
1818 * advantage of new APIC bus architecture.
1821 if (physids_empty(apic_id_map))
1822 apic_id_map = phys_cpu_present_map;
1824 spin_lock_irqsave(&ioapic_lock, flags);
1825 reg_00.raw = io_apic_read(ioapic, 0);
1826 spin_unlock_irqrestore(&ioapic_lock, flags);
1828 if (apic_id >= IO_APIC_MAX_ID) {
1829 apic_printk(APIC_QUIET, KERN_WARNING "IOAPIC[%d]: Invalid apic_id %d, trying "
1830 "%d\n", ioapic, apic_id, reg_00.bits.ID);
1831 apic_id = reg_00.bits.ID;
1835 * Every APIC in a system must have a unique ID or we get lots of nice
1836 * 'stuck on smp_invalidate_needed IPI wait' messages.
1838 if (physid_isset(apic_id, apic_id_map)) {
1840 for (i = 0; i < IO_APIC_MAX_ID; i++) {
1841 if (!physid_isset(i, apic_id_map))
1845 if (i == IO_APIC_MAX_ID)
1846 panic("Max apic_id exceeded!\n");
1848 apic_printk(APIC_VERBOSE, KERN_WARNING "IOAPIC[%d]: apic_id %d already used, "
1849 "trying %d\n", ioapic, apic_id, i);
1854 physid_set(apic_id, apic_id_map);
1856 if (reg_00.bits.ID != apic_id) {
1857 reg_00.bits.ID = apic_id;
1859 spin_lock_irqsave(&ioapic_lock, flags);
1860 io_apic_write(ioapic, 0, reg_00.raw);
1861 reg_00.raw = io_apic_read(ioapic, 0);
1862 spin_unlock_irqrestore(&ioapic_lock, flags);
1865 if (reg_00.bits.ID != apic_id)
1866 panic("IOAPIC[%d]: Unable change apic_id!\n", ioapic);
1869 apic_printk(APIC_VERBOSE,KERN_INFO "IOAPIC[%d]: Assigned apic_id %d\n", ioapic, apic_id);
1875 int __init io_apic_get_version (int ioapic)
1877 union IO_APIC_reg_01 reg_01;
1878 unsigned long flags;
1880 spin_lock_irqsave(&ioapic_lock, flags);
1881 reg_01.raw = io_apic_read(ioapic, 1);
1882 spin_unlock_irqrestore(&ioapic_lock, flags);
1884 return reg_01.bits.version;
1888 int __init io_apic_get_redir_entries (int ioapic)
1890 union IO_APIC_reg_01 reg_01;
1891 unsigned long flags;
1893 spin_lock_irqsave(&ioapic_lock, flags);
1894 reg_01.raw = io_apic_read(ioapic, 1);
1895 spin_unlock_irqrestore(&ioapic_lock, flags);
1897 return reg_01.bits.entries;
1901 int io_apic_set_pci_routing (int ioapic, int pin, int irq, int edge_level, int active_high_low)
1903 struct IO_APIC_route_entry entry;
1904 unsigned long flags;
1906 if (!IO_APIC_IRQ(irq)) {
1907 apic_printk(APIC_QUIET,KERN_ERR "IOAPIC[%d]: Invalid reference to IRQ 0\n",
1913 * Generate a PCI IRQ routing entry and program the IOAPIC accordingly.
1914 * Note that we mask (disable) IRQs now -- these get enabled when the
1915 * corresponding device driver registers for this IRQ.
1918 memset(&entry,0,sizeof(entry));
1920 entry.delivery_mode = INT_DELIVERY_MODE;
1921 entry.dest_mode = INT_DEST_MODE;
1922 entry.dest.logical.logical_dest = cpu_mask_to_apicid(TARGET_CPUS);
1923 entry.trigger = edge_level;
1924 entry.polarity = active_high_low;
1925 entry.mask = 1; /* Disabled (masked) */
1928 * IRQs < 16 are already in the irq_2_pin[] map
1931 add_pin_to_irq(irq, ioapic, pin);
1933 entry.vector = assign_irq_vector(irq);
1935 apic_printk(APIC_VERBOSE,KERN_DEBUG "IOAPIC[%d]: Set PCI routing entry (%d-%d -> 0x%x -> "
1936 "IRQ %d Mode:%i Active:%i)\n", ioapic,
1937 mp_ioapics[ioapic].mpc_apicid, pin, entry.vector, irq,
1938 edge_level, active_high_low);
1940 ioapic_register_intr(irq, entry.vector, edge_level);
1942 if (!ioapic && (irq < 16))
1943 disable_8259A_irq(irq);
1945 spin_lock_irqsave(&ioapic_lock, flags);
1946 io_apic_write(ioapic, 0x11+2*pin, *(((int *)&entry)+1));
1947 io_apic_write(ioapic, 0x10+2*pin, *(((int *)&entry)+0));
1948 spin_unlock_irqrestore(&ioapic_lock, flags);
1953 #endif /*CONFIG_ACPI_BOOT*/
1957 * This function currently is only a helper for the i386 smp boot process where
1958 * we need to reprogram the ioredtbls to cater for the cpus which have come online
1959 * so mask in all cases should simply be TARGET_CPUS
1961 void __init setup_ioapic_dest(void)
1963 int pin, ioapic, irq, irq_entry;
1965 if (skip_ioapic_setup == 1)
1968 for (ioapic = 0; ioapic < nr_ioapics; ioapic++) {
1969 for (pin = 0; pin < nr_ioapic_registers[ioapic]; pin++) {
1970 irq_entry = find_irq_entry(ioapic, pin, mp_INT);
1971 if (irq_entry == -1)
1973 irq = pin_2_irq(irq_entry, ioapic, pin);
1974 set_ioapic_affinity_irq(irq, TARGET_CPUS);