arch/x86_64/kernel/io_apic.c

   1 /*
   2  *      Intel IO-APIC support for multi-Pentium hosts.
   3  *
   4  *      Copyright (C) 1997, 1998, 1999, 2000 Ingo Molnar, Hajnalka Szabo
   5  *
   6  *      Many thanks to Stig Venaas for trying out countless experimental
   7  *      patches and reporting/debugging problems patiently!
   8  *
   9  *      (c) 1999, Multiple IO-APIC support, developed by
  10  *      Ken-ichi Yaku <yaku@css1.kbnes.nec.co.jp> and
  11  *      Hidemi Kishimoto <kisimoto@css1.kbnes.nec.co.jp>,
  12  *      further tested and cleaned up by Zach Brown <zab@redhat.com>
  13  *      and Ingo Molnar <mingo@redhat.com>
  14  *
  15  *      Fixes
  16  *      Maciej W. Rozycki       :       Bits for genuine 82489DX APICs;
  17  *                                      thanks to Eric Gilmore
  18  *                                      and Rolf G. Tews
  19  *                                      for testing these extensively
  20  *      Paul Diefenbaugh        :       Added full ACPI support
  21  */
  22
  23 #include <linux/mm.h>
  24 #include <linux/irq.h>
  25 #include <linux/interrupt.h>
  26 #include <linux/init.h>
  27 #include <linux/delay.h>
  28 #include <linux/sched.h>
  29 #include <linux/config.h>
  30 #include <linux/smp_lock.h>
  31 #include <linux/mc146818rtc.h>
  32 #include <linux/acpi.h>
  33 #include <linux/sysdev.h>
  34
  35 #include <asm/io.h>
  36 #include <asm/smp.h>
  37 #include <asm/desc.h>
  38 #include <asm/proto.h>
  39 #include <asm/mach_apic.h>
  40
  41 #define __apicdebuginit  __init
  42
  43 int sis_apic_bug; /* not actually supported, dummy for compile */
  44
  45 static spinlock_t ioapic_lock = SPIN_LOCK_UNLOCKED;
  46
  47 /*
  48  * # of IRQ routing registers
  49  */
  50 int nr_ioapic_registers[MAX_IO_APICS];
  51
  52 /*
  53  * Rough estimation of how many shared IRQs there are, can
  54  * be changed anytime.
  55  */
  56 #define MAX_PLUS_SHARED_IRQS NR_IRQS
  57 #define PIN_MAP_SIZE (MAX_PLUS_SHARED_IRQS + NR_IRQS)
  58
  59 /*
  60  * This is performance-critical, we want to do it O(1)
  61  *
  62  * the indexing order of this array favors 1:1 mappings
  63  * between pins and IRQs.
  64  */
  65
  66 static struct irq_pin_list {
  67         short apic, pin, next;
  68 } irq_2_pin[PIN_MAP_SIZE];
  69
  70 int vector_irq[NR_VECTORS] = { [0 ... NR_VECTORS - 1] = -1};
  71 #ifdef CONFIG_PCI_MSI
  72 #define vector_to_irq(vector)   \
  73         (platform_legacy_irq(vector) ? vector : vector_irq[vector])
  74 #else
  75 #define vector_to_irq(vector)   (vector)
  76 #endif
  77
  78 /*
  79  * The common case is 1:1 IRQ<->pin mappings. Sometimes there are
  80  * shared ISA-space IRQs, so we have to support them. We are super
  81  * fast in the common case, and fast for shared ISA-space IRQs.
  82  */
  83 static void add_pin_to_irq(unsigned int irq, int apic, int pin)
  84 {
  85         static int first_free_entry = NR_IRQS;
  86         struct irq_pin_list *entry = irq_2_pin + irq;
  87
  88         while (entry->next)
  89                 entry = irq_2_pin + entry->next;
  90
  91         if (entry->pin != -1) {
  92                 entry->next = first_free_entry;
  93                 entry = irq_2_pin + entry->next;
  94                 if (++first_free_entry >= PIN_MAP_SIZE)
  95                         panic("io_apic.c: whoops");
  96         }
  97         entry->apic = apic;
  98         entry->pin = pin;
  99 }
 100
 101 #define __DO_ACTION(R, ACTION, FINAL)                                   \
 102                                                                         \
 103 {                                                                       \
 104         int pin;                                                        \
 105         struct irq_pin_list *entry = irq_2_pin + irq;                   \
 106                                                                         \
 107         for (;;) {                                                      \
 108                 unsigned int reg;                                       \
 109                 pin = entry->pin;                                       \
 110                 if (pin == -1)                                          \
 111                         break;                                          \
 112                 reg = io_apic_read(entry->apic, 0x10 + R + pin*2);      \
 113                 reg ACTION;                                             \
 114                 io_apic_modify(entry->apic, reg);                       \
 115                 if (!entry->next)                                       \
 116                         break;                                          \
 117                 entry = irq_2_pin + entry->next;                        \
 118         }                                                               \
 119         FINAL;                                                          \
 120 }
 121
 122 #define DO_ACTION(name,R,ACTION, FINAL)                                 \
 123                                                                         \
 124         static void name##_IO_APIC_irq (unsigned int irq)               \
 125         __DO_ACTION(R, ACTION, FINAL)
 126
 127 DO_ACTION( __mask,             0, |= 0x00010000, io_apic_sync(entry->apic) )
 128                                                 /* mask = 1 */
 129 DO_ACTION( __unmask,           0, &= 0xfffeffff, )
 130                                                 /* mask = 0 */
 131
 132 static void mask_IO_APIC_irq (unsigned int irq)
 133 {
 134         unsigned long flags;
 135
 136         spin_lock_irqsave(&ioapic_lock, flags);
 137         __mask_IO_APIC_irq(irq);
 138         spin_unlock_irqrestore(&ioapic_lock, flags);
 139 }
 140
 141 static void unmask_IO_APIC_irq (unsigned int irq)
 142 {
 143         unsigned long flags;
 144
 145         spin_lock_irqsave(&ioapic_lock, flags);
 146         __unmask_IO_APIC_irq(irq);
 147         spin_unlock_irqrestore(&ioapic_lock, flags);
 148 }
 149
 150 void clear_IO_APIC_pin(unsigned int apic, unsigned int pin)
 151 {
 152         struct IO_APIC_route_entry entry;
 153         unsigned long flags;
 154
 155         /* Check delivery_mode to be sure we're not clearing an SMI pin */
 156         spin_lock_irqsave(&ioapic_lock, flags);
 157         *(((int*)&entry) + 0) = io_apic_read(apic, 0x10 + 2 * pin);
 158         *(((int*)&entry) + 1) = io_apic_read(apic, 0x11 + 2 * pin);
 159         spin_unlock_irqrestore(&ioapic_lock, flags);
 160         if (entry.delivery_mode == dest_SMI)
 161                 return;
 162         /*
 163          * Disable it in the IO-APIC irq-routing table:
 164          */
 165         memset(&entry, 0, sizeof(entry));
 166         entry.mask = 1;
 167         spin_lock_irqsave(&ioapic_lock, flags);
 168         io_apic_write(apic, 0x10 + 2 * pin, *(((int *)&entry) + 0));
 169         io_apic_write(apic, 0x11 + 2 * pin, *(((int *)&entry) + 1));
 170         spin_unlock_irqrestore(&ioapic_lock, flags);
 171 }
 172
 173 static void clear_IO_APIC (void)
 174 {
 175         int apic, pin;
 176
 177         for (apic = 0; apic < nr_ioapics; apic++)
 178                 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++)
 179                         clear_IO_APIC_pin(apic, pin);
 180 }
 181
 182 /*
 183  * support for broken MP BIOSs, enables hand-redirection of PIRQ0-7 to
 184  * specific CPU-side IRQs.
 185  */
 186
 187 #define MAX_PIRQS 8
 188 int pirq_entries [MAX_PIRQS];
 189 int pirqs_enabled;
 190 int skip_ioapic_setup;
 191 int ioapic_force;
 192
 193 /* dummy parsing: see setup.c */
 194
 195 static int __init disable_ioapic_setup(char *str)
 196 {
 197         skip_ioapic_setup = 1;
 198         return 1;
 199 }
 200
 201 static int __init enable_ioapic_setup(char *str)
 202 {
 203         ioapic_force = 1;
 204         skip_ioapic_setup = 0;
 205         return 1;
 206 }
 207
 208 __setup("noapic", disable_ioapic_setup);
 209 __setup("apic", enable_ioapic_setup);
 210
 211 #include <asm/pci-direct.h>
 212 #include <linux/pci_ids.h>
 213 #include <linux/pci.h>
 214
 215 /* Temporary Hack. Nvidia and VIA boards currently only work with IO-APIC
 216    off. Check for an Nvidia or VIA PCI bridge and turn it off.
 217    Use pci direct infrastructure because this runs before the PCI subsystem.
 218
 219    Can be overwritten with "apic"
 220
 221    And another hack to disable the IOMMU on VIA chipsets.
 222
 223    Kludge-O-Rama. */
 224 void __init check_ioapic(void)
 225 {
 226         int num,slot,func;
 227         if (ioapic_force)
 228                 return;
 229
 230         /* Poor man's PCI discovery */
 231         for (num = 0; num < 32; num++) {
 232                 for (slot = 0; slot < 32; slot++) {
 233                         for (func = 0; func < 8; func++) {
 234                                 u32 class;
 235                                 u32 vendor;
 236                                 u8 type;
 237                                 class = read_pci_config(num,slot,func,
 238                                                         PCI_CLASS_REVISION);
 239                                 if (class == 0xffffffff)
 240                                         break;
 241
 242                                 if ((class >> 16) != PCI_CLASS_BRIDGE_PCI)
 243                                         continue;
 244
 245                                 vendor = read_pci_config(num, slot, func,
 246                                                          PCI_VENDOR_ID);
 247                                 vendor &= 0xffff;
 248                                 switch (vendor) {
 249                                 case PCI_VENDOR_ID_VIA:
 250 #ifdef CONFIG_GART_IOMMU
 251                                         if ((end_pfn >= (0xffffffff>>PAGE_SHIFT) ||
 252                                              force_iommu) &&
 253                                             !iommu_aperture_allowed) {
 254                                                 printk(KERN_INFO
 255     "Looks like a VIA chipset. Disabling IOMMU. Overwrite with \"iommu=allowed\"\n");
 256                                                 iommu_aperture_disabled = 1;
 257                                         }
 258 #endif
 259                                         return;
 260                                 case PCI_VENDOR_ID_NVIDIA:
 261 #ifdef CONFIG_ACPI
 262                                         /* All timer overrides on Nvidia
 263                                            seem to be wrong. Skip them. */
 264                                         acpi_skip_timer_override = 1;
 265                                         printk(KERN_INFO
 266              "Nvidia board detected. Ignoring ACPI timer override.\n");
 267 #endif
 268                                         /* RED-PEN skip them on mptables too? */
 269                                         return;
 270                                 }
 271
 272                                 /* No multi-function device? */
 273                                 type = read_pci_config_byte(num,slot,func,
 274                                                             PCI_HEADER_TYPE);
 275                                 if (!(type & 0x80))
 276                                         break;
 277                         }
 278                 }
 279         }
 280 }
 281
 282 static int __init ioapic_pirq_setup(char *str)
 283 {
 284         int i, max;
 285         int ints[MAX_PIRQS+1];
 286
 287         get_options(str, ARRAY_SIZE(ints), ints);
 288
 289         for (i = 0; i < MAX_PIRQS; i++)
 290                 pirq_entries[i] = -1;
 291
 292         pirqs_enabled = 1;
 293         apic_printk(APIC_VERBOSE, "PIRQ redirection, working around broken MP-BIOS.\n");
 294         max = MAX_PIRQS;
 295         if (ints[0] < MAX_PIRQS)
 296                 max = ints[0];
 297
 298         for (i = 0; i < max; i++) {
 299                 apic_printk(APIC_VERBOSE, "... PIRQ%d -> IRQ %d\n", i, ints[i+1]);
 300                 /*
 301                  * PIRQs are mapped upside down, usually.
 302                  */
 303                 pirq_entries[MAX_PIRQS-i-1] = ints[i+1];
 304         }
 305         return 1;
 306 }
 307
 308 __setup("pirq=", ioapic_pirq_setup);
 309
 310 /*
 311  * Find the IRQ entry number of a certain pin.
 312  */
 313 static int find_irq_entry(int apic, int pin, int type)
 314 {
 315         int i;
 316
 317         for (i = 0; i < mp_irq_entries; i++)
 318                 if (mp_irqs[i].mpc_irqtype == type &&
 319                     (mp_irqs[i].mpc_dstapic == mp_ioapics[apic].mpc_apicid ||
 320                      mp_irqs[i].mpc_dstapic == MP_APIC_ALL) &&
 321                     mp_irqs[i].mpc_dstirq == pin)
 322                         return i;
 323
 324         return -1;
 325 }
 326
 327 /*
 328  * Find the pin to which IRQ[irq] (ISA) is connected
 329  */
 330 static int __init find_isa_irq_pin(int irq, int type)
 331 {
 332         int i;
 333
 334         for (i = 0; i < mp_irq_entries; i++) {
 335                 int lbus = mp_irqs[i].mpc_srcbus;
 336
 337                 if ((mp_bus_id_to_type[lbus] == MP_BUS_ISA ||
 338                      mp_bus_id_to_type[lbus] == MP_BUS_EISA ||
 339                      mp_bus_id_to_type[lbus] == MP_BUS_MCA) &&
 340                     (mp_irqs[i].mpc_irqtype == type) &&
 341                     (mp_irqs[i].mpc_srcbusirq == irq))
 342
 343                         return mp_irqs[i].mpc_dstirq;
 344         }
 345         return -1;
 346 }
 347
 348 /*
 349  * Find a specific PCI IRQ entry.
 350  * Not an __init, possibly needed by modules
 351  */
 352 static int pin_2_irq(int idx, int apic, int pin);
 353
 354 int IO_APIC_get_PCI_irq_vector(int bus, int slot, int pin)
 355 {
 356         int apic, i, best_guess = -1;
 357
 358         apic_printk(APIC_DEBUG, "querying PCI -> IRQ mapping bus:%d, slot:%d, pin:%d.\n",
 359                 bus, slot, pin);
 360         if (mp_bus_id_to_pci_bus[bus] == -1) {
 361                 apic_printk(APIC_VERBOSE, "PCI BIOS passed nonexistent PCI bus %d!\n", bus);
 362                 return -1;
 363         }
 364         for (i = 0; i < mp_irq_entries; i++) {
 365                 int lbus = mp_irqs[i].mpc_srcbus;
 366
 367                 for (apic = 0; apic < nr_ioapics; apic++)
 368                         if (mp_ioapics[apic].mpc_apicid == mp_irqs[i].mpc_dstapic ||
 369                             mp_irqs[i].mpc_dstapic == MP_APIC_ALL)
 370                                 break;
 371
 372                 if ((mp_bus_id_to_type[lbus] == MP_BUS_PCI) &&
 373                     !mp_irqs[i].mpc_irqtype &&
 374                     (bus == lbus) &&
 375                     (slot == ((mp_irqs[i].mpc_srcbusirq >> 2) & 0x1f))) {
 376                         int irq = pin_2_irq(i,apic,mp_irqs[i].mpc_dstirq);
 377
 378                         if (!(apic || IO_APIC_IRQ(irq)))
 379                                 continue;
 380
 381                         if (pin == (mp_irqs[i].mpc_srcbusirq & 3))
 382                                 return irq;
 383                         /*
 384                          * Use the first all-but-pin matching entry as a
 385                          * best-guess fuzzy result for broken mptables.
 386                          */
 387                         if (best_guess < 0)
 388                                 best_guess = irq;
 389                 }
 390         }
 391         return best_guess;
 392 }
 393
 394 /*
 395  * EISA Edge/Level control register, ELCR
 396  */
 397 static int EISA_ELCR(unsigned int irq)
 398 {
 399         if (irq < 16) {
 400                 unsigned int port = 0x4d0 + (irq >> 3);
 401                 return (inb(port) >> (irq & 7)) & 1;
 402         }
 403         apic_printk(APIC_VERBOSE, "Broken MPtable reports ISA irq %d\n", irq);
 404         return 0;
 405 }
 406
 407 /* EISA interrupts are always polarity zero and can be edge or level
 408  * trigger depending on the ELCR value.  If an interrupt is listed as
 409  * EISA conforming in the MP table, that means its trigger type must
 410  * be read in from the ELCR */
 411
 412 #define default_EISA_trigger(idx)       (EISA_ELCR(mp_irqs[idx].mpc_srcbusirq))
 413 #define default_EISA_polarity(idx)      (0)
 414
 415 /* ISA interrupts are always polarity zero edge triggered,
 416  * when listed as conforming in the MP table. */
 417
 418 #define default_ISA_trigger(idx)        (0)
 419 #define default_ISA_polarity(idx)       (0)
 420
 421 /* PCI interrupts are always polarity one level triggered,
 422  * when listed as conforming in the MP table. */
 423
 424 #define default_PCI_trigger(idx)        (1)
 425 #define default_PCI_polarity(idx)       (1)
 426
 427 /* MCA interrupts are always polarity zero level triggered,
 428  * when listed as conforming in the MP table. */
 429
 430 #define default_MCA_trigger(idx)        (1)
 431 #define default_MCA_polarity(idx)       (0)
 432
 433 static int __init MPBIOS_polarity(int idx)
 434 {
 435         int bus = mp_irqs[idx].mpc_srcbus;
 436         int polarity;
 437
 438         /*
 439          * Determine IRQ line polarity (high active or low active):
 440          */
 441         switch (mp_irqs[idx].mpc_irqflag & 3)
 442         {
 443                 case 0: /* conforms, ie. bus-type dependent polarity */
 444                 {
 445                         switch (mp_bus_id_to_type[bus])
 446                         {
 447                                 case MP_BUS_ISA: /* ISA pin */
 448                                 {
 449                                         polarity = default_ISA_polarity(idx);
 450                                         break;
 451                                 }
 452                                 case MP_BUS_EISA: /* EISA pin */
 453                                 {
 454                                         polarity = default_EISA_polarity(idx);
 455                                         break;
 456                                 }
 457                                 case MP_BUS_PCI: /* PCI pin */
 458                                 {
 459                                         polarity = default_PCI_polarity(idx);
 460                                         break;
 461                                 }
 462                                 case MP_BUS_MCA: /* MCA pin */
 463                                 {
 464                                         polarity = default_MCA_polarity(idx);
 465                                         break;
 466                                 }
 467                                 default:
 468                                 {
 469                                         printk(KERN_WARNING "broken BIOS!!\n");
 470                                         polarity = 1;
 471                                         break;
 472                                 }
 473                         }
 474                         break;
 475                 }
 476                 case 1: /* high active */
 477                 {
 478                         polarity = 0;
 479                         break;
 480                 }
 481                 case 2: /* reserved */
 482                 {
 483                         printk(KERN_WARNING "broken BIOS!!\n");
 484                         polarity = 1;
 485                         break;
 486                 }
 487                 case 3: /* low active */
 488                 {
 489                         polarity = 1;
 490                         break;
 491                 }
 492                 default: /* invalid */
 493                 {
 494                         printk(KERN_WARNING "broken BIOS!!\n");
 495                         polarity = 1;
 496                         break;
 497                 }
 498         }
 499         return polarity;
 500 }
 501
 502 static int MPBIOS_trigger(int idx)
 503 {
 504         int bus = mp_irqs[idx].mpc_srcbus;
 505         int trigger;
 506
 507         /*
 508          * Determine IRQ trigger mode (edge or level sensitive):
 509          */
 510         switch ((mp_irqs[idx].mpc_irqflag>>2) & 3)
 511         {
 512                 case 0: /* conforms, ie. bus-type dependent */
 513                 {
 514                         switch (mp_bus_id_to_type[bus])
 515                         {
 516                                 case MP_BUS_ISA: /* ISA pin */
 517                                 {
 518                                         trigger = default_ISA_trigger(idx);
 519                                         break;
 520                                 }
 521                                 case MP_BUS_EISA: /* EISA pin */
 522                                 {
 523                                         trigger = default_EISA_trigger(idx);
 524                                         break;
 525                                 }
 526                                 case MP_BUS_PCI: /* PCI pin */
 527                                 {
 528                                         trigger = default_PCI_trigger(idx);
 529                                         break;
 530                                 }
 531                                 case MP_BUS_MCA: /* MCA pin */
 532                                 {
 533                                         trigger = default_MCA_trigger(idx);
 534                                         break;
 535                                 }
 536                                 default:
 537                                 {
 538                                         printk(KERN_WARNING "broken BIOS!!\n");
 539                                         trigger = 1;
 540                                         break;
 541                                 }
 542                         }
 543                         break;
 544                 }
 545                 case 1: /* edge */
 546                 {
 547                         trigger = 0;
 548                         break;
 549                 }
 550                 case 2: /* reserved */
 551                 {
 552                         printk(KERN_WARNING "broken BIOS!!\n");
 553                         trigger = 1;
 554                         break;
 555                 }
 556                 case 3: /* level */
 557                 {
 558                         trigger = 1;
 559                         break;
 560                 }
 561                 default: /* invalid */
 562                 {
 563                         printk(KERN_WARNING "broken BIOS!!\n");
 564                         trigger = 0;
 565                         break;
 566                 }
 567         }
 568         return trigger;
 569 }
 570
 571 static inline int irq_polarity(int idx)
 572 {
 573         return MPBIOS_polarity(idx);
 574 }
 575
 576 static inline int irq_trigger(int idx)
 577 {
 578         return MPBIOS_trigger(idx);
 579 }
 580
 581 static int pin_2_irq(int idx, int apic, int pin)
 582 {
 583         int irq, i;
 584         int bus = mp_irqs[idx].mpc_srcbus;
 585
 586         /*
 587          * Debugging check, we are in big trouble if this message pops up!
 588          */
 589         if (mp_irqs[idx].mpc_dstirq != pin)
 590                 printk(KERN_ERR "broken BIOS or MPTABLE parser, ayiee!!\n");
 591
 592         switch (mp_bus_id_to_type[bus])
 593         {
 594                 case MP_BUS_ISA: /* ISA pin */
 595                 case MP_BUS_EISA:
 596                 case MP_BUS_MCA:
 597                 {
 598                         irq = mp_irqs[idx].mpc_srcbusirq;
 599                         break;
 600                 }
 601                 case MP_BUS_PCI: /* PCI pin */
 602                 {
 603                         /*
 604                          * PCI IRQs are mapped in order
 605                          */
 606                         i = irq = 0;
 607                         while (i < apic)
 608                                 irq += nr_ioapic_registers[i++];
 609                         irq += pin;
 610                         break;
 611                 }
 612                 default:
 613                 {
 614                         printk(KERN_ERR "unknown bus type %d.\n",bus);
 615                         irq = 0;
 616                         break;
 617                 }
 618         }
 619
 620         /*
 621          * PCI IRQ command line redirection. Yes, limits are hardcoded.
 622          */
 623         if ((pin >= 16) && (pin <= 23)) {
 624                 if (pirq_entries[pin-16] != -1) {
 625                         if (!pirq_entries[pin-16]) {
 626                                 apic_printk(APIC_VERBOSE, "disabling PIRQ%d\n", pin-16);
 627                         } else {
 628                                 irq = pirq_entries[pin-16];
 629                                 apic_printk(APIC_VERBOSE, "using PIRQ%d -> IRQ %d\n",
 630                                                 pin-16, irq);
 631                         }
 632                 }
 633         }
 634         return irq;
 635 }
 636
 637 static inline int IO_APIC_irq_trigger(int irq)
 638 {
 639         int apic, idx, pin;
 640
 641         for (apic = 0; apic < nr_ioapics; apic++) {
 642                 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
 643                         idx = find_irq_entry(apic,pin,mp_INT);
 644                         if ((idx != -1) && (irq == pin_2_irq(idx,apic,pin)))
 645                                 return irq_trigger(idx);
 646                 }
 647         }
 648         /*
 649          * nonexistent IRQs are edge default
 650          */
 651         return 0;
 652 }
 653
 654 /* irq_vectors is indexed by the sum of all RTEs in all I/O APICs. */
 655 u8 irq_vector[NR_IRQ_VECTORS] = { FIRST_DEVICE_VECTOR , 0 };
 656
 657 int assign_irq_vector(int irq)
 658 {
 659         static int current_vector = FIRST_DEVICE_VECTOR, offset = 0;
 660
 661         BUG_ON(irq >= NR_IRQ_VECTORS);
 662         if (IO_APIC_VECTOR(irq) > 0)
 663                 return IO_APIC_VECTOR(irq);
 664 next:
 665         current_vector += 8;
 666         if (current_vector == IA32_SYSCALL_VECTOR)
 667                 goto next;
 668
 669         if (current_vector >= FIRST_SYSTEM_VECTOR) {
 670                 offset++;
 671                 if (!(offset%8))
 672                         return -ENOSPC;
 673                 current_vector = FIRST_DEVICE_VECTOR + offset;
 674         }
 675
 676         vector_irq[current_vector] = irq;
 677         if (irq != AUTO_ASSIGN)
 678                 IO_APIC_VECTOR(irq) = current_vector;
 679
 680         return current_vector;
 681 }
 682
 683 extern void (*interrupt[NR_IRQS])(void);
 684 static struct hw_interrupt_type ioapic_level_type;
 685 static struct hw_interrupt_type ioapic_edge_type;
 686
 687 #define IOAPIC_AUTO     -1
 688 #define IOAPIC_EDGE     0
 689 #define IOAPIC_LEVEL    1
 690
 691 static inline void ioapic_register_intr(int irq, int vector, unsigned long trigger)
 692 {
 693         if (use_pci_vector() && !platform_legacy_irq(irq)) {
 694                 if ((trigger == IOAPIC_AUTO && IO_APIC_irq_trigger(irq)) ||
 695                                 trigger == IOAPIC_LEVEL)
 696                         irq_desc[vector].handler = &ioapic_level_type;
 697                 else
 698                         irq_desc[vector].handler = &ioapic_edge_type;
 699                 set_intr_gate(vector, interrupt[vector]);
 700         } else  {
 701                 if ((trigger == IOAPIC_AUTO && IO_APIC_irq_trigger(irq)) ||
 702                                 trigger == IOAPIC_LEVEL)
 703                         irq_desc[irq].handler = &ioapic_level_type;
 704                 else
 705                         irq_desc[irq].handler = &ioapic_edge_type;
 706                 set_intr_gate(vector, interrupt[irq]);
 707         }
 708 }
 709
 710 void __init setup_IO_APIC_irqs(void)
 711 {
 712         struct IO_APIC_route_entry entry;
 713         int apic, pin, idx, irq, first_notcon = 1, vector;
 714         unsigned long flags;
 715
 716         apic_printk(APIC_VERBOSE, KERN_DEBUG "init IO_APIC IRQs\n");
 717
 718         for (apic = 0; apic < nr_ioapics; apic++) {
 719         for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
 720
 721                 /*
 722                  * add it to the IO-APIC irq-routing table:
 723                  */
 724                 memset(&entry,0,sizeof(entry));
 725
 726                 entry.delivery_mode = INT_DELIVERY_MODE;
 727                 entry.dest_mode = INT_DEST_MODE;
 728                 entry.mask = 0;                         /* enable IRQ */
 729                 entry.dest.logical.logical_dest = cpu_mask_to_apicid(TARGET_CPUS);
 730
 731                 idx = find_irq_entry(apic,pin,mp_INT);
 732                 if (idx == -1) {
 733                         if (first_notcon) {
 734                                 apic_printk(APIC_VERBOSE, KERN_DEBUG " IO-APIC (apicid-pin) %d-%d", mp_ioapics[apic].mpc_apicid, pin);
 735                                 first_notcon = 0;
 736                         } else
 737                                 apic_printk(APIC_VERBOSE, ", %d-%d", mp_ioapics[apic].mpc_apicid, pin);
 738                         continue;
 739                 }
 740
 741                 entry.trigger = irq_trigger(idx);
 742                 entry.polarity = irq_polarity(idx);
 743
 744                 if (irq_trigger(idx)) {
 745                         entry.trigger = 1;
 746                         entry.mask = 1;
 747                         entry.dest.logical.logical_dest = cpu_mask_to_apicid(TARGET_CPUS);
 748                 }
 749
 750                 irq = pin_2_irq(idx, apic, pin);
 751                 add_pin_to_irq(irq, apic, pin);
 752
 753                 if (!apic && !IO_APIC_IRQ(irq))
 754                         continue;
 755
 756                 if (IO_APIC_IRQ(irq)) {
 757                         vector = assign_irq_vector(irq);
 758                         entry.vector = vector;
 759
 760                         ioapic_register_intr(irq, vector, IOAPIC_AUTO);
 761                         if (!apic && (irq < 16))
 762                                 disable_8259A_irq(irq);
 763                 }
 764                 spin_lock_irqsave(&ioapic_lock, flags);
 765                 io_apic_write(apic, 0x11+2*pin, *(((int *)&entry)+1));
 766                 io_apic_write(apic, 0x10+2*pin, *(((int *)&entry)+0));
 767                 spin_unlock_irqrestore(&ioapic_lock, flags);
 768         }
 769         }
 770
 771         if (!first_notcon)
 772                 apic_printk(APIC_VERBOSE," not connected.\n");
 773 }
 774
 775 /*
 776  * Set up the 8259A-master output pin as broadcast to all
 777  * CPUs.
 778  */
 779 void __init setup_ExtINT_IRQ0_pin(unsigned int pin, int vector)
 780 {
 781         struct IO_APIC_route_entry entry;
 782         unsigned long flags;
 783
 784         memset(&entry,0,sizeof(entry));
 785
 786         disable_8259A_irq(0);
 787
 788         /* mask LVT0 */
 789         apic_write_around(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT);
 790
 791         /*
 792          * We use logical delivery to get the timer IRQ
 793          * to the first CPU.
 794          */
 795         entry.dest_mode = INT_DEST_MODE;
 796         entry.mask = 0;                                 /* unmask IRQ now */
 797         entry.dest.logical.logical_dest = cpu_mask_to_apicid(TARGET_CPUS);
 798         entry.delivery_mode = INT_DELIVERY_MODE;
 799         entry.polarity = 0;
 800         entry.trigger = 0;
 801         entry.vector = vector;
 802
 803         /*
 804          * The timer IRQ doesn't have to know that behind the
 805          * scene we have a 8259A-master in AEOI mode ...
 806          */
 807         irq_desc[0].handler = &ioapic_edge_type;
 808
 809         /*
 810          * Add it to the IO-APIC irq-routing table:
 811          */
 812         spin_lock_irqsave(&ioapic_lock, flags);
 813         io_apic_write(0, 0x11+2*pin, *(((int *)&entry)+1));
 814         io_apic_write(0, 0x10+2*pin, *(((int *)&entry)+0));
 815         spin_unlock_irqrestore(&ioapic_lock, flags);
 816
 817         enable_8259A_irq(0);
 818 }
 819
 820 void __init UNEXPECTED_IO_APIC(void)
 821 {
 822 }
 823
 824 void __apicdebuginit print_IO_APIC(void)
 825 {
 826         int apic, i;
 827         union IO_APIC_reg_00 reg_00;
 828         union IO_APIC_reg_01 reg_01;
 829         union IO_APIC_reg_02 reg_02;
 830         unsigned long flags;
 831
 832         if (apic_verbosity == APIC_QUIET)
 833                 return;
 834
 835         printk(KERN_DEBUG "number of MP IRQ sources: %d.\n", mp_irq_entries);
 836         for (i = 0; i < nr_ioapics; i++)
 837                 printk(KERN_DEBUG "number of IO-APIC #%d registers: %d.\n",
 838                        mp_ioapics[i].mpc_apicid, nr_ioapic_registers[i]);
 839
 840         /*
 841          * We are a bit conservative about what we expect.  We have to
 842          * know about every hardware change ASAP.
 843          */
 844         printk(KERN_INFO "testing the IO APIC.......................\n");
 845
 846         for (apic = 0; apic < nr_ioapics; apic++) {
 847
 848         spin_lock_irqsave(&ioapic_lock, flags);
 849         reg_00.raw = io_apic_read(apic, 0);
 850         reg_01.raw = io_apic_read(apic, 1);
 851         if (reg_01.bits.version >= 0x10)
 852                 reg_02.raw = io_apic_read(apic, 2);
 853         spin_unlock_irqrestore(&ioapic_lock, flags);
 854
 855         printk("\n");
 856         printk(KERN_DEBUG "IO APIC #%d......\n", mp_ioapics[apic].mpc_apicid);
 857         printk(KERN_DEBUG ".... register #00: %08X\n", reg_00.raw);
 858         printk(KERN_DEBUG ".......    : physical APIC id: %02X\n", reg_00.bits.ID);
 859         if (reg_00.bits.__reserved_1 || reg_00.bits.__reserved_2)
 860                 UNEXPECTED_IO_APIC();
 861
 862         printk(KERN_DEBUG ".... register #01: %08X\n", *(int *)&reg_01);
 863         printk(KERN_DEBUG ".......     : max redirection entries: %04X\n", reg_01.bits.entries);
 864         if (    (reg_01.bits.entries != 0x0f) && /* older (Neptune) boards */
 865                 (reg_01.bits.entries != 0x17) && /* typical ISA+PCI boards */
 866                 (reg_01.bits.entries != 0x1b) && /* Compaq Proliant boards */
 867                 (reg_01.bits.entries != 0x1f) && /* dual Xeon boards */
 868                 (reg_01.bits.entries != 0x22) && /* bigger Xeon boards */
 869                 (reg_01.bits.entries != 0x2E) &&
 870                 (reg_01.bits.entries != 0x3F) &&
 871                 (reg_01.bits.entries != 0x03)
 872         )
 873                 UNEXPECTED_IO_APIC();
 874
 875         printk(KERN_DEBUG ".......     : PRQ implemented: %X\n", reg_01.bits.PRQ);
 876         printk(KERN_DEBUG ".......     : IO APIC version: %04X\n", reg_01.bits.version);
 877         if (    (reg_01.bits.version != 0x01) && /* 82489DX IO-APICs */
 878                 (reg_01.bits.version != 0x02) && /* 82801BA IO-APICs (ICH2) */
 879                 (reg_01.bits.version != 0x10) && /* oldest IO-APICs */
 880                 (reg_01.bits.version != 0x11) && /* Pentium/Pro IO-APICs */
 881                 (reg_01.bits.version != 0x13) && /* Xeon IO-APICs */
 882                 (reg_01.bits.version != 0x20)    /* Intel P64H (82806 AA) */
 883         )
 884                 UNEXPECTED_IO_APIC();
 885         if (reg_01.bits.__reserved_1 || reg_01.bits.__reserved_2)
 886                 UNEXPECTED_IO_APIC();
 887
 888         if (reg_01.bits.version >= 0x10) {
 889                 printk(KERN_DEBUG ".... register #02: %08X\n", reg_02.raw);
 890                 printk(KERN_DEBUG ".......     : arbitration: %02X\n", reg_02.bits.arbitration);
 891                 if (reg_02.bits.__reserved_1 || reg_02.bits.__reserved_2)
 892                         UNEXPECTED_IO_APIC();
 893         }
 894
 895         printk(KERN_DEBUG ".... IRQ redirection table:\n");
 896
 897         printk(KERN_DEBUG " NR Log Phy Mask Trig IRR Pol"
 898                           " Stat Dest Deli Vect:   \n");
 899
 900         for (i = 0; i <= reg_01.bits.entries; i++) {
 901                 struct IO_APIC_route_entry entry;
 902
 903                 spin_lock_irqsave(&ioapic_lock, flags);
 904                 *(((int *)&entry)+0) = io_apic_read(apic, 0x10+i*2);
 905                 *(((int *)&entry)+1) = io_apic_read(apic, 0x11+i*2);
 906                 spin_unlock_irqrestore(&ioapic_lock, flags);
 907
 908                 printk(KERN_DEBUG " %02x %03X %02X  ",
 909                         i,
 910                         entry.dest.logical.logical_dest,
 911                         entry.dest.physical.physical_dest
 912                 );
 913
 914                 printk("%1d    %1d    %1d   %1d   %1d    %1d    %1d    %02X\n",
 915                         entry.mask,
 916                         entry.trigger,
 917                         entry.irr,
 918                         entry.polarity,
 919                         entry.delivery_status,
 920                         entry.dest_mode,
 921                         entry.delivery_mode,
 922                         entry.vector
 923                 );
 924         }
 925         }
 926         if (use_pci_vector())
 927                 printk(KERN_INFO "Using vector-based indexing\n");
 928         printk(KERN_DEBUG "IRQ to pin mappings:\n");
 929         for (i = 0; i < NR_IRQS; i++) {
 930                 struct irq_pin_list *entry = irq_2_pin + i;
 931                 if (entry->pin < 0)
 932                         continue;
 933                 if (use_pci_vector() && !platform_legacy_irq(i))
 934                         printk(KERN_DEBUG "IRQ%d ", IO_APIC_VECTOR(i));
 935                 else
 936                         printk(KERN_DEBUG "IRQ%d ", i);
 937                 for (;;) {
 938                         printk("-> %d:%d", entry->apic, entry->pin);
 939                         if (!entry->next)
 940                                 break;
 941                         entry = irq_2_pin + entry->next;
 942                 }
 943                 printk("\n");
 944         }
 945
 946         printk(KERN_INFO ".................................... done.\n");
 947
 948         return;
 949 }
 950
 951 static __apicdebuginit void print_APIC_bitfield (int base)
 952 {
 953         unsigned int v;
 954         int i, j;
 955
 956         if (apic_verbosity == APIC_QUIET)
 957                 return;
 958
 959         printk(KERN_DEBUG "0123456789abcdef0123456789abcdef\n" KERN_DEBUG);
 960         for (i = 0; i < 8; i++) {
 961                 v = apic_read(base + i*0x10);
 962                 for (j = 0; j < 32; j++) {
 963                         if (v & (1<<j))
 964                                 printk("1");
 965                         else
 966                                 printk("0");
 967                 }
 968                 printk("\n");
 969         }
 970 }
 971
 972 void __apicdebuginit print_local_APIC(void * dummy)
 973 {
 974         unsigned int v, ver, maxlvt;
 975
 976         if (apic_verbosity == APIC_QUIET)
 977                 return;
 978
 979         printk("\n" KERN_DEBUG "printing local APIC contents on CPU#%d/%d:\n",
 980                 smp_processor_id(), hard_smp_processor_id());
 981         v = apic_read(APIC_ID);
 982         printk(KERN_INFO "... APIC ID:      %08x (%01x)\n", v, GET_APIC_ID(v));
 983         v = apic_read(APIC_LVR);
 984         printk(KERN_INFO "... APIC VERSION: %08x\n", v);
 985         ver = GET_APIC_VERSION(v);
 986         maxlvt = get_maxlvt();
 987
 988         v = apic_read(APIC_TASKPRI);
 989         printk(KERN_DEBUG "... APIC TASKPRI: %08x (%02x)\n", v, v & APIC_TPRI_MASK);
 990
 991         if (APIC_INTEGRATED(ver)) {                     /* !82489DX */
 992                 v = apic_read(APIC_ARBPRI);
 993                 printk(KERN_DEBUG "... APIC ARBPRI: %08x (%02x)\n", v,
 994                         v & APIC_ARBPRI_MASK);
 995                 v = apic_read(APIC_PROCPRI);
 996                 printk(KERN_DEBUG "... APIC PROCPRI: %08x\n", v);
 997         }
 998
 999         v = apic_read(APIC_EOI);
1000         printk(KERN_DEBUG "... APIC EOI: %08x\n", v);
1001         v = apic_read(APIC_RRR);
1002         printk(KERN_DEBUG "... APIC RRR: %08x\n", v);
1003         v = apic_read(APIC_LDR);
1004         printk(KERN_DEBUG "... APIC LDR: %08x\n", v);
1005         v = apic_read(APIC_DFR);
1006         printk(KERN_DEBUG "... APIC DFR: %08x\n", v);
1007         v = apic_read(APIC_SPIV);
1008         printk(KERN_DEBUG "... APIC SPIV: %08x\n", v);
1009
1010         printk(KERN_DEBUG "... APIC ISR field:\n");
1011         print_APIC_bitfield(APIC_ISR);
1012         printk(KERN_DEBUG "... APIC TMR field:\n");
1013         print_APIC_bitfield(APIC_TMR);
1014         printk(KERN_DEBUG "... APIC IRR field:\n");
1015         print_APIC_bitfield(APIC_IRR);
1016
1017         if (APIC_INTEGRATED(ver)) {             /* !82489DX */
1018                 if (maxlvt > 3)         /* Due to the Pentium erratum 3AP. */
1019                         apic_write(APIC_ESR, 0);
1020                 v = apic_read(APIC_ESR);
1021                 printk(KERN_DEBUG "... APIC ESR: %08x\n", v);
1022         }
1023
1024         v = apic_read(APIC_ICR);
1025         printk(KERN_DEBUG "... APIC ICR: %08x\n", v);
1026         v = apic_read(APIC_ICR2);
1027         printk(KERN_DEBUG "... APIC ICR2: %08x\n", v);
1028
1029         v = apic_read(APIC_LVTT);
1030         printk(KERN_DEBUG "... APIC LVTT: %08x\n", v);
1031
1032         if (maxlvt > 3) {                       /* PC is LVT#4. */
1033                 v = apic_read(APIC_LVTPC);
1034                 printk(KERN_DEBUG "... APIC LVTPC: %08x\n", v);
1035         }
1036         v = apic_read(APIC_LVT0);
1037         printk(KERN_DEBUG "... APIC LVT0: %08x\n", v);
1038         v = apic_read(APIC_LVT1);
1039         printk(KERN_DEBUG "... APIC LVT1: %08x\n", v);
1040
1041         if (maxlvt > 2) {                       /* ERR is LVT#3. */
1042                 v = apic_read(APIC_LVTERR);
1043                 printk(KERN_DEBUG "... APIC LVTERR: %08x\n", v);
1044         }
1045
1046         v = apic_read(APIC_TMICT);
1047         printk(KERN_DEBUG "... APIC TMICT: %08x\n", v);
1048         v = apic_read(APIC_TMCCT);
1049         printk(KERN_DEBUG "... APIC TMCCT: %08x\n", v);
1050         v = apic_read(APIC_TDCR);
1051         printk(KERN_DEBUG "... APIC TDCR: %08x\n", v);
1052         printk("\n");
1053 }
1054
1055 void print_all_local_APICs (void)
1056 {
1057         on_each_cpu(print_local_APIC, NULL, 1, 1);
1058 }
1059
1060 void __apicdebuginit print_PIC(void)
1061 {
1062         extern spinlock_t i8259A_lock;
1063         unsigned int v;
1064         unsigned long flags;
1065
1066         if (apic_verbosity == APIC_QUIET)
1067                 return;
1068
1069         printk(KERN_DEBUG "\nprinting PIC contents\n");
1070
1071         spin_lock_irqsave(&i8259A_lock, flags);
1072
1073         v = inb(0xa1) << 8 | inb(0x21);
1074         printk(KERN_DEBUG "... PIC  IMR: %04x\n", v);
1075
1076         v = inb(0xa0) << 8 | inb(0x20);
1077         printk(KERN_DEBUG "... PIC  IRR: %04x\n", v);
1078
1079         outb(0x0b,0xa0);
1080         outb(0x0b,0x20);
1081         v = inb(0xa0) << 8 | inb(0x20);
1082         outb(0x0a,0xa0);
1083         outb(0x0a,0x20);
1084
1085         spin_unlock_irqrestore(&i8259A_lock, flags);
1086
1087         printk(KERN_DEBUG "... PIC  ISR: %04x\n", v);
1088
1089         v = inb(0x4d1) << 8 | inb(0x4d0);
1090         printk(KERN_DEBUG "... PIC ELCR: %04x\n", v);
1091 }
1092
1093 static void __init enable_IO_APIC(void)
1094 {
1095         union IO_APIC_reg_01 reg_01;
1096         int i;
1097         unsigned long flags;
1098
1099         for (i = 0; i < PIN_MAP_SIZE; i++) {
1100                 irq_2_pin[i].pin = -1;
1101                 irq_2_pin[i].next = 0;
1102         }
1103         if (!pirqs_enabled)
1104                 for (i = 0; i < MAX_PIRQS; i++)
1105                         pirq_entries[i] = -1;
1106
1107         /*
1108          * The number of IO-APIC IRQ registers (== #pins):
1109          */
1110         for (i = 0; i < nr_ioapics; i++) {
1111                 spin_lock_irqsave(&ioapic_lock, flags);
1112                 reg_01.raw = io_apic_read(i, 1);
1113                 spin_unlock_irqrestore(&ioapic_lock, flags);
1114                 nr_ioapic_registers[i] = reg_01.bits.entries+1;
1115         }
1116
1117         /*
1118          * Do not trust the IO-APIC being empty at bootup
1119          */
1120         clear_IO_APIC();
1121 }
1122
1123 /*
1124  * Not an __init, needed by the reboot code
1125  */
1126 void disable_IO_APIC(void)
1127 {
1128         /*
1129          * Clear the IO-APIC before rebooting:
1130          */
1131         clear_IO_APIC();
1132
1133         disconnect_bsp_APIC();
1134 }
1135
1136 /*
1137  * function to set the IO-APIC physical IDs based on the
1138  * values stored in the MPC table.
1139  *
1140  * by Matt Domsch <Matt_Domsch@dell.com>  Tue Dec 21 12:25:05 CST 1999
1141  */
1142
1143 static void __init setup_ioapic_ids_from_mpc (void)
1144 {
1145         union IO_APIC_reg_00 reg_00;
1146         int apic;
1147         int i;
1148         unsigned char old_id;
1149         unsigned long flags;
1150
1151         /*
1152          * Set the IOAPIC ID to the value stored in the MPC table.
1153          */
1154         for (apic = 0; apic < nr_ioapics; apic++) {
1155
1156                 /* Read the register 0 value */
1157                 spin_lock_irqsave(&ioapic_lock, flags);
1158                 reg_00.raw = io_apic_read(apic, 0);
1159                 spin_unlock_irqrestore(&ioapic_lock, flags);
1160
1161                 old_id = mp_ioapics[apic].mpc_apicid;
1162
1163                 if (mp_ioapics[apic].mpc_apicid >= 0xf) {
1164                         apic_printk(APIC_QUIET,KERN_ERR "BIOS bug, IO-APIC#%d ID is %d in the MPC table!...\n",
1165                                 apic, mp_ioapics[apic].mpc_apicid);
1166                         apic_printk(APIC_QUIET,KERN_ERR "... fixing up to %d. (tell your hw vendor)\n",
1167                                 reg_00.bits.ID);
1168                         mp_ioapics[apic].mpc_apicid = reg_00.bits.ID;
1169                 }
1170
1171                 printk(KERN_INFO "Using IO-APIC %d\n", mp_ioapics[apic].mpc_apicid);
1172
1173
1174                 /*
1175                  * We need to adjust the IRQ routing table
1176                  * if the ID changed.
1177                  */
1178                 if (old_id != mp_ioapics[apic].mpc_apicid)
1179                         for (i = 0; i < mp_irq_entries; i++)
1180                                 if (mp_irqs[i].mpc_dstapic == old_id)
1181                                         mp_irqs[i].mpc_dstapic
1182                                                 = mp_ioapics[apic].mpc_apicid;
1183
1184                 /*
1185                  * Read the right value from the MPC table and
1186                  * write it into the ID register.
1187                  */
1188                 apic_printk(APIC_VERBOSE,KERN_INFO "...changing IO-APIC physical APIC ID to %d ...",
1189                                 mp_ioapics[apic].mpc_apicid);
1190
1191                 reg_00.bits.ID = mp_ioapics[apic].mpc_apicid;
1192                 spin_lock_irqsave(&ioapic_lock, flags);
1193                 io_apic_write(apic, 0, reg_00.raw);
1194                 spin_unlock_irqrestore(&ioapic_lock, flags);
1195
1196                 /*
1197                  * Sanity check
1198                  */
1199                 spin_lock_irqsave(&ioapic_lock, flags);
1200                 reg_00.raw = io_apic_read(apic, 0);
1201                 spin_unlock_irqrestore(&ioapic_lock, flags);
1202                 if (reg_00.bits.ID != mp_ioapics[apic].mpc_apicid)
1203                         printk("could not set ID!\n");
1204                 else
1205                         apic_printk(APIC_VERBOSE," ok.\n");
1206         }
1207 }
1208
1209 /*
1210  * There is a nasty bug in some older SMP boards, their mptable lies
1211  * about the timer IRQ. We do the following to work around the situation:
1212  *
1213  *      - timer IRQ defaults to IO-APIC IRQ
1214  *      - if this function detects that timer IRQs are defunct, then we fall
1215  *        back to ISA timer IRQs
1216  */
1217 static int __init timer_irq_works(void)
1218 {
1219         unsigned long t1 = jiffies;
1220
1221         local_irq_enable();
1222         /* Let ten ticks pass... */
1223         mdelay((10 * 1000) / HZ);
1224
1225         /*
1226          * Expect a few ticks at least, to be sure some possible
1227          * glue logic does not lock up after one or two first
1228          * ticks in a non-ExtINT mode.  Also the local APIC
1229          * might have cached one ExtINT interrupt.  Finally, at
1230          * least one tick may be lost due to delays.
1231          */
1232
1233         /* jiffies wrap? */
1234         if (jiffies - t1 > 4)
1235                 return 1;
1236         return 0;
1237 }
1238
1239 /*
1240  * In the SMP+IOAPIC case it might happen that there are an unspecified
1241  * number of pending IRQ events unhandled. These cases are very rare,
1242  * so we 'resend' these IRQs via IPIs, to the same CPU. It's much
1243  * better to do it this way as thus we do not have to be aware of
1244  * 'pending' interrupts in the IRQ path, except at this point.
1245  */
1246 /*
1247  * Edge triggered needs to resend any interrupt
1248  * that was delayed but this is now handled in the device
1249  * independent code.
1250  */
1251
1252 /*
1253  * Starting up a edge-triggered IO-APIC interrupt is
1254  * nasty - we need to make sure that we get the edge.
1255  * If it is already asserted for some reason, we need
1256  * return 1 to indicate that is was pending.
1257  *
1258  * This is not complete - we should be able to fake
1259  * an edge even if it isn't on the 8259A...
1260  */
1261
1262 static unsigned int startup_edge_ioapic_irq(unsigned int irq)
1263 {
1264         int was_pending = 0;
1265         unsigned long flags;
1266
1267         spin_lock_irqsave(&ioapic_lock, flags);
1268         if (irq < 16) {
1269                 disable_8259A_irq(irq);
1270                 if (i8259A_irq_pending(irq))
1271                         was_pending = 1;
1272         }
1273         __unmask_IO_APIC_irq(irq);
1274         spin_unlock_irqrestore(&ioapic_lock, flags);
1275
1276         return was_pending;
1277 }
1278
1279 /*
1280  * Once we have recorded IRQ_PENDING already, we can mask the
1281  * interrupt for real. This prevents IRQ storms from unhandled
1282  * devices.
1283  */
1284 static void ack_edge_ioapic_irq(unsigned int irq)
1285 {
1286         if ((irq_desc[irq].status & (IRQ_PENDING | IRQ_DISABLED))
1287                                         == (IRQ_PENDING | IRQ_DISABLED))
1288                 mask_IO_APIC_irq(irq);
1289         ack_APIC_irq();
1290 }
1291
1292 /*
1293  * Level triggered interrupts can just be masked,
1294  * and shutting down and starting up the interrupt
1295  * is the same as enabling and disabling them -- except
1296  * with a startup need to return a "was pending" value.
1297  *
1298  * Level triggered interrupts are special because we
1299  * do not touch any IO-APIC register while handling
1300  * them. We ack the APIC in the end-IRQ handler, not
1301  * in the start-IRQ-handler. Protection against reentrance
1302  * from the same interrupt is still provided, both by the
1303  * generic IRQ layer and by the fact that an unacked local
1304  * APIC does not accept IRQs.
1305  */
1306 static unsigned int startup_level_ioapic_irq (unsigned int irq)
1307 {
1308         unmask_IO_APIC_irq(irq);
1309
1310         return 0; /* don't check for pending */
1311 }
1312
1313 static void end_level_ioapic_irq (unsigned int irq)
1314 {
1315         ack_APIC_irq();
1316 }
1317
1318 static void set_ioapic_affinity_irq(unsigned int irq, cpumask_t mask)
1319 {
1320         unsigned long flags;
1321         unsigned int dest;
1322
1323         dest = cpu_mask_to_apicid(mask);
1324
1325         /*
1326          * Only the high 8 bits are valid.
1327          */
1328         dest = SET_APIC_LOGICAL_ID(dest);
1329
1330         spin_lock_irqsave(&ioapic_lock, flags);
1331         __DO_ACTION(1, = dest, )
1332         spin_unlock_irqrestore(&ioapic_lock, flags);
1333 }
1334
1335 #ifdef CONFIG_PCI_MSI
1336 static unsigned int startup_edge_ioapic_vector(unsigned int vector)
1337 {
1338         int irq = vector_to_irq(vector);
1339
1340         return startup_edge_ioapic_irq(irq);
1341 }
1342
1343 static void ack_edge_ioapic_vector(unsigned int vector)
1344 {
1345         int irq = vector_to_irq(vector);
1346
1347         ack_edge_ioapic_irq(irq);
1348 }
1349
1350 static unsigned int startup_level_ioapic_vector (unsigned int vector)
1351 {
1352         int irq = vector_to_irq(vector);
1353
1354         return startup_level_ioapic_irq (irq);
1355 }
1356
1357 static void end_level_ioapic_vector (unsigned int vector)
1358 {
1359         int irq = vector_to_irq(vector);
1360
1361         end_level_ioapic_irq(irq);
1362 }
1363
1364 static void mask_IO_APIC_vector (unsigned int vector)
1365 {
1366         int irq = vector_to_irq(vector);
1367
1368         mask_IO_APIC_irq(irq);
1369 }
1370
1371 static void unmask_IO_APIC_vector (unsigned int vector)
1372 {
1373         int irq = vector_to_irq(vector);
1374
1375         unmask_IO_APIC_irq(irq);
1376 }
1377
1378 static void set_ioapic_affinity_vector (unsigned int vector,
1379                                         cpumask_t cpu_mask)
1380 {
1381         int irq = vector_to_irq(vector);
1382
1383         set_ioapic_affinity_irq(irq, cpu_mask);
1384 }
1385 #endif
1386
1387 /*
1388  * Level and edge triggered IO-APIC interrupts need different handling,
1389  * so we use two separate IRQ descriptors. Edge triggered IRQs can be
1390  * handled with the level-triggered descriptor, but that one has slightly
1391  * more overhead. Level-triggered interrupts cannot be handled with the
1392  * edge-triggered handler, without risking IRQ storms and other ugly
1393  * races.
1394  */
1395
1396 static struct hw_interrupt_type ioapic_edge_type = {
1397         .typename = "IO-APIC-edge",
1398         .startup        = startup_edge_ioapic,
1399         .shutdown       = shutdown_edge_ioapic,
1400         .enable         = enable_edge_ioapic,
1401         .disable        = disable_edge_ioapic,
1402         .ack            = ack_edge_ioapic,
1403         .end            = end_edge_ioapic,
1404         .set_affinity = set_ioapic_affinity,
1405 };
1406
1407 static struct hw_interrupt_type ioapic_level_type = {
1408         .typename = "IO-APIC-level",
1409         .startup        = startup_level_ioapic,
1410         .shutdown       = shutdown_level_ioapic,
1411         .enable         = enable_level_ioapic,
1412         .disable        = disable_level_ioapic,
1413         .ack            = mask_and_ack_level_ioapic,
1414         .end            = end_level_ioapic,
1415         .set_affinity = set_ioapic_affinity,
1416 };
1417
1418 static inline void init_IO_APIC_traps(void)
1419 {
1420         int irq;
1421
1422         /*
1423          * NOTE! The local APIC isn't very good at handling
1424          * multiple interrupts at the same interrupt level.
1425          * As the interrupt level is determined by taking the
1426          * vector number and shifting that right by 4, we
1427          * want to spread these out a bit so that they don't
1428          * all fall in the same interrupt level.
1429          *
1430          * Also, we've got to be careful not to trash gate
1431          * 0x80, because int 0x80 is hm, kind of importantish. ;)
1432          */
1433         for (irq = 0; irq < NR_IRQS ; irq++) {
1434                 int tmp = irq;
1435                 if (use_pci_vector()) {
1436                         if (!platform_legacy_irq(tmp))
1437                                 if ((tmp = vector_to_irq(tmp)) == -1)
1438                                         continue;
1439                 }
1440                 if (IO_APIC_IRQ(tmp) && !IO_APIC_VECTOR(tmp)) {
1441                         /*
1442                          * Hmm.. We don't have an entry for this,
1443                          * so default to an old-fashioned 8259
1444                          * interrupt if we can..
1445                          */
1446                         if (irq < 16)
1447                                 make_8259A_irq(irq);
1448                         else
1449                                 /* Strange. Oh, well.. */
1450                                 irq_desc[irq].handler = &no_irq_type;
1451                 }
1452         }
1453 }
1454
1455 static void enable_lapic_irq (unsigned int irq)
1456 {
1457         unsigned long v;
1458
1459         v = apic_read(APIC_LVT0);
1460         apic_write_around(APIC_LVT0, v & ~APIC_LVT_MASKED);
1461 }
1462
1463 static void disable_lapic_irq (unsigned int irq)
1464 {
1465         unsigned long v;
1466
1467         v = apic_read(APIC_LVT0);
1468         apic_write_around(APIC_LVT0, v | APIC_LVT_MASKED);
1469 }
1470
1471 static void ack_lapic_irq (unsigned int irq)
1472 {
1473         ack_APIC_irq();
1474 }
1475
1476 static void end_lapic_irq (unsigned int i) { /* nothing */ }
1477
1478 static struct hw_interrupt_type lapic_irq_type = {
1479         .typename = "local-APIC-edge",
1480         .startup = NULL, /* startup_irq() not used for IRQ0 */
1481         .shutdown = NULL, /* shutdown_irq() not used for IRQ0 */
1482         .enable = enable_lapic_irq,
1483         .disable = disable_lapic_irq,
1484         .ack = ack_lapic_irq,
1485         .end = end_lapic_irq,
1486 };
1487
1488 static void setup_nmi (void)
1489 {
1490         /*
1491          * Dirty trick to enable the NMI watchdog ...
1492          * We put the 8259A master into AEOI mode and
1493          * unmask on all local APICs LVT0 as NMI.
1494          *
1495          * The idea to use the 8259A in AEOI mode ('8259A Virtual Wire')
1496          * is from Maciej W. Rozycki - so we do not have to EOI from
1497          * the NMI handler or the timer interrupt.
1498          */
1499         printk(KERN_INFO "activating NMI Watchdog ...");
1500
1501         enable_NMI_through_LVT0(NULL);
1502
1503         printk(" done.\n");
1504 }
1505
1506 /*
1507  * This looks a bit hackish but it's about the only one way of sending
1508  * a few INTA cycles to 8259As and any associated glue logic.  ICR does
1509  * not support the ExtINT mode, unfortunately.  We need to send these
1510  * cycles as some i82489DX-based boards have glue logic that keeps the
1511  * 8259A interrupt line asserted until INTA.  --macro
1512  */
1513 static inline void unlock_ExtINT_logic(void)
1514 {
1515         int pin, i;
1516         struct IO_APIC_route_entry entry0, entry1;
1517         unsigned char save_control, save_freq_select;
1518         unsigned long flags;
1519
1520         pin = find_isa_irq_pin(8, mp_INT);
1521         if (pin == -1)
1522                 return;
1523
1524         spin_lock_irqsave(&ioapic_lock, flags);
1525         *(((int *)&entry0) + 1) = io_apic_read(0, 0x11 + 2 * pin);
1526         *(((int *)&entry0) + 0) = io_apic_read(0, 0x10 + 2 * pin);
1527         spin_unlock_irqrestore(&ioapic_lock, flags);
1528         clear_IO_APIC_pin(0, pin);
1529
1530         memset(&entry1, 0, sizeof(entry1));
1531
1532         entry1.dest_mode = 0;                   /* physical delivery */
1533         entry1.mask = 0;                        /* unmask IRQ now */
1534         entry1.dest.physical.physical_dest = hard_smp_processor_id();
1535         entry1.delivery_mode = dest_ExtINT;
1536         entry1.polarity = entry0.polarity;
1537         entry1.trigger = 0;
1538         entry1.vector = 0;
1539
1540         spin_lock_irqsave(&ioapic_lock, flags);
1541         io_apic_write(0, 0x11 + 2 * pin, *(((int *)&entry1) + 1));
1542         io_apic_write(0, 0x10 + 2 * pin, *(((int *)&entry1) + 0));
1543         spin_unlock_irqrestore(&ioapic_lock, flags);
1544
1545         save_control = CMOS_READ(RTC_CONTROL);
1546         save_freq_select = CMOS_READ(RTC_FREQ_SELECT);
1547         CMOS_WRITE((save_freq_select & ~RTC_RATE_SELECT) | 0x6,
1548                    RTC_FREQ_SELECT);
1549         CMOS_WRITE(save_control | RTC_PIE, RTC_CONTROL);
1550
1551         i = 100;
1552         while (i-- > 0) {
1553                 mdelay(10);
1554                 if ((CMOS_READ(RTC_INTR_FLAGS) & RTC_PF) == RTC_PF)
1555                         i -= 10;
1556         }
1557
1558         CMOS_WRITE(save_control, RTC_CONTROL);
1559         CMOS_WRITE(save_freq_select, RTC_FREQ_SELECT);
1560         clear_IO_APIC_pin(0, pin);
1561
1562         spin_lock_irqsave(&ioapic_lock, flags);
1563         io_apic_write(0, 0x11 + 2 * pin, *(((int *)&entry0) + 1));
1564         io_apic_write(0, 0x10 + 2 * pin, *(((int *)&entry0) + 0));
1565         spin_unlock_irqrestore(&ioapic_lock, flags);
1566 }
1567
1568 /*
1569  * This code may look a bit paranoid, but it's supposed to cooperate with
1570  * a wide range of boards and BIOS bugs.  Fortunately only the timer IRQ
1571  * is so screwy.  Thanks to Brian Perkins for testing/hacking this beast
1572  * fanatically on his truly buggy board.
1573  */
1574 static inline void check_timer(void)
1575 {
1576         int pin1, pin2;
1577         int vector;
1578
1579         /*
1580          * get/set the timer IRQ vector:
1581          */
1582         disable_8259A_irq(0);
1583         vector = assign_irq_vector(0);
1584         set_intr_gate(vector, interrupt[0]);
1585
1586         /*
1587          * Subtle, code in do_timer_interrupt() expects an AEOI
1588          * mode for the 8259A whenever interrupts are routed
1589          * through I/O APICs.  Also IRQ0 has to be enabled in
1590          * the 8259A which implies the virtual wire has to be
1591          * disabled in the local APIC.
1592          */
1593         apic_write_around(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT);
1594         init_8259A(1);
1595         enable_8259A_irq(0);
1596
1597         pin1 = find_isa_irq_pin(0, mp_INT);
1598         pin2 = find_isa_irq_pin(0, mp_ExtINT);
1599
1600         apic_printk(APIC_VERBOSE,KERN_INFO "..TIMER: vector=0x%02X pin1=%d pin2=%d\n", vector, pin1, pin2);
1601
1602         if (pin1 != -1) {
1603                 /*
1604                  * Ok, does IRQ0 through the IOAPIC work?
1605                  */
1606                 unmask_IO_APIC_irq(0);
1607                 if (timer_irq_works()) {
1608                         nmi_watchdog_default();
1609                         if (nmi_watchdog == NMI_IO_APIC) {
1610                                 disable_8259A_irq(0);
1611                                 setup_nmi();
1612                                 enable_8259A_irq(0);
1613                                 check_nmi_watchdog();
1614                         }
1615                         return;
1616                 }
1617                 clear_IO_APIC_pin(0, pin1);
1618                 apic_printk(APIC_QUIET,KERN_ERR "..MP-BIOS bug: 8254 timer not connected to IO-APIC\n");
1619         }
1620
1621         apic_printk(APIC_VERBOSE,KERN_INFO "...trying to set up timer (IRQ0) through the 8259A ... ");
1622         if (pin2 != -1) {
1623                 apic_printk(APIC_VERBOSE,"\n..... (found pin %d) ...", pin2);
1624                 /*
1625                  * legacy devices should be connected to IO APIC #0
1626                  */
1627                 setup_ExtINT_IRQ0_pin(pin2, vector);
1628                 if (timer_irq_works()) {
1629                         printk("works.\n");
1630                         nmi_watchdog_default();
1631                         if (nmi_watchdog == NMI_IO_APIC) {
1632                                 setup_nmi();
1633                                 check_nmi_watchdog();
1634                         }
1635                         return;
1636                 }
1637                 /*
1638                  * Cleanup, just in case ...
1639                  */
1640                 clear_IO_APIC_pin(0, pin2);
1641         }
1642         printk(" failed.\n");
1643
1644         if (nmi_watchdog) {
1645                 printk(KERN_WARNING "timer doesn't work through the IO-APIC - disabling NMI Watchdog!\n");
1646                 nmi_watchdog = 0;
1647         }
1648
1649         apic_printk(APIC_VERBOSE, KERN_INFO "...trying to set up timer as Virtual Wire IRQ...");
1650
1651         disable_8259A_irq(0);
1652         irq_desc[0].handler = &lapic_irq_type;
1653         apic_write_around(APIC_LVT0, APIC_DM_FIXED | vector);   /* Fixed mode */
1654         enable_8259A_irq(0);
1655
1656         if (timer_irq_works()) {
1657                 apic_printk(APIC_QUIET, " works.\n");
1658                 return;
1659         }
1660         apic_write_around(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_FIXED | vector);
1661         apic_printk(APIC_VERBOSE," failed.\n");
1662
1663         apic_printk(APIC_VERBOSE, KERN_INFO "...trying to set up timer as ExtINT IRQ...");
1664
1665         init_8259A(0);
1666         make_8259A_irq(0);
1667         apic_write_around(APIC_LVT0, APIC_DM_EXTINT);
1668
1669         unlock_ExtINT_logic();
1670
1671         if (timer_irq_works()) {
1672                 apic_printk(APIC_VERBOSE," works.\n");
1673                 return;
1674         }
1675         apic_printk(APIC_VERBOSE," failed :(.\n");
1676         panic("IO-APIC + timer doesn't work! Try using the 'noapic' kernel parameter\n");
1677 }
1678
1679 /*
1680  *
1681  * IRQ's that are handled by the PIC in the MPS IOAPIC case.
1682  * - IRQ2 is the cascade IRQ, and cannot be a io-apic IRQ.
1683  *   Linux doesn't really care, as it's not actually used
1684  *   for any interrupt handling anyway.
1685  */
1686 #define PIC_IRQS        (1<<2)
1687
1688 void __init setup_IO_APIC(void)
1689 {
1690         enable_IO_APIC();
1691
1692         if (acpi_ioapic)
1693                 io_apic_irqs = ~0;      /* all IRQs go through IOAPIC */
1694         else
1695                 io_apic_irqs = ~PIC_IRQS;
1696
1697         apic_printk(APIC_VERBOSE, "ENABLING IO-APIC IRQs\n");
1698
1699         /*
1700          * Set up the IO-APIC IRQ routing table.
1701          */
1702         if (!acpi_ioapic)
1703                 setup_ioapic_ids_from_mpc();
1704         sync_Arb_IDs();
1705         setup_IO_APIC_irqs();
1706         init_IO_APIC_traps();
1707         check_timer();
1708         if (!acpi_ioapic)
1709                 print_IO_APIC();
1710 }
1711
1712 struct sysfs_ioapic_data {
1713         struct sys_device dev;
1714         struct IO_APIC_route_entry entry[0];
1715 };
1716 static struct sysfs_ioapic_data * mp_ioapic_data[MAX_IO_APICS];
1717
1718 static int ioapic_suspend(struct sys_device *dev, u32 state)
1719 {
1720         struct IO_APIC_route_entry *entry;
1721         struct sysfs_ioapic_data *data;
1722         unsigned long flags;
1723         int i;
1724
1725         data = container_of(dev, struct sysfs_ioapic_data, dev);
1726         entry = data->entry;
1727         spin_lock_irqsave(&ioapic_lock, flags);
1728         for (i = 0; i < nr_ioapic_registers[dev->id]; i ++, entry ++ ) {
1729                 *(((int *)entry) + 1) = io_apic_read(dev->id, 0x11 + 2 * i);
1730                 *(((int *)entry) + 0) = io_apic_read(dev->id, 0x10 + 2 * i);
1731         }
1732         spin_unlock_irqrestore(&ioapic_lock, flags);
1733
1734         return 0;
1735 }
1736
1737 static int ioapic_resume(struct sys_device *dev)
1738 {
1739         struct IO_APIC_route_entry *entry;
1740         struct sysfs_ioapic_data *data;
1741         unsigned long flags;
1742         union IO_APIC_reg_00 reg_00;
1743         int i;
1744
1745         data = container_of(dev, struct sysfs_ioapic_data, dev);
1746         entry = data->entry;
1747
1748         spin_lock_irqsave(&ioapic_lock, flags);
1749         reg_00.raw = io_apic_read(dev->id, 0);
1750         if (reg_00.bits.ID != mp_ioapics[dev->id].mpc_apicid) {
1751                 reg_00.bits.ID = mp_ioapics[dev->id].mpc_apicid;
1752                 io_apic_write(dev->id, 0, reg_00.raw);
1753         }
1754         for (i = 0; i < nr_ioapic_registers[dev->id]; i ++, entry ++ ) {
1755                 io_apic_write(dev->id, 0x11+2*i, *(((int *)entry)+1));
1756                 io_apic_write(dev->id, 0x10+2*i, *(((int *)entry)+0));
1757         }
1758         spin_unlock_irqrestore(&ioapic_lock, flags);
1759
1760         return 0;
1761 }
1762
1763 static struct sysdev_class ioapic_sysdev_class = {
1764         set_kset_name("ioapic"),
1765         .suspend = ioapic_suspend,
1766         .resume = ioapic_resume,
1767 };
1768
1769 static int __init ioapic_init_sysfs(void)
1770 {
1771         struct sys_device * dev;
1772         int i, size, error = 0;
1773
1774         error = sysdev_class_register(&ioapic_sysdev_class);
1775         if (error)
1776                 return error;
1777
1778         for (i = 0; i < nr_ioapics; i++ ) {
1779                 size = sizeof(struct sys_device) + nr_ioapic_registers[i]
1780                         * sizeof(struct IO_APIC_route_entry);
1781                 mp_ioapic_data[i] = kmalloc(size, GFP_KERNEL);
1782                 if (!mp_ioapic_data[i]) {
1783                         printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i);
1784                         continue;
1785                 }
1786                 memset(mp_ioapic_data[i], 0, size);
1787                 dev = &mp_ioapic_data[i]->dev;
1788                 dev->id = i;
1789                 dev->cls = &ioapic_sysdev_class;
1790                 error = sysdev_register(dev);
1791                 if (error) {
1792                         kfree(mp_ioapic_data[i]);
1793                         mp_ioapic_data[i] = NULL;
1794                         printk(KERN_ERR "Can't suspend/resume IOAPIC %d\n", i);
1795                         continue;
1796                 }
1797         }
1798
1799         return 0;
1800 }
1801
1802 device_initcall(ioapic_init_sysfs);
1803
1804 /* --------------------------------------------------------------------------
1805                           ACPI-based IOAPIC Configuration
1806    -------------------------------------------------------------------------- */
1807
1808 #ifdef CONFIG_ACPI_BOOT
1809
1810 #define IO_APIC_MAX_ID          0xFE
1811
1812 int __init io_apic_get_unique_id (int ioapic, int apic_id)
1813 {
1814         union IO_APIC_reg_00 reg_00;
1815         static physid_mask_t apic_id_map;
1816         unsigned long flags;
1817         int i = 0;
1818
1819         /*
1820          * The P4 platform supports up to 256 APIC IDs on two separate APIC
1821          * buses (one for LAPICs, one for IOAPICs), where predecessors only
1822          * supports up to 16 on one shared APIC bus.
1823          *
1824          * TBD: Expand LAPIC/IOAPIC support on P4-class systems to take full
1825          *      advantage of new APIC bus architecture.
1826          */
1827
1828         if (physids_empty(apic_id_map))
1829                 apic_id_map = phys_cpu_present_map;
1830
1831         spin_lock_irqsave(&ioapic_lock, flags);
1832         reg_00.raw = io_apic_read(ioapic, 0);
1833         spin_unlock_irqrestore(&ioapic_lock, flags);
1834
1835         if (apic_id >= IO_APIC_MAX_ID) {
1836                 apic_printk(APIC_QUIET, KERN_WARNING "IOAPIC[%d]: Invalid apic_id %d, trying "
1837                         "%d\n", ioapic, apic_id, reg_00.bits.ID);
1838                 apic_id = reg_00.bits.ID;
1839         }
1840
1841         /*
1842          * Every APIC in a system must have a unique ID or we get lots of nice
1843          * 'stuck on smp_invalidate_needed IPI wait' messages.
1844          */
1845         if (physid_isset(apic_id, apic_id_map)) {
1846
1847                 for (i = 0; i < IO_APIC_MAX_ID; i++) {
1848                         if (!physid_isset(i, apic_id_map))
1849                                 break;
1850                 }
1851
1852                 if (i == IO_APIC_MAX_ID)
1853                         panic("Max apic_id exceeded!\n");
1854
1855                 apic_printk(APIC_VERBOSE, KERN_WARNING "IOAPIC[%d]: apic_id %d already used, "
1856                         "trying %d\n", ioapic, apic_id, i);
1857
1858                 apic_id = i;
1859         }
1860
1861         physid_set(apic_id, apic_id_map);
1862
1863         if (reg_00.bits.ID != apic_id) {
1864                 reg_00.bits.ID = apic_id;
1865
1866                 spin_lock_irqsave(&ioapic_lock, flags);
1867                 io_apic_write(ioapic, 0, reg_00.raw);
1868                 reg_00.raw = io_apic_read(ioapic, 0);
1869                 spin_unlock_irqrestore(&ioapic_lock, flags);
1870
1871                 /* Sanity check */
1872                 if (reg_00.bits.ID != apic_id)
1873                         panic("IOAPIC[%d]: Unable change apic_id!\n", ioapic);
1874         }
1875
1876         apic_printk(APIC_VERBOSE,KERN_INFO "IOAPIC[%d]: Assigned apic_id %d\n", ioapic, apic_id);
1877
1878         return apic_id;
1879 }
1880
1881
1882 int __init io_apic_get_version (int ioapic)
1883 {
1884         union IO_APIC_reg_01    reg_01;
1885         unsigned long flags;
1886
1887         spin_lock_irqsave(&ioapic_lock, flags);
1888         reg_01.raw = io_apic_read(ioapic, 1);
1889         spin_unlock_irqrestore(&ioapic_lock, flags);
1890
1891         return reg_01.bits.version;
1892 }
1893
1894
1895 int __init io_apic_get_redir_entries (int ioapic)
1896 {
1897         union IO_APIC_reg_01    reg_01;
1898         unsigned long flags;
1899
1900         spin_lock_irqsave(&ioapic_lock, flags);
1901         reg_01.raw = io_apic_read(ioapic, 1);
1902         spin_unlock_irqrestore(&ioapic_lock, flags);
1903
1904         return reg_01.bits.entries;
1905 }
1906
1907
1908 int io_apic_set_pci_routing (int ioapic, int pin, int irq, int edge_level, int active_high_low)
1909 {
1910         struct IO_APIC_route_entry entry;
1911         unsigned long flags;
1912
1913         if (!IO_APIC_IRQ(irq)) {
1914                 apic_printk(APIC_QUIET,KERN_ERR "IOAPIC[%d]: Invalid reference to IRQ 0\n",
1915                         ioapic);
1916                 return -EINVAL;
1917         }
1918
1919         /*
1920          * Generate a PCI IRQ routing entry and program the IOAPIC accordingly.
1921          * Note that we mask (disable) IRQs now -- these get enabled when the
1922          * corresponding device driver registers for this IRQ.
1923          */
1924
1925         memset(&entry,0,sizeof(entry));
1926
1927         entry.delivery_mode = INT_DELIVERY_MODE;
1928         entry.dest_mode = INT_DEST_MODE;
1929         entry.dest.logical.logical_dest = cpu_mask_to_apicid(TARGET_CPUS);
1930         entry.trigger = edge_level;
1931         entry.polarity = active_high_low;
1932         entry.mask = 1;                                  /* Disabled (masked) */
1933
1934         /*
1935          * IRQs < 16 are already in the irq_2_pin[] map
1936          */
1937         if (irq >= 16)
1938                 add_pin_to_irq(irq, ioapic, pin);
1939
1940         entry.vector = assign_irq_vector(irq);
1941
1942         apic_printk(APIC_VERBOSE,KERN_DEBUG "IOAPIC[%d]: Set PCI routing entry (%d-%d -> 0x%x -> "
1943                 "IRQ %d Mode:%i Active:%i)\n", ioapic,
1944                mp_ioapics[ioapic].mpc_apicid, pin, entry.vector, irq,
1945                edge_level, active_high_low);
1946
1947         ioapic_register_intr(irq, entry.vector, edge_level);
1948
1949         if (!ioapic && (irq < 16))
1950                 disable_8259A_irq(irq);
1951
1952         spin_lock_irqsave(&ioapic_lock, flags);
1953         io_apic_write(ioapic, 0x11+2*pin, *(((int *)&entry)+1));
1954         io_apic_write(ioapic, 0x10+2*pin, *(((int *)&entry)+0));
1955         spin_unlock_irqrestore(&ioapic_lock, flags);
1956
1957         return 0;
1958 }
1959
1960 #endif /*CONFIG_ACPI_BOOT*/
1961
1962
1963 /*
1964  * This function currently is only a helper for the i386 smp boot process where
1965  * we need to reprogram the ioredtbls to cater for the cpus which have come online
1966  * so mask in all cases should simply be TARGET_CPUS
1967  */
1968 void __init setup_ioapic_dest(void)
1969 {
1970         int pin, ioapic, irq, irq_entry;
1971
1972         if (skip_ioapic_setup == 1)
1973                 return;
1974
1975         for (ioapic = 0; ioapic < nr_ioapics; ioapic++) {
1976                 for (pin = 0; pin < nr_ioapic_registers[ioapic]; pin++) {
1977                         irq_entry = find_irq_entry(ioapic, pin, mp_INT);
1978                         if (irq_entry == -1)
1979                                 continue;
1980                         irq = pin_2_irq(irq_entry, ioapic, pin);
1981                         set_ioapic_affinity_irq(irq, TARGET_CPUS);
1982                 }
1983
1984         }
1985 }