2 * Intel IO-APIC support for multi-Pentium hosts.
4 * Copyright (C) 1997, 1998, 1999, 2000 Ingo Molnar, Hajnalka Szabo
6 * Many thanks to Stig Venaas for trying out countless experimental
7 * patches and reporting/debugging problems patiently!
9 * (c) 1999, Multiple IO-APIC support, developed by
10 * Ken-ichi Yaku <yaku@css1.kbnes.nec.co.jp> and
11 * Hidemi Kishimoto <kisimoto@css1.kbnes.nec.co.jp>,
12 * further tested and cleaned up by Zach Brown <zab@redhat.com>
13 * and Ingo Molnar <mingo@redhat.com>
16 * Maciej W. Rozycki : Bits for genuine 82489DX APICs;
17 * thanks to Eric Gilmore
19 * for testing these extensively
20 * Paul Diefenbaugh : Added full ACPI support
24 #include <linux/irq.h>
25 #include <linux/interrupt.h>
26 #include <linux/init.h>
27 #include <linux/delay.h>
28 #include <linux/sched.h>
29 #include <linux/config.h>
30 #include <linux/smp_lock.h>
31 #include <linux/mc146818rtc.h>
32 #include <linux/acpi.h>
37 #include <asm/proto.h>
39 int sis_apic_bug; /* not actually supported, dummy for compile */
41 #undef APIC_LOCKUP_DEBUG
43 #define APIC_LOCKUP_DEBUG
45 static spinlock_t ioapic_lock = SPIN_LOCK_UNLOCKED;
48 * # of IRQ routing registers
50 int nr_ioapic_registers[MAX_IO_APICS];
53 * Rough estimation of how many shared IRQs there are, can
56 #define MAX_PLUS_SHARED_IRQS NR_IRQS
57 #define PIN_MAP_SIZE (MAX_PLUS_SHARED_IRQS + NR_IRQS)
60 * This is performance-critical, we want to do it O(1)
62 * the indexing order of this array favors 1:1 mappings
63 * between pins and IRQs.
66 static struct irq_pin_list {
67 short apic, pin, next;
68 } irq_2_pin[PIN_MAP_SIZE];
70 #ifdef CONFIG_PCI_USE_VECTOR
71 int vector_irq[NR_IRQS] = { [0 ... NR_IRQS -1] = -1};
72 #define vector_to_irq(vector) \
73 (platform_legacy_irq(vector) ? vector : vector_irq[vector])
75 #define vector_to_irq(vector) (vector)
79 * The common case is 1:1 IRQ<->pin mappings. Sometimes there are
80 * shared ISA-space IRQs, so we have to support them. We are super
81 * fast in the common case, and fast for shared ISA-space IRQs.
83 static void __init add_pin_to_irq(unsigned int irq, int apic, int pin)
85 static int first_free_entry = NR_IRQS;
86 struct irq_pin_list *entry = irq_2_pin + irq;
89 entry = irq_2_pin + entry->next;
91 if (entry->pin != -1) {
92 entry->next = first_free_entry;
93 entry = irq_2_pin + entry->next;
94 if (++first_free_entry >= PIN_MAP_SIZE)
95 panic("io_apic.c: whoops");
101 #define __DO_ACTION(R, ACTION, FINAL) \
105 struct irq_pin_list *entry = irq_2_pin + irq; \
112 reg = io_apic_read(entry->apic, 0x10 + R + pin*2); \
114 io_apic_modify(entry->apic, reg); \
117 entry = irq_2_pin + entry->next; \
122 #define DO_ACTION(name,R,ACTION, FINAL) \
124 static void name##_IO_APIC_irq (unsigned int irq) \
125 __DO_ACTION(R, ACTION, FINAL)
127 DO_ACTION( __mask, 0, |= 0x00010000, io_apic_sync(entry->apic) )
129 DO_ACTION( __unmask, 0, &= 0xfffeffff, )
131 DO_ACTION( __mask_and_edge, 0, = (reg & 0xffff7fff) | 0x00010000, )
132 /* mask = 1, trigger = 0 */
133 DO_ACTION( __unmask_and_level, 0, = (reg & 0xfffeffff) | 0x00008000, )
134 /* mask = 0, trigger = 1 */
136 static void mask_IO_APIC_irq (unsigned int irq)
140 spin_lock_irqsave(&ioapic_lock, flags);
141 __mask_IO_APIC_irq(irq);
142 spin_unlock_irqrestore(&ioapic_lock, flags);
145 static void unmask_IO_APIC_irq (unsigned int irq)
149 spin_lock_irqsave(&ioapic_lock, flags);
150 __unmask_IO_APIC_irq(irq);
151 spin_unlock_irqrestore(&ioapic_lock, flags);
154 void clear_IO_APIC_pin(unsigned int apic, unsigned int pin)
156 struct IO_APIC_route_entry entry;
159 /* Check delivery_mode to be sure we're not clearing an SMI pin */
160 spin_lock_irqsave(&ioapic_lock, flags);
161 *(((int*)&entry) + 0) = io_apic_read(apic, 0x10 + 2 * pin);
162 *(((int*)&entry) + 1) = io_apic_read(apic, 0x11 + 2 * pin);
163 spin_unlock_irqrestore(&ioapic_lock, flags);
164 if (entry.delivery_mode == dest_SMI)
167 * Disable it in the IO-APIC irq-routing table:
169 memset(&entry, 0, sizeof(entry));
171 spin_lock_irqsave(&ioapic_lock, flags);
172 io_apic_write(apic, 0x10 + 2 * pin, *(((int *)&entry) + 0));
173 io_apic_write(apic, 0x11 + 2 * pin, *(((int *)&entry) + 1));
174 spin_unlock_irqrestore(&ioapic_lock, flags);
177 static void clear_IO_APIC (void)
181 for (apic = 0; apic < nr_ioapics; apic++)
182 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++)
183 clear_IO_APIC_pin(apic, pin);
187 * support for broken MP BIOSs, enables hand-redirection of PIRQ0-7 to
188 * specific CPU-side IRQs.
192 int pirq_entries [MAX_PIRQS];
194 int skip_ioapic_setup;
197 /* dummy parsing: see setup.c */
199 static int __init disable_ioapic_setup(char *str)
201 skip_ioapic_setup = 1;
205 static int __init enable_ioapic_setup(char *str)
208 skip_ioapic_setup = 0;
212 __setup("noapic", disable_ioapic_setup);
213 __setup("apic", enable_ioapic_setup);
215 #include <asm/pci-direct.h>
216 #include <linux/pci_ids.h>
217 #include <linux/pci.h>
219 /* Temporary Hack. Nvidia and VIA boards currently only work with IO-APIC
220 off. Check for an Nvidia or VIA PCI bridge and turn it off.
221 Use pci direct infrastructure because this runs before the PCI subsystem.
223 Can be overwritten with "apic"
225 And another hack to disable the IOMMU on VIA chipsets.
228 void __init check_ioapic(void)
234 /* Poor man's PCI discovery */
235 for (num = 0; num < 32; num++) {
236 for (slot = 0; slot < 32; slot++) {
237 for (func = 0; func < 8; func++) {
240 class = read_pci_config(num,slot,func,
242 if (class == 0xffffffff)
245 if ((class >> 16) != PCI_CLASS_BRIDGE_PCI)
248 vendor = read_pci_config(num, slot, func,
252 case PCI_VENDOR_ID_VIA:
253 #ifdef CONFIG_GART_IOMMU
254 if (end_pfn >= (0xffffffff>>PAGE_SHIFT) &&
255 !iommu_aperture_allowed) {
257 "Looks like a VIA chipset. Disabling IOMMU. Overwrite with \"iommu=allowed\"\n");
258 iommu_aperture_disabled = 1;
262 case PCI_VENDOR_ID_NVIDIA:
265 "PCI bridge %02x:%02x from %x found. Setting \"noapic\". Overwrite with \"apic\"\n",
267 skip_ioapic_setup = 1;
272 /* No multi-function device? */
273 u8 type = read_pci_config_byte(num,slot,func,
282 static int __init ioapic_pirq_setup(char *str)
285 int ints[MAX_PIRQS+1];
287 get_options(str, ARRAY_SIZE(ints), ints);
289 for (i = 0; i < MAX_PIRQS; i++)
290 pirq_entries[i] = -1;
293 printk(KERN_INFO "PIRQ redirection, working around broken MP-BIOS.\n");
295 if (ints[0] < MAX_PIRQS)
298 for (i = 0; i < max; i++) {
299 printk(KERN_DEBUG "... PIRQ%d -> IRQ %d\n", i, ints[i+1]);
301 * PIRQs are mapped upside down, usually.
303 pirq_entries[MAX_PIRQS-i-1] = ints[i+1];
308 __setup("pirq=", ioapic_pirq_setup);
311 * Find the IRQ entry number of a certain pin.
313 static int __init find_irq_entry(int apic, int pin, int type)
317 for (i = 0; i < mp_irq_entries; i++)
318 if (mp_irqs[i].mpc_irqtype == type &&
319 (mp_irqs[i].mpc_dstapic == mp_ioapics[apic].mpc_apicid ||
320 mp_irqs[i].mpc_dstapic == MP_APIC_ALL) &&
321 mp_irqs[i].mpc_dstirq == pin)
328 * Find the pin to which IRQ[irq] (ISA) is connected
330 static int __init find_isa_irq_pin(int irq, int type)
334 for (i = 0; i < mp_irq_entries; i++) {
335 int lbus = mp_irqs[i].mpc_srcbus;
337 if ((mp_bus_id_to_type[lbus] == MP_BUS_ISA ||
338 mp_bus_id_to_type[lbus] == MP_BUS_EISA ||
339 mp_bus_id_to_type[lbus] == MP_BUS_MCA) &&
340 (mp_irqs[i].mpc_irqtype == type) &&
341 (mp_irqs[i].mpc_srcbusirq == irq))
343 return mp_irqs[i].mpc_dstirq;
349 * Find a specific PCI IRQ entry.
350 * Not an __init, possibly needed by modules
352 static int pin_2_irq(int idx, int apic, int pin);
354 int IO_APIC_get_PCI_irq_vector(int bus, int slot, int pin)
356 int apic, i, best_guess = -1;
358 Dprintk("querying PCI -> IRQ mapping bus:%d, slot:%d, pin:%d.\n",
360 if (mp_bus_id_to_pci_bus[bus] == -1) {
361 printk(KERN_WARNING "PCI BIOS passed nonexistent PCI bus %d!\n", bus);
364 for (i = 0; i < mp_irq_entries; i++) {
365 int lbus = mp_irqs[i].mpc_srcbus;
367 for (apic = 0; apic < nr_ioapics; apic++)
368 if (mp_ioapics[apic].mpc_apicid == mp_irqs[i].mpc_dstapic ||
369 mp_irqs[i].mpc_dstapic == MP_APIC_ALL)
372 if ((mp_bus_id_to_type[lbus] == MP_BUS_PCI) &&
373 !mp_irqs[i].mpc_irqtype &&
375 (slot == ((mp_irqs[i].mpc_srcbusirq >> 2) & 0x1f))) {
376 int irq = pin_2_irq(i,apic,mp_irqs[i].mpc_dstirq);
378 if (!(apic || IO_APIC_IRQ(irq)))
381 if (pin == (mp_irqs[i].mpc_srcbusirq & 3))
384 * Use the first all-but-pin matching entry as a
385 * best-guess fuzzy result for broken mptables.
395 * EISA Edge/Level control register, ELCR
397 static int __init EISA_ELCR(unsigned int irq)
400 unsigned int port = 0x4d0 + (irq >> 3);
401 return (inb(port) >> (irq & 7)) & 1;
403 printk(KERN_INFO "Broken MPtable reports ISA irq %d\n", irq);
407 /* EISA interrupts are always polarity zero and can be edge or level
408 * trigger depending on the ELCR value. If an interrupt is listed as
409 * EISA conforming in the MP table, that means its trigger type must
410 * be read in from the ELCR */
412 #define default_EISA_trigger(idx) (EISA_ELCR(mp_irqs[idx].mpc_srcbusirq))
413 #define default_EISA_polarity(idx) (0)
415 /* ISA interrupts are always polarity zero edge triggered,
416 * when listed as conforming in the MP table. */
418 #define default_ISA_trigger(idx) (0)
419 #define default_ISA_polarity(idx) (0)
421 /* PCI interrupts are always polarity one level triggered,
422 * when listed as conforming in the MP table. */
424 #define default_PCI_trigger(idx) (1)
425 #define default_PCI_polarity(idx) (1)
427 /* MCA interrupts are always polarity zero level triggered,
428 * when listed as conforming in the MP table. */
430 #define default_MCA_trigger(idx) (1)
431 #define default_MCA_polarity(idx) (0)
433 static int __init MPBIOS_polarity(int idx)
435 int bus = mp_irqs[idx].mpc_srcbus;
439 * Determine IRQ line polarity (high active or low active):
441 switch (mp_irqs[idx].mpc_irqflag & 3)
443 case 0: /* conforms, ie. bus-type dependent polarity */
445 switch (mp_bus_id_to_type[bus])
447 case MP_BUS_ISA: /* ISA pin */
449 polarity = default_ISA_polarity(idx);
452 case MP_BUS_EISA: /* EISA pin */
454 polarity = default_EISA_polarity(idx);
457 case MP_BUS_PCI: /* PCI pin */
459 polarity = default_PCI_polarity(idx);
462 case MP_BUS_MCA: /* MCA pin */
464 polarity = default_MCA_polarity(idx);
469 printk(KERN_WARNING "broken BIOS!!\n");
476 case 1: /* high active */
481 case 2: /* reserved */
483 printk(KERN_WARNING "broken BIOS!!\n");
487 case 3: /* low active */
492 default: /* invalid */
494 printk(KERN_WARNING "broken BIOS!!\n");
502 static int __init MPBIOS_trigger(int idx)
504 int bus = mp_irqs[idx].mpc_srcbus;
508 * Determine IRQ trigger mode (edge or level sensitive):
510 switch ((mp_irqs[idx].mpc_irqflag>>2) & 3)
512 case 0: /* conforms, ie. bus-type dependent */
514 switch (mp_bus_id_to_type[bus])
516 case MP_BUS_ISA: /* ISA pin */
518 trigger = default_ISA_trigger(idx);
521 case MP_BUS_EISA: /* EISA pin */
523 trigger = default_EISA_trigger(idx);
526 case MP_BUS_PCI: /* PCI pin */
528 trigger = default_PCI_trigger(idx);
531 case MP_BUS_MCA: /* MCA pin */
533 trigger = default_MCA_trigger(idx);
538 printk(KERN_WARNING "broken BIOS!!\n");
550 case 2: /* reserved */
552 printk(KERN_WARNING "broken BIOS!!\n");
561 default: /* invalid */
563 printk(KERN_WARNING "broken BIOS!!\n");
571 static inline int irq_polarity(int idx)
573 return MPBIOS_polarity(idx);
576 static inline int irq_trigger(int idx)
578 return MPBIOS_trigger(idx);
581 static int pin_2_irq(int idx, int apic, int pin)
584 int bus = mp_irqs[idx].mpc_srcbus;
587 * Debugging check, we are in big trouble if this message pops up!
589 if (mp_irqs[idx].mpc_dstirq != pin)
590 printk(KERN_ERR "broken BIOS or MPTABLE parser, ayiee!!\n");
592 switch (mp_bus_id_to_type[bus])
594 case MP_BUS_ISA: /* ISA pin */
598 irq = mp_irqs[idx].mpc_srcbusirq;
601 case MP_BUS_PCI: /* PCI pin */
604 * PCI IRQs are mapped in order
608 irq += nr_ioapic_registers[i++];
614 printk(KERN_ERR "unknown bus type %d.\n",bus);
621 * PCI IRQ command line redirection. Yes, limits are hardcoded.
623 if ((pin >= 16) && (pin <= 23)) {
624 if (pirq_entries[pin-16] != -1) {
625 if (!pirq_entries[pin-16]) {
626 printk(KERN_DEBUG "disabling PIRQ%d\n", pin-16);
628 irq = pirq_entries[pin-16];
629 printk(KERN_DEBUG "using PIRQ%d -> IRQ %d\n",
637 static inline int IO_APIC_irq_trigger(int irq)
641 for (apic = 0; apic < nr_ioapics; apic++) {
642 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
643 idx = find_irq_entry(apic,pin,mp_INT);
644 if ((idx != -1) && (irq == pin_2_irq(idx,apic,pin)))
645 return irq_trigger(idx);
649 * nonexistent IRQs are edge default
654 /* irq_vectors is indexed by the sum of all RTEs in all I/O APICs. */
655 u8 irq_vector[NR_IRQ_VECTORS] = { FIRST_DEVICE_VECTOR , 0 };
657 #ifndef CONFIG_PCI_USE_VECTOR
658 int __init assign_irq_vector(int irq)
660 static int current_vector = FIRST_DEVICE_VECTOR, offset = 0;
661 BUG_ON(irq >= NR_IRQ_VECTORS);
662 if (IO_APIC_VECTOR(irq) > 0)
663 return IO_APIC_VECTOR(irq);
666 if (current_vector == IA32_SYSCALL_VECTOR)
669 if (current_vector > FIRST_SYSTEM_VECTOR) {
671 current_vector = FIRST_DEVICE_VECTOR + offset;
674 if (current_vector == FIRST_SYSTEM_VECTOR)
675 panic("ran out of interrupt sources!");
677 IO_APIC_VECTOR(irq) = current_vector;
678 return current_vector;
682 extern void (*interrupt[NR_IRQS])(void);
683 static struct hw_interrupt_type ioapic_level_type;
684 static struct hw_interrupt_type ioapic_edge_type;
686 #define IOAPIC_AUTO -1
687 #define IOAPIC_EDGE 0
688 #define IOAPIC_LEVEL 1
690 static inline void ioapic_register_intr(int irq, int vector, unsigned long trigger)
692 if (use_pci_vector() && !platform_legacy_irq(irq)) {
693 if ((trigger == IOAPIC_AUTO && IO_APIC_irq_trigger(irq)) ||
694 trigger == IOAPIC_LEVEL)
695 irq_desc[vector].handler = &ioapic_level_type;
697 irq_desc[vector].handler = &ioapic_edge_type;
698 set_intr_gate(vector, interrupt[vector]);
700 if ((trigger == IOAPIC_AUTO && IO_APIC_irq_trigger(irq)) ||
701 trigger == IOAPIC_LEVEL)
702 irq_desc[irq].handler = &ioapic_level_type;
704 irq_desc[irq].handler = &ioapic_edge_type;
705 set_intr_gate(vector, interrupt[irq]);
709 void __init setup_IO_APIC_irqs(void)
711 struct IO_APIC_route_entry entry;
712 int apic, pin, idx, irq, first_notcon = 1, vector;
715 printk(KERN_DEBUG "init IO_APIC IRQs\n");
717 for (apic = 0; apic < nr_ioapics; apic++) {
718 for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
721 * add it to the IO-APIC irq-routing table:
723 memset(&entry,0,sizeof(entry));
725 entry.delivery_mode = dest_LowestPrio;
726 entry.dest_mode = INT_DELIVERY_MODE;
727 entry.mask = 0; /* enable IRQ */
728 entry.dest.logical.logical_dest = TARGET_CPUS;
730 idx = find_irq_entry(apic,pin,mp_INT);
733 printk(KERN_DEBUG " IO-APIC (apicid-pin) %d-%d", mp_ioapics[apic].mpc_apicid, pin);
736 printk(", %d-%d", mp_ioapics[apic].mpc_apicid, pin);
740 entry.trigger = irq_trigger(idx);
741 entry.polarity = irq_polarity(idx);
743 if (irq_trigger(idx)) {
746 entry.dest.logical.logical_dest = TARGET_CPUS;
749 irq = pin_2_irq(idx, apic, pin);
750 add_pin_to_irq(irq, apic, pin);
752 if (!apic && !IO_APIC_IRQ(irq))
755 if (IO_APIC_IRQ(irq)) {
756 vector = assign_irq_vector(irq);
757 entry.vector = vector;
759 ioapic_register_intr(irq, vector, IOAPIC_AUTO);
760 if (!apic && (irq < 16))
761 disable_8259A_irq(irq);
763 spin_lock_irqsave(&ioapic_lock, flags);
764 io_apic_write(apic, 0x11+2*pin, *(((int *)&entry)+1));
765 io_apic_write(apic, 0x10+2*pin, *(((int *)&entry)+0));
766 spin_unlock_irqrestore(&ioapic_lock, flags);
771 printk(" not connected.\n");
775 * Set up the 8259A-master output pin as broadcast to all
778 void __init setup_ExtINT_IRQ0_pin(unsigned int pin, int vector)
780 struct IO_APIC_route_entry entry;
783 memset(&entry,0,sizeof(entry));
785 disable_8259A_irq(0);
788 apic_write_around(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT);
791 * We use logical delivery to get the timer IRQ
794 entry.dest_mode = INT_DELIVERY_MODE;
795 entry.mask = 0; /* unmask IRQ now */
796 entry.dest.logical.logical_dest = TARGET_CPUS;
797 entry.delivery_mode = dest_LowestPrio;
800 entry.vector = vector;
803 * The timer IRQ doesn't have to know that behind the
804 * scene we have a 8259A-master in AEOI mode ...
806 irq_desc[0].handler = &ioapic_edge_type;
809 * Add it to the IO-APIC irq-routing table:
811 spin_lock_irqsave(&ioapic_lock, flags);
812 io_apic_write(0, 0x11+2*pin, *(((int *)&entry)+1));
813 io_apic_write(0, 0x10+2*pin, *(((int *)&entry)+0));
814 spin_unlock_irqrestore(&ioapic_lock, flags);
819 void __init UNEXPECTED_IO_APIC(void)
822 printk(KERN_WARNING " WARNING: unexpected IO-APIC, please mail\n");
823 printk(KERN_WARNING " to linux-smp@vger.kernel.org\n");
827 void __init print_IO_APIC(void)
830 union IO_APIC_reg_00 reg_00;
831 union IO_APIC_reg_01 reg_01;
832 union IO_APIC_reg_02 reg_02;
835 printk(KERN_DEBUG "number of MP IRQ sources: %d.\n", mp_irq_entries);
836 for (i = 0; i < nr_ioapics; i++)
837 printk(KERN_DEBUG "number of IO-APIC #%d registers: %d.\n",
838 mp_ioapics[i].mpc_apicid, nr_ioapic_registers[i]);
841 * We are a bit conservative about what we expect. We have to
842 * know about every hardware change ASAP.
844 printk(KERN_INFO "testing the IO APIC.......................\n");
846 for (apic = 0; apic < nr_ioapics; apic++) {
848 spin_lock_irqsave(&ioapic_lock, flags);
849 reg_00.raw = io_apic_read(apic, 0);
850 reg_01.raw = io_apic_read(apic, 1);
851 if (reg_01.bits.version >= 0x10)
852 reg_02.raw = io_apic_read(apic, 2);
853 spin_unlock_irqrestore(&ioapic_lock, flags);
856 printk(KERN_DEBUG "IO APIC #%d......\n", mp_ioapics[apic].mpc_apicid);
857 printk(KERN_DEBUG ".... register #00: %08X\n", reg_00.raw);
858 printk(KERN_DEBUG "....... : physical APIC id: %02X\n", reg_00.bits.ID);
859 if (reg_00.bits.__reserved_1 || reg_00.bits.__reserved_2)
860 UNEXPECTED_IO_APIC();
862 printk(KERN_DEBUG ".... register #01: %08X\n", *(int *)®_01);
863 printk(KERN_DEBUG "....... : max redirection entries: %04X\n", reg_01.bits.entries);
864 if ( (reg_01.bits.entries != 0x0f) && /* older (Neptune) boards */
865 (reg_01.bits.entries != 0x17) && /* typical ISA+PCI boards */
866 (reg_01.bits.entries != 0x1b) && /* Compaq Proliant boards */
867 (reg_01.bits.entries != 0x1f) && /* dual Xeon boards */
868 (reg_01.bits.entries != 0x22) && /* bigger Xeon boards */
869 (reg_01.bits.entries != 0x2E) &&
870 (reg_01.bits.entries != 0x3F) &&
871 (reg_01.bits.entries != 0x03)
873 UNEXPECTED_IO_APIC();
875 printk(KERN_DEBUG "....... : PRQ implemented: %X\n", reg_01.bits.PRQ);
876 printk(KERN_DEBUG "....... : IO APIC version: %04X\n", reg_01.bits.version);
877 if ( (reg_01.bits.version != 0x01) && /* 82489DX IO-APICs */
878 (reg_01.bits.version != 0x02) && /* 82801BA IO-APICs (ICH2) */
879 (reg_01.bits.version != 0x10) && /* oldest IO-APICs */
880 (reg_01.bits.version != 0x11) && /* Pentium/Pro IO-APICs */
881 (reg_01.bits.version != 0x13) && /* Xeon IO-APICs */
882 (reg_01.bits.version != 0x20) /* Intel P64H (82806 AA) */
884 UNEXPECTED_IO_APIC();
885 if (reg_01.bits.__reserved_1 || reg_01.bits.__reserved_2)
886 UNEXPECTED_IO_APIC();
888 if (reg_01.bits.version >= 0x10) {
889 printk(KERN_DEBUG ".... register #02: %08X\n", reg_02.raw);
890 printk(KERN_DEBUG "....... : arbitration: %02X\n", reg_02.bits.arbitration);
891 if (reg_02.bits.__reserved_1 || reg_02.bits.__reserved_2)
892 UNEXPECTED_IO_APIC();
895 printk(KERN_DEBUG ".... IRQ redirection table:\n");
897 printk(KERN_DEBUG " NR Log Phy Mask Trig IRR Pol"
898 " Stat Dest Deli Vect: \n");
900 for (i = 0; i <= reg_01.bits.entries; i++) {
901 struct IO_APIC_route_entry entry;
903 spin_lock_irqsave(&ioapic_lock, flags);
904 *(((int *)&entry)+0) = io_apic_read(apic, 0x10+i*2);
905 *(((int *)&entry)+1) = io_apic_read(apic, 0x11+i*2);
906 spin_unlock_irqrestore(&ioapic_lock, flags);
908 printk(KERN_DEBUG " %02x %03X %02X ",
910 entry.dest.logical.logical_dest,
911 entry.dest.physical.physical_dest
914 printk("%1d %1d %1d %1d %1d %1d %1d %02X\n",
919 entry.delivery_status,
926 printk(KERN_DEBUG "IRQ to pin mappings:\n");
927 for (i = 0; i < NR_IRQS; i++) {
928 struct irq_pin_list *entry = irq_2_pin + i;
931 printk(KERN_DEBUG "IRQ%d ", i);
933 printk("-> %d:%d", entry->apic, entry->pin);
936 entry = irq_2_pin + entry->next;
941 printk(KERN_INFO ".................................... done.\n");
946 static void print_APIC_bitfield (int base)
951 printk(KERN_DEBUG "0123456789abcdef0123456789abcdef\n" KERN_DEBUG);
952 for (i = 0; i < 8; i++) {
953 v = apic_read(base + i*0x10);
954 for (j = 0; j < 32; j++) {
964 void /*__init*/ print_local_APIC(void * dummy)
966 unsigned int v, ver, maxlvt;
968 printk("\n" KERN_DEBUG "printing local APIC contents on CPU#%d/%d:\n",
969 smp_processor_id(), hard_smp_processor_id());
970 v = apic_read(APIC_ID);
971 printk(KERN_INFO "... APIC ID: %08x (%01x)\n", v, GET_APIC_ID(v));
972 v = apic_read(APIC_LVR);
973 printk(KERN_INFO "... APIC VERSION: %08x\n", v);
974 ver = GET_APIC_VERSION(v);
975 maxlvt = get_maxlvt();
977 v = apic_read(APIC_TASKPRI);
978 printk(KERN_DEBUG "... APIC TASKPRI: %08x (%02x)\n", v, v & APIC_TPRI_MASK);
980 if (APIC_INTEGRATED(ver)) { /* !82489DX */
981 v = apic_read(APIC_ARBPRI);
982 printk(KERN_DEBUG "... APIC ARBPRI: %08x (%02x)\n", v,
983 v & APIC_ARBPRI_MASK);
984 v = apic_read(APIC_PROCPRI);
985 printk(KERN_DEBUG "... APIC PROCPRI: %08x\n", v);
988 v = apic_read(APIC_EOI);
989 printk(KERN_DEBUG "... APIC EOI: %08x\n", v);
990 v = apic_read(APIC_RRR);
991 printk(KERN_DEBUG "... APIC RRR: %08x\n", v);
992 v = apic_read(APIC_LDR);
993 printk(KERN_DEBUG "... APIC LDR: %08x\n", v);
994 v = apic_read(APIC_DFR);
995 printk(KERN_DEBUG "... APIC DFR: %08x\n", v);
996 v = apic_read(APIC_SPIV);
997 printk(KERN_DEBUG "... APIC SPIV: %08x\n", v);
999 printk(KERN_DEBUG "... APIC ISR field:\n");
1000 print_APIC_bitfield(APIC_ISR);
1001 printk(KERN_DEBUG "... APIC TMR field:\n");
1002 print_APIC_bitfield(APIC_TMR);
1003 printk(KERN_DEBUG "... APIC IRR field:\n");
1004 print_APIC_bitfield(APIC_IRR);
1006 if (APIC_INTEGRATED(ver)) { /* !82489DX */
1007 if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */
1008 apic_write(APIC_ESR, 0);
1009 v = apic_read(APIC_ESR);
1010 printk(KERN_DEBUG "... APIC ESR: %08x\n", v);
1013 v = apic_read(APIC_ICR);
1014 printk(KERN_DEBUG "... APIC ICR: %08x\n", v);
1015 v = apic_read(APIC_ICR2);
1016 printk(KERN_DEBUG "... APIC ICR2: %08x\n", v);
1018 v = apic_read(APIC_LVTT);
1019 printk(KERN_DEBUG "... APIC LVTT: %08x\n", v);
1021 if (maxlvt > 3) { /* PC is LVT#4. */
1022 v = apic_read(APIC_LVTPC);
1023 printk(KERN_DEBUG "... APIC LVTPC: %08x\n", v);
1025 v = apic_read(APIC_LVT0);
1026 printk(KERN_DEBUG "... APIC LVT0: %08x\n", v);
1027 v = apic_read(APIC_LVT1);
1028 printk(KERN_DEBUG "... APIC LVT1: %08x\n", v);
1030 if (maxlvt > 2) { /* ERR is LVT#3. */
1031 v = apic_read(APIC_LVTERR);
1032 printk(KERN_DEBUG "... APIC LVTERR: %08x\n", v);
1035 v = apic_read(APIC_TMICT);
1036 printk(KERN_DEBUG "... APIC TMICT: %08x\n", v);
1037 v = apic_read(APIC_TMCCT);
1038 printk(KERN_DEBUG "... APIC TMCCT: %08x\n", v);
1039 v = apic_read(APIC_TDCR);
1040 printk(KERN_DEBUG "... APIC TDCR: %08x\n", v);
1044 void print_all_local_APICs (void)
1046 on_each_cpu(print_local_APIC, NULL, 1, 1);
1049 void /*__init*/ print_PIC(void)
1051 extern spinlock_t i8259A_lock;
1053 unsigned long flags;
1055 printk(KERN_DEBUG "\nprinting PIC contents\n");
1057 spin_lock_irqsave(&i8259A_lock, flags);
1059 v = inb(0xa1) << 8 | inb(0x21);
1060 printk(KERN_DEBUG "... PIC IMR: %04x\n", v);
1062 v = inb(0xa0) << 8 | inb(0x20);
1063 printk(KERN_DEBUG "... PIC IRR: %04x\n", v);
1067 v = inb(0xa0) << 8 | inb(0x20);
1071 spin_unlock_irqrestore(&i8259A_lock, flags);
1073 printk(KERN_DEBUG "... PIC ISR: %04x\n", v);
1075 v = inb(0x4d1) << 8 | inb(0x4d0);
1076 printk(KERN_DEBUG "... PIC ELCR: %04x\n", v);
1079 static void __init enable_IO_APIC(void)
1081 union IO_APIC_reg_01 reg_01;
1083 unsigned long flags;
1085 for (i = 0; i < PIN_MAP_SIZE; i++) {
1086 irq_2_pin[i].pin = -1;
1087 irq_2_pin[i].next = 0;
1090 for (i = 0; i < MAX_PIRQS; i++)
1091 pirq_entries[i] = -1;
1094 * The number of IO-APIC IRQ registers (== #pins):
1096 for (i = 0; i < nr_ioapics; i++) {
1097 spin_lock_irqsave(&ioapic_lock, flags);
1098 reg_01.raw = io_apic_read(i, 1);
1099 spin_unlock_irqrestore(&ioapic_lock, flags);
1100 nr_ioapic_registers[i] = reg_01.bits.entries+1;
1104 * Do not trust the IO-APIC being empty at bootup
1110 * Not an __init, needed by the reboot code
1112 void disable_IO_APIC(void)
1115 * Clear the IO-APIC before rebooting:
1119 disconnect_bsp_APIC();
1123 * function to set the IO-APIC physical IDs based on the
1124 * values stored in the MPC table.
1126 * by Matt Domsch <Matt_Domsch@dell.com> Tue Dec 21 12:25:05 CST 1999
1129 static void __init setup_ioapic_ids_from_mpc (void)
1131 union IO_APIC_reg_00 reg_00;
1132 physid_mask_t phys_id_present_map = phys_cpu_present_map;
1135 unsigned char old_id;
1136 unsigned long flags;
1139 * Set the IOAPIC ID to the value stored in the MPC table.
1141 for (apic = 0; apic < nr_ioapics; apic++) {
1143 /* Read the register 0 value */
1144 spin_lock_irqsave(&ioapic_lock, flags);
1145 reg_00.raw = io_apic_read(apic, 0);
1146 spin_unlock_irqrestore(&ioapic_lock, flags);
1148 old_id = mp_ioapics[apic].mpc_apicid;
1150 if (mp_ioapics[apic].mpc_apicid >= 0xf) {
1151 printk(KERN_ERR "BIOS bug, IO-APIC#%d ID is %d in the MPC table!...\n",
1152 apic, mp_ioapics[apic].mpc_apicid);
1153 printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n",
1155 mp_ioapics[apic].mpc_apicid = reg_00.bits.ID;
1159 * Sanity check, is the ID really free? Every APIC in a
1160 * system must have a unique ID or we get lots of nice
1161 * 'stuck on smp_invalidate_needed IPI wait' messages.
1163 if (physid_isset(mp_ioapics[apic].mpc_apicid, phys_id_present_map)) {
1164 printk(KERN_ERR "BIOS bug, IO-APIC#%d ID %d is already used!...\n",
1165 apic, mp_ioapics[apic].mpc_apicid);
1166 for (i = 0; i < 0xf; i++)
1167 if (!physid_isset(i, phys_id_present_map))
1170 panic("Max APIC ID exceeded!\n");
1171 printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n",
1173 physid_set(i, phys_id_present_map);
1174 mp_ioapics[apic].mpc_apicid = i;
1177 "Using IO-APIC %d\n", mp_ioapics[apic].mpc_apicid);
1178 physid_set(mp_ioapics[apic].mpc_apicid, phys_id_present_map);
1183 * We need to adjust the IRQ routing table
1184 * if the ID changed.
1186 if (old_id != mp_ioapics[apic].mpc_apicid)
1187 for (i = 0; i < mp_irq_entries; i++)
1188 if (mp_irqs[i].mpc_dstapic == old_id)
1189 mp_irqs[i].mpc_dstapic
1190 = mp_ioapics[apic].mpc_apicid;
1193 * Read the right value from the MPC table and
1194 * write it into the ID register.
1196 printk(KERN_INFO "...changing IO-APIC physical APIC ID to %d ...",
1197 mp_ioapics[apic].mpc_apicid);
1199 reg_00.bits.ID = mp_ioapics[apic].mpc_apicid;
1200 spin_lock_irqsave(&ioapic_lock, flags);
1201 io_apic_write(apic, 0, reg_00.raw);
1202 spin_unlock_irqrestore(&ioapic_lock, flags);
1207 spin_lock_irqsave(&ioapic_lock, flags);
1208 reg_00.raw = io_apic_read(apic, 0);
1209 spin_unlock_irqrestore(&ioapic_lock, flags);
1210 if (reg_00.bits.ID != mp_ioapics[apic].mpc_apicid)
1211 panic("could not set ID!\n");
1218 * There is a nasty bug in some older SMP boards, their mptable lies
1219 * about the timer IRQ. We do the following to work around the situation:
1221 * - timer IRQ defaults to IO-APIC IRQ
1222 * - if this function detects that timer IRQs are defunct, then we fall
1223 * back to ISA timer IRQs
1225 static int __init timer_irq_works(void)
1227 unsigned long t1 = jiffies;
1230 /* Let ten ticks pass... */
1231 mdelay((10 * 1000) / HZ);
1234 * Expect a few ticks at least, to be sure some possible
1235 * glue logic does not lock up after one or two first
1236 * ticks in a non-ExtINT mode. Also the local APIC
1237 * might have cached one ExtINT interrupt. Finally, at
1238 * least one tick may be lost due to delays.
1242 if (jiffies - t1 > 4)
1248 * In the SMP+IOAPIC case it might happen that there are an unspecified
1249 * number of pending IRQ events unhandled. These cases are very rare,
1250 * so we 'resend' these IRQs via IPIs, to the same CPU. It's much
1251 * better to do it this way as thus we do not have to be aware of
1252 * 'pending' interrupts in the IRQ path, except at this point.
1255 * Edge triggered needs to resend any interrupt
1256 * that was delayed but this is now handled in the device
1261 * Starting up a edge-triggered IO-APIC interrupt is
1262 * nasty - we need to make sure that we get the edge.
1263 * If it is already asserted for some reason, we need
1264 * return 1 to indicate that is was pending.
1266 * This is not complete - we should be able to fake
1267 * an edge even if it isn't on the 8259A...
1270 static unsigned int startup_edge_ioapic_irq(unsigned int irq)
1272 int was_pending = 0;
1273 unsigned long flags;
1275 spin_lock_irqsave(&ioapic_lock, flags);
1277 disable_8259A_irq(irq);
1278 if (i8259A_irq_pending(irq))
1281 __unmask_IO_APIC_irq(irq);
1282 spin_unlock_irqrestore(&ioapic_lock, flags);
1288 * Once we have recorded IRQ_PENDING already, we can mask the
1289 * interrupt for real. This prevents IRQ storms from unhandled
1292 static void ack_edge_ioapic_irq(unsigned int irq)
1294 if ((irq_desc[irq].status & (IRQ_PENDING | IRQ_DISABLED))
1295 == (IRQ_PENDING | IRQ_DISABLED))
1296 mask_IO_APIC_irq(irq);
1301 * Level triggered interrupts can just be masked,
1302 * and shutting down and starting up the interrupt
1303 * is the same as enabling and disabling them -- except
1304 * with a startup need to return a "was pending" value.
1306 * Level triggered interrupts are special because we
1307 * do not touch any IO-APIC register while handling
1308 * them. We ack the APIC in the end-IRQ handler, not
1309 * in the start-IRQ-handler. Protection against reentrance
1310 * from the same interrupt is still provided, both by the
1311 * generic IRQ layer and by the fact that an unacked local
1312 * APIC does not accept IRQs.
1314 static unsigned int startup_level_ioapic_irq (unsigned int irq)
1316 unmask_IO_APIC_irq(irq);
1318 return 0; /* don't check for pending */
1321 static void end_level_ioapic_irq (unsigned int irq)
1327 * It appears there is an erratum which affects at least version 0x11
1328 * of I/O APIC (that's the 82093AA and cores integrated into various
1329 * chipsets). Under certain conditions a level-triggered interrupt is
1330 * erroneously delivered as edge-triggered one but the respective IRR
1331 * bit gets set nevertheless. As a result the I/O unit expects an EOI
1332 * message but it will never arrive and further interrupts are blocked
1333 * from the source. The exact reason is so far unknown, but the
1334 * phenomenon was observed when two consecutive interrupt requests
1335 * from a given source get delivered to the same CPU and the source is
1336 * temporarily disabled in between.
1338 * A workaround is to simulate an EOI message manually. We achieve it
1339 * by setting the trigger mode to edge and then to level when the edge
1340 * trigger mode gets detected in the TMR of a local APIC for a
1341 * level-triggered interrupt. We mask the source for the time of the
1342 * operation to prevent an edge-triggered interrupt escaping meanwhile.
1343 * The idea is from Manfred Spraul. --macro
1345 i = IO_APIC_VECTOR(irq);
1346 v = apic_read(APIC_TMR + ((i & ~0x1f) >> 1));
1350 if (!(v & (1 << (i & 0x1f)))) {
1351 #ifdef APIC_LOCKUP_DEBUG
1352 struct irq_pin_list *entry;
1355 #ifdef APIC_MISMATCH_DEBUG
1356 atomic_inc(&irq_mis_count);
1358 spin_lock(&ioapic_lock);
1359 __mask_and_edge_IO_APIC_irq(irq);
1360 #ifdef APIC_LOCKUP_DEBUG
1361 for (entry = irq_2_pin + irq;;) {
1364 if (entry->pin == -1)
1366 reg = io_apic_read(entry->apic, 0x10 + entry->pin * 2);
1367 if (reg & 0x00004000)
1368 printk(KERN_CRIT "Aieee!!! Remote IRR"
1369 " still set after unlock!\n");
1372 entry = irq_2_pin + entry->next;
1375 __unmask_and_level_IO_APIC_irq(irq);
1376 spin_unlock(&ioapic_lock);
1380 static void set_ioapic_affinity_irq(unsigned int irq, cpumask_t mask)
1382 unsigned long flags;
1385 dest = cpu_mask_to_apicid(mk_cpumask_const(mask));
1388 * Only the first 8 bits are valid.
1392 spin_lock_irqsave(&ioapic_lock, flags);
1393 __DO_ACTION(1, = dest, )
1394 spin_unlock_irqrestore(&ioapic_lock, flags);
1397 #ifdef CONFIG_PCI_USE_VECTOR
1398 static unsigned int startup_edge_ioapic_vector(unsigned int vector)
1400 int irq = vector_to_irq(vector);
1402 return startup_edge_ioapic_irq(irq);
1405 static void ack_edge_ioapic_vector(unsigned int vector)
1407 int irq = vector_to_irq(vector);
1409 ack_edge_ioapic_irq(irq);
1412 static unsigned int startup_level_ioapic_vector (unsigned int vector)
1414 int irq = vector_to_irq(vector);
1416 return startup_level_ioapic_irq (irq);
1419 static void end_level_ioapic_vector (unsigned int vector)
1421 int irq = vector_to_irq(vector);
1423 end_level_ioapic_irq(irq);
1426 static void mask_IO_APIC_vector (unsigned int vector)
1428 int irq = vector_to_irq(vector);
1430 mask_IO_APIC_irq(irq);
1433 static void unmask_IO_APIC_vector (unsigned int vector)
1435 int irq = vector_to_irq(vector);
1437 unmask_IO_APIC_irq(irq);
1440 static void set_ioapic_affinity_vector (unsigned int vector,
1443 int irq = vector_to_irq(vector);
1445 set_ioapic_affinity_irq(irq, cpu_mask);
1450 * Level and edge triggered IO-APIC interrupts need different handling,
1451 * so we use two separate IRQ descriptors. Edge triggered IRQs can be
1452 * handled with the level-triggered descriptor, but that one has slightly
1453 * more overhead. Level-triggered interrupts cannot be handled with the
1454 * edge-triggered handler, without risking IRQ storms and other ugly
1458 static struct hw_interrupt_type ioapic_edge_type = {
1459 .typename = "IO-APIC-edge",
1460 .startup = startup_edge_ioapic,
1461 .shutdown = shutdown_edge_ioapic,
1462 .enable = enable_edge_ioapic,
1463 .disable = disable_edge_ioapic,
1464 .ack = ack_edge_ioapic,
1465 .end = end_edge_ioapic,
1466 .set_affinity = set_ioapic_affinity,
1469 static struct hw_interrupt_type ioapic_level_type = {
1470 .typename = "IO-APIC-level",
1471 .startup = startup_level_ioapic,
1472 .shutdown = shutdown_level_ioapic,
1473 .enable = enable_level_ioapic,
1474 .disable = disable_level_ioapic,
1475 .ack = mask_and_ack_level_ioapic,
1476 .end = end_level_ioapic,
1477 .set_affinity = set_ioapic_affinity,
1480 static inline void init_IO_APIC_traps(void)
1485 * NOTE! The local APIC isn't very good at handling
1486 * multiple interrupts at the same interrupt level.
1487 * As the interrupt level is determined by taking the
1488 * vector number and shifting that right by 4, we
1489 * want to spread these out a bit so that they don't
1490 * all fall in the same interrupt level.
1492 * Also, we've got to be careful not to trash gate
1493 * 0x80, because int 0x80 is hm, kind of importantish. ;)
1495 for (irq = 0; irq < NR_IRQS ; irq++) {
1497 if (use_pci_vector()) {
1498 if (!platform_legacy_irq(tmp))
1499 if ((tmp = vector_to_irq(tmp)) == -1)
1502 if (IO_APIC_IRQ(tmp) && !IO_APIC_VECTOR(tmp)) {
1504 * Hmm.. We don't have an entry for this,
1505 * so default to an old-fashioned 8259
1506 * interrupt if we can..
1509 make_8259A_irq(irq);
1511 /* Strange. Oh, well.. */
1512 irq_desc[irq].handler = &no_irq_type;
1517 static void enable_lapic_irq (unsigned int irq)
1521 v = apic_read(APIC_LVT0);
1522 apic_write_around(APIC_LVT0, v & ~APIC_LVT_MASKED);
1525 static void disable_lapic_irq (unsigned int irq)
1529 v = apic_read(APIC_LVT0);
1530 apic_write_around(APIC_LVT0, v | APIC_LVT_MASKED);
1533 static void ack_lapic_irq (unsigned int irq)
1538 static void end_lapic_irq (unsigned int i) { /* nothing */ }
1540 static struct hw_interrupt_type lapic_irq_type = {
1541 .typename = "local-APIC-edge",
1542 .startup = NULL, /* startup_irq() not used for IRQ0 */
1543 .shutdown = NULL, /* shutdown_irq() not used for IRQ0 */
1544 .enable = enable_lapic_irq,
1545 .disable = disable_lapic_irq,
1546 .ack = ack_lapic_irq,
1547 .end = end_lapic_irq,
1550 static void setup_nmi (void)
1553 * Dirty trick to enable the NMI watchdog ...
1554 * We put the 8259A master into AEOI mode and
1555 * unmask on all local APICs LVT0 as NMI.
1557 * The idea to use the 8259A in AEOI mode ('8259A Virtual Wire')
1558 * is from Maciej W. Rozycki - so we do not have to EOI from
1559 * the NMI handler or the timer interrupt.
1561 printk(KERN_INFO "activating NMI Watchdog ...");
1563 enable_NMI_through_LVT0(NULL);
1569 * This looks a bit hackish but it's about the only one way of sending
1570 * a few INTA cycles to 8259As and any associated glue logic. ICR does
1571 * not support the ExtINT mode, unfortunately. We need to send these
1572 * cycles as some i82489DX-based boards have glue logic that keeps the
1573 * 8259A interrupt line asserted until INTA. --macro
1575 static inline void unlock_ExtINT_logic(void)
1578 struct IO_APIC_route_entry entry0, entry1;
1579 unsigned char save_control, save_freq_select;
1580 unsigned long flags;
1582 pin = find_isa_irq_pin(8, mp_INT);
1586 spin_lock_irqsave(&ioapic_lock, flags);
1587 *(((int *)&entry0) + 1) = io_apic_read(0, 0x11 + 2 * pin);
1588 *(((int *)&entry0) + 0) = io_apic_read(0, 0x10 + 2 * pin);
1589 spin_unlock_irqrestore(&ioapic_lock, flags);
1590 clear_IO_APIC_pin(0, pin);
1592 memset(&entry1, 0, sizeof(entry1));
1594 entry1.dest_mode = 0; /* physical delivery */
1595 entry1.mask = 0; /* unmask IRQ now */
1596 entry1.dest.physical.physical_dest = hard_smp_processor_id();
1597 entry1.delivery_mode = dest_ExtINT;
1598 entry1.polarity = entry0.polarity;
1602 spin_lock_irqsave(&ioapic_lock, flags);
1603 io_apic_write(0, 0x11 + 2 * pin, *(((int *)&entry1) + 1));
1604 io_apic_write(0, 0x10 + 2 * pin, *(((int *)&entry1) + 0));
1605 spin_unlock_irqrestore(&ioapic_lock, flags);
1607 save_control = CMOS_READ(RTC_CONTROL);
1608 save_freq_select = CMOS_READ(RTC_FREQ_SELECT);
1609 CMOS_WRITE((save_freq_select & ~RTC_RATE_SELECT) | 0x6,
1611 CMOS_WRITE(save_control | RTC_PIE, RTC_CONTROL);
1616 if ((CMOS_READ(RTC_INTR_FLAGS) & RTC_PF) == RTC_PF)
1620 CMOS_WRITE(save_control, RTC_CONTROL);
1621 CMOS_WRITE(save_freq_select, RTC_FREQ_SELECT);
1622 clear_IO_APIC_pin(0, pin);
1624 spin_lock_irqsave(&ioapic_lock, flags);
1625 io_apic_write(0, 0x11 + 2 * pin, *(((int *)&entry0) + 1));
1626 io_apic_write(0, 0x10 + 2 * pin, *(((int *)&entry0) + 0));
1627 spin_unlock_irqrestore(&ioapic_lock, flags);
1631 * This code may look a bit paranoid, but it's supposed to cooperate with
1632 * a wide range of boards and BIOS bugs. Fortunately only the timer IRQ
1633 * is so screwy. Thanks to Brian Perkins for testing/hacking this beast
1634 * fanatically on his truly buggy board.
1636 static inline void check_timer(void)
1642 * get/set the timer IRQ vector:
1644 disable_8259A_irq(0);
1645 vector = assign_irq_vector(0);
1646 set_intr_gate(vector, interrupt[0]);
1649 * Subtle, code in do_timer_interrupt() expects an AEOI
1650 * mode for the 8259A whenever interrupts are routed
1651 * through I/O APICs. Also IRQ0 has to be enabled in
1652 * the 8259A which implies the virtual wire has to be
1653 * disabled in the local APIC.
1655 apic_write_around(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT);
1657 enable_8259A_irq(0);
1659 pin1 = find_isa_irq_pin(0, mp_INT);
1660 pin2 = find_isa_irq_pin(0, mp_ExtINT);
1662 printk(KERN_INFO "..TIMER: vector=0x%02X pin1=%d pin2=%d\n", vector, pin1, pin2);
1666 * Ok, does IRQ0 through the IOAPIC work?
1668 unmask_IO_APIC_irq(0);
1669 if (timer_irq_works()) {
1670 nmi_watchdog_default();
1671 if (nmi_watchdog == NMI_IO_APIC) {
1672 disable_8259A_irq(0);
1674 enable_8259A_irq(0);
1675 check_nmi_watchdog();
1679 clear_IO_APIC_pin(0, pin1);
1680 printk(KERN_ERR "..MP-BIOS bug: 8254 timer not connected to IO-APIC\n");
1683 printk(KERN_INFO "...trying to set up timer (IRQ0) through the 8259A ... ");
1685 printk("\n..... (found pin %d) ...", pin2);
1687 * legacy devices should be connected to IO APIC #0
1689 setup_ExtINT_IRQ0_pin(pin2, vector);
1690 if (timer_irq_works()) {
1692 nmi_watchdog_default();
1693 if (nmi_watchdog == NMI_IO_APIC) {
1695 check_nmi_watchdog();
1700 * Cleanup, just in case ...
1702 clear_IO_APIC_pin(0, pin2);
1704 printk(" failed.\n");
1707 printk(KERN_WARNING "timer doesn't work through the IO-APIC - disabling NMI Watchdog!\n");
1711 printk(KERN_INFO "...trying to set up timer as Virtual Wire IRQ...");
1713 disable_8259A_irq(0);
1714 irq_desc[0].handler = &lapic_irq_type;
1715 apic_write_around(APIC_LVT0, APIC_DM_FIXED | vector); /* Fixed mode */
1716 enable_8259A_irq(0);
1718 if (timer_irq_works()) {
1719 printk(" works.\n");
1722 apic_write_around(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_FIXED | vector);
1723 printk(" failed.\n");
1725 printk(KERN_INFO "...trying to set up timer as ExtINT IRQ...");
1729 apic_write_around(APIC_LVT0, APIC_DM_EXTINT);
1731 unlock_ExtINT_logic();
1733 if (timer_irq_works()) {
1734 printk(" works.\n");
1737 printk(" failed :(.\n");
1738 panic("IO-APIC + timer doesn't work! pester mingo@redhat.com");
1743 * IRQ's that are handled by the PIC in the MPS IOAPIC case.
1744 * - IRQ2 is the cascade IRQ, and cannot be a io-apic IRQ.
1745 * Linux doesn't really care, as it's not actually used
1746 * for any interrupt handling anyway.
1748 #define PIC_IRQS (1<<2)
1750 void __init setup_IO_APIC(void)
1755 io_apic_irqs = ~0; /* all IRQs go through IOAPIC */
1757 io_apic_irqs = ~PIC_IRQS;
1759 printk("ENABLING IO-APIC IRQs\n");
1762 * Set up the IO-APIC IRQ routing table.
1765 setup_ioapic_ids_from_mpc();
1767 setup_IO_APIC_irqs();
1768 init_IO_APIC_traps();
1774 /* --------------------------------------------------------------------------
1775 ACPI-based IOAPIC Configuration
1776 -------------------------------------------------------------------------- */
1778 #ifdef CONFIG_ACPI_BOOT
1780 #define IO_APIC_MAX_ID 15
1782 int __init io_apic_get_unique_id (int ioapic, int apic_id)
1784 union IO_APIC_reg_00 reg_00;
1785 static physid_mask_t apic_id_map;
1786 unsigned long flags;
1790 * The P4 platform supports up to 256 APIC IDs on two separate APIC
1791 * buses (one for LAPICs, one for IOAPICs), where predecessors only
1792 * supports up to 16 on one shared APIC bus.
1794 * TBD: Expand LAPIC/IOAPIC support on P4-class systems to take full
1795 * advantage of new APIC bus architecture.
1798 if (physids_empty(apic_id_map))
1799 apic_id_map = phys_cpu_present_map;
1801 spin_lock_irqsave(&ioapic_lock, flags);
1802 reg_00.raw = io_apic_read(ioapic, 0);
1803 spin_unlock_irqrestore(&ioapic_lock, flags);
1805 if (apic_id >= IO_APIC_MAX_ID) {
1806 printk(KERN_WARNING "IOAPIC[%d]: Invalid apic_id %d, trying "
1807 "%d\n", ioapic, apic_id, reg_00.bits.ID);
1808 apic_id = reg_00.bits.ID;
1812 * Every APIC in a system must have a unique ID or we get lots of nice
1813 * 'stuck on smp_invalidate_needed IPI wait' messages.
1815 if (physid_isset(apic_id, apic_id_map)) {
1817 for (i = 0; i < IO_APIC_MAX_ID; i++) {
1818 if (!physid_isset(i, apic_id_map))
1822 if (i == IO_APIC_MAX_ID)
1823 panic("Max apic_id exceeded!\n");
1825 printk(KERN_WARNING "IOAPIC[%d]: apic_id %d already used, "
1826 "trying %d\n", ioapic, apic_id, i);
1831 physid_set(apic_id, apic_id_map);
1833 if (reg_00.bits.ID != apic_id) {
1834 reg_00.bits.ID = apic_id;
1836 spin_lock_irqsave(&ioapic_lock, flags);
1837 io_apic_write(ioapic, 0, reg_00.raw);
1838 reg_00.raw = io_apic_read(ioapic, 0);
1839 spin_unlock_irqrestore(&ioapic_lock, flags);
1842 if (reg_00.bits.ID != apic_id)
1843 panic("IOAPIC[%d]: Unable change apic_id!\n", ioapic);
1846 printk(KERN_INFO "IOAPIC[%d]: Assigned apic_id %d\n", ioapic, apic_id);
1852 int __init io_apic_get_version (int ioapic)
1854 union IO_APIC_reg_01 reg_01;
1855 unsigned long flags;
1857 spin_lock_irqsave(&ioapic_lock, flags);
1858 reg_01.raw = io_apic_read(ioapic, 1);
1859 spin_unlock_irqrestore(&ioapic_lock, flags);
1861 return reg_01.bits.version;
1865 int __init io_apic_get_redir_entries (int ioapic)
1867 union IO_APIC_reg_01 reg_01;
1868 unsigned long flags;
1870 spin_lock_irqsave(&ioapic_lock, flags);
1871 reg_01.raw = io_apic_read(ioapic, 1);
1872 spin_unlock_irqrestore(&ioapic_lock, flags);
1874 return reg_01.bits.entries;
1878 int io_apic_set_pci_routing (int ioapic, int pin, int irq, int edge_level, int active_high_low)
1880 struct IO_APIC_route_entry entry;
1881 unsigned long flags;
1883 if (!IO_APIC_IRQ(irq)) {
1884 printk(KERN_ERR "IOAPIC[%d]: Invalid reference to IRQ 0\n",
1890 * Generate a PCI IRQ routing entry and program the IOAPIC accordingly.
1891 * Note that we mask (disable) IRQs now -- these get enabled when the
1892 * corresponding device driver registers for this IRQ.
1895 memset(&entry,0,sizeof(entry));
1897 entry.delivery_mode = dest_LowestPrio;
1898 entry.dest_mode = INT_DELIVERY_MODE;
1899 entry.dest.logical.logical_dest = TARGET_CPUS;
1900 entry.trigger = edge_level;
1901 entry.polarity = active_high_low;
1902 entry.mask = 1; /* Disabled (masked) */
1905 * IRQs < 16 are already in the irq_2_pin[] map
1908 add_pin_to_irq(irq, ioapic, pin);
1910 entry.vector = assign_irq_vector(irq);
1912 printk(KERN_DEBUG "IOAPIC[%d]: Set PCI routing entry (%d-%d -> 0x%x -> "
1913 "IRQ %d Mode:%i Active:%i)\n", ioapic,
1914 mp_ioapics[ioapic].mpc_apicid, pin, entry.vector, irq,
1915 edge_level, active_high_low);
1917 if (use_pci_vector() && !platform_legacy_irq(irq))
1918 irq = IO_APIC_VECTOR(irq);
1920 irq_desc[irq].handler = &ioapic_level_type;
1922 irq_desc[irq].handler = &ioapic_edge_type;
1925 set_intr_gate(entry.vector, interrupt[irq]);
1927 if (!ioapic && (irq < 16))
1928 disable_8259A_irq(irq);
1930 spin_lock_irqsave(&ioapic_lock, flags);
1931 io_apic_write(ioapic, 0x11+2*pin, *(((int *)&entry)+1));
1932 io_apic_write(ioapic, 0x10+2*pin, *(((int *)&entry)+0));
1933 spin_unlock_irqrestore(&ioapic_lock, flags);
1938 #endif /*CONFIG_ACPI_BOOT*/
1941 void send_IPI_self(int vector)
1948 apic_wait_icr_idle();
1949 cfg = APIC_DM_FIXED | APIC_DEST_SELF | vector | APIC_DEST_LOGICAL;
1952 * Send the IPI. The write to APIC_ICR fires this off.
1954 apic_write_around(APIC_ICR, cfg);