2 * Intel Multiprocessor Specification 1.1 and 1.4
3 * compliant MP-table parsing routines.
5 * (c) 1995 Alan Cox, Building #3 <alan@redhat.com>
6 * (c) 1998, 1999, 2000 Ingo Molnar <mingo@redhat.com>
9 * Erich Boleyn : MP v1.4 and additional changes.
10 * Alan Cox : Added EBDA scanning
11 * Ingo Molnar : various cleanups and rewrites
12 * Maciej W. Rozycki: Bits for default MP configurations
13 * Paul Diefenbaugh: Added full ACPI support
17 #include <linux/init.h>
18 #include <linux/delay.h>
19 #include <linux/config.h>
20 #include <linux/bootmem.h>
21 #include <linux/smp_lock.h>
22 #include <linux/kernel_stat.h>
23 #include <linux/mc146818rtc.h>
24 #include <linux/acpi.h>
25 #include <linux/module.h>
29 #include <asm/mpspec.h>
30 #include <asm/pgalloc.h>
31 #include <asm/io_apic.h>
32 #include <asm/proto.h>
35 /* Have we found an MP table */
37 unsigned int __initdata maxcpus = NR_CPUS;
42 * Various Linux-internal data structures created from the
45 unsigned char apic_version [MAX_APICS];
46 unsigned char mp_bus_id_to_type [MAX_MP_BUSSES] = { [0 ... MAX_MP_BUSSES-1] = -1 };
47 int mp_bus_id_to_pci_bus [MAX_MP_BUSSES] = { [0 ... MAX_MP_BUSSES-1] = -1 };
49 static int mp_current_pci_id = 0;
50 /* I/O APIC entries */
51 struct mpc_config_ioapic mp_ioapics[MAX_IO_APICS];
53 /* # of MP IRQ source entries */
54 struct mpc_config_intsrc mp_irqs[MAX_IRQ_SOURCES];
56 /* MP IRQ source entries */
61 unsigned long mp_lapic_addr = 0;
65 /* Processor that is doing the boot up */
66 unsigned int boot_cpu_id = -1U;
67 /* Internal processor count */
68 unsigned int num_processors __initdata = 0;
70 unsigned disabled_cpus __initdata;
72 /* Bitmask of physically existing CPUs */
73 physid_mask_t phys_cpu_present_map = PHYSID_MASK_NONE;
75 /* ACPI MADT entry parsing functions */
77 extern struct acpi_boot_flags acpi_boot;
78 #ifdef CONFIG_X86_LOCAL_APIC
79 extern int acpi_parse_lapic (acpi_table_entry_header *header);
80 extern int acpi_parse_lapic_addr_ovr (acpi_table_entry_header *header);
81 extern int acpi_parse_lapic_nmi (acpi_table_entry_header *header);
82 #endif /*CONFIG_X86_LOCAL_APIC*/
83 #ifdef CONFIG_X86_IO_APIC
84 extern int acpi_parse_ioapic (acpi_table_entry_header *header);
85 #endif /*CONFIG_X86_IO_APIC*/
86 #endif /*CONFIG_ACPI*/
88 u8 bios_cpu_apicid[NR_CPUS] = { [0 ... NR_CPUS-1] = BAD_APICID };
92 * Intel MP BIOS table parsing routines:
96 * Checksum an MP configuration block.
99 static int __init mpf_checksum(unsigned char *mp, int len)
110 static void __cpuinit MP_processor_info (struct mpc_config_processor *m)
116 if (!(m->mpc_cpuflag & CPU_ENABLED)) {
121 printk(KERN_INFO "Processor #%d %d:%d APIC version %d\n",
123 (m->mpc_cpufeature & CPU_FAMILY_MASK)>>8,
124 (m->mpc_cpufeature & CPU_MODEL_MASK)>>4,
127 if (m->mpc_cpuflag & CPU_BOOTPROCESSOR) {
128 Dprintk(" Bootup CPU\n");
129 boot_cpu_id = m->mpc_apicid;
131 if (num_processors >= NR_CPUS) {
132 printk(KERN_WARNING "WARNING: NR_CPUS limit of %i reached."
133 " Processor ignored.\n", NR_CPUS);
138 cpus_complement(tmp_map, cpu_present_map);
139 cpu = first_cpu(tmp_map);
142 if ((int)m->mpc_apicid > MAX_APICS) {
143 printk(KERN_ERR "Processor #%d INVALID. (Max ID: %d).\n",
144 m->mpc_apicid, MAX_APICS);
148 ver = m->mpc_apicver;
150 physid_set(m->mpc_apicid, phys_cpu_present_map);
155 printk(KERN_ERR "BIOS bug, APIC version is 0 for CPU#%d! fixing up to 0x10. (tell your hw vendor)\n", m->mpc_apicid);
158 apic_version[m->mpc_apicid] = ver;
159 if (m->mpc_cpuflag & CPU_BOOTPROCESSOR) {
161 * bios_cpu_apicid is required to have processors listed
162 * in same order as logical cpu numbers. Hence the first
163 * entry is BSP, and so on.
167 bios_cpu_apicid[cpu] = m->mpc_apicid;
168 x86_cpu_to_apicid[cpu] = m->mpc_apicid;
170 cpu_set(cpu, cpu_possible_map);
171 cpu_set(cpu, cpu_present_map);
174 void __init MP_processor_info (struct mpc_config_processor *m)
178 #endif /* CONFIG_XEN */
180 static void __init MP_bus_info (struct mpc_config_bus *m)
184 memcpy(str, m->mpc_bustype, 6);
186 Dprintk("Bus #%d is %s\n", m->mpc_busid, str);
188 if (strncmp(str, "ISA", 3) == 0) {
189 mp_bus_id_to_type[m->mpc_busid] = MP_BUS_ISA;
190 } else if (strncmp(str, "EISA", 4) == 0) {
191 mp_bus_id_to_type[m->mpc_busid] = MP_BUS_EISA;
192 } else if (strncmp(str, "PCI", 3) == 0) {
193 mp_bus_id_to_type[m->mpc_busid] = MP_BUS_PCI;
194 mp_bus_id_to_pci_bus[m->mpc_busid] = mp_current_pci_id;
196 } else if (strncmp(str, "MCA", 3) == 0) {
197 mp_bus_id_to_type[m->mpc_busid] = MP_BUS_MCA;
199 printk(KERN_ERR "Unknown bustype %s\n", str);
203 static void __init MP_ioapic_info (struct mpc_config_ioapic *m)
205 if (!(m->mpc_flags & MPC_APIC_USABLE))
208 printk("I/O APIC #%d Version %d at 0x%X.\n",
209 m->mpc_apicid, m->mpc_apicver, m->mpc_apicaddr);
210 if (nr_ioapics >= MAX_IO_APICS) {
211 printk(KERN_ERR "Max # of I/O APICs (%d) exceeded (found %d).\n",
212 MAX_IO_APICS, nr_ioapics);
213 panic("Recompile kernel with bigger MAX_IO_APICS!.\n");
215 if (!m->mpc_apicaddr) {
216 printk(KERN_ERR "WARNING: bogus zero I/O APIC address"
217 " found in MP table, skipping!\n");
220 mp_ioapics[nr_ioapics] = *m;
224 static void __init MP_intsrc_info (struct mpc_config_intsrc *m)
226 mp_irqs [mp_irq_entries] = *m;
227 Dprintk("Int: type %d, pol %d, trig %d, bus %d,"
228 " IRQ %02x, APIC ID %x, APIC INT %02x\n",
229 m->mpc_irqtype, m->mpc_irqflag & 3,
230 (m->mpc_irqflag >> 2) & 3, m->mpc_srcbus,
231 m->mpc_srcbusirq, m->mpc_dstapic, m->mpc_dstirq);
232 if (++mp_irq_entries >= MAX_IRQ_SOURCES)
233 panic("Max # of irq sources exceeded!!\n");
236 static void __init MP_lintsrc_info (struct mpc_config_lintsrc *m)
238 Dprintk("Lint: type %d, pol %d, trig %d, bus %d,"
239 " IRQ %02x, APIC ID %x, APIC LINT %02x\n",
240 m->mpc_irqtype, m->mpc_irqflag & 3,
241 (m->mpc_irqflag >> 2) &3, m->mpc_srcbusid,
242 m->mpc_srcbusirq, m->mpc_destapic, m->mpc_destapiclint);
244 * Well it seems all SMP boards in existence
245 * use ExtINT/LVT1 == LINT0 and
246 * NMI/LVT2 == LINT1 - the following check
247 * will show us if this assumptions is false.
248 * Until then we do not have to add baggage.
250 if ((m->mpc_irqtype == mp_ExtINT) &&
251 (m->mpc_destapiclint != 0))
253 if ((m->mpc_irqtype == mp_NMI) &&
254 (m->mpc_destapiclint != 1))
262 static int __init smp_read_mpc(struct mp_config_table *mpc)
265 int count=sizeof(*mpc);
266 unsigned char *mpt=((unsigned char *)mpc)+count;
268 if (memcmp(mpc->mpc_signature,MPC_SIGNATURE,4)) {
269 printk("SMP mptable: bad signature [%c%c%c%c]!\n",
270 mpc->mpc_signature[0],
271 mpc->mpc_signature[1],
272 mpc->mpc_signature[2],
273 mpc->mpc_signature[3]);
276 if (mpf_checksum((unsigned char *)mpc,mpc->mpc_length)) {
277 printk("SMP mptable: checksum error!\n");
280 if (mpc->mpc_spec!=0x01 && mpc->mpc_spec!=0x04) {
281 printk(KERN_ERR "SMP mptable: bad table version (%d)!!\n",
285 if (!mpc->mpc_lapic) {
286 printk(KERN_ERR "SMP mptable: null local APIC address!\n");
289 memcpy(str,mpc->mpc_oem,8);
291 printk(KERN_INFO "OEM ID: %s ",str);
293 memcpy(str,mpc->mpc_productid,12);
295 printk("Product ID: %s ",str);
297 printk("APIC at: 0x%X\n",mpc->mpc_lapic);
299 /* save the local APIC address, it might be non-default */
301 mp_lapic_addr = mpc->mpc_lapic;
304 * Now process the configuration blocks.
306 while (count < mpc->mpc_length) {
310 struct mpc_config_processor *m=
311 (struct mpc_config_processor *)mpt;
313 MP_processor_info(m);
320 struct mpc_config_bus *m=
321 (struct mpc_config_bus *)mpt;
329 struct mpc_config_ioapic *m=
330 (struct mpc_config_ioapic *)mpt;
338 struct mpc_config_intsrc *m=
339 (struct mpc_config_intsrc *)mpt;
348 struct mpc_config_lintsrc *m=
349 (struct mpc_config_lintsrc *)mpt;
357 clustered_apic_check();
359 printk(KERN_ERR "SMP mptable: no processors registered!\n");
360 return num_processors;
363 static int __init ELCR_trigger(unsigned int irq)
367 port = 0x4d0 + (irq >> 3);
368 return (inb(port) >> (irq & 7)) & 1;
371 static void __init construct_default_ioirq_mptable(int mpc_default_type)
373 struct mpc_config_intsrc intsrc;
375 int ELCR_fallback = 0;
377 intsrc.mpc_type = MP_INTSRC;
378 intsrc.mpc_irqflag = 0; /* conforming */
379 intsrc.mpc_srcbus = 0;
380 intsrc.mpc_dstapic = mp_ioapics[0].mpc_apicid;
382 intsrc.mpc_irqtype = mp_INT;
385 * If true, we have an ISA/PCI system with no IRQ entries
386 * in the MP table. To prevent the PCI interrupts from being set up
387 * incorrectly, we try to use the ELCR. The sanity check to see if
388 * there is good ELCR data is very simple - IRQ0, 1, 2 and 13 can
389 * never be level sensitive, so we simply see if the ELCR agrees.
390 * If it does, we assume it's valid.
392 if (mpc_default_type == 5) {
393 printk(KERN_INFO "ISA/PCI bus type with no IRQ information... falling back to ELCR\n");
395 if (ELCR_trigger(0) || ELCR_trigger(1) || ELCR_trigger(2) || ELCR_trigger(13))
396 printk(KERN_ERR "ELCR contains invalid data... not using ELCR\n");
398 printk(KERN_INFO "Using ELCR to identify PCI interrupts\n");
403 for (i = 0; i < 16; i++) {
404 switch (mpc_default_type) {
406 if (i == 0 || i == 13)
407 continue; /* IRQ0 & IRQ13 not connected */
411 continue; /* IRQ2 is never connected */
416 * If the ELCR indicates a level-sensitive interrupt, we
417 * copy that information over to the MP table in the
418 * irqflag field (level sensitive, active high polarity).
421 intsrc.mpc_irqflag = 13;
423 intsrc.mpc_irqflag = 0;
426 intsrc.mpc_srcbusirq = i;
427 intsrc.mpc_dstirq = i ? i : 2; /* IRQ0 to INTIN2 */
428 MP_intsrc_info(&intsrc);
431 intsrc.mpc_irqtype = mp_ExtINT;
432 intsrc.mpc_srcbusirq = 0;
433 intsrc.mpc_dstirq = 0; /* 8259A to INTIN0 */
434 MP_intsrc_info(&intsrc);
437 static inline void __init construct_default_ISA_mptable(int mpc_default_type)
439 struct mpc_config_processor processor;
440 struct mpc_config_bus bus;
441 struct mpc_config_ioapic ioapic;
442 struct mpc_config_lintsrc lintsrc;
443 int linttypes[2] = { mp_ExtINT, mp_NMI };
447 * local APIC has default address
449 mp_lapic_addr = APIC_DEFAULT_PHYS_BASE;
452 * 2 CPUs, numbered 0 & 1.
454 processor.mpc_type = MP_PROCESSOR;
455 /* Either an integrated APIC or a discrete 82489DX. */
456 processor.mpc_apicver = mpc_default_type > 4 ? 0x10 : 0x01;
457 processor.mpc_cpuflag = CPU_ENABLED;
458 processor.mpc_cpufeature = (boot_cpu_data.x86 << 8) |
459 (boot_cpu_data.x86_model << 4) |
460 boot_cpu_data.x86_mask;
461 processor.mpc_featureflag = boot_cpu_data.x86_capability[0];
462 processor.mpc_reserved[0] = 0;
463 processor.mpc_reserved[1] = 0;
464 for (i = 0; i < 2; i++) {
465 processor.mpc_apicid = i;
466 MP_processor_info(&processor);
469 bus.mpc_type = MP_BUS;
471 switch (mpc_default_type) {
473 printk(KERN_ERR "???\nUnknown standard configuration %d\n",
478 memcpy(bus.mpc_bustype, "ISA ", 6);
483 memcpy(bus.mpc_bustype, "EISA ", 6);
487 memcpy(bus.mpc_bustype, "MCA ", 6);
490 if (mpc_default_type > 4) {
492 memcpy(bus.mpc_bustype, "PCI ", 6);
496 ioapic.mpc_type = MP_IOAPIC;
497 ioapic.mpc_apicid = 2;
498 ioapic.mpc_apicver = mpc_default_type > 4 ? 0x10 : 0x01;
499 ioapic.mpc_flags = MPC_APIC_USABLE;
500 ioapic.mpc_apicaddr = 0xFEC00000;
501 MP_ioapic_info(&ioapic);
504 * We set up most of the low 16 IO-APIC pins according to MPS rules.
506 construct_default_ioirq_mptable(mpc_default_type);
508 lintsrc.mpc_type = MP_LINTSRC;
509 lintsrc.mpc_irqflag = 0; /* conforming */
510 lintsrc.mpc_srcbusid = 0;
511 lintsrc.mpc_srcbusirq = 0;
512 lintsrc.mpc_destapic = MP_APIC_ALL;
513 for (i = 0; i < 2; i++) {
514 lintsrc.mpc_irqtype = linttypes[i];
515 lintsrc.mpc_destapiclint = i;
516 MP_lintsrc_info(&lintsrc);
520 static struct intel_mp_floating *mpf_found;
523 * Scan the memory blocks for an SMP configuration block.
525 void __init get_smp_config (void)
527 struct intel_mp_floating *mpf = mpf_found;
530 * ACPI supports both logical (e.g. Hyper-Threading) and physical
531 * processors, where MPS only supports physical.
533 if (acpi_lapic && acpi_ioapic) {
534 printk(KERN_INFO "Using ACPI (MADT) for SMP configuration information\n");
538 printk(KERN_INFO "Using ACPI for processor (LAPIC) configuration information\n");
540 printk("Intel MultiProcessor Specification v1.%d\n", mpf->mpf_specification);
541 if (mpf->mpf_feature2 & (1<<7)) {
542 printk(KERN_INFO " IMCR and PIC compatibility mode.\n");
545 printk(KERN_INFO " Virtual Wire compatibility mode.\n");
550 * Now see if we need to read further.
552 if (mpf->mpf_feature1 != 0) {
554 printk(KERN_INFO "Default MP configuration #%d\n", mpf->mpf_feature1);
555 construct_default_ISA_mptable(mpf->mpf_feature1);
557 } else if (mpf->mpf_physptr) {
560 * Read the physical hardware table. Anything here will
561 * override the defaults.
563 if (!smp_read_mpc(isa_bus_to_virt(mpf->mpf_physptr))) {
564 smp_found_config = 0;
565 printk(KERN_ERR "BIOS bug, MP table errors detected!...\n");
566 printk(KERN_ERR "... disabling SMP support. (tell your hw vendor)\n");
570 * If there are no explicit MP IRQ entries, then we are
571 * broken. We set up most of the low 16 IO-APIC pins to
572 * ISA defaults and hope it will work.
574 if (!mp_irq_entries) {
575 struct mpc_config_bus bus;
577 printk(KERN_ERR "BIOS bug, no explicit IRQ entries, using default mptable. (tell your hw vendor)\n");
579 bus.mpc_type = MP_BUS;
581 memcpy(bus.mpc_bustype, "ISA ", 6);
584 construct_default_ioirq_mptable(0);
590 printk(KERN_INFO "Processors: %d\n", num_processors);
592 * Only use the first configuration found.
596 static int __init smp_scan_config (unsigned long base, unsigned long length)
598 extern void __bad_mpf_size(void);
599 unsigned int *bp = isa_bus_to_virt(base);
600 struct intel_mp_floating *mpf;
602 Dprintk("Scan SMP from %p for %ld bytes.\n", bp,length);
603 if (sizeof(*mpf) != 16)
607 mpf = (struct intel_mp_floating *)bp;
608 if ((*bp == SMP_MAGIC_IDENT) &&
609 (mpf->mpf_length == 1) &&
610 !mpf_checksum((unsigned char *)bp, 16) &&
611 ((mpf->mpf_specification == 1)
612 || (mpf->mpf_specification == 4)) ) {
614 smp_found_config = 1;
624 void __init find_intel_smp (void)
626 unsigned int address;
629 * FIXME: Linux assumes you have 640K of base ram..
630 * this continues the error...
632 * 1) Scan the bottom 1K for a signature
633 * 2) Scan the top 1K of base RAM
634 * 3) Scan the 64K of bios
636 if (smp_scan_config(0x0,0x400) ||
637 smp_scan_config(639*0x400,0x400) ||
638 smp_scan_config(0xF0000,0x10000))
641 * If it is an SMP machine we should know now, unless the
642 * configuration is in an EISA/MCA bus machine with an
643 * extended bios data area.
645 * there is a real-mode segmented pointer pointing to the
646 * 4K EBDA area at 0x40E, calculate and scan it here.
648 * NOTE! There are Linux loaders that will corrupt the EBDA
649 * area, and as such this kind of SMP config may be less
650 * trustworthy, simply because the SMP table may have been
651 * stomped on during early boot. These loaders are buggy and
655 address = *(unsigned short *)phys_to_virt(0x40E);
657 if (smp_scan_config(address, 0x1000))
660 /* If we have come this far, we did not find an MP table */
661 printk(KERN_INFO "No mptable found.\n");
665 * - Intel MP Configuration Table
667 void __init find_smp_config (void)
669 #ifdef CONFIG_X86_LOCAL_APIC
675 /* --------------------------------------------------------------------------
676 ACPI-based MP Configuration
677 -------------------------------------------------------------------------- */
681 void __init mp_register_lapic_address (
685 mp_lapic_addr = (unsigned long) address;
687 set_fixmap_nocache(FIX_APIC_BASE, mp_lapic_addr);
689 if (boot_cpu_id == -1U)
690 boot_cpu_id = GET_APIC_ID(apic_read(APIC_ID));
692 Dprintk("Boot CPU = %d\n", boot_cpu_physical_apicid);
697 void __cpuinit mp_register_lapic (
701 struct mpc_config_processor processor;
704 if (id >= MAX_APICS) {
705 printk(KERN_WARNING "Processor #%d invalid (max %d)\n",
710 if (id == boot_cpu_physical_apicid)
714 processor.mpc_type = MP_PROCESSOR;
715 processor.mpc_apicid = id;
716 processor.mpc_apicver = GET_APIC_VERSION(apic_read(APIC_LVR));
717 processor.mpc_cpuflag = (enabled ? CPU_ENABLED : 0);
718 processor.mpc_cpuflag |= (boot_cpu ? CPU_BOOTPROCESSOR : 0);
719 processor.mpc_cpufeature = (boot_cpu_data.x86 << 8) |
720 (boot_cpu_data.x86_model << 4) | boot_cpu_data.x86_mask;
721 processor.mpc_featureflag = boot_cpu_data.x86_capability[0];
722 processor.mpc_reserved[0] = 0;
723 processor.mpc_reserved[1] = 0;
726 MP_processor_info(&processor);
729 #ifdef CONFIG_X86_IO_APIC
732 #define MP_MAX_IOAPIC_PIN 127
734 static struct mp_ioapic_routing {
738 u32 pin_programmed[4];
739 } mp_ioapic_routing[MAX_IO_APICS];
742 static int mp_find_ioapic (
747 /* Find the IOAPIC that manages this GSI. */
748 for (i = 0; i < nr_ioapics; i++) {
749 if ((gsi >= mp_ioapic_routing[i].gsi_start)
750 && (gsi <= mp_ioapic_routing[i].gsi_end))
754 printk(KERN_ERR "ERROR: Unable to locate IOAPIC for GSI %d\n", gsi);
760 void __init mp_register_ioapic (
767 if (nr_ioapics >= MAX_IO_APICS) {
768 printk(KERN_ERR "ERROR: Max # of I/O APICs (%d) exceeded "
769 "(found %d)\n", MAX_IO_APICS, nr_ioapics);
770 panic("Recompile kernel with bigger MAX_IO_APICS!\n");
773 printk(KERN_ERR "WARNING: Bogus (zero) I/O APIC address"
774 " found in MADT table, skipping!\n");
780 mp_ioapics[idx].mpc_type = MP_IOAPIC;
781 mp_ioapics[idx].mpc_flags = MPC_APIC_USABLE;
782 mp_ioapics[idx].mpc_apicaddr = address;
785 set_fixmap_nocache(FIX_IO_APIC_BASE_0 + idx, address);
787 mp_ioapics[idx].mpc_apicid = id;
788 mp_ioapics[idx].mpc_apicver = io_apic_get_version(idx);
791 * Build basic IRQ lookup table to facilitate gsi->io_apic lookups
792 * and to prevent reprogramming of IOAPIC pins (PCI IRQs).
794 mp_ioapic_routing[idx].apic_id = mp_ioapics[idx].mpc_apicid;
795 mp_ioapic_routing[idx].gsi_start = gsi_base;
796 mp_ioapic_routing[idx].gsi_end = gsi_base +
797 io_apic_get_redir_entries(idx);
799 printk(KERN_INFO "IOAPIC[%d]: apic_id %d, version %d, address 0x%x, "
800 "GSI %d-%d\n", idx, mp_ioapics[idx].mpc_apicid,
801 mp_ioapics[idx].mpc_apicver, mp_ioapics[idx].mpc_apicaddr,
802 mp_ioapic_routing[idx].gsi_start,
803 mp_ioapic_routing[idx].gsi_end);
809 void __init mp_override_legacy_irq (
815 struct mpc_config_intsrc intsrc;
820 * Convert 'gsi' to 'ioapic.pin'.
822 ioapic = mp_find_ioapic(gsi);
825 pin = gsi - mp_ioapic_routing[ioapic].gsi_start;
828 * TBD: This check is for faulty timer entries, where the override
829 * erroneously sets the trigger to level, resulting in a HUGE
830 * increase of timer interrupts!
832 if ((bus_irq == 0) && (trigger == 3))
835 intsrc.mpc_type = MP_INTSRC;
836 intsrc.mpc_irqtype = mp_INT;
837 intsrc.mpc_irqflag = (trigger << 2) | polarity;
838 intsrc.mpc_srcbus = MP_ISA_BUS;
839 intsrc.mpc_srcbusirq = bus_irq; /* IRQ */
840 intsrc.mpc_dstapic = mp_ioapics[ioapic].mpc_apicid; /* APIC ID */
841 intsrc.mpc_dstirq = pin; /* INTIN# */
843 Dprintk("Int: type %d, pol %d, trig %d, bus %d, irq %d, %d-%d\n",
844 intsrc.mpc_irqtype, intsrc.mpc_irqflag & 3,
845 (intsrc.mpc_irqflag >> 2) & 3, intsrc.mpc_srcbus,
846 intsrc.mpc_srcbusirq, intsrc.mpc_dstapic, intsrc.mpc_dstirq);
848 mp_irqs[mp_irq_entries] = intsrc;
849 if (++mp_irq_entries == MAX_IRQ_SOURCES)
850 panic("Max # of irq sources exceeded!\n");
856 void __init mp_config_acpi_legacy_irqs (void)
858 struct mpc_config_intsrc intsrc;
863 * Fabricate the legacy ISA bus (bus #31).
865 mp_bus_id_to_type[MP_ISA_BUS] = MP_BUS_ISA;
866 Dprintk("Bus #%d is ISA\n", MP_ISA_BUS);
869 * Locate the IOAPIC that manages the ISA IRQs (0-15).
871 ioapic = mp_find_ioapic(0);
875 intsrc.mpc_type = MP_INTSRC;
876 intsrc.mpc_irqflag = 0; /* Conforming */
877 intsrc.mpc_srcbus = MP_ISA_BUS;
878 intsrc.mpc_dstapic = mp_ioapics[ioapic].mpc_apicid;
881 * Use the default configuration for the IRQs 0-15. Unless
882 * overridden by (MADT) interrupt source override entries.
884 for (i = 0; i < 16; i++) {
887 for (idx = 0; idx < mp_irq_entries; idx++) {
888 struct mpc_config_intsrc *irq = mp_irqs + idx;
890 /* Do we already have a mapping for this ISA IRQ? */
891 if (irq->mpc_srcbus == MP_ISA_BUS && irq->mpc_srcbusirq == i)
894 /* Do we already have a mapping for this IOAPIC pin */
895 if ((irq->mpc_dstapic == intsrc.mpc_dstapic) &&
896 (irq->mpc_dstirq == i))
900 if (idx != mp_irq_entries) {
901 printk(KERN_DEBUG "ACPI: IRQ%d used by override.\n", i);
902 continue; /* IRQ already used */
905 intsrc.mpc_irqtype = mp_INT;
906 intsrc.mpc_srcbusirq = i; /* Identity mapped */
907 intsrc.mpc_dstirq = i;
909 Dprintk("Int: type %d, pol %d, trig %d, bus %d, irq %d, "
910 "%d-%d\n", intsrc.mpc_irqtype, intsrc.mpc_irqflag & 3,
911 (intsrc.mpc_irqflag >> 2) & 3, intsrc.mpc_srcbus,
912 intsrc.mpc_srcbusirq, intsrc.mpc_dstapic,
915 mp_irqs[mp_irq_entries] = intsrc;
916 if (++mp_irq_entries == MAX_IRQ_SOURCES)
917 panic("Max # of irq sources exceeded!\n");
923 #define MAX_GSI_NUM 4096
925 int mp_register_gsi(u32 gsi, int triggering, int polarity)
930 static int pci_irq = 16;
932 * Mapping between Global System Interrupts, which
933 * represent all possible interrupts, to the IRQs
934 * assigned to actual devices.
936 static int gsi_to_irq[MAX_GSI_NUM];
938 if (acpi_irq_model != ACPI_IRQ_MODEL_IOAPIC)
941 /* Don't set up the ACPI SCI because it's already set up */
942 if (acpi_fadt.sci_int == gsi)
945 ioapic = mp_find_ioapic(gsi);
947 printk(KERN_WARNING "No IOAPIC for GSI %u\n", gsi);
951 ioapic_pin = gsi - mp_ioapic_routing[ioapic].gsi_start;
954 * Avoid pin reprogramming. PRTs typically include entries
955 * with redundant pin->gsi mappings (but unique PCI devices);
956 * we only program the IOAPIC on the first.
958 bit = ioapic_pin % 32;
959 idx = (ioapic_pin < 32) ? 0 : (ioapic_pin / 32);
961 printk(KERN_ERR "Invalid reference to IOAPIC pin "
962 "%d-%d\n", mp_ioapic_routing[ioapic].apic_id,
966 if ((1<<bit) & mp_ioapic_routing[ioapic].pin_programmed[idx]) {
967 Dprintk(KERN_DEBUG "Pin %d-%d already programmed\n",
968 mp_ioapic_routing[ioapic].apic_id, ioapic_pin);
969 return gsi_to_irq[gsi];
972 mp_ioapic_routing[ioapic].pin_programmed[idx] |= (1<<bit);
974 if (triggering == ACPI_LEVEL_SENSITIVE) {
976 * For PCI devices assign IRQs in order, avoiding gaps
977 * due to unused I/O APIC pins.
980 if (gsi < MAX_GSI_NUM) {
982 * Retain the VIA chipset work-around (gsi > 15), but
983 * avoid a problem where the 8254 timer (IRQ0) is setup
984 * via an override (so it's not on pin 0 of the ioapic),
985 * and at the same time, the pin 0 interrupt is a PCI
986 * type. The gsi > 15 test could cause these two pins
987 * to be shared as IRQ0, and they are not shareable.
988 * So test for this condition, and if necessary, avoid
991 if (gsi > 15 || (gsi == 0 && !timer_uses_ioapic_pin_0))
994 * Don't assign IRQ used by ACPI SCI
996 if (gsi == acpi_fadt.sci_int)
998 gsi_to_irq[irq] = gsi;
1000 printk(KERN_ERR "GSI %u is too high\n", gsi);
1005 io_apic_set_pci_routing(ioapic, ioapic_pin, gsi,
1006 triggering == ACPI_EDGE_SENSITIVE ? 0 : 1,
1007 polarity == ACPI_ACTIVE_HIGH ? 0 : 1);
1011 #endif /*CONFIG_X86_IO_APIC*/
1012 #endif /*CONFIG_ACPI*/