2 * Intel Multiprocessor Specification 1.1 and 1.4
3 * compliant MP-table parsing routines.
5 * (c) 1995 Alan Cox, Building #3 <alan@redhat.com>
6 * (c) 1998, 1999, 2000 Ingo Molnar <mingo@redhat.com>
9 * Erich Boleyn : MP v1.4 and additional changes.
10 * Alan Cox : Added EBDA scanning
11 * Ingo Molnar : various cleanups and rewrites
12 * Maciej W. Rozycki: Bits for default MP configurations
13 * Paul Diefenbaugh: Added full ACPI support
17 #include <linux/irq.h>
18 #include <linux/init.h>
19 #include <linux/delay.h>
20 #include <linux/config.h>
21 #include <linux/bootmem.h>
22 #include <linux/smp_lock.h>
23 #include <linux/kernel_stat.h>
24 #include <linux/mc146818rtc.h>
25 #include <linux/acpi.h>
29 #include <asm/mpspec.h>
30 #include <asm/pgalloc.h>
31 #include <asm/io_apic.h>
32 #include <asm/proto.h>
34 /* Have we found an MP table */
36 unsigned int __initdata maxcpus = NR_CPUS;
41 * Various Linux-internal data structures created from the
44 int apic_version [MAX_APICS];
45 unsigned char mp_bus_id_to_type [MAX_MP_BUSSES] = { [0 ... MAX_MP_BUSSES-1] = -1 };
46 int mp_bus_id_to_pci_bus [MAX_MP_BUSSES] = { [0 ... MAX_MP_BUSSES-1] = -1 };
47 cpumask_t mp_bus_to_cpumask [MAX_MP_BUSSES] = { [0 ... MAX_MP_BUSSES-1] = CPU_MASK_ALL };
49 int mp_current_pci_id = 0;
50 /* I/O APIC entries */
51 struct mpc_config_ioapic mp_ioapics[MAX_IO_APICS];
53 /* # of MP IRQ source entries */
54 struct mpc_config_intsrc mp_irqs[MAX_IRQ_SOURCES];
56 /* MP IRQ source entries */
61 unsigned long mp_lapic_addr = 0;
65 /* Processor that is doing the boot up */
66 unsigned int boot_cpu_id = -1U;
67 /* Internal processor count */
68 static unsigned int num_processors = 0;
70 /* Bitmask of physically existing CPUs */
71 physid_mask_t phys_cpu_present_map = PHYSID_MASK_NONE;
73 /* ACPI MADT entry parsing functions */
74 #ifdef CONFIG_ACPI_BOOT
75 extern struct acpi_boot_flags acpi_boot;
76 #ifdef CONFIG_X86_LOCAL_APIC
77 extern int acpi_parse_lapic (acpi_table_entry_header *header);
78 extern int acpi_parse_lapic_addr_ovr (acpi_table_entry_header *header);
79 extern int acpi_parse_lapic_nmi (acpi_table_entry_header *header);
80 #endif /*CONFIG_X86_LOCAL_APIC*/
81 #ifdef CONFIG_X86_IO_APIC
82 extern int acpi_parse_ioapic (acpi_table_entry_header *header);
83 #endif /*CONFIG_X86_IO_APIC*/
84 #endif /*CONFIG_ACPI_BOOT*/
86 u8 bios_cpu_apicid[NR_CPUS] = { [0 ... NR_CPUS-1] = BAD_APICID };
90 * Intel MP BIOS table parsing routines:
94 * Checksum an MP configuration block.
97 static int __init mpf_checksum(unsigned char *mp, int len)
107 static void __init MP_processor_info (struct mpc_config_processor *m)
111 if (!(m->mpc_cpuflag & CPU_ENABLED))
114 printk(KERN_INFO "Processor #%d %d:%d APIC version %d\n",
116 (m->mpc_cpufeature & CPU_FAMILY_MASK)>>8,
117 (m->mpc_cpufeature & CPU_MODEL_MASK)>>4,
120 if (m->mpc_cpuflag & CPU_BOOTPROCESSOR) {
121 Dprintk(" Bootup CPU\n");
122 boot_cpu_id = m->mpc_apicid;
124 if (num_processors >= NR_CPUS) {
125 printk(KERN_WARNING "WARNING: NR_CPUS limit of %i reached."
126 " Processor ignored.\n", NR_CPUS);
129 if (num_processors >= maxcpus) {
130 printk(KERN_WARNING "WARNING: maxcpus limit of %i reached."
131 " Processor ignored.\n", maxcpus);
137 if (m->mpc_apicid > MAX_APICS) {
138 printk(KERN_ERR "Processor #%d INVALID. (Max ID: %d).\n",
139 m->mpc_apicid, MAX_APICS);
142 ver = m->mpc_apicver;
144 physid_set(m->mpc_apicid, phys_cpu_present_map);
149 printk(KERN_ERR "BIOS bug, APIC version is 0 for CPU#%d! fixing up to 0x10. (tell your hw vendor)\n", m->mpc_apicid);
152 apic_version[m->mpc_apicid] = ver;
153 bios_cpu_apicid[num_processors - 1] = m->mpc_apicid;
156 static void __init MP_bus_info (struct mpc_config_bus *m)
160 memcpy(str, m->mpc_bustype, 6);
162 Dprintk("Bus #%d is %s\n", m->mpc_busid, str);
164 if (strncmp(str, "ISA", 3) == 0) {
165 mp_bus_id_to_type[m->mpc_busid] = MP_BUS_ISA;
166 } else if (strncmp(str, "EISA", 4) == 0) {
167 mp_bus_id_to_type[m->mpc_busid] = MP_BUS_EISA;
168 } else if (strncmp(str, "PCI", 3) == 0) {
169 mp_bus_id_to_type[m->mpc_busid] = MP_BUS_PCI;
170 mp_bus_id_to_pci_bus[m->mpc_busid] = mp_current_pci_id;
172 } else if (strncmp(str, "MCA", 3) == 0) {
173 mp_bus_id_to_type[m->mpc_busid] = MP_BUS_MCA;
175 printk(KERN_ERR "Unknown bustype %s\n", str);
179 static void __init MP_ioapic_info (struct mpc_config_ioapic *m)
181 if (!(m->mpc_flags & MPC_APIC_USABLE))
184 printk("I/O APIC #%d Version %d at 0x%X.\n",
185 m->mpc_apicid, m->mpc_apicver, m->mpc_apicaddr);
186 if (nr_ioapics >= MAX_IO_APICS) {
187 printk(KERN_ERR "Max # of I/O APICs (%d) exceeded (found %d).\n",
188 MAX_IO_APICS, nr_ioapics);
189 panic("Recompile kernel with bigger MAX_IO_APICS!.\n");
191 if (!m->mpc_apicaddr) {
192 printk(KERN_ERR "WARNING: bogus zero I/O APIC address"
193 " found in MP table, skipping!\n");
196 mp_ioapics[nr_ioapics] = *m;
200 static void __init MP_intsrc_info (struct mpc_config_intsrc *m)
202 mp_irqs [mp_irq_entries] = *m;
203 Dprintk("Int: type %d, pol %d, trig %d, bus %d,"
204 " IRQ %02x, APIC ID %x, APIC INT %02x\n",
205 m->mpc_irqtype, m->mpc_irqflag & 3,
206 (m->mpc_irqflag >> 2) & 3, m->mpc_srcbus,
207 m->mpc_srcbusirq, m->mpc_dstapic, m->mpc_dstirq);
208 if (++mp_irq_entries == MAX_IRQ_SOURCES)
209 panic("Max # of irq sources exceeded!!\n");
212 static void __init MP_lintsrc_info (struct mpc_config_lintsrc *m)
214 Dprintk("Lint: type %d, pol %d, trig %d, bus %d,"
215 " IRQ %02x, APIC ID %x, APIC LINT %02x\n",
216 m->mpc_irqtype, m->mpc_irqflag & 3,
217 (m->mpc_irqflag >> 2) &3, m->mpc_srcbusid,
218 m->mpc_srcbusirq, m->mpc_destapic, m->mpc_destapiclint);
220 * Well it seems all SMP boards in existence
221 * use ExtINT/LVT1 == LINT0 and
222 * NMI/LVT2 == LINT1 - the following check
223 * will show us if this assumptions is false.
224 * Until then we do not have to add baggage.
226 if ((m->mpc_irqtype == mp_ExtINT) &&
227 (m->mpc_destapiclint != 0))
229 if ((m->mpc_irqtype == mp_NMI) &&
230 (m->mpc_destapiclint != 1))
238 static int __init smp_read_mpc(struct mp_config_table *mpc)
241 int count=sizeof(*mpc);
242 unsigned char *mpt=((unsigned char *)mpc)+count;
244 if (memcmp(mpc->mpc_signature,MPC_SIGNATURE,4)) {
245 printk("SMP mptable: bad signature [%c%c%c%c]!\n",
246 mpc->mpc_signature[0],
247 mpc->mpc_signature[1],
248 mpc->mpc_signature[2],
249 mpc->mpc_signature[3]);
252 if (mpf_checksum((unsigned char *)mpc,mpc->mpc_length)) {
253 printk("SMP mptable: checksum error!\n");
256 if (mpc->mpc_spec!=0x01 && mpc->mpc_spec!=0x04) {
257 printk(KERN_ERR "SMP mptable: bad table version (%d)!!\n",
261 if (!mpc->mpc_lapic) {
262 printk(KERN_ERR "SMP mptable: null local APIC address!\n");
265 memcpy(str,mpc->mpc_oem,8);
267 printk(KERN_INFO "OEM ID: %s ",str);
269 memcpy(str,mpc->mpc_productid,12);
271 printk(KERN_INFO "Product ID: %s ",str);
273 printk(KERN_INFO "APIC at: 0x%X\n",mpc->mpc_lapic);
275 /* save the local APIC address, it might be non-default */
277 mp_lapic_addr = mpc->mpc_lapic;
280 * Now process the configuration blocks.
282 while (count < mpc->mpc_length) {
286 struct mpc_config_processor *m=
287 (struct mpc_config_processor *)mpt;
289 MP_processor_info(m);
296 struct mpc_config_bus *m=
297 (struct mpc_config_bus *)mpt;
305 struct mpc_config_ioapic *m=
306 (struct mpc_config_ioapic *)mpt;
314 struct mpc_config_intsrc *m=
315 (struct mpc_config_intsrc *)mpt;
324 struct mpc_config_lintsrc *m=
325 (struct mpc_config_lintsrc *)mpt;
334 printk(KERN_ERR "SMP mptable: no processors registered!\n");
335 return num_processors;
338 static int __init ELCR_trigger(unsigned int irq)
342 port = 0x4d0 + (irq >> 3);
343 return (inb(port) >> (irq & 7)) & 1;
346 static void __init construct_default_ioirq_mptable(int mpc_default_type)
348 struct mpc_config_intsrc intsrc;
350 int ELCR_fallback = 0;
352 intsrc.mpc_type = MP_INTSRC;
353 intsrc.mpc_irqflag = 0; /* conforming */
354 intsrc.mpc_srcbus = 0;
355 intsrc.mpc_dstapic = mp_ioapics[0].mpc_apicid;
357 intsrc.mpc_irqtype = mp_INT;
360 * If true, we have an ISA/PCI system with no IRQ entries
361 * in the MP table. To prevent the PCI interrupts from being set up
362 * incorrectly, we try to use the ELCR. The sanity check to see if
363 * there is good ELCR data is very simple - IRQ0, 1, 2 and 13 can
364 * never be level sensitive, so we simply see if the ELCR agrees.
365 * If it does, we assume it's valid.
367 if (mpc_default_type == 5) {
368 printk(KERN_INFO "ISA/PCI bus type with no IRQ information... falling back to ELCR\n");
370 if (ELCR_trigger(0) || ELCR_trigger(1) || ELCR_trigger(2) || ELCR_trigger(13))
371 printk(KERN_ERR "ELCR contains invalid data... not using ELCR\n");
373 printk(KERN_INFO "Using ELCR to identify PCI interrupts\n");
378 for (i = 0; i < 16; i++) {
379 switch (mpc_default_type) {
381 if (i == 0 || i == 13)
382 continue; /* IRQ0 & IRQ13 not connected */
386 continue; /* IRQ2 is never connected */
391 * If the ELCR indicates a level-sensitive interrupt, we
392 * copy that information over to the MP table in the
393 * irqflag field (level sensitive, active high polarity).
396 intsrc.mpc_irqflag = 13;
398 intsrc.mpc_irqflag = 0;
401 intsrc.mpc_srcbusirq = i;
402 intsrc.mpc_dstirq = i ? i : 2; /* IRQ0 to INTIN2 */
403 MP_intsrc_info(&intsrc);
406 intsrc.mpc_irqtype = mp_ExtINT;
407 intsrc.mpc_srcbusirq = 0;
408 intsrc.mpc_dstirq = 0; /* 8259A to INTIN0 */
409 MP_intsrc_info(&intsrc);
412 static inline void __init construct_default_ISA_mptable(int mpc_default_type)
414 struct mpc_config_processor processor;
415 struct mpc_config_bus bus;
416 struct mpc_config_ioapic ioapic;
417 struct mpc_config_lintsrc lintsrc;
418 int linttypes[2] = { mp_ExtINT, mp_NMI };
422 * local APIC has default address
424 mp_lapic_addr = APIC_DEFAULT_PHYS_BASE;
427 * 2 CPUs, numbered 0 & 1.
429 processor.mpc_type = MP_PROCESSOR;
430 /* Either an integrated APIC or a discrete 82489DX. */
431 processor.mpc_apicver = mpc_default_type > 4 ? 0x10 : 0x01;
432 processor.mpc_cpuflag = CPU_ENABLED;
433 processor.mpc_cpufeature = (boot_cpu_data.x86 << 8) |
434 (boot_cpu_data.x86_model << 4) |
435 boot_cpu_data.x86_mask;
436 processor.mpc_featureflag = boot_cpu_data.x86_capability[0];
437 processor.mpc_reserved[0] = 0;
438 processor.mpc_reserved[1] = 0;
439 for (i = 0; i < 2; i++) {
440 processor.mpc_apicid = i;
441 MP_processor_info(&processor);
444 bus.mpc_type = MP_BUS;
446 switch (mpc_default_type) {
448 printk(KERN_ERR "???\nUnknown standard configuration %d\n",
453 memcpy(bus.mpc_bustype, "ISA ", 6);
458 memcpy(bus.mpc_bustype, "EISA ", 6);
462 memcpy(bus.mpc_bustype, "MCA ", 6);
465 if (mpc_default_type > 4) {
467 memcpy(bus.mpc_bustype, "PCI ", 6);
471 ioapic.mpc_type = MP_IOAPIC;
472 ioapic.mpc_apicid = 2;
473 ioapic.mpc_apicver = mpc_default_type > 4 ? 0x10 : 0x01;
474 ioapic.mpc_flags = MPC_APIC_USABLE;
475 ioapic.mpc_apicaddr = 0xFEC00000;
476 MP_ioapic_info(&ioapic);
479 * We set up most of the low 16 IO-APIC pins according to MPS rules.
481 construct_default_ioirq_mptable(mpc_default_type);
483 lintsrc.mpc_type = MP_LINTSRC;
484 lintsrc.mpc_irqflag = 0; /* conforming */
485 lintsrc.mpc_srcbusid = 0;
486 lintsrc.mpc_srcbusirq = 0;
487 lintsrc.mpc_destapic = MP_APIC_ALL;
488 for (i = 0; i < 2; i++) {
489 lintsrc.mpc_irqtype = linttypes[i];
490 lintsrc.mpc_destapiclint = i;
491 MP_lintsrc_info(&lintsrc);
495 static struct intel_mp_floating *mpf_found;
498 * Scan the memory blocks for an SMP configuration block.
500 void __init get_smp_config (void)
502 struct intel_mp_floating *mpf = mpf_found;
505 * ACPI may be used to obtain the entire SMP configuration or just to
506 * enumerate/configure processors (CONFIG_ACPI_BOOT). Note that
507 * ACPI supports both logical (e.g. Hyper-Threading) and physical
508 * processors, where MPS only supports physical.
510 if (acpi_lapic && acpi_ioapic) {
511 printk(KERN_INFO "Using ACPI (MADT) for SMP configuration information\n");
515 printk(KERN_INFO "Using ACPI for processor (LAPIC) configuration information\n");
517 printk("Intel MultiProcessor Specification v1.%d\n", mpf->mpf_specification);
518 if (mpf->mpf_feature2 & (1<<7)) {
519 printk(KERN_INFO " IMCR and PIC compatibility mode.\n");
522 printk(KERN_INFO " Virtual Wire compatibility mode.\n");
527 * Now see if we need to read further.
529 if (mpf->mpf_feature1 != 0) {
531 printk(KERN_INFO "Default MP configuration #%d\n", mpf->mpf_feature1);
532 construct_default_ISA_mptable(mpf->mpf_feature1);
534 } else if (mpf->mpf_physptr) {
537 * Read the physical hardware table. Anything here will
538 * override the defaults.
540 if (!smp_read_mpc((void *)(unsigned long)mpf->mpf_physptr)) {
541 smp_found_config = 0;
542 printk(KERN_ERR "BIOS bug, MP table errors detected!...\n");
543 printk(KERN_ERR "... disabling SMP support. (tell your hw vendor)\n");
547 * If there are no explicit MP IRQ entries, then we are
548 * broken. We set up most of the low 16 IO-APIC pins to
549 * ISA defaults and hope it will work.
551 if (!mp_irq_entries) {
552 struct mpc_config_bus bus;
554 printk(KERN_ERR "BIOS bug, no explicit IRQ entries, using default mptable. (tell your hw vendor)\n");
556 bus.mpc_type = MP_BUS;
558 memcpy(bus.mpc_bustype, "ISA ", 6);
561 construct_default_ioirq_mptable(0);
567 printk(KERN_INFO "Processors: %d\n", num_processors);
569 * Only use the first configuration found.
573 static int __init smp_scan_config (unsigned long base, unsigned long length)
575 extern void __bad_mpf_size(void);
576 unsigned int *bp = phys_to_virt(base);
577 struct intel_mp_floating *mpf;
578 static int printed __initdata;
580 Dprintk("Scan SMP from %p for %ld bytes.\n", bp,length);
581 if (sizeof(*mpf) != 16)
585 mpf = (struct intel_mp_floating *)bp;
586 if ((*bp == SMP_MAGIC_IDENT) &&
587 (mpf->mpf_length == 1) &&
588 !mpf_checksum((unsigned char *)bp, 16) &&
589 ((mpf->mpf_specification == 1)
590 || (mpf->mpf_specification == 4)) ) {
592 smp_found_config = 1;
593 reserve_bootmem_generic(virt_to_phys(mpf), PAGE_SIZE);
594 if (mpf->mpf_physptr)
595 reserve_bootmem_generic(mpf->mpf_physptr, PAGE_SIZE);
603 printk(KERN_INFO "No mptable found.\n");
609 void __init find_intel_smp (void)
611 unsigned int address;
614 * FIXME: Linux assumes you have 640K of base ram..
615 * this continues the error...
617 * 1) Scan the bottom 1K for a signature
618 * 2) Scan the top 1K of base RAM
619 * 3) Scan the 64K of bios
621 if (smp_scan_config(0x0,0x400) ||
622 smp_scan_config(639*0x400,0x400) ||
623 smp_scan_config(0xF0000,0x10000))
626 * If it is an SMP machine we should know now, unless the
627 * configuration is in an EISA/MCA bus machine with an
628 * extended bios data area.
630 * there is a real-mode segmented pointer pointing to the
631 * 4K EBDA area at 0x40E, calculate and scan it here.
633 * NOTE! There are Linux loaders that will corrupt the EBDA
634 * area, and as such this kind of SMP config may be less
635 * trustworthy, simply because the SMP table may have been
636 * stomped on during early boot. These loaders are buggy and
640 address = *(unsigned short *)phys_to_virt(0x40E);
642 smp_scan_config(address, 0x1000);
646 * - Intel MP Configuration Table
648 void __init find_smp_config (void)
650 #ifdef CONFIG_X86_LOCAL_APIC
656 /* --------------------------------------------------------------------------
657 ACPI-based MP Configuration
658 -------------------------------------------------------------------------- */
660 #ifdef CONFIG_ACPI_BOOT
662 void __init mp_register_lapic_address (
665 mp_lapic_addr = (unsigned long) address;
667 set_fixmap_nocache(FIX_APIC_BASE, mp_lapic_addr);
669 if (boot_cpu_id == -1U)
670 boot_cpu_id = GET_APIC_ID(apic_read(APIC_ID));
672 Dprintk("Boot CPU = %d\n", boot_cpu_physical_apicid);
676 void __init mp_register_lapic (
680 struct mpc_config_processor processor;
683 if (id >= MAX_APICS) {
684 printk(KERN_WARNING "Processor #%d invalid (max %d)\n",
689 if (id == boot_cpu_physical_apicid)
692 processor.mpc_type = MP_PROCESSOR;
693 processor.mpc_apicid = id;
694 processor.mpc_apicver = 0x10; /* TBD: lapic version */
695 processor.mpc_cpuflag = (enabled ? CPU_ENABLED : 0);
696 processor.mpc_cpuflag |= (boot_cpu ? CPU_BOOTPROCESSOR : 0);
697 processor.mpc_cpufeature = (boot_cpu_data.x86 << 8) |
698 (boot_cpu_data.x86_model << 4) | boot_cpu_data.x86_mask;
699 processor.mpc_featureflag = boot_cpu_data.x86_capability[0];
700 processor.mpc_reserved[0] = 0;
701 processor.mpc_reserved[1] = 0;
703 MP_processor_info(&processor);
706 #ifdef CONFIG_X86_IO_APIC
709 #define MP_MAX_IOAPIC_PIN 127
711 struct mp_ioapic_routing {
715 u32 pin_programmed[4];
716 } mp_ioapic_routing[MAX_IO_APICS];
719 static int __init mp_find_ioapic (
724 /* Find the IOAPIC that manages this GSI. */
725 for (i = 0; i < nr_ioapics; i++) {
726 if ((gsi >= mp_ioapic_routing[i].gsi_start)
727 && (gsi <= mp_ioapic_routing[i].gsi_end))
731 printk(KERN_ERR "ERROR: Unable to locate IOAPIC for GSI %d\n", gsi);
737 void __init mp_register_ioapic (
744 if (nr_ioapics >= MAX_IO_APICS) {
745 printk(KERN_ERR "ERROR: Max # of I/O APICs (%d) exceeded "
746 "(found %d)\n", MAX_IO_APICS, nr_ioapics);
747 panic("Recompile kernel with bigger MAX_IO_APICS!\n");
750 printk(KERN_ERR "WARNING: Bogus (zero) I/O APIC address"
751 " found in MADT table, skipping!\n");
757 mp_ioapics[idx].mpc_type = MP_IOAPIC;
758 mp_ioapics[idx].mpc_flags = MPC_APIC_USABLE;
759 mp_ioapics[idx].mpc_apicaddr = address;
761 set_fixmap_nocache(FIX_IO_APIC_BASE_0 + idx, address);
762 mp_ioapics[idx].mpc_apicid = io_apic_get_unique_id(idx, id);
763 mp_ioapics[idx].mpc_apicver = io_apic_get_version(idx);
766 * Build basic IRQ lookup table to facilitate gsi->io_apic lookups
767 * and to prevent reprogramming of IOAPIC pins (PCI IRQs).
769 mp_ioapic_routing[idx].apic_id = mp_ioapics[idx].mpc_apicid;
770 mp_ioapic_routing[idx].gsi_start = gsi_base;
771 mp_ioapic_routing[idx].gsi_end = gsi_base +
772 io_apic_get_redir_entries(idx);
774 printk(KERN_INFO "IOAPIC[%d]: apic_id %d, version %d, address 0x%x, "
775 "GSI %d-%d\n", idx, mp_ioapics[idx].mpc_apicid,
776 mp_ioapics[idx].mpc_apicver, mp_ioapics[idx].mpc_apicaddr,
777 mp_ioapic_routing[idx].gsi_start,
778 mp_ioapic_routing[idx].gsi_end);
784 void __init mp_override_legacy_irq (
790 struct mpc_config_intsrc intsrc;
795 * Convert 'gsi' to 'ioapic.pin'.
797 ioapic = mp_find_ioapic(gsi);
800 pin = gsi - mp_ioapic_routing[ioapic].gsi_start;
803 * TBD: This check is for faulty timer entries, where the override
804 * erroneously sets the trigger to level, resulting in a HUGE
805 * increase of timer interrupts!
807 if ((bus_irq == 0) && (trigger == 3))
810 intsrc.mpc_type = MP_INTSRC;
811 intsrc.mpc_irqtype = mp_INT;
812 intsrc.mpc_irqflag = (trigger << 2) | polarity;
813 intsrc.mpc_srcbus = MP_ISA_BUS;
814 intsrc.mpc_srcbusirq = bus_irq; /* IRQ */
815 intsrc.mpc_dstapic = mp_ioapics[ioapic].mpc_apicid; /* APIC ID */
816 intsrc.mpc_dstirq = pin; /* INTIN# */
818 Dprintk("Int: type %d, pol %d, trig %d, bus %d, irq %d, %d-%d\n",
819 intsrc.mpc_irqtype, intsrc.mpc_irqflag & 3,
820 (intsrc.mpc_irqflag >> 2) & 3, intsrc.mpc_srcbus,
821 intsrc.mpc_srcbusirq, intsrc.mpc_dstapic, intsrc.mpc_dstirq);
823 mp_irqs[mp_irq_entries] = intsrc;
824 if (++mp_irq_entries == MAX_IRQ_SOURCES)
825 panic("Max # of irq sources exceeded!\n");
831 void __init mp_config_acpi_legacy_irqs (void)
833 struct mpc_config_intsrc intsrc;
838 * Fabricate the legacy ISA bus (bus #31).
840 mp_bus_id_to_type[MP_ISA_BUS] = MP_BUS_ISA;
841 Dprintk("Bus #%d is ISA\n", MP_ISA_BUS);
844 * Locate the IOAPIC that manages the ISA IRQs (0-15).
846 ioapic = mp_find_ioapic(0);
850 intsrc.mpc_type = MP_INTSRC;
851 intsrc.mpc_irqflag = 0; /* Conforming */
852 intsrc.mpc_srcbus = MP_ISA_BUS;
853 intsrc.mpc_dstapic = mp_ioapics[ioapic].mpc_apicid;
856 * Use the default configuration for the IRQs 0-15. Unless
857 * overridden by (MADT) interrupt source override entries.
859 for (i = 0; i < 16; i++) {
862 for (idx = 0; idx < mp_irq_entries; idx++)
863 if (mp_irqs[idx].mpc_srcbus == MP_ISA_BUS &&
864 (mp_irqs[idx].mpc_srcbusirq == i ||
865 mp_irqs[idx].mpc_dstirq == i))
868 if (idx != mp_irq_entries) {
869 printk(KERN_DEBUG "ACPI: IRQ%d used by override.\n", i);
870 continue; /* IRQ already used */
873 intsrc.mpc_irqtype = mp_INT;
874 intsrc.mpc_srcbusirq = i; /* Identity mapped */
875 intsrc.mpc_dstirq = i;
877 Dprintk("Int: type %d, pol %d, trig %d, bus %d, irq %d, "
878 "%d-%d\n", intsrc.mpc_irqtype, intsrc.mpc_irqflag & 3,
879 (intsrc.mpc_irqflag >> 2) & 3, intsrc.mpc_srcbus,
880 intsrc.mpc_srcbusirq, intsrc.mpc_dstapic,
883 mp_irqs[mp_irq_entries] = intsrc;
884 if (++mp_irq_entries == MAX_IRQ_SOURCES)
885 panic("Max # of irq sources exceeded!\n");
892 extern FADT_DESCRIPTOR acpi_fadt;
894 #ifdef CONFIG_ACPI_PCI
896 void __init mp_parse_prt (void)
898 struct list_head *node = NULL;
899 struct acpi_prt_entry *entry = NULL;
905 int active_high_low = 0;
908 * Parsing through the PCI Interrupt Routing Table (PRT) and program
909 * routing for all static (IOAPIC-direct) entries.
911 list_for_each(node, &acpi_prt.entries) {
912 entry = list_entry(node, struct acpi_prt_entry, node);
914 /* Need to get gsi for dynamic entry */
915 if (entry->link.handle) {
916 gsi = acpi_pci_link_get_irq(entry->link.handle, entry->link.index, &edge_level, &active_high_low);
920 /* Hardwired GSI. Assume PCI standard settings */
921 gsi = entry->link.index;
926 /* Don't set up the ACPI SCI because it's already set up */
927 if (acpi_fadt.sci_int == gsi) {
928 /* we still need to set up the entry's irq */
929 acpi_gsi_to_irq(gsi, &entry->irq);
933 ioapic = mp_find_ioapic(gsi);
936 ioapic_pin = gsi - mp_ioapic_routing[ioapic].gsi_start;
939 * Avoid pin reprogramming. PRTs typically include entries
940 * with redundant pin->gsi mappings (but unique PCI devices);
941 * we only only program the IOAPIC on the first.
943 bit = ioapic_pin % 32;
944 idx = (ioapic_pin < 32) ? 0 : (ioapic_pin / 32);
946 printk(KERN_ERR "Invalid reference to IOAPIC pin "
947 "%d-%d\n", mp_ioapic_routing[ioapic].apic_id,
951 if ((1<<bit) & mp_ioapic_routing[ioapic].pin_programmed[idx]) {
952 Dprintk(KERN_DEBUG "Pin %d-%d already programmed\n",
953 mp_ioapic_routing[ioapic].apic_id, ioapic_pin);
954 acpi_gsi_to_irq(gsi, &entry->irq);
958 mp_ioapic_routing[ioapic].pin_programmed[idx] |= (1<<bit);
959 if (!io_apic_set_pci_routing(ioapic, ioapic_pin, gsi, edge_level, active_high_low)) {
960 acpi_gsi_to_irq(gsi, &entry->irq);
962 printk(KERN_DEBUG "%02x:%02x:%02x[%c] -> %d-%d -> IRQ %d\n",
963 entry->id.segment, entry->id.bus,
964 entry->id.device, ('A' + entry->pin),
965 mp_ioapic_routing[ioapic].apic_id, ioapic_pin,
974 #endif /*CONFIG_ACPI_PCI*/
976 #endif /*CONFIG_X86_IO_APIC*/
978 #endif /*CONFIG_ACPI_BOOT*/