2 * Intel Multiprocessor Specification 1.1 and 1.4
3 * compliant MP-table parsing routines.
5 * (c) 1995 Alan Cox, Building #3 <alan@redhat.com>
6 * (c) 1998, 1999, 2000 Ingo Molnar <mingo@redhat.com>
9 * Erich Boleyn : MP v1.4 and additional changes.
10 * Alan Cox : Added EBDA scanning
11 * Ingo Molnar : various cleanups and rewrites
12 * Maciej W. Rozycki: Bits for default MP configurations
13 * Paul Diefenbaugh: Added full ACPI support
17 #include <linux/init.h>
18 #include <linux/delay.h>
19 #include <linux/bootmem.h>
20 #include <linux/smp_lock.h>
21 #include <linux/kernel_stat.h>
22 #include <linux/mc146818rtc.h>
23 #include <linux/acpi.h>
24 #include <linux/module.h>
28 #include <asm/mpspec.h>
29 #include <asm/pgalloc.h>
30 #include <asm/io_apic.h>
31 #include <asm/proto.h>
34 /* Have we found an MP table */
36 unsigned int __initdata maxcpus = NR_CPUS;
39 * Various Linux-internal data structures created from the
42 DECLARE_BITMAP(mp_bus_not_pci, MAX_MP_BUSSES);
43 int mp_bus_id_to_pci_bus [MAX_MP_BUSSES] = { [0 ... MAX_MP_BUSSES-1] = -1 };
45 static int mp_current_pci_id = 0;
46 /* I/O APIC entries */
47 struct mpc_config_ioapic mp_ioapics[MAX_IO_APICS];
49 /* # of MP IRQ source entries */
50 struct mpc_config_intsrc mp_irqs[MAX_IRQ_SOURCES];
52 /* MP IRQ source entries */
56 unsigned long mp_lapic_addr = 0;
60 /* Processor that is doing the boot up */
61 unsigned int boot_cpu_id = -1U;
62 /* Internal processor count */
63 unsigned int num_processors __initdata = 0;
65 unsigned disabled_cpus __initdata;
67 /* Bitmask of physically existing CPUs */
68 physid_mask_t phys_cpu_present_map = PHYSID_MASK_NONE;
70 u8 bios_cpu_apicid[NR_CPUS] = { [0 ... NR_CPUS-1] = BAD_APICID };
74 * Intel MP BIOS table parsing routines:
78 * Checksum an MP configuration block.
81 static int __init mpf_checksum(unsigned char *mp, int len)
91 static void __cpuinit MP_processor_info (struct mpc_config_processor *m)
96 char *bootup_cpu = "";
98 if (!(m->mpc_cpuflag & CPU_ENABLED)) {
102 if (m->mpc_cpuflag & CPU_BOOTPROCESSOR) {
103 bootup_cpu = " (Bootup-CPU)";
104 boot_cpu_id = m->mpc_apicid;
107 printk(KERN_INFO "Processor #%d%s\n", m->mpc_apicid, bootup_cpu);
109 if (num_processors >= NR_CPUS) {
110 printk(KERN_WARNING "WARNING: NR_CPUS limit of %i reached."
111 " Processor ignored.\n", NR_CPUS);
114 #endif /* !CONFIG_XEN */
117 cpus_complement(tmp_map, cpu_present_map);
118 cpu = first_cpu(tmp_map);
120 physid_set(m->mpc_apicid, phys_cpu_present_map);
121 if (m->mpc_cpuflag & CPU_BOOTPROCESSOR) {
123 * bios_cpu_apicid is required to have processors listed
124 * in same order as logical cpu numbers. Hence the first
125 * entry is BSP, and so on.
129 bios_cpu_apicid[cpu] = m->mpc_apicid;
130 x86_cpu_to_apicid[cpu] = m->mpc_apicid;
132 cpu_set(cpu, cpu_possible_map);
133 cpu_set(cpu, cpu_present_map);
134 #endif /* CONFIG_XEN */
137 static void __init MP_bus_info (struct mpc_config_bus *m)
141 memcpy(str, m->mpc_bustype, 6);
143 Dprintk("Bus #%d is %s\n", m->mpc_busid, str);
145 if (strncmp(str, "ISA", 3) == 0) {
146 set_bit(m->mpc_busid, mp_bus_not_pci);
147 } else if (strncmp(str, "PCI", 3) == 0) {
148 clear_bit(m->mpc_busid, mp_bus_not_pci);
149 mp_bus_id_to_pci_bus[m->mpc_busid] = mp_current_pci_id;
152 printk(KERN_ERR "Unknown bustype %s\n", str);
156 static int bad_ioapic(unsigned long address)
158 if (nr_ioapics >= MAX_IO_APICS) {
159 printk(KERN_ERR "ERROR: Max # of I/O APICs (%d) exceeded "
160 "(found %d)\n", MAX_IO_APICS, nr_ioapics);
161 panic("Recompile kernel with bigger MAX_IO_APICS!\n");
164 printk(KERN_ERR "WARNING: Bogus (zero) I/O APIC address"
165 " found in table, skipping!\n");
171 static void __init MP_ioapic_info (struct mpc_config_ioapic *m)
173 if (!(m->mpc_flags & MPC_APIC_USABLE))
176 printk("I/O APIC #%d at 0x%X.\n",
177 m->mpc_apicid, m->mpc_apicaddr);
179 if (bad_ioapic(m->mpc_apicaddr))
182 mp_ioapics[nr_ioapics] = *m;
186 static void __init MP_intsrc_info (struct mpc_config_intsrc *m)
188 mp_irqs [mp_irq_entries] = *m;
189 Dprintk("Int: type %d, pol %d, trig %d, bus %d,"
190 " IRQ %02x, APIC ID %x, APIC INT %02x\n",
191 m->mpc_irqtype, m->mpc_irqflag & 3,
192 (m->mpc_irqflag >> 2) & 3, m->mpc_srcbus,
193 m->mpc_srcbusirq, m->mpc_dstapic, m->mpc_dstirq);
194 if (++mp_irq_entries >= MAX_IRQ_SOURCES)
195 panic("Max # of irq sources exceeded!!\n");
198 static void __init MP_lintsrc_info (struct mpc_config_lintsrc *m)
200 Dprintk("Lint: type %d, pol %d, trig %d, bus %d,"
201 " IRQ %02x, APIC ID %x, APIC LINT %02x\n",
202 m->mpc_irqtype, m->mpc_irqflag & 3,
203 (m->mpc_irqflag >> 2) &3, m->mpc_srcbusid,
204 m->mpc_srcbusirq, m->mpc_destapic, m->mpc_destapiclint);
211 static int __init smp_read_mpc(struct mp_config_table *mpc)
214 int count=sizeof(*mpc);
215 unsigned char *mpt=((unsigned char *)mpc)+count;
217 if (memcmp(mpc->mpc_signature,MPC_SIGNATURE,4)) {
218 printk("MPTABLE: bad signature [%c%c%c%c]!\n",
219 mpc->mpc_signature[0],
220 mpc->mpc_signature[1],
221 mpc->mpc_signature[2],
222 mpc->mpc_signature[3]);
225 if (mpf_checksum((unsigned char *)mpc,mpc->mpc_length)) {
226 printk("MPTABLE: checksum error!\n");
229 if (mpc->mpc_spec!=0x01 && mpc->mpc_spec!=0x04) {
230 printk(KERN_ERR "MPTABLE: bad table version (%d)!!\n",
234 if (!mpc->mpc_lapic) {
235 printk(KERN_ERR "MPTABLE: null local APIC address!\n");
238 memcpy(str,mpc->mpc_oem,8);
240 printk(KERN_INFO "MPTABLE: OEM ID: %s ",str);
242 memcpy(str,mpc->mpc_productid,12);
244 printk("MPTABLE: Product ID: %s ",str);
246 printk("MPTABLE: APIC at: 0x%X\n",mpc->mpc_lapic);
248 /* save the local APIC address, it might be non-default */
250 mp_lapic_addr = mpc->mpc_lapic;
253 * Now process the configuration blocks.
255 while (count < mpc->mpc_length) {
259 struct mpc_config_processor *m=
260 (struct mpc_config_processor *)mpt;
262 MP_processor_info(m);
269 struct mpc_config_bus *m=
270 (struct mpc_config_bus *)mpt;
278 struct mpc_config_ioapic *m=
279 (struct mpc_config_ioapic *)mpt;
287 struct mpc_config_intsrc *m=
288 (struct mpc_config_intsrc *)mpt;
297 struct mpc_config_lintsrc *m=
298 (struct mpc_config_lintsrc *)mpt;
306 clustered_apic_check();
308 printk(KERN_ERR "MPTABLE: no processors registered!\n");
309 return num_processors;
312 static int __init ELCR_trigger(unsigned int irq)
316 port = 0x4d0 + (irq >> 3);
317 return (inb(port) >> (irq & 7)) & 1;
320 static void __init construct_default_ioirq_mptable(int mpc_default_type)
322 struct mpc_config_intsrc intsrc;
324 int ELCR_fallback = 0;
326 intsrc.mpc_type = MP_INTSRC;
327 intsrc.mpc_irqflag = 0; /* conforming */
328 intsrc.mpc_srcbus = 0;
329 intsrc.mpc_dstapic = mp_ioapics[0].mpc_apicid;
331 intsrc.mpc_irqtype = mp_INT;
334 * If true, we have an ISA/PCI system with no IRQ entries
335 * in the MP table. To prevent the PCI interrupts from being set up
336 * incorrectly, we try to use the ELCR. The sanity check to see if
337 * there is good ELCR data is very simple - IRQ0, 1, 2 and 13 can
338 * never be level sensitive, so we simply see if the ELCR agrees.
339 * If it does, we assume it's valid.
341 if (mpc_default_type == 5) {
342 printk(KERN_INFO "ISA/PCI bus type with no IRQ information... falling back to ELCR\n");
344 if (ELCR_trigger(0) || ELCR_trigger(1) || ELCR_trigger(2) || ELCR_trigger(13))
345 printk(KERN_ERR "ELCR contains invalid data... not using ELCR\n");
347 printk(KERN_INFO "Using ELCR to identify PCI interrupts\n");
352 for (i = 0; i < 16; i++) {
353 switch (mpc_default_type) {
355 if (i == 0 || i == 13)
356 continue; /* IRQ0 & IRQ13 not connected */
360 continue; /* IRQ2 is never connected */
365 * If the ELCR indicates a level-sensitive interrupt, we
366 * copy that information over to the MP table in the
367 * irqflag field (level sensitive, active high polarity).
370 intsrc.mpc_irqflag = 13;
372 intsrc.mpc_irqflag = 0;
375 intsrc.mpc_srcbusirq = i;
376 intsrc.mpc_dstirq = i ? i : 2; /* IRQ0 to INTIN2 */
377 MP_intsrc_info(&intsrc);
380 intsrc.mpc_irqtype = mp_ExtINT;
381 intsrc.mpc_srcbusirq = 0;
382 intsrc.mpc_dstirq = 0; /* 8259A to INTIN0 */
383 MP_intsrc_info(&intsrc);
386 static inline void __init construct_default_ISA_mptable(int mpc_default_type)
388 struct mpc_config_processor processor;
389 struct mpc_config_bus bus;
390 struct mpc_config_ioapic ioapic;
391 struct mpc_config_lintsrc lintsrc;
392 int linttypes[2] = { mp_ExtINT, mp_NMI };
396 * local APIC has default address
398 mp_lapic_addr = APIC_DEFAULT_PHYS_BASE;
401 * 2 CPUs, numbered 0 & 1.
403 processor.mpc_type = MP_PROCESSOR;
404 processor.mpc_apicver = 0;
405 processor.mpc_cpuflag = CPU_ENABLED;
406 processor.mpc_cpufeature = 0;
407 processor.mpc_featureflag = 0;
408 processor.mpc_reserved[0] = 0;
409 processor.mpc_reserved[1] = 0;
410 for (i = 0; i < 2; i++) {
411 processor.mpc_apicid = i;
412 MP_processor_info(&processor);
415 bus.mpc_type = MP_BUS;
417 switch (mpc_default_type) {
419 printk(KERN_ERR "???\nUnknown standard configuration %d\n",
424 memcpy(bus.mpc_bustype, "ISA ", 6);
428 if (mpc_default_type > 4) {
430 memcpy(bus.mpc_bustype, "PCI ", 6);
434 ioapic.mpc_type = MP_IOAPIC;
435 ioapic.mpc_apicid = 2;
436 ioapic.mpc_apicver = 0;
437 ioapic.mpc_flags = MPC_APIC_USABLE;
438 ioapic.mpc_apicaddr = 0xFEC00000;
439 MP_ioapic_info(&ioapic);
442 * We set up most of the low 16 IO-APIC pins according to MPS rules.
444 construct_default_ioirq_mptable(mpc_default_type);
446 lintsrc.mpc_type = MP_LINTSRC;
447 lintsrc.mpc_irqflag = 0; /* conforming */
448 lintsrc.mpc_srcbusid = 0;
449 lintsrc.mpc_srcbusirq = 0;
450 lintsrc.mpc_destapic = MP_APIC_ALL;
451 for (i = 0; i < 2; i++) {
452 lintsrc.mpc_irqtype = linttypes[i];
453 lintsrc.mpc_destapiclint = i;
454 MP_lintsrc_info(&lintsrc);
458 static struct intel_mp_floating *mpf_found;
461 * Scan the memory blocks for an SMP configuration block.
463 void __init get_smp_config (void)
465 struct intel_mp_floating *mpf = mpf_found;
468 * ACPI supports both logical (e.g. Hyper-Threading) and physical
469 * processors, where MPS only supports physical.
471 if (acpi_lapic && acpi_ioapic) {
472 printk(KERN_INFO "Using ACPI (MADT) for SMP configuration information\n");
476 printk(KERN_INFO "Using ACPI for processor (LAPIC) configuration information\n");
478 printk("Intel MultiProcessor Specification v1.%d\n", mpf->mpf_specification);
481 * Now see if we need to read further.
483 if (mpf->mpf_feature1 != 0) {
485 printk(KERN_INFO "Default MP configuration #%d\n", mpf->mpf_feature1);
486 construct_default_ISA_mptable(mpf->mpf_feature1);
488 } else if (mpf->mpf_physptr) {
491 * Read the physical hardware table. Anything here will
492 * override the defaults.
495 if (!smp_read_mpc(isa_bus_to_virt(mpf->mpf_physptr))) {
497 if (!smp_read_mpc(phys_to_virt(mpf->mpf_physptr))) {
499 smp_found_config = 0;
500 printk(KERN_ERR "BIOS bug, MP table errors detected!...\n");
501 printk(KERN_ERR "... disabling SMP support. (tell your hw vendor)\n");
505 * If there are no explicit MP IRQ entries, then we are
506 * broken. We set up most of the low 16 IO-APIC pins to
507 * ISA defaults and hope it will work.
509 if (!mp_irq_entries) {
510 struct mpc_config_bus bus;
512 printk(KERN_ERR "BIOS bug, no explicit IRQ entries, using default mptable. (tell your hw vendor)\n");
514 bus.mpc_type = MP_BUS;
516 memcpy(bus.mpc_bustype, "ISA ", 6);
519 construct_default_ioirq_mptable(0);
525 printk(KERN_INFO "Processors: %d\n", num_processors);
527 * Only use the first configuration found.
531 static int __init smp_scan_config (unsigned long base, unsigned long length)
533 extern void __bad_mpf_size(void);
535 unsigned int *bp = isa_bus_to_virt(base);
537 unsigned int *bp = phys_to_virt(base);
540 struct intel_mp_floating *mpf;
542 Dprintk("Scan SMP from %p for %ld bytes.\n", bp,length);
543 if (sizeof(*mpf) != 16)
547 mpf = (struct intel_mp_floating *)bp;
548 if ((*bp == SMP_MAGIC_IDENT) &&
549 (mpf->mpf_length == 1) &&
550 !mpf_checksum((unsigned char *)bp, 16) &&
551 ((mpf->mpf_specification == 1)
552 || (mpf->mpf_specification == 4)) ) {
554 smp_found_config = 1;
556 reserve_bootmem_generic(virt_to_phys(mpf), PAGE_SIZE);
557 if (mpf->mpf_physptr)
558 reserve_bootmem_generic(mpf->mpf_physptr, PAGE_SIZE);
569 void __init find_smp_config(void)
571 unsigned int address;
574 * FIXME: Linux assumes you have 640K of base ram..
575 * this continues the error...
577 * 1) Scan the bottom 1K for a signature
578 * 2) Scan the top 1K of base RAM
579 * 3) Scan the 64K of bios
581 if (smp_scan_config(0x0,0x400) ||
582 smp_scan_config(639*0x400,0x400) ||
583 smp_scan_config(0xF0000,0x10000))
586 * If it is an SMP machine we should know now.
588 * there is a real-mode segmented pointer pointing to the
589 * 4K EBDA area at 0x40E, calculate and scan it here.
591 * NOTE! There are Linux loaders that will corrupt the EBDA
592 * area, and as such this kind of SMP config may be less
593 * trustworthy, simply because the SMP table may have been
594 * stomped on during early boot. These loaders are buggy and
598 address = *(unsigned short *)phys_to_virt(0x40E);
600 if (smp_scan_config(address, 0x1000))
603 /* If we have come this far, we did not find an MP table */
604 printk(KERN_INFO "No mptable found.\n");
607 /* --------------------------------------------------------------------------
608 ACPI-based MP Configuration
609 -------------------------------------------------------------------------- */
613 void __init mp_register_lapic_address(u64 address)
616 mp_lapic_addr = (unsigned long) address;
617 set_fixmap_nocache(FIX_APIC_BASE, mp_lapic_addr);
618 if (boot_cpu_id == -1U)
619 boot_cpu_id = GET_APIC_ID(apic_read(APIC_ID));
623 void __cpuinit mp_register_lapic (u8 id, u8 enabled)
625 struct mpc_config_processor processor;
628 if (id == boot_cpu_id)
632 processor.mpc_type = MP_PROCESSOR;
633 processor.mpc_apicid = id;
634 processor.mpc_apicver = 0;
635 processor.mpc_cpuflag = (enabled ? CPU_ENABLED : 0);
636 processor.mpc_cpuflag |= (boot_cpu ? CPU_BOOTPROCESSOR : 0);
637 processor.mpc_cpufeature = 0;
638 processor.mpc_featureflag = 0;
639 processor.mpc_reserved[0] = 0;
640 processor.mpc_reserved[1] = 0;
643 MP_processor_info(&processor);
647 #define MP_MAX_IOAPIC_PIN 127
649 static struct mp_ioapic_routing {
653 u32 pin_programmed[4];
654 } mp_ioapic_routing[MAX_IO_APICS];
656 static int mp_find_ioapic(int gsi)
660 /* Find the IOAPIC that manages this GSI. */
661 for (i = 0; i < nr_ioapics; i++) {
662 if ((gsi >= mp_ioapic_routing[i].gsi_start)
663 && (gsi <= mp_ioapic_routing[i].gsi_end))
667 printk(KERN_ERR "ERROR: Unable to locate IOAPIC for GSI %d\n", gsi);
671 void __init mp_register_ioapic(u8 id, u32 address, u32 gsi_base)
675 if (bad_ioapic(address))
680 mp_ioapics[idx].mpc_type = MP_IOAPIC;
681 mp_ioapics[idx].mpc_flags = MPC_APIC_USABLE;
682 mp_ioapics[idx].mpc_apicaddr = address;
685 set_fixmap_nocache(FIX_IO_APIC_BASE_0 + idx, address);
687 mp_ioapics[idx].mpc_apicid = id;
688 mp_ioapics[idx].mpc_apicver = 0;
691 * Build basic IRQ lookup table to facilitate gsi->io_apic lookups
692 * and to prevent reprogramming of IOAPIC pins (PCI IRQs).
694 mp_ioapic_routing[idx].apic_id = mp_ioapics[idx].mpc_apicid;
695 mp_ioapic_routing[idx].gsi_start = gsi_base;
696 mp_ioapic_routing[idx].gsi_end = gsi_base +
697 io_apic_get_redir_entries(idx);
699 printk(KERN_INFO "IOAPIC[%d]: apic_id %d, address 0x%x, "
700 "GSI %d-%d\n", idx, mp_ioapics[idx].mpc_apicid,
701 mp_ioapics[idx].mpc_apicaddr,
702 mp_ioapic_routing[idx].gsi_start,
703 mp_ioapic_routing[idx].gsi_end);
707 mp_override_legacy_irq(u8 bus_irq, u8 polarity, u8 trigger, u32 gsi)
709 struct mpc_config_intsrc intsrc;
714 * Convert 'gsi' to 'ioapic.pin'.
716 ioapic = mp_find_ioapic(gsi);
719 pin = gsi - mp_ioapic_routing[ioapic].gsi_start;
722 * TBD: This check is for faulty timer entries, where the override
723 * erroneously sets the trigger to level, resulting in a HUGE
724 * increase of timer interrupts!
726 if ((bus_irq == 0) && (trigger == 3))
729 intsrc.mpc_type = MP_INTSRC;
730 intsrc.mpc_irqtype = mp_INT;
731 intsrc.mpc_irqflag = (trigger << 2) | polarity;
732 intsrc.mpc_srcbus = MP_ISA_BUS;
733 intsrc.mpc_srcbusirq = bus_irq; /* IRQ */
734 intsrc.mpc_dstapic = mp_ioapics[ioapic].mpc_apicid; /* APIC ID */
735 intsrc.mpc_dstirq = pin; /* INTIN# */
737 Dprintk("Int: type %d, pol %d, trig %d, bus %d, irq %d, %d-%d\n",
738 intsrc.mpc_irqtype, intsrc.mpc_irqflag & 3,
739 (intsrc.mpc_irqflag >> 2) & 3, intsrc.mpc_srcbus,
740 intsrc.mpc_srcbusirq, intsrc.mpc_dstapic, intsrc.mpc_dstirq);
742 mp_irqs[mp_irq_entries] = intsrc;
743 if (++mp_irq_entries == MAX_IRQ_SOURCES)
744 panic("Max # of irq sources exceeded!\n");
747 void __init mp_config_acpi_legacy_irqs(void)
749 struct mpc_config_intsrc intsrc;
754 * Fabricate the legacy ISA bus (bus #31).
756 set_bit(MP_ISA_BUS, mp_bus_not_pci);
759 * Locate the IOAPIC that manages the ISA IRQs (0-15).
761 ioapic = mp_find_ioapic(0);
765 intsrc.mpc_type = MP_INTSRC;
766 intsrc.mpc_irqflag = 0; /* Conforming */
767 intsrc.mpc_srcbus = MP_ISA_BUS;
768 intsrc.mpc_dstapic = mp_ioapics[ioapic].mpc_apicid;
771 * Use the default configuration for the IRQs 0-15. Unless
772 * overridden by (MADT) interrupt source override entries.
774 for (i = 0; i < 16; i++) {
777 for (idx = 0; idx < mp_irq_entries; idx++) {
778 struct mpc_config_intsrc *irq = mp_irqs + idx;
780 /* Do we already have a mapping for this ISA IRQ? */
781 if (irq->mpc_srcbus == MP_ISA_BUS && irq->mpc_srcbusirq == i)
784 /* Do we already have a mapping for this IOAPIC pin */
785 if ((irq->mpc_dstapic == intsrc.mpc_dstapic) &&
786 (irq->mpc_dstirq == i))
790 if (idx != mp_irq_entries) {
791 printk(KERN_DEBUG "ACPI: IRQ%d used by override.\n", i);
792 continue; /* IRQ already used */
795 intsrc.mpc_irqtype = mp_INT;
796 intsrc.mpc_srcbusirq = i; /* Identity mapped */
797 intsrc.mpc_dstirq = i;
799 Dprintk("Int: type %d, pol %d, trig %d, bus %d, irq %d, "
800 "%d-%d\n", intsrc.mpc_irqtype, intsrc.mpc_irqflag & 3,
801 (intsrc.mpc_irqflag >> 2) & 3, intsrc.mpc_srcbus,
802 intsrc.mpc_srcbusirq, intsrc.mpc_dstapic,
805 mp_irqs[mp_irq_entries] = intsrc;
806 if (++mp_irq_entries == MAX_IRQ_SOURCES)
807 panic("Max # of irq sources exceeded!\n");
811 int mp_register_gsi(u32 gsi, int triggering, int polarity)
817 if (acpi_irq_model != ACPI_IRQ_MODEL_IOAPIC)
820 /* Don't set up the ACPI SCI because it's already set up */
821 if (acpi_fadt.sci_int == gsi)
824 ioapic = mp_find_ioapic(gsi);
826 printk(KERN_WARNING "No IOAPIC for GSI %u\n", gsi);
830 ioapic_pin = gsi - mp_ioapic_routing[ioapic].gsi_start;
833 * Avoid pin reprogramming. PRTs typically include entries
834 * with redundant pin->gsi mappings (but unique PCI devices);
835 * we only program the IOAPIC on the first.
837 bit = ioapic_pin % 32;
838 idx = (ioapic_pin < 32) ? 0 : (ioapic_pin / 32);
840 printk(KERN_ERR "Invalid reference to IOAPIC pin "
841 "%d-%d\n", mp_ioapic_routing[ioapic].apic_id,
845 if ((1<<bit) & mp_ioapic_routing[ioapic].pin_programmed[idx]) {
846 Dprintk(KERN_DEBUG "Pin %d-%d already programmed\n",
847 mp_ioapic_routing[ioapic].apic_id, ioapic_pin);
851 mp_ioapic_routing[ioapic].pin_programmed[idx] |= (1<<bit);
853 io_apic_set_pci_routing(ioapic, ioapic_pin, gsi,
854 triggering == ACPI_EDGE_SENSITIVE ? 0 : 1,
855 polarity == ACPI_ACTIVE_HIGH ? 0 : 1);
858 #endif /*CONFIG_ACPI*/