2 * x86 SMP booting functions
4 * (c) 1995 Alan Cox, Building #3 <alan@redhat.com>
5 * (c) 1998, 1999, 2000 Ingo Molnar <mingo@redhat.com>
6 * Copyright 2001 Andi Kleen, SuSE Labs.
8 * Much of the core SMP work is based on previous work by Thomas Radke, to
9 * whom a great many thanks are extended.
11 * Thanks to Intel for making available several different Pentium,
12 * Pentium Pro and Pentium-II/Xeon MP machines.
13 * Original development of Linux SMP code supported by Caldera.
15 * This code is released under the GNU General Public License version 2 or
19 * Felix Koop : NR_CPUS used properly
20 * Jose Renau : Handle single CPU case.
21 * Alan Cox : By repeated request 8) - Total BogoMIP report.
22 * Greg Wright : Fix for kernel stacks panic.
23 * Erich Boleyn : MP v1.4 and additional changes.
24 * Matthias Sattler : Changes for 2.1 kernel map.
25 * Michel Lespinasse : Changes for 2.1 kernel map.
26 * Michael Chastain : Change trampoline.S to gnu as.
27 * Alan Cox : Dumb bug: 'B' step PPro's are fine
28 * Ingo Molnar : Added APIC timers, based on code
30 * Ingo Molnar : various cleanups and rewrites
31 * Tigran Aivazian : fixed "0.00 in /proc/uptime on SMP" bug.
32 * Maciej W. Rozycki : Bits for genuine 82489DX APICs
33 * Andi Kleen : Changed for SMP boot into long mode.
34 * Rusty Russell : Hacked into shape for new "hotplug" boot process.
37 #include <linux/config.h>
38 #include <linux/init.h>
41 #include <linux/kernel_stat.h>
42 #include <linux/smp_lock.h>
43 #include <linux/irq.h>
44 #include <linux/bootmem.h>
45 #include <linux/thread_info.h>
46 #include <linux/module.h>
48 #include <linux/delay.h>
49 #include <linux/mc146818rtc.h>
51 #include <asm/pgalloc.h>
53 #include <asm/kdebug.h>
54 #include <asm/tlbflush.h>
55 #include <asm/proto.h>
57 /* Number of siblings per CPU package */
58 int smp_num_siblings = 1;
59 /* Package ID of each logical CPU */
60 u8 phys_proc_id[NR_CPUS] = { [0 ... NR_CPUS-1] = BAD_APICID };
62 /* Bitmask of currently online CPUs */
63 cpumask_t cpu_online_map;
65 static cpumask_t cpu_callin_map;
66 cpumask_t cpu_callout_map;
67 static cpumask_t smp_commenced_mask;
69 /* Per CPU bogomips and other parameters */
70 struct cpuinfo_x86 cpu_data[NR_CPUS] __cacheline_aligned;
72 /* Set when the idlers are all forked */
73 int smp_threads_ready;
75 cpumask_t cpu_sibling_map[NR_CPUS] __cacheline_aligned;
78 * Trampoline 80x86 program as an array.
81 extern unsigned char trampoline_data [];
82 extern unsigned char trampoline_end [];
85 * Currently trivial. Write the real->protected mode
86 * bootstrap into the page concerned. The caller
87 * has made sure it's suitably aligned.
90 static unsigned long __init setup_trampoline(void)
92 void *tramp = __va(SMP_TRAMPOLINE_BASE);
93 extern volatile __u32 tramp_gdt_ptr;
94 tramp_gdt_ptr = __pa_symbol(&cpu_gdt_table);
95 memcpy(tramp, trampoline_data, trampoline_end - trampoline_data);
96 return virt_to_phys(tramp);
100 * The bootstrap kernel entry code has set these up. Save them for
104 static void __init smp_store_cpu_info(int id)
106 struct cpuinfo_x86 *c = cpu_data + id;
113 * TSC synchronization.
115 * We first check whether all CPUs have their TSC's synchronized,
116 * then we print a warning if not, and always resync.
119 static atomic_t tsc_start_flag = ATOMIC_INIT(0);
120 static atomic_t tsc_count_start = ATOMIC_INIT(0);
121 static atomic_t tsc_count_stop = ATOMIC_INIT(0);
122 static unsigned long long tsc_values[NR_CPUS];
126 extern unsigned int fast_gettimeoffset_quotient;
128 static void __init synchronize_tsc_bp (void)
131 unsigned long long t0;
132 unsigned long long sum, avg;
137 printk(KERN_INFO "checking TSC synchronization across %u CPUs: ",num_booting_cpus());
141 atomic_set(&tsc_start_flag, 1);
145 * We loop a few times to get a primed instruction cache,
146 * then the last pass is more or less synchronized and
147 * the BP and APs set their cycle counters to zero all at
148 * once. This reduces the chance of having random offsets
149 * between the processors, and guarantees that the maximum
150 * delay between the cycle counters is never bigger than
151 * the latency of information-passing (cachelines) between
154 for (i = 0; i < NR_LOOPS; i++) {
156 * all APs synchronize but they loop on '== num_cpus'
158 while (atomic_read(&tsc_count_start) != num_booting_cpus()-1) mb();
159 atomic_set(&tsc_count_stop, 0);
162 * this lets the APs save their current TSC:
164 atomic_inc(&tsc_count_start);
167 rdtscll(tsc_values[smp_processor_id()]);
169 * We clear the TSC in the last loop:
175 * Wait for all APs to leave the synchronization point:
177 while (atomic_read(&tsc_count_stop) != num_booting_cpus()-1) mb();
178 atomic_set(&tsc_count_start, 0);
180 atomic_inc(&tsc_count_stop);
184 for (i = 0; i < NR_CPUS; i++) {
185 if (cpu_isset(i, cpu_callout_map)) {
190 avg = sum / num_booting_cpus();
193 for (i = 0; i < NR_CPUS; i++) {
194 if (!cpu_isset(i, cpu_callout_map))
197 delta = tsc_values[i] - avg;
201 * We report bigger than 2 microseconds clock differences.
203 if (delta > 2*one_usec) {
209 realdelta = delta / one_usec;
210 if (tsc_values[i] < avg)
211 realdelta = -realdelta;
213 printk("BIOS BUG: CPU#%d improperly initialized, has %ld usecs TSC skew! FIXED.\n",
223 static void __init synchronize_tsc_ap (void)
228 * Not every cpu is online at the time
229 * this gets called, so we first wait for the BP to
230 * finish SMP initialization:
232 while (!atomic_read(&tsc_start_flag)) mb();
234 for (i = 0; i < NR_LOOPS; i++) {
235 atomic_inc(&tsc_count_start);
236 while (atomic_read(&tsc_count_start) != num_booting_cpus()) mb();
239 rdtscll(tsc_values[smp_processor_id()]);
243 atomic_inc(&tsc_count_stop);
244 while (atomic_read(&tsc_count_stop) != num_booting_cpus()) mb();
249 static atomic_t init_deasserted;
251 void __init smp_callin(void)
254 unsigned long timeout;
257 * If waken up by an INIT in an 82489DX configuration
258 * we may get here before an INIT-deassert IPI reaches
259 * our local APIC. We have to wait for the IPI or we'll
260 * lock up on an APIC access.
262 while (!atomic_read(&init_deasserted));
265 * (This works even if the APIC is not enabled.)
267 phys_id = GET_APIC_ID(apic_read(APIC_ID));
268 cpuid = smp_processor_id();
269 if (cpu_isset(cpuid, cpu_callin_map)) {
270 panic("smp_callin: phys CPU#%d, CPU#%d already present??\n",
273 Dprintk("CPU#%d (phys ID: %d) waiting for CALLOUT\n", cpuid, phys_id);
276 * STARTUP IPIs are fragile beasts as they might sometimes
277 * trigger some glue motherboard logic. Complete APIC bus
278 * silence for 1 second, this overestimates the time the
279 * boot CPU is spending to send the up to 2 STARTUP IPIs
280 * by a factor of two. This should be enough.
284 * Waiting 2s total for startup (udelay is not yet working)
286 timeout = jiffies + 2*HZ;
287 while (time_before(jiffies, timeout)) {
289 * Has the boot CPU finished it's STARTUP sequence?
291 if (cpu_isset(cpuid, cpu_callout_map))
296 if (!time_before(jiffies, timeout)) {
297 panic("smp_callin: CPU%d started up but did not get a callout!\n",
302 * the boot CPU has finished the init stage and is spinning
303 * on callin_map until we finish. We are free to set up this
304 * CPU, first the APIC. (this is probably redundant on most
308 Dprintk("CALLIN, before setup_local_APIC().\n");
317 Dprintk("Stack at about %p\n",&cpuid);
319 disable_APIC_timer();
322 * Save our processor parameters
324 smp_store_cpu_info(cpuid);
329 * Allow the master to continue.
331 cpu_set(cpuid, cpu_callin_map);
334 * Synchronize the TSC with the BP
337 synchronize_tsc_ap();
343 * Activate a secondary processor.
345 void __init start_secondary(void)
348 * Dont put anything before smp_callin(), SMP
349 * booting is too fragile that we want to limit the
350 * things done here to the most necessary things.
355 /* otherwise gcc will move up the smp_processor_id before the cpu_init */
358 Dprintk("cpu %d: waiting for commence\n", smp_processor_id());
359 while (!cpu_isset(smp_processor_id(), smp_commenced_mask))
362 Dprintk("cpu %d: setting up apic clock\n", smp_processor_id());
363 setup_secondary_APIC_clock();
365 Dprintk("cpu %d: enabling apic timer\n", smp_processor_id());
367 if (nmi_watchdog == NMI_IO_APIC) {
368 disable_8259A_irq(0);
369 enable_NMI_through_LVT0(NULL);
377 * low-memory mappings have been cleared, flush them from
378 * the local TLBs too.
382 Dprintk("cpu %d eSetting cpu_online_map\n", smp_processor_id());
383 cpu_set(smp_processor_id(), cpu_online_map);
389 extern volatile unsigned long init_rsp;
390 extern void (*initial_code)(void);
393 static inline void inquire_remote_apic(int apicid)
395 unsigned i, regs[] = { APIC_ID >> 4, APIC_LVR >> 4, APIC_SPIV >> 4 };
396 char *names[] = { "ID", "VERSION", "SPIV" };
399 printk(KERN_INFO "Inquiring remote APIC #%d...\n", apicid);
401 for (i = 0; i < sizeof(regs) / sizeof(*regs); i++) {
402 printk("... APIC #%d %s: ", apicid, names[i]);
407 apic_wait_icr_idle();
409 apic_write_around(APIC_ICR2, SET_APIC_DEST_FIELD(apicid));
410 apic_write_around(APIC_ICR, APIC_DM_REMRD | regs[i]);
415 status = apic_read(APIC_ICR) & APIC_ICR_RR_MASK;
416 } while (status == APIC_ICR_RR_INPROG && timeout++ < 1000);
419 case APIC_ICR_RR_VALID:
420 status = apic_read(APIC_RRR);
421 printk("%08x\n", status);
430 static int __init wakeup_secondary_via_INIT(int phys_apicid, unsigned int start_rip)
432 unsigned long send_status = 0, accept_status = 0;
433 int maxlvt, timeout, num_starts, j;
435 Dprintk("Asserting INIT.\n");
438 * Turn INIT on target chip
440 apic_write_around(APIC_ICR2, SET_APIC_DEST_FIELD(phys_apicid));
445 apic_write_around(APIC_ICR, APIC_INT_LEVELTRIG | APIC_INT_ASSERT
448 Dprintk("Waiting for send to finish...\n");
453 send_status = apic_read(APIC_ICR) & APIC_ICR_BUSY;
454 } while (send_status && (timeout++ < 1000));
458 Dprintk("Deasserting INIT.\n");
461 apic_write_around(APIC_ICR2, SET_APIC_DEST_FIELD(phys_apicid));
464 apic_write_around(APIC_ICR, APIC_INT_LEVELTRIG | APIC_DM_INIT);
466 Dprintk("Waiting for send to finish...\n");
471 send_status = apic_read(APIC_ICR) & APIC_ICR_BUSY;
472 } while (send_status && (timeout++ < 1000));
474 atomic_set(&init_deasserted, 1);
477 * Should we send STARTUP IPIs ?
479 * Determine this based on the APIC version.
480 * If we don't have an integrated APIC, don't send the STARTUP IPIs.
482 if (APIC_INTEGRATED(apic_version[phys_apicid]))
488 * Run STARTUP IPI loop.
490 Dprintk("#startup loops: %d.\n", num_starts);
492 maxlvt = get_maxlvt();
494 for (j = 1; j <= num_starts; j++) {
495 Dprintk("Sending STARTUP #%d.\n",j);
496 apic_read_around(APIC_SPIV);
497 apic_write(APIC_ESR, 0);
499 Dprintk("After apic_write.\n");
506 apic_write_around(APIC_ICR2, SET_APIC_DEST_FIELD(phys_apicid));
508 /* Boot on the stack */
509 /* Kick the second */
510 apic_write_around(APIC_ICR, APIC_DM_STARTUP
511 | (start_rip >> 12));
514 * Give the other CPU some time to accept the IPI.
518 Dprintk("Startup point 1.\n");
520 Dprintk("Waiting for send to finish...\n");
525 send_status = apic_read(APIC_ICR) & APIC_ICR_BUSY;
526 } while (send_status && (timeout++ < 1000));
529 * Give the other CPU some time to accept the IPI.
533 * Due to the Pentium erratum 3AP.
536 apic_read_around(APIC_SPIV);
537 apic_write(APIC_ESR, 0);
539 accept_status = (apic_read(APIC_ESR) & 0xEF);
540 if (send_status || accept_status)
543 Dprintk("After Startup.\n");
546 printk(KERN_ERR "APIC never delivered???\n");
548 printk(KERN_ERR "APIC delivery error (%lx).\n", accept_status);
550 return (send_status | accept_status);
553 static void __init do_boot_cpu (int apicid)
555 struct task_struct *idle;
556 unsigned long boot_error;
558 unsigned long start_rip;
562 * We can't use kernel_thread since we must avoid to
563 * reschedule the child.
565 idle = fork_idle(cpu);
567 panic("failed fork for CPU %d", cpu);
568 x86_cpu_to_apicid[cpu] = apicid;
570 cpu_pda[cpu].pcurrent = idle;
572 start_rip = setup_trampoline();
574 init_rsp = idle->thread.rsp;
575 per_cpu(init_tss,cpu).rsp0 = init_rsp;
576 initial_code = start_secondary;
577 clear_ti_thread_flag(idle->thread_info, TIF_FORK);
579 printk(KERN_INFO "Booting processor %d/%d rip %lx rsp %lx\n", cpu, apicid,
580 start_rip, init_rsp);
583 * This grunge runs the startup process for
584 * the targeted processor.
587 atomic_set(&init_deasserted, 0);
589 Dprintk("Setting warm reset code and vector.\n");
591 CMOS_WRITE(0xa, 0xf);
594 *((volatile unsigned short *) phys_to_virt(0x469)) = start_rip >> 4;
596 *((volatile unsigned short *) phys_to_virt(0x467)) = start_rip & 0xf;
600 * Be paranoid about clearing APIC errors.
602 if (APIC_INTEGRATED(apic_version[apicid])) {
603 apic_read_around(APIC_SPIV);
604 apic_write(APIC_ESR, 0);
609 * Status is now clean
614 * Starting actual IPI sequence...
616 boot_error = wakeup_secondary_via_INIT(apicid, start_rip);
620 * allow APs to start initializing.
622 Dprintk("Before Callout %d.\n", cpu);
623 cpu_set(cpu, cpu_callout_map);
624 Dprintk("After Callout %d.\n", cpu);
627 * Wait 5s total for a response
629 for (timeout = 0; timeout < 50000; timeout++) {
630 if (cpu_isset(cpu, cpu_callin_map))
631 break; /* It has booted */
635 if (cpu_isset(cpu, cpu_callin_map)) {
636 /* number CPUs logically, starting from 1 (BSP is 0) */
638 print_cpu_info(&cpu_data[cpu]);
639 Dprintk("CPU has booted.\n");
642 if (*((volatile unsigned char *)phys_to_virt(SMP_TRAMPOLINE_BASE))
644 /* trampoline started but...? */
645 printk("Stuck ??\n");
647 /* trampoline code not run */
648 printk("Not responding.\n");
650 inquire_remote_apic(apicid);
655 cpu_clear(cpu, cpu_callout_map); /* was set here (do_boot_cpu()) */
656 clear_bit(cpu, &cpu_initialized); /* was set by cpu_init() */
658 x86_cpu_to_apicid[cpu] = BAD_APICID;
659 x86_cpu_to_log_apicid[cpu] = BAD_APICID;
663 cycles_t cacheflush_time;
664 unsigned long cache_decay_ticks;
666 static void smp_tune_scheduling (void)
668 int cachesize; /* kB */
669 unsigned long bandwidth = 1000; /* MB/s */
671 * Rough estimation for SMP scheduling, this is the number of
672 * cycles it takes for a fully memory-limited process to flush
673 * the SMP-local cache.
675 * (For a P5 this pretty much means we will choose another idle
676 * CPU almost always at wakeup time (this is due to the small
677 * L1 cache), on PIIs it's around 50-100 usecs, depending on
683 * this basically disables processor-affinity
684 * scheduling on SMP without a TSC.
689 cachesize = boot_cpu_data.x86_cache_size;
690 if (cachesize == -1) {
691 cachesize = 16; /* Pentiums, 2x8kB cache */
695 cacheflush_time = (cpu_khz>>10) * (cachesize<<10) / bandwidth;
698 cache_decay_ticks = (long)cacheflush_time/cpu_khz * HZ / 1000;
700 printk(KERN_INFO "per-CPU timeslice cutoff: %ld.%02ld usecs.\n",
701 (long)cacheflush_time/(cpu_khz/1000),
702 ((long)cacheflush_time*100/(cpu_khz/1000)) % 100);
703 printk(KERN_INFO "task migration cache decay timeout: %ld msecs.\n",
704 (cache_decay_ticks + 1) * 1000 / HZ);
708 * Cycle through the processors sending APIC IPIs to boot each.
711 static void __init smp_boot_cpus(unsigned int max_cpus)
713 unsigned apicid, cpu, bit, kicked;
715 nmi_watchdog_default();
718 * Setup boot CPU information
720 smp_store_cpu_info(0); /* Final full version of the data */
721 printk(KERN_INFO "CPU%d: ", 0);
722 print_cpu_info(&cpu_data[0]);
724 current_thread_info()->cpu = 0;
725 smp_tune_scheduling();
727 if (!physid_isset(hard_smp_processor_id(), phys_cpu_present_map)) {
728 printk("weird, boot CPU (#%d) not listed by the BIOS.\n",
729 hard_smp_processor_id());
730 physid_set(hard_smp_processor_id(), phys_cpu_present_map);
734 * If we couldn't find an SMP configuration at boot time,
735 * get out of here now!
737 if (!smp_found_config) {
738 printk(KERN_NOTICE "SMP motherboard not detected.\n");
740 cpu_online_map = cpumask_of_cpu(0);
741 phys_cpu_present_map = physid_mask_of_physid(0);
742 if (APIC_init_uniprocessor())
743 printk(KERN_NOTICE "Local APIC not detected."
744 " Using dummy APIC emulation.\n");
749 * Should not be necessary because the MP table should list the boot
750 * CPU too, but we do it for the sake of robustness anyway.
752 if (!physid_isset(boot_cpu_id, phys_cpu_present_map)) {
753 printk(KERN_NOTICE "weird, boot CPU (#%d) not listed by the BIOS.\n",
755 physid_set(hard_smp_processor_id(), phys_cpu_present_map);
759 * If we couldn't find a local APIC, then get out of here now!
761 if (APIC_INTEGRATED(apic_version[boot_cpu_id]) && !cpu_has_apic) {
762 printk(KERN_ERR "BIOS bug, local APIC #%d not detected!...\n",
764 printk(KERN_ERR "... forcing use of dummy APIC emulation. (tell your hw vendor)\n");
766 cpu_online_map = cpumask_of_cpu(0);
767 phys_cpu_present_map = physid_mask_of_physid(0);
775 * If SMP should be disabled, then really disable it!
778 smp_found_config = 0;
779 printk(KERN_INFO "SMP mode deactivated, forcing use of dummy APIC emulation.\n");
781 cpu_online_map = cpumask_of_cpu(0);
782 phys_cpu_present_map = physid_mask_of_physid(0);
790 if (GET_APIC_ID(apic_read(APIC_ID)) != boot_cpu_id)
793 x86_cpu_to_apicid[0] = boot_cpu_id;
796 * Now scan the CPU present map and fire up the other CPUs.
798 Dprintk("CPU present map: %lx\n", physids_coerce(phys_cpu_present_map));
801 for (bit = 0; kicked < NR_CPUS && bit < MAX_APICS; bit++) {
802 apicid = cpu_present_to_apicid(bit);
804 * Don't even attempt to start the boot CPU!
806 if (apicid == boot_cpu_id || (apicid == BAD_APICID))
809 if (!physid_isset(apicid, phys_cpu_present_map))
811 if ((max_cpus >= 0) && (max_cpus <= cpucount+1))
819 * Cleanup possible dangling ends...
823 * Install writable page 0 entry to set BIOS data area.
828 * Paranoid: Set warm reset code and vector here back
833 *((volatile int *) phys_to_virt(0x467)) = 0;
837 * Allow the user to impress friends.
840 Dprintk("Before bogomips.\n");
842 printk(KERN_INFO "Only one processor found.\n");
844 unsigned long bogosum = 0;
845 for (cpu = 0; cpu < NR_CPUS; cpu++)
846 if (cpu_isset(cpu, cpu_callout_map))
847 bogosum += cpu_data[cpu].loops_per_jiffy;
848 printk(KERN_INFO "Total of %d processors activated (%lu.%02lu BogoMIPS).\n",
851 (bogosum/(5000/HZ))%100);
852 Dprintk("Before bogocount - setting activated=1.\n");
856 * Construct cpu_sibling_map[], so that we can tell the
857 * sibling CPU efficiently.
859 for (cpu = 0; cpu < NR_CPUS; cpu++)
860 cpus_clear(cpu_sibling_map[cpu]);
862 for (cpu = 0; cpu < NR_CPUS; cpu++) {
865 if (!cpu_isset(cpu, cpu_callout_map))
868 if (smp_num_siblings > 1) {
869 for (i = 0; i < NR_CPUS; i++) {
870 if (!cpu_isset(i, cpu_callout_map))
872 if (phys_proc_id[cpu] == phys_proc_id[i]) {
874 cpu_set(i, cpu_sibling_map[cpu]);
879 cpu_set(cpu, cpu_sibling_map[cpu]);
882 if (siblings != smp_num_siblings) {
884 "WARNING: %d siblings found for CPU%d, should be %d\n",
885 siblings, cpu, smp_num_siblings);
886 smp_num_siblings = siblings;
890 Dprintk("Boot done.\n");
893 * Here we can be sure that there is an IO-APIC in the system. Let's
896 if (!skip_ioapic_setup && nr_ioapics)
901 setup_boot_APIC_clock();
904 * Synchronize the TSC with the AP
906 if (cpu_has_tsc && cpucount)
907 synchronize_tsc_bp();
913 /* These are wrappers to interface to the new boot process. Someone
914 who understands all this stuff should rewrite it properly. --RR 15/Jul/02 */
915 void __init smp_prepare_cpus(unsigned int max_cpus)
917 smp_boot_cpus(max_cpus);
920 void __devinit smp_prepare_boot_cpu(void)
922 cpu_set(smp_processor_id(), cpu_online_map);
923 cpu_set(smp_processor_id(), cpu_callout_map);
926 int __devinit __cpu_up(unsigned int cpu)
928 /* This only works at boot for x86. See "rewrite" above. */
929 if (cpu_isset(cpu, smp_commenced_mask)) {
934 /* In case one didn't come up */
935 if (!cpu_isset(cpu, cpu_callin_map)) {
941 /* Unleash the CPU! */
942 Dprintk("waiting for cpu %d\n", cpu);
944 cpu_set(cpu, smp_commenced_mask);
945 while (!cpu_isset(cpu, cpu_online_map))
950 void __init smp_cpus_done(unsigned int max_cpus)
952 #ifdef CONFIG_X86_IO_APIC