2 * linux/arch/x86_64/kernel/head.S -- start in 32bit and switch to 64bit
4 * Copyright (C) 2000 Andrea Arcangeli <andrea@suse.de> SuSE
5 * Copyright (C) 2000 Pavel Machek <pavel@suse.cz>
6 * Copyright (C) 2000 Karsten Keil <kkeil@suse.de>
7 * Copyright (C) 2001,2002 Andi Kleen <ak@suse.de>
9 * $Id: head.S,v 1.49 2002/03/19 17:39:25 ak Exp $
11 * Jun Nakajima <jun.nakajima@intel.com>
16 #include <linux/linkage.h>
19 .ascii "GUEST_OS=linux,GUEST_VER=2.6,XEN_VER=3.0,VIRT_BASE=0xffffffff80100000"
20 .ascii ",LOADER=generic"
21 /* .ascii ",PT_MODE_WRITABLE" */
25 #include <linux/threads.h>
27 #include <asm/segment.h>
30 #include <asm/cache.h>
31 /* #include <asm/thread_info.h> */
34 /* we are not able to switch in one step to the final KERNEL ADRESS SPACE
35 * because we need identity-mapped pages on setup so define __START_KERNEL to
36 * 0x100000 for this stage
44 movq init_rsp(%rip),%rsp
45 /* Copy the necessary stuff from xen_start_info structure. */
46 movq $xen_start_info_union,%rdi
47 movq $64,%rcx /* sizeof (union xen_start_info_union) / sizeof (long) */
53 #endif /* CONFIG_SMP */
55 /* zero EFLAGS after setting rsp */
58 movq initial_code(%rip),%rax
61 /* SMP bootup changes these two */
64 .quad x86_64_start_kernel
67 .quad init_thread_union+THREAD_SIZE-8
69 ENTRY(early_idt_handler)
71 movq 8(%rsp),%rsi # get rip
73 leaq early_idt_msg(%rip),%rdi
78 .asciz "PANIC: early exception rip %lx error %lx cr2 %lx\n"
82 movl $(__USER_DS),%eax # DS/ES contains default USER segment
85 movl $(__KERNEL_DS),%eax
86 movw %ax,%ss # after changing gdt.
87 popq %rax # get the retrun address
97 * This default setting generates an ident mapping at address 0x100000
98 * and a mapping for the kernel that precisely maps virtual address
99 * 0xffffffff80000000 to physical address 0x000000. (always using
100 * 2Mbyte large pages provided by PAE mode)
103 ENTRY(init_level4_pgt)
107 * We update two pgd entries to make kernel and user pgd consistent
108 * at pgd_populate(). It can be used for kernel modules. So we place
109 * this page here for those cases to avoid memory corruption.
110 * We also use this page to establish the initiali mapping for
114 ENTRY(init_level4_user_pgt)
118 * This is used for vsyscall area mapping as we have a different
119 * level4 page table for user.
122 ENTRY(level3_user_pgt)
127 /* The TLS descriptors are currently at a different place compared to i386.
128 Hopefully nobody expects them at a fixed place (Wine?) */
129 .quad 0x0000000000000000 /* NULL descriptor */
130 .quad 0x008ffa000000ffff /* __KERNEL_COMPAT32_CS */
131 .quad 0x00affa000000ffff /* __KERNEL_CS */
132 .quad 0x00cff2000000ffff /* __KERNEL_DS */
134 .quad 0x00cffa000000ffff /* __USER32_CS */
135 .quad 0x00cff2000000ffff /* __USER_DS, __USER32_DS */
136 .quad 0x00affa000000ffff /* __USER_CS */
137 .quad 0x00cffa000000ffff /* __KERNEL32_CS */
140 .quad 0,0,0 /* three TLS descriptors */
141 .quad 0 /* unused now */
144 /* asm/segment.h:GDT_ENTRIES must match this */
145 /* This should be a multiple of the cache line size */
146 /* GDTs of other CPUs: */
147 .fill (GDT_SIZE * NR_CPUS) - (gdt_end - cpu_gdt_table)
150 ENTRY(empty_zero_page)
153 ENTRY(empty_bad_page)
156 ENTRY(empty_bad_pte_table)
159 ENTRY(empty_bad_pmd_table)
162 #ifdef CONFIG_ACPI_SLEEP
163 ENTRY(wakeup_level4_pgt)
164 .quad 0x0000000000102007 /* -> level3_ident_pgt */
166 .quad 0x000000000010a007
168 /* (2^48-(2*1024*1024*1024))/(2^39) = 511 */
169 .quad 0x0000000000103007 /* -> level3_kernel_pgt */
177 .word gdt_end-cpu_gdt_table
188 .quad 0x0000000000000000 /* This one is magic */
189 .quad 0x0000000000000000 /* unused */
190 .quad 0x00af9a000000ffff /* __KERNEL_CS */
193 /* We need valid kernel segments for data and code in long mode too
194 * IRET will check the segment types kkeil 2000/10/28
195 * Also sysret mandates a special GDT layout
199 .align L1_CACHE_BYTES
201 .align L1_CACHE_BYTES