2 * IDE tuning and bus mastering support for the CS5510/CS5520
5 * The CS5510/CS5520 are slightly unusual devices. Unlike the
6 * typical IDE controllers they do bus mastering with the drive in
7 * PIO mode and smarter silicon.
9 * The practical upshot of this is that we must always tune the
10 * drive for the right PIO mode. We must also ignore all the blacklists
11 * and the drive bus mastering DMA information. Also to confuse matters
12 * further we can do DMA on PIO only drives.
14 * DMA on the 5510 also requires we disable_hlt() during DMA on early
17 * *** This driver is strictly experimental ***
19 * (c) Copyright Red Hat Inc 2002
21 * This program is free software; you can redistribute it and/or modify it
22 * under the terms of the GNU General Public License as published by the
23 * Free Software Foundation; either version 2, or (at your option) any
26 * This program is distributed in the hope that it will be useful, but
27 * WITHOUT ANY WARRANTY; without even the implied warranty of
28 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
29 * General Public License for more details.
32 * Not publically available.
34 #include <linux/kernel.h>
35 #include <linux/module.h>
36 #include <linux/pci.h>
37 #include <linux/init.h>
38 #include <linux/blkdev.h>
39 #include <linux/delay.h>
40 #include <scsi/scsi_host.h>
41 #include <linux/libata.h>
43 #define DRV_NAME "pata_cs5520"
44 #define DRV_VERSION "0.6.3"
53 static const struct pio_clocks cs5520_pio_clocks[]={
62 * cs5520_set_timings - program PIO timings
66 * Program the PIO mode timings for the controller according to the pio
70 static void cs5520_set_timings(struct ata_port *ap, struct ata_device *adev, int pio)
72 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
73 int slave = adev->devno;
77 /* Channel command timing */
78 pci_write_config_byte(pdev, 0x62 + ap->port_no,
79 (cs5520_pio_clocks[pio].recovery << 4) |
80 (cs5520_pio_clocks[pio].assert));
81 /* FIXME: should these use address ? */
82 /* Read command timing */
83 pci_write_config_byte(pdev, 0x64 + 4*ap->port_no + slave,
84 (cs5520_pio_clocks[pio].recovery << 4) |
85 (cs5520_pio_clocks[pio].assert));
86 /* Write command timing */
87 pci_write_config_byte(pdev, 0x66 + 4*ap->port_no + slave,
88 (cs5520_pio_clocks[pio].recovery << 4) |
89 (cs5520_pio_clocks[pio].assert));
93 * cs5520_enable_dma - turn on DMA bits
95 * Turn on the DMA bits for this disk. Needed because the BIOS probably
96 * has not done the work for us. Belongs in the core SATA code.
99 static void cs5520_enable_dma(struct ata_port *ap, struct ata_device *adev)
101 /* Set the DMA enable/disable flag */
102 u8 reg = inb(ap->ioaddr.bmdma_addr + 0x02);
103 reg |= 1<<(adev->devno + 5);
104 outb(reg, ap->ioaddr.bmdma_addr + 0x02);
108 * cs5520_set_dmamode - program DMA timings
112 * Program the DMA mode timings for the controller according to the pio
113 * clocking table. Note that this device sets the DMA timings to PIO
114 * mode values. This may seem bizarre but the 5520 architecture talks
115 * PIO mode to the disk and DMA mode to the controller so the underlying
116 * transfers are PIO timed.
119 static void cs5520_set_dmamode(struct ata_port *ap, struct ata_device *adev)
121 static const int dma_xlate[3] = { XFER_PIO_0, XFER_PIO_3, XFER_PIO_4 };
122 cs5520_set_timings(ap, adev, dma_xlate[adev->dma_mode]);
123 cs5520_enable_dma(ap, adev);
127 * cs5520_set_piomode - program PIO timings
131 * Program the PIO mode timings for the controller according to the pio
132 * clocking table. We know pio_mode will equal dma_mode because of the
133 * CS5520 architecture. At least once we turned DMA on and wrote a
137 static void cs5520_set_piomode(struct ata_port *ap, struct ata_device *adev)
139 cs5520_set_timings(ap, adev, adev->pio_mode);
143 static int cs5520_pre_reset(struct ata_port *ap)
145 ap->cbl = ATA_CBL_PATA40;
146 return ata_std_prereset(ap);
149 static void cs5520_error_handler(struct ata_port *ap)
151 return ata_bmdma_drive_eh(ap, cs5520_pre_reset, ata_std_softreset, NULL, ata_std_postreset);
154 static struct scsi_host_template cs5520_sht = {
155 .module = THIS_MODULE,
157 .ioctl = ata_scsi_ioctl,
158 .queuecommand = ata_scsi_queuecmd,
159 .can_queue = ATA_DEF_QUEUE,
160 .this_id = ATA_SHT_THIS_ID,
161 .sg_tablesize = LIBATA_MAX_PRD,
162 .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
163 .emulated = ATA_SHT_EMULATED,
164 .use_clustering = ATA_SHT_USE_CLUSTERING,
165 .proc_name = DRV_NAME,
166 .dma_boundary = ATA_DMA_BOUNDARY,
167 .slave_configure = ata_scsi_slave_config,
168 .slave_destroy = ata_scsi_slave_destroy,
169 .bios_param = ata_std_bios_param,
171 .resume = ata_scsi_device_resume,
172 .suspend = ata_scsi_device_suspend,
176 static struct ata_port_operations cs5520_port_ops = {
177 .port_disable = ata_port_disable,
178 .set_piomode = cs5520_set_piomode,
179 .set_dmamode = cs5520_set_dmamode,
181 .tf_load = ata_tf_load,
182 .tf_read = ata_tf_read,
183 .check_status = ata_check_status,
184 .exec_command = ata_exec_command,
185 .dev_select = ata_std_dev_select,
187 .freeze = ata_bmdma_freeze,
188 .thaw = ata_bmdma_thaw,
189 .error_handler = cs5520_error_handler,
190 .post_internal_cmd = ata_bmdma_post_internal_cmd,
192 .bmdma_setup = ata_bmdma_setup,
193 .bmdma_start = ata_bmdma_start,
194 .bmdma_stop = ata_bmdma_stop,
195 .bmdma_status = ata_bmdma_status,
196 .qc_prep = ata_qc_prep,
197 .qc_issue = ata_qc_issue_prot,
198 .data_xfer = ata_pio_data_xfer,
200 .irq_handler = ata_interrupt,
201 .irq_clear = ata_bmdma_irq_clear,
203 .port_start = ata_port_start,
204 .port_stop = ata_port_stop,
205 .host_stop = ata_host_stop,
208 static int __devinit cs5520_init_one(struct pci_dev *dev, const struct pci_device_id *id)
211 static struct ata_probe_ent probe[2];
214 /* IDE port enable bits */
215 pci_read_config_byte(dev, 0x60, &pcicfg);
217 /* Check if the ATA ports are enabled */
218 if ((pcicfg & 3) == 0)
221 if ((pcicfg & 0x40) == 0) {
222 printk(KERN_WARNING DRV_NAME ": DMA mode disabled. Enabling.\n");
223 pci_write_config_byte(dev, 0x60, pcicfg | 0x40);
226 /* Perform set up for DMA */
227 if (pci_enable_device_bars(dev, 1<<2)) {
228 printk(KERN_ERR DRV_NAME ": unable to configure BAR2.\n");
232 if (pci_set_dma_mask(dev, DMA_32BIT_MASK)) {
233 printk(KERN_ERR DRV_NAME ": unable to configure DMA mask.\n");
236 if (pci_set_consistent_dma_mask(dev, DMA_32BIT_MASK)) {
237 printk(KERN_ERR DRV_NAME ": unable to configure consistent DMA mask.\n");
241 /* We have to do our own plumbing as the PCI setup for this
242 chipset is non-standard so we can't punt to the libata code */
244 INIT_LIST_HEAD(&probe[0].node);
245 probe[0].dev = pci_dev_to_dev(dev);
246 probe[0].port_ops = &cs5520_port_ops;
247 probe[0].sht = &cs5520_sht;
248 probe[0].pio_mask = 0x1F;
249 probe[0].mwdma_mask = id->driver_data;
251 probe[0].irq_flags = 0;
252 probe[0].port_flags = ATA_FLAG_SLAVE_POSS|ATA_FLAG_SRST;
253 probe[0].n_ports = 1;
254 probe[0].port[0].cmd_addr = 0x1F0;
255 probe[0].port[0].ctl_addr = 0x3F6;
256 probe[0].port[0].altstatus_addr = 0x3F6;
257 probe[0].port[0].bmdma_addr = pci_resource_start(dev, 2);
259 /* The secondary lurks at different addresses but is otherwise
263 INIT_LIST_HEAD(&probe[1].node);
265 probe[1].port[0].cmd_addr = 0x170;
266 probe[1].port[0].ctl_addr = 0x376;
267 probe[1].port[0].altstatus_addr = 0x376;
268 probe[1].port[0].bmdma_addr = pci_resource_start(dev, 2) + 8;
270 /* Let libata fill in the port details */
271 ata_std_ports(&probe[0].port[0]);
272 ata_std_ports(&probe[1].port[0]);
274 /* Now add the ports that are active */
276 ports += ata_device_add(&probe[0]);
278 ports += ata_device_add(&probe[1]);
285 * cs5520_remove_one - device unload
286 * @pdev: PCI device being removed
288 * Handle an unplug/unload event for a PCI device. Unload the
289 * PCI driver but do not use the default handler as we manage
290 * resources ourself and *MUST NOT* disable the device as it has
294 static void __devexit cs5520_remove_one(struct pci_dev *pdev)
296 struct device *dev = pci_dev_to_dev(pdev);
297 struct ata_host *host = dev_get_drvdata(dev);
299 ata_host_remove(host);
300 dev_set_drvdata(dev, NULL);
305 * cs5520_reinit_one - device resume
308 * Do any reconfiguration work needed by a resume from RAM. We need
309 * to restore DMA mode support on BIOSen which disabled it
312 static int cs5520_reinit_one(struct pci_dev *pdev)
315 pci_read_config_byte(pdev, 0x60, &pcicfg);
316 if ((pcicfg & 0x40) == 0)
317 pci_write_config_byte(pdev, 0x60, pcicfg | 0x40);
318 return ata_pci_device_resume(pdev);
322 /* For now keep DMA off. We can set it for all but A rev CS5510 once the
323 core ATA code can handle it */
325 static const struct pci_device_id pata_cs5520[] = {
326 { PCI_VDEVICE(CYRIX, PCI_DEVICE_ID_CYRIX_5510), },
327 { PCI_VDEVICE(CYRIX, PCI_DEVICE_ID_CYRIX_5520), },
332 static struct pci_driver cs5520_pci_driver = {
334 .id_table = pata_cs5520,
335 .probe = cs5520_init_one,
336 .remove = cs5520_remove_one,
338 .suspend = ata_pci_device_suspend,
339 .resume = cs5520_reinit_one,
343 static int __init cs5520_init(void)
345 return pci_register_driver(&cs5520_pci_driver);
348 static void __exit cs5520_exit(void)
350 pci_unregister_driver(&cs5520_pci_driver);
353 MODULE_AUTHOR("Alan Cox");
354 MODULE_DESCRIPTION("low-level driver for Cyrix CS5510/5520");
355 MODULE_LICENSE("GPL");
356 MODULE_DEVICE_TABLE(pci, pata_cs5520);
357 MODULE_VERSION(DRV_VERSION);
359 module_init(cs5520_init);
360 module_exit(cs5520_exit);