2 * sata_promise.c - Promise SATA
4 * Maintained by: Jeff Garzik <jgarzik@pobox.com>
5 * Please ALWAYS copy linux-ide@vger.kernel.org
8 * Copyright 2003-2004 Red Hat, Inc.
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2, or (at your option)
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
21 * You should have received a copy of the GNU General Public License
22 * along with this program; see the file COPYING. If not, write to
23 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
26 * libata documentation is available via 'make {ps|pdf}docs',
27 * as Documentation/DocBook/libata.*
29 * Hardware information only available under NDA.
33 #include <linux/kernel.h>
34 #include <linux/module.h>
35 #include <linux/pci.h>
36 #include <linux/init.h>
37 #include <linux/blkdev.h>
38 #include <linux/delay.h>
39 #include <linux/interrupt.h>
40 #include <linux/sched.h>
41 #include <linux/device.h>
42 #include <scsi/scsi_host.h>
43 #include <scsi/scsi_cmnd.h>
44 #include <linux/libata.h>
46 #include "sata_promise.h"
48 #define DRV_NAME "sata_promise"
49 #define DRV_VERSION "1.05"
53 PDC_PKT_SUBMIT = 0x40, /* Command packet pointer addr */
54 PDC_INT_SEQMASK = 0x40, /* Mask of asserted SEQ INTs */
55 PDC_FLASH_CTL = 0x44, /* Flash control register */
56 PDC_GLOBAL_CTL = 0x48, /* Global control/status (per port) */
57 PDC_CTLSTAT = 0x60, /* IDE control and status (per port) */
58 PDC_SATA_PLUG_CSR = 0x6C, /* SATA Plug control/status reg */
59 PDC2_SATA_PLUG_CSR = 0x60, /* SATAII Plug control/status reg */
60 PDC_TBG_MODE = 0x41C, /* TBG mode (not SATAII) */
61 PDC_SLEW_CTL = 0x470, /* slew rate control reg (not SATAII) */
63 PDC_ERR_MASK = (1<<19) | (1<<20) | (1<<21) | (1<<22) |
64 (1<<8) | (1<<9) | (1<<10),
66 board_2037x = 0, /* FastTrak S150 TX2plus */
67 board_20319 = 1, /* FastTrak S150 TX4 */
68 board_20619 = 2, /* FastTrak TX4000 */
69 board_2057x = 3, /* SATAII150 Tx2plus */
70 board_40518 = 4, /* SATAII150 Tx4 */
72 PDC_HAS_PATA = (1 << 1), /* PDC20375/20575 has PATA */
74 /* PDC_CTLSTAT bit definitions */
75 PDC_DMA_ENABLE = (1 << 7),
76 PDC_IRQ_DISABLE = (1 << 10),
77 PDC_RESET = (1 << 11), /* HDMA reset */
79 PDC_COMMON_FLAGS = ATA_FLAG_NO_LEGACY |
80 ATA_FLAG_MMIO | ATA_FLAG_NO_ATAPI |
84 PDC_FLAG_GEN_II = (1 << 0),
88 struct pdc_port_priv {
93 struct pdc_host_priv {
95 unsigned long port_flags[ATA_MAX_PORTS];
98 static u32 pdc_sata_scr_read (struct ata_port *ap, unsigned int sc_reg);
99 static void pdc_sata_scr_write (struct ata_port *ap, unsigned int sc_reg, u32 val);
100 static int pdc_ata_init_one (struct pci_dev *pdev, const struct pci_device_id *ent);
101 static irqreturn_t pdc_interrupt (int irq, void *dev_instance);
102 static void pdc_eng_timeout(struct ata_port *ap);
103 static int pdc_port_start(struct ata_port *ap);
104 static void pdc_port_stop(struct ata_port *ap);
105 static void pdc_pata_phy_reset(struct ata_port *ap);
106 static void pdc_qc_prep(struct ata_queued_cmd *qc);
107 static void pdc_tf_load_mmio(struct ata_port *ap, const struct ata_taskfile *tf);
108 static void pdc_exec_command_mmio(struct ata_port *ap, const struct ata_taskfile *tf);
109 static void pdc_irq_clear(struct ata_port *ap);
110 static unsigned int pdc_qc_issue_prot(struct ata_queued_cmd *qc);
111 static void pdc_host_stop(struct ata_host *host);
112 static void pdc_freeze(struct ata_port *ap);
113 static void pdc_thaw(struct ata_port *ap);
114 static void pdc_error_handler(struct ata_port *ap);
115 static void pdc_post_internal_cmd(struct ata_queued_cmd *qc);
118 static struct scsi_host_template pdc_ata_sht = {
119 .module = THIS_MODULE,
121 .ioctl = ata_scsi_ioctl,
122 .queuecommand = ata_scsi_queuecmd,
123 .can_queue = ATA_DEF_QUEUE,
124 .this_id = ATA_SHT_THIS_ID,
125 .sg_tablesize = LIBATA_MAX_PRD,
126 .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
127 .emulated = ATA_SHT_EMULATED,
128 .use_clustering = ATA_SHT_USE_CLUSTERING,
129 .proc_name = DRV_NAME,
130 .dma_boundary = ATA_DMA_BOUNDARY,
131 .slave_configure = ata_scsi_slave_config,
132 .slave_destroy = ata_scsi_slave_destroy,
133 .bios_param = ata_std_bios_param,
136 static const struct ata_port_operations pdc_sata_ops = {
137 .port_disable = ata_port_disable,
138 .tf_load = pdc_tf_load_mmio,
139 .tf_read = ata_tf_read,
140 .check_status = ata_check_status,
141 .exec_command = pdc_exec_command_mmio,
142 .dev_select = ata_std_dev_select,
144 .qc_prep = pdc_qc_prep,
145 .qc_issue = pdc_qc_issue_prot,
146 .freeze = pdc_freeze,
148 .error_handler = pdc_error_handler,
149 .post_internal_cmd = pdc_post_internal_cmd,
150 .data_xfer = ata_mmio_data_xfer,
151 .irq_handler = pdc_interrupt,
152 .irq_clear = pdc_irq_clear,
154 .scr_read = pdc_sata_scr_read,
155 .scr_write = pdc_sata_scr_write,
156 .port_start = pdc_port_start,
157 .port_stop = pdc_port_stop,
158 .host_stop = pdc_host_stop,
161 static const struct ata_port_operations pdc_pata_ops = {
162 .port_disable = ata_port_disable,
163 .tf_load = pdc_tf_load_mmio,
164 .tf_read = ata_tf_read,
165 .check_status = ata_check_status,
166 .exec_command = pdc_exec_command_mmio,
167 .dev_select = ata_std_dev_select,
169 .phy_reset = pdc_pata_phy_reset,
171 .qc_prep = pdc_qc_prep,
172 .qc_issue = pdc_qc_issue_prot,
173 .data_xfer = ata_mmio_data_xfer,
174 .eng_timeout = pdc_eng_timeout,
175 .irq_handler = pdc_interrupt,
176 .irq_clear = pdc_irq_clear,
178 .port_start = pdc_port_start,
179 .port_stop = pdc_port_stop,
180 .host_stop = pdc_host_stop,
183 static const struct ata_port_info pdc_port_info[] = {
187 .flags = PDC_COMMON_FLAGS,
188 .pio_mask = 0x1f, /* pio0-4 */
189 .mwdma_mask = 0x07, /* mwdma0-2 */
190 .udma_mask = 0x7f, /* udma0-6 ; FIXME */
191 .port_ops = &pdc_sata_ops,
197 .flags = PDC_COMMON_FLAGS | ATA_FLAG_SATA,
198 .pio_mask = 0x1f, /* pio0-4 */
199 .mwdma_mask = 0x07, /* mwdma0-2 */
200 .udma_mask = 0x7f, /* udma0-6 ; FIXME */
201 .port_ops = &pdc_sata_ops,
207 .flags = PDC_COMMON_FLAGS | ATA_FLAG_SRST | ATA_FLAG_SLAVE_POSS,
208 .pio_mask = 0x1f, /* pio0-4 */
209 .mwdma_mask = 0x07, /* mwdma0-2 */
210 .udma_mask = 0x7f, /* udma0-6 ; FIXME */
211 .port_ops = &pdc_pata_ops,
217 .flags = PDC_COMMON_FLAGS,
218 .pio_mask = 0x1f, /* pio0-4 */
219 .mwdma_mask = 0x07, /* mwdma0-2 */
220 .udma_mask = 0x7f, /* udma0-6 ; FIXME */
221 .port_ops = &pdc_sata_ops,
227 .flags = PDC_COMMON_FLAGS | ATA_FLAG_SATA,
228 .pio_mask = 0x1f, /* pio0-4 */
229 .mwdma_mask = 0x07, /* mwdma0-2 */
230 .udma_mask = 0x7f, /* udma0-6 ; FIXME */
231 .port_ops = &pdc_sata_ops,
235 static const struct pci_device_id pdc_ata_pci_tbl[] = {
236 { PCI_VDEVICE(PROMISE, 0x3371), board_2037x },
237 { PCI_VDEVICE(PROMISE, 0x3373), board_2037x },
238 { PCI_VDEVICE(PROMISE, 0x3375), board_2037x },
239 { PCI_VDEVICE(PROMISE, 0x3376), board_2037x },
240 { PCI_VDEVICE(PROMISE, 0x3570), board_2057x },
241 { PCI_VDEVICE(PROMISE, 0x3571), board_2057x },
242 { PCI_VDEVICE(PROMISE, 0x3574), board_2057x },
243 { PCI_VDEVICE(PROMISE, 0x3577), board_2057x },
244 { PCI_VDEVICE(PROMISE, 0x3d73), board_2057x },
245 { PCI_VDEVICE(PROMISE, 0x3d75), board_2057x },
247 { PCI_VDEVICE(PROMISE, 0x3318), board_20319 },
248 { PCI_VDEVICE(PROMISE, 0x3319), board_20319 },
249 { PCI_VDEVICE(PROMISE, 0x3515), board_20319 },
250 { PCI_VDEVICE(PROMISE, 0x3519), board_20319 },
251 { PCI_VDEVICE(PROMISE, 0x3d17), board_40518 },
252 { PCI_VDEVICE(PROMISE, 0x3d18), board_40518 },
254 { PCI_VDEVICE(PROMISE, 0x6629), board_20619 },
256 { } /* terminate list */
260 static struct pci_driver pdc_ata_pci_driver = {
262 .id_table = pdc_ata_pci_tbl,
263 .probe = pdc_ata_init_one,
264 .remove = ata_pci_remove_one,
268 static int pdc_port_start(struct ata_port *ap)
270 struct device *dev = ap->host->dev;
271 struct pdc_host_priv *hp = ap->host->private_data;
272 struct pdc_port_priv *pp;
275 /* fix up port flags and cable type for SATA+PATA chips */
276 ap->flags |= hp->port_flags[ap->port_no];
277 if (ap->flags & ATA_FLAG_SATA)
278 ap->cbl = ATA_CBL_SATA;
280 rc = ata_port_start(ap);
284 pp = kzalloc(sizeof(*pp), GFP_KERNEL);
290 pp->pkt = dma_alloc_coherent(dev, 128, &pp->pkt_dma, GFP_KERNEL);
296 ap->private_data = pp;
298 /* fix up PHYMODE4 align timing */
299 if ((hp->flags & PDC_FLAG_GEN_II) && sata_scr_valid(ap)) {
300 void __iomem *mmio = (void __iomem *) ap->ioaddr.scr_addr;
303 tmp = readl(mmio + 0x014);
304 tmp = (tmp & ~3) | 1; /* set bits 1:0 = 0:1 */
305 writel(tmp, mmio + 0x014);
318 static void pdc_port_stop(struct ata_port *ap)
320 struct device *dev = ap->host->dev;
321 struct pdc_port_priv *pp = ap->private_data;
323 ap->private_data = NULL;
324 dma_free_coherent(dev, 128, pp->pkt, pp->pkt_dma);
330 static void pdc_host_stop(struct ata_host *host)
332 struct pdc_host_priv *hp = host->private_data;
334 ata_pci_host_stop(host);
340 static void pdc_reset_port(struct ata_port *ap)
342 void __iomem *mmio = (void __iomem *) ap->ioaddr.cmd_addr + PDC_CTLSTAT;
346 for (i = 11; i > 0; i--) {
359 readl(mmio); /* flush */
362 static void pdc_pata_cbl_detect(struct ata_port *ap)
365 void __iomem *mmio = (void __iomem *) ap->ioaddr.cmd_addr + PDC_CTLSTAT + 0x03;
370 ap->cbl = ATA_CBL_PATA40;
371 ap->udma_mask &= ATA_UDMA_MASK_40C;
373 ap->cbl = ATA_CBL_PATA80;
376 static void pdc_pata_phy_reset(struct ata_port *ap)
378 pdc_pata_cbl_detect(ap);
384 static u32 pdc_sata_scr_read (struct ata_port *ap, unsigned int sc_reg)
386 if (sc_reg > SCR_CONTROL || ap->cbl != ATA_CBL_SATA)
388 return readl((void __iomem *) ap->ioaddr.scr_addr + (sc_reg * 4));
392 static void pdc_sata_scr_write (struct ata_port *ap, unsigned int sc_reg,
395 if (sc_reg > SCR_CONTROL || ap->cbl != ATA_CBL_SATA)
397 writel(val, (void __iomem *) ap->ioaddr.scr_addr + (sc_reg * 4));
400 static void pdc_qc_prep(struct ata_queued_cmd *qc)
402 struct pdc_port_priv *pp = qc->ap->private_data;
407 switch (qc->tf.protocol) {
412 case ATA_PROT_NODATA:
413 i = pdc_pkt_header(&qc->tf, qc->ap->prd_dma,
414 qc->dev->devno, pp->pkt);
416 if (qc->tf.flags & ATA_TFLAG_LBA48)
417 i = pdc_prep_lba48(&qc->tf, pp->pkt, i);
419 i = pdc_prep_lba28(&qc->tf, pp->pkt, i);
421 pdc_pkt_footer(&qc->tf, pp->pkt, i);
429 static void pdc_freeze(struct ata_port *ap)
431 void __iomem *mmio = (void __iomem *) ap->ioaddr.cmd_addr;
434 tmp = readl(mmio + PDC_CTLSTAT);
435 tmp |= PDC_IRQ_DISABLE;
436 tmp &= ~PDC_DMA_ENABLE;
437 writel(tmp, mmio + PDC_CTLSTAT);
438 readl(mmio + PDC_CTLSTAT); /* flush */
441 static void pdc_thaw(struct ata_port *ap)
443 void __iomem *mmio = (void __iomem *) ap->ioaddr.cmd_addr;
447 readl(mmio + PDC_INT_SEQMASK);
449 /* turn IRQ back on */
450 tmp = readl(mmio + PDC_CTLSTAT);
451 tmp &= ~PDC_IRQ_DISABLE;
452 writel(tmp, mmio + PDC_CTLSTAT);
453 readl(mmio + PDC_CTLSTAT); /* flush */
456 static void pdc_error_handler(struct ata_port *ap)
458 ata_reset_fn_t hardreset;
460 if (!(ap->pflags & ATA_PFLAG_FROZEN))
464 if (sata_scr_valid(ap))
465 hardreset = sata_std_hardreset;
467 /* perform recovery */
468 ata_do_eh(ap, ata_std_prereset, ata_std_softreset, hardreset,
472 static void pdc_post_internal_cmd(struct ata_queued_cmd *qc)
474 struct ata_port *ap = qc->ap;
476 if (qc->flags & ATA_QCFLAG_FAILED)
477 qc->err_mask |= AC_ERR_OTHER;
479 /* make DMA engine forget about the failed command */
484 static void pdc_eng_timeout(struct ata_port *ap)
486 struct ata_host *host = ap->host;
488 struct ata_queued_cmd *qc;
493 spin_lock_irqsave(&host->lock, flags);
495 qc = ata_qc_from_tag(ap, ap->active_tag);
497 switch (qc->tf.protocol) {
499 case ATA_PROT_NODATA:
500 ata_port_printk(ap, KERN_ERR, "command timeout\n");
501 drv_stat = ata_wait_idle(ap);
502 qc->err_mask |= __ac_err_mask(drv_stat);
506 drv_stat = ata_busy_wait(ap, ATA_BUSY | ATA_DRQ, 1000);
508 ata_port_printk(ap, KERN_ERR,
509 "unknown timeout, cmd 0x%x stat 0x%x\n",
510 qc->tf.command, drv_stat);
512 qc->err_mask |= ac_err_mask(drv_stat);
516 spin_unlock_irqrestore(&host->lock, flags);
517 ata_eh_qc_complete(qc);
521 static inline unsigned int pdc_host_intr( struct ata_port *ap,
522 struct ata_queued_cmd *qc)
524 unsigned int handled = 0;
526 void __iomem *mmio = (void __iomem *) ap->ioaddr.cmd_addr + PDC_GLOBAL_CTL;
529 if (tmp & PDC_ERR_MASK) {
530 qc->err_mask |= AC_ERR_DEV;
534 switch (qc->tf.protocol) {
536 case ATA_PROT_NODATA:
537 qc->err_mask |= ac_err_mask(ata_wait_idle(ap));
543 ap->stats.idle_irq++;
550 static void pdc_irq_clear(struct ata_port *ap)
552 struct ata_host *host = ap->host;
553 void __iomem *mmio = host->mmio_base;
555 readl(mmio + PDC_INT_SEQMASK);
558 static irqreturn_t pdc_interrupt (int irq, void *dev_instance)
560 struct ata_host *host = dev_instance;
564 unsigned int handled = 0;
565 void __iomem *mmio_base;
569 if (!host || !host->mmio_base) {
570 VPRINTK("QUICK EXIT\n");
574 mmio_base = host->mmio_base;
576 /* reading should also clear interrupts */
577 mask = readl(mmio_base + PDC_INT_SEQMASK);
579 if (mask == 0xffffffff) {
580 VPRINTK("QUICK EXIT 2\n");
584 spin_lock(&host->lock);
586 mask &= 0xffff; /* only 16 tags possible */
588 VPRINTK("QUICK EXIT 3\n");
592 writel(mask, mmio_base + PDC_INT_SEQMASK);
594 for (i = 0; i < host->n_ports; i++) {
595 VPRINTK("port %u\n", i);
597 tmp = mask & (1 << (i + 1));
599 !(ap->flags & ATA_FLAG_DISABLED)) {
600 struct ata_queued_cmd *qc;
602 qc = ata_qc_from_tag(ap, ap->active_tag);
603 if (qc && (!(qc->tf.flags & ATA_TFLAG_POLLING)))
604 handled += pdc_host_intr(ap, qc);
611 spin_unlock(&host->lock);
612 return IRQ_RETVAL(handled);
615 static inline void pdc_packet_start(struct ata_queued_cmd *qc)
617 struct ata_port *ap = qc->ap;
618 struct pdc_port_priv *pp = ap->private_data;
619 unsigned int port_no = ap->port_no;
620 u8 seq = (u8) (port_no + 1);
622 VPRINTK("ENTER, ap %p\n", ap);
624 writel(0x00000001, ap->host->mmio_base + (seq * 4));
625 readl(ap->host->mmio_base + (seq * 4)); /* flush */
628 wmb(); /* flush PRD, pkt writes */
629 writel(pp->pkt_dma, (void __iomem *) ap->ioaddr.cmd_addr + PDC_PKT_SUBMIT);
630 readl((void __iomem *) ap->ioaddr.cmd_addr + PDC_PKT_SUBMIT); /* flush */
633 static unsigned int pdc_qc_issue_prot(struct ata_queued_cmd *qc)
635 switch (qc->tf.protocol) {
637 case ATA_PROT_NODATA:
638 pdc_packet_start(qc);
641 case ATA_PROT_ATAPI_DMA:
649 return ata_qc_issue_prot(qc);
652 static void pdc_tf_load_mmio(struct ata_port *ap, const struct ata_taskfile *tf)
654 WARN_ON (tf->protocol == ATA_PROT_DMA ||
655 tf->protocol == ATA_PROT_NODATA);
660 static void pdc_exec_command_mmio(struct ata_port *ap, const struct ata_taskfile *tf)
662 WARN_ON (tf->protocol == ATA_PROT_DMA ||
663 tf->protocol == ATA_PROT_NODATA);
664 ata_exec_command(ap, tf);
668 static void pdc_ata_setup_port(struct ata_ioports *port, unsigned long base)
670 port->cmd_addr = base;
671 port->data_addr = base;
673 port->error_addr = base + 0x4;
674 port->nsect_addr = base + 0x8;
675 port->lbal_addr = base + 0xc;
676 port->lbam_addr = base + 0x10;
677 port->lbah_addr = base + 0x14;
678 port->device_addr = base + 0x18;
680 port->status_addr = base + 0x1c;
681 port->altstatus_addr =
682 port->ctl_addr = base + 0x38;
686 static void pdc_host_init(unsigned int chip_id, struct ata_probe_ent *pe)
688 void __iomem *mmio = pe->mmio_base;
689 struct pdc_host_priv *hp = pe->private_data;
693 if (hp->flags & PDC_FLAG_GEN_II)
694 hotplug_offset = PDC2_SATA_PLUG_CSR;
696 hotplug_offset = PDC_SATA_PLUG_CSR;
699 * Except for the hotplug stuff, this is voodoo from the
700 * Promise driver. Label this entire section
701 * "TODO: figure out why we do this"
704 /* enable BMR_BURST, maybe change FIFO_SHD to 8 dwords */
705 tmp = readl(mmio + PDC_FLASH_CTL);
706 tmp |= 0x02000; /* bit 13 (enable bmr burst) */
707 if (!(hp->flags & PDC_FLAG_GEN_II))
708 tmp |= 0x10000; /* bit 16 (fifo threshold at 8 dw) */
709 writel(tmp, mmio + PDC_FLASH_CTL);
711 /* clear plug/unplug flags for all ports */
712 tmp = readl(mmio + hotplug_offset);
713 writel(tmp | 0xff, mmio + hotplug_offset);
715 /* mask plug/unplug ints */
716 tmp = readl(mmio + hotplug_offset);
717 writel(tmp | 0xff0000, mmio + hotplug_offset);
719 /* don't initialise TBG or SLEW on 2nd generation chips */
720 if (hp->flags & PDC_FLAG_GEN_II)
723 /* reduce TBG clock to 133 Mhz. */
724 tmp = readl(mmio + PDC_TBG_MODE);
725 tmp &= ~0x30000; /* clear bit 17, 16*/
726 tmp |= 0x10000; /* set bit 17:16 = 0:1 */
727 writel(tmp, mmio + PDC_TBG_MODE);
729 readl(mmio + PDC_TBG_MODE); /* flush */
732 /* adjust slew rate control register. */
733 tmp = readl(mmio + PDC_SLEW_CTL);
734 tmp &= 0xFFFFF03F; /* clear bit 11 ~ 6 */
735 tmp |= 0x00000900; /* set bit 11-9 = 100b , bit 8-6 = 100 */
736 writel(tmp, mmio + PDC_SLEW_CTL);
739 static int pdc_ata_init_one (struct pci_dev *pdev, const struct pci_device_id *ent)
741 static int printed_version;
742 struct ata_probe_ent *probe_ent = NULL;
743 struct pdc_host_priv *hp;
745 void __iomem *mmio_base;
746 unsigned int board_idx = (unsigned int) ent->driver_data;
747 int pci_dev_busy = 0;
751 if (!printed_version++)
752 dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n");
754 rc = pci_enable_device(pdev);
758 rc = pci_request_regions(pdev, DRV_NAME);
764 rc = pci_set_dma_mask(pdev, ATA_DMA_MASK);
766 goto err_out_regions;
767 rc = pci_set_consistent_dma_mask(pdev, ATA_DMA_MASK);
769 goto err_out_regions;
771 probe_ent = kzalloc(sizeof(*probe_ent), GFP_KERNEL);
772 if (probe_ent == NULL) {
774 goto err_out_regions;
777 probe_ent->dev = pci_dev_to_dev(pdev);
778 INIT_LIST_HEAD(&probe_ent->node);
780 mmio_base = pci_iomap(pdev, 3, 0);
781 if (mmio_base == NULL) {
783 goto err_out_free_ent;
785 base = (unsigned long) mmio_base;
787 hp = kzalloc(sizeof(*hp), GFP_KERNEL);
790 goto err_out_free_ent;
793 probe_ent->private_data = hp;
795 probe_ent->sht = pdc_port_info[board_idx].sht;
796 probe_ent->port_flags = pdc_port_info[board_idx].flags;
797 probe_ent->pio_mask = pdc_port_info[board_idx].pio_mask;
798 probe_ent->mwdma_mask = pdc_port_info[board_idx].mwdma_mask;
799 probe_ent->udma_mask = pdc_port_info[board_idx].udma_mask;
800 probe_ent->port_ops = pdc_port_info[board_idx].port_ops;
802 probe_ent->irq = pdev->irq;
803 probe_ent->irq_flags = IRQF_SHARED;
804 probe_ent->mmio_base = mmio_base;
806 pdc_ata_setup_port(&probe_ent->port[0], base + 0x200);
807 pdc_ata_setup_port(&probe_ent->port[1], base + 0x280);
809 probe_ent->port[0].scr_addr = base + 0x400;
810 probe_ent->port[1].scr_addr = base + 0x500;
812 /* notice 4-port boards */
815 hp->flags |= PDC_FLAG_GEN_II;
818 probe_ent->n_ports = 4;
820 pdc_ata_setup_port(&probe_ent->port[2], base + 0x300);
821 pdc_ata_setup_port(&probe_ent->port[3], base + 0x380);
823 probe_ent->port[2].scr_addr = base + 0x600;
824 probe_ent->port[3].scr_addr = base + 0x700;
827 hp->flags |= PDC_FLAG_GEN_II;
830 /* TX2plus boards also have a PATA port */
831 tmp = readb(mmio_base + PDC_FLASH_CTL+1);
833 probe_ent->n_ports = 3;
834 pdc_ata_setup_port(&probe_ent->port[2], base + 0x300);
835 hp->port_flags[2] = ATA_FLAG_SLAVE_POSS;
836 printk(KERN_INFO DRV_NAME " PATA port found\n");
838 probe_ent->n_ports = 2;
839 hp->port_flags[0] = ATA_FLAG_SATA;
840 hp->port_flags[1] = ATA_FLAG_SATA;
843 probe_ent->n_ports = 4;
845 pdc_ata_setup_port(&probe_ent->port[2], base + 0x300);
846 pdc_ata_setup_port(&probe_ent->port[3], base + 0x380);
848 probe_ent->port[2].scr_addr = base + 0x600;
849 probe_ent->port[3].scr_addr = base + 0x700;
856 pci_set_master(pdev);
858 /* initialize adapter */
859 pdc_host_init(board_idx, probe_ent);
861 /* FIXME: Need any other frees than hp? */
862 if (!ata_device_add(probe_ent))
872 pci_release_regions(pdev);
875 pci_disable_device(pdev);
880 static int __init pdc_ata_init(void)
882 return pci_register_driver(&pdc_ata_pci_driver);
886 static void __exit pdc_ata_exit(void)
888 pci_unregister_driver(&pdc_ata_pci_driver);
892 MODULE_AUTHOR("Jeff Garzik");
893 MODULE_DESCRIPTION("Promise ATA TX2/TX4/TX4000 low-level driver");
894 MODULE_LICENSE("GPL");
895 MODULE_DEVICE_TABLE(pci, pdc_ata_pci_tbl);
896 MODULE_VERSION(DRV_VERSION);
898 module_init(pdc_ata_init);
899 module_exit(pdc_ata_exit);