2 * sata_sil24.c - Driver for Silicon Image 3124/3132 SATA-2 controllers
4 * Copyright 2005 Tejun Heo
6 * Based on preview driver from Silicon Image.
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2, or (at your option) any
13 * This program is distributed in the hope that it will be useful, but
14 * WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
16 * General Public License for more details.
20 #include <linux/kernel.h>
21 #include <linux/module.h>
22 #include <linux/pci.h>
23 #include <linux/blkdev.h>
24 #include <linux/delay.h>
25 #include <linux/interrupt.h>
26 #include <linux/dma-mapping.h>
27 #include <linux/device.h>
28 #include <scsi/scsi_host.h>
29 #include <scsi/scsi_cmnd.h>
30 #include <linux/libata.h>
33 #define DRV_NAME "sata_sil24"
34 #define DRV_VERSION "0.3"
37 * Port request block (PRB) 32 bytes
47 * Scatter gather entry (SGE) 16 bytes
58 struct sil24_port_multiplier {
65 * Global controller registers (128 bytes @ BAR0)
68 HOST_SLOT_STAT = 0x00, /* 32 bit slot stat * 4 */
72 HOST_BIST_CTRL = 0x50,
73 HOST_BIST_PTRN = 0x54,
74 HOST_BIST_STAT = 0x58,
75 HOST_MEM_BIST_STAT = 0x5c,
76 HOST_FLASH_CMD = 0x70,
78 HOST_FLASH_DATA = 0x74,
79 HOST_TRANSITION_DETECT = 0x75,
80 HOST_GPIO_CTRL = 0x76,
81 HOST_I2C_ADDR = 0x78, /* 32 bit */
83 HOST_I2C_XFER_CNT = 0x7e,
86 /* HOST_SLOT_STAT bits */
87 HOST_SSTAT_ATTN = (1 << 31),
90 HOST_CTRL_M66EN = (1 << 16), /* M66EN PCI bus signal */
91 HOST_CTRL_TRDY = (1 << 17), /* latched PCI TRDY */
92 HOST_CTRL_STOP = (1 << 18), /* latched PCI STOP */
93 HOST_CTRL_DEVSEL = (1 << 19), /* latched PCI DEVSEL */
94 HOST_CTRL_REQ64 = (1 << 20), /* latched PCI REQ64 */
95 HOST_CTRL_GLOBAL_RST = (1 << 31), /* global reset */
99 * (8192 bytes @ +0x0000, +0x2000, +0x4000 and +0x6000 @ BAR2)
101 PORT_REGS_SIZE = 0x2000,
103 PORT_LRAM = 0x0000, /* 31 LRAM slots and PMP regs */
104 PORT_LRAM_SLOT_SZ = 0x0080, /* 32 bytes PRB + 2 SGE, ACT... */
106 PORT_PMP = 0x0f80, /* 8 bytes PMP * 16 (128 bytes) */
107 PORT_PMP_STATUS = 0x0000, /* port device status offset */
108 PORT_PMP_QACTIVE = 0x0004, /* port device QActive offset */
109 PORT_PMP_SIZE = 0x0008, /* 8 bytes per PMP */
112 PORT_CTRL_STAT = 0x1000, /* write: ctrl-set, read: stat */
113 PORT_CTRL_CLR = 0x1004, /* write: ctrl-clear */
114 PORT_IRQ_STAT = 0x1008, /* high: status, low: interrupt */
115 PORT_IRQ_ENABLE_SET = 0x1010, /* write: enable-set */
116 PORT_IRQ_ENABLE_CLR = 0x1014, /* write: enable-clear */
117 PORT_ACTIVATE_UPPER_ADDR= 0x101c,
118 PORT_EXEC_FIFO = 0x1020, /* command execution fifo */
119 PORT_CMD_ERR = 0x1024, /* command error number */
120 PORT_FIS_CFG = 0x1028,
121 PORT_FIFO_THRES = 0x102c,
123 PORT_DECODE_ERR_CNT = 0x1040,
124 PORT_DECODE_ERR_THRESH = 0x1042,
125 PORT_CRC_ERR_CNT = 0x1044,
126 PORT_CRC_ERR_THRESH = 0x1046,
127 PORT_HSHK_ERR_CNT = 0x1048,
128 PORT_HSHK_ERR_THRESH = 0x104a,
130 PORT_PHY_CFG = 0x1050,
131 PORT_SLOT_STAT = 0x1800,
132 PORT_CMD_ACTIVATE = 0x1c00, /* 64 bit cmd activate * 31 (248 bytes) */
133 PORT_CONTEXT = 0x1e04,
134 PORT_EXEC_DIAG = 0x1e00, /* 32bit exec diag * 16 (64 bytes, 0-10 used on 3124) */
135 PORT_PSD_DIAG = 0x1e40, /* 32bit psd diag * 16 (64 bytes, 0-8 used on 3124) */
136 PORT_SCONTROL = 0x1f00,
137 PORT_SSTATUS = 0x1f04,
138 PORT_SERROR = 0x1f08,
139 PORT_SACTIVE = 0x1f0c,
141 /* PORT_CTRL_STAT bits */
142 PORT_CS_PORT_RST = (1 << 0), /* port reset */
143 PORT_CS_DEV_RST = (1 << 1), /* device reset */
144 PORT_CS_INIT = (1 << 2), /* port initialize */
145 PORT_CS_IRQ_WOC = (1 << 3), /* interrupt write one to clear */
146 PORT_CS_CDB16 = (1 << 5), /* 0=12b cdb, 1=16b cdb */
147 PORT_CS_PMP_RESUME = (1 << 6), /* PMP resume */
148 PORT_CS_32BIT_ACTV = (1 << 10), /* 32-bit activation */
149 PORT_CS_PMP_EN = (1 << 13), /* port multiplier enable */
150 PORT_CS_RDY = (1 << 31), /* port ready to accept commands */
152 /* PORT_IRQ_STAT/ENABLE_SET/CLR */
153 /* bits[11:0] are masked */
154 PORT_IRQ_COMPLETE = (1 << 0), /* command(s) completed */
155 PORT_IRQ_ERROR = (1 << 1), /* command execution error */
156 PORT_IRQ_PORTRDY_CHG = (1 << 2), /* port ready change */
157 PORT_IRQ_PWR_CHG = (1 << 3), /* power management change */
158 PORT_IRQ_PHYRDY_CHG = (1 << 4), /* PHY ready change */
159 PORT_IRQ_COMWAKE = (1 << 5), /* COMWAKE received */
160 PORT_IRQ_UNK_FIS = (1 << 6), /* unknown FIS received */
161 PORT_IRQ_DEV_XCHG = (1 << 7), /* device exchanged */
162 PORT_IRQ_8B10B = (1 << 8), /* 8b/10b decode error threshold */
163 PORT_IRQ_CRC = (1 << 9), /* CRC error threshold */
164 PORT_IRQ_HANDSHAKE = (1 << 10), /* handshake error threshold */
165 PORT_IRQ_SDB_NOTIFY = (1 << 11), /* SDB notify received */
167 DEF_PORT_IRQ = PORT_IRQ_COMPLETE | PORT_IRQ_ERROR |
168 PORT_IRQ_PHYRDY_CHG | PORT_IRQ_DEV_XCHG |
171 /* bits[27:16] are unmasked (raw) */
172 PORT_IRQ_RAW_SHIFT = 16,
173 PORT_IRQ_MASKED_MASK = 0x7ff,
174 PORT_IRQ_RAW_MASK = (0x7ff << PORT_IRQ_RAW_SHIFT),
176 /* ENABLE_SET/CLR specific, intr steering - 2 bit field */
177 PORT_IRQ_STEER_SHIFT = 30,
178 PORT_IRQ_STEER_MASK = (3 << PORT_IRQ_STEER_SHIFT),
180 /* PORT_CMD_ERR constants */
181 PORT_CERR_DEV = 1, /* Error bit in D2H Register FIS */
182 PORT_CERR_SDB = 2, /* Error bit in SDB FIS */
183 PORT_CERR_DATA = 3, /* Error in data FIS not detected by dev */
184 PORT_CERR_SEND = 4, /* Initial cmd FIS transmission failure */
185 PORT_CERR_INCONSISTENT = 5, /* Protocol mismatch */
186 PORT_CERR_DIRECTION = 6, /* Data direction mismatch */
187 PORT_CERR_UNDERRUN = 7, /* Ran out of SGEs while writing */
188 PORT_CERR_OVERRUN = 8, /* Ran out of SGEs while reading */
189 PORT_CERR_PKT_PROT = 11, /* DIR invalid in 1st PIO setup of ATAPI */
190 PORT_CERR_SGT_BOUNDARY = 16, /* PLD ecode 00 - SGT not on qword boundary */
191 PORT_CERR_SGT_TGTABRT = 17, /* PLD ecode 01 - target abort */
192 PORT_CERR_SGT_MSTABRT = 18, /* PLD ecode 10 - master abort */
193 PORT_CERR_SGT_PCIPERR = 19, /* PLD ecode 11 - PCI parity err while fetching SGT */
194 PORT_CERR_CMD_BOUNDARY = 24, /* ctrl[15:13] 001 - PRB not on qword boundary */
195 PORT_CERR_CMD_TGTABRT = 25, /* ctrl[15:13] 010 - target abort */
196 PORT_CERR_CMD_MSTABRT = 26, /* ctrl[15:13] 100 - master abort */
197 PORT_CERR_CMD_PCIPERR = 27, /* ctrl[15:13] 110 - PCI parity err while fetching PRB */
198 PORT_CERR_XFR_UNDEF = 32, /* PSD ecode 00 - undefined */
199 PORT_CERR_XFR_TGTABRT = 33, /* PSD ecode 01 - target abort */
200 PORT_CERR_XFR_MSTABRT = 34, /* PSD ecode 10 - master abort */
201 PORT_CERR_XFR_PCIPERR = 35, /* PSD ecode 11 - PCI prity err during transfer */
202 PORT_CERR_SENDSERVICE = 36, /* FIS received while sending service */
204 /* bits of PRB control field */
205 PRB_CTRL_PROTOCOL = (1 << 0), /* override def. ATA protocol */
206 PRB_CTRL_PACKET_READ = (1 << 4), /* PACKET cmd read */
207 PRB_CTRL_PACKET_WRITE = (1 << 5), /* PACKET cmd write */
208 PRB_CTRL_NIEN = (1 << 6), /* Mask completion irq */
209 PRB_CTRL_SRST = (1 << 7), /* Soft reset request (ign BSY?) */
211 /* PRB protocol field */
212 PRB_PROT_PACKET = (1 << 0),
213 PRB_PROT_TCQ = (1 << 1),
214 PRB_PROT_NCQ = (1 << 2),
215 PRB_PROT_READ = (1 << 3),
216 PRB_PROT_WRITE = (1 << 4),
217 PRB_PROT_TRANSPARENT = (1 << 5),
222 SGE_TRM = (1 << 31), /* Last SGE in chain */
223 SGE_LNK = (1 << 30), /* linked list
224 Points to SGT, not SGE */
225 SGE_DRD = (1 << 29), /* discard data read (/dev/null)
226 data address ignored */
236 SIL24_COMMON_FLAGS = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
237 ATA_FLAG_MMIO | ATA_FLAG_PIO_DMA |
238 ATA_FLAG_NCQ | ATA_FLAG_SKIP_D2H_BSY,
239 SIL24_FLAG_PCIX_IRQ_WOC = (1 << 24), /* IRQ loss errata on PCI-X */
241 IRQ_STAT_4PORTS = 0xf,
244 struct sil24_ata_block {
245 struct sil24_prb prb;
246 struct sil24_sge sge[LIBATA_MAX_PRD];
249 struct sil24_atapi_block {
250 struct sil24_prb prb;
252 struct sil24_sge sge[LIBATA_MAX_PRD - 1];
255 union sil24_cmd_block {
256 struct sil24_ata_block ata;
257 struct sil24_atapi_block atapi;
260 static struct sil24_cerr_info {
261 unsigned int err_mask, action;
263 } sil24_cerr_db[] = {
264 [0] = { AC_ERR_DEV, ATA_EH_REVALIDATE,
266 [PORT_CERR_DEV] = { AC_ERR_DEV, ATA_EH_REVALIDATE,
267 "device error via D2H FIS" },
268 [PORT_CERR_SDB] = { AC_ERR_DEV, ATA_EH_REVALIDATE,
269 "device error via SDB FIS" },
270 [PORT_CERR_DATA] = { AC_ERR_ATA_BUS, ATA_EH_SOFTRESET,
271 "error in data FIS" },
272 [PORT_CERR_SEND] = { AC_ERR_ATA_BUS, ATA_EH_SOFTRESET,
273 "failed to transmit command FIS" },
274 [PORT_CERR_INCONSISTENT] = { AC_ERR_HSM, ATA_EH_SOFTRESET,
275 "protocol mismatch" },
276 [PORT_CERR_DIRECTION] = { AC_ERR_HSM, ATA_EH_SOFTRESET,
277 "data directon mismatch" },
278 [PORT_CERR_UNDERRUN] = { AC_ERR_HSM, ATA_EH_SOFTRESET,
279 "ran out of SGEs while writing" },
280 [PORT_CERR_OVERRUN] = { AC_ERR_HSM, ATA_EH_SOFTRESET,
281 "ran out of SGEs while reading" },
282 [PORT_CERR_PKT_PROT] = { AC_ERR_HSM, ATA_EH_SOFTRESET,
283 "invalid data directon for ATAPI CDB" },
284 [PORT_CERR_SGT_BOUNDARY] = { AC_ERR_SYSTEM, ATA_EH_SOFTRESET,
285 "SGT no on qword boundary" },
286 [PORT_CERR_SGT_TGTABRT] = { AC_ERR_HOST_BUS, ATA_EH_SOFTRESET,
287 "PCI target abort while fetching SGT" },
288 [PORT_CERR_SGT_MSTABRT] = { AC_ERR_HOST_BUS, ATA_EH_SOFTRESET,
289 "PCI master abort while fetching SGT" },
290 [PORT_CERR_SGT_PCIPERR] = { AC_ERR_HOST_BUS, ATA_EH_SOFTRESET,
291 "PCI parity error while fetching SGT" },
292 [PORT_CERR_CMD_BOUNDARY] = { AC_ERR_SYSTEM, ATA_EH_SOFTRESET,
293 "PRB not on qword boundary" },
294 [PORT_CERR_CMD_TGTABRT] = { AC_ERR_HOST_BUS, ATA_EH_SOFTRESET,
295 "PCI target abort while fetching PRB" },
296 [PORT_CERR_CMD_MSTABRT] = { AC_ERR_HOST_BUS, ATA_EH_SOFTRESET,
297 "PCI master abort while fetching PRB" },
298 [PORT_CERR_CMD_PCIPERR] = { AC_ERR_HOST_BUS, ATA_EH_SOFTRESET,
299 "PCI parity error while fetching PRB" },
300 [PORT_CERR_XFR_UNDEF] = { AC_ERR_HOST_BUS, ATA_EH_SOFTRESET,
301 "undefined error while transferring data" },
302 [PORT_CERR_XFR_TGTABRT] = { AC_ERR_HOST_BUS, ATA_EH_SOFTRESET,
303 "PCI target abort while transferring data" },
304 [PORT_CERR_XFR_MSTABRT] = { AC_ERR_HOST_BUS, ATA_EH_SOFTRESET,
305 "PCI master abort while transferring data" },
306 [PORT_CERR_XFR_PCIPERR] = { AC_ERR_HOST_BUS, ATA_EH_SOFTRESET,
307 "PCI parity error while transferring data" },
308 [PORT_CERR_SENDSERVICE] = { AC_ERR_HSM, ATA_EH_SOFTRESET,
309 "FIS received while sending service FIS" },
315 * The preview driver always returned 0 for status. We emulate it
316 * here from the previous interrupt.
318 struct sil24_port_priv {
319 union sil24_cmd_block *cmd_block; /* 32 cmd blocks */
320 dma_addr_t cmd_block_dma; /* DMA base addr for them */
321 struct ata_taskfile tf; /* Cached taskfile registers */
324 /* ap->host->private_data */
325 struct sil24_host_priv {
326 void __iomem *host_base; /* global controller control (128 bytes @BAR0) */
327 void __iomem *port_base; /* port registers (4 * 8192 bytes @BAR2) */
330 static void sil24_dev_config(struct ata_port *ap, struct ata_device *dev);
331 static u8 sil24_check_status(struct ata_port *ap);
332 static u32 sil24_scr_read(struct ata_port *ap, unsigned sc_reg);
333 static void sil24_scr_write(struct ata_port *ap, unsigned sc_reg, u32 val);
334 static void sil24_tf_read(struct ata_port *ap, struct ata_taskfile *tf);
335 static void sil24_qc_prep(struct ata_queued_cmd *qc);
336 static unsigned int sil24_qc_issue(struct ata_queued_cmd *qc);
337 static void sil24_irq_clear(struct ata_port *ap);
338 static irqreturn_t sil24_interrupt(int irq, void *dev_instance);
339 static void sil24_freeze(struct ata_port *ap);
340 static void sil24_thaw(struct ata_port *ap);
341 static void sil24_error_handler(struct ata_port *ap);
342 static void sil24_post_internal_cmd(struct ata_queued_cmd *qc);
343 static int sil24_port_start(struct ata_port *ap);
344 static void sil24_port_stop(struct ata_port *ap);
345 static void sil24_host_stop(struct ata_host *host);
346 static int sil24_init_one(struct pci_dev *pdev, const struct pci_device_id *ent);
348 static int sil24_pci_device_resume(struct pci_dev *pdev);
351 static const struct pci_device_id sil24_pci_tbl[] = {
352 { PCI_VDEVICE(CMD, 0x3124), BID_SIL3124 },
353 { PCI_VDEVICE(INTEL, 0x3124), BID_SIL3124 },
354 { PCI_VDEVICE(CMD, 0x3132), BID_SIL3132 },
355 { PCI_VDEVICE(CMD, 0x3131), BID_SIL3131 },
356 { PCI_VDEVICE(CMD, 0x3531), BID_SIL3131 },
358 { } /* terminate list */
361 static struct pci_driver sil24_pci_driver = {
363 .id_table = sil24_pci_tbl,
364 .probe = sil24_init_one,
365 .remove = ata_pci_remove_one, /* safe? */
367 .suspend = ata_pci_device_suspend,
368 .resume = sil24_pci_device_resume,
372 static struct scsi_host_template sil24_sht = {
373 .module = THIS_MODULE,
375 .ioctl = ata_scsi_ioctl,
376 .queuecommand = ata_scsi_queuecmd,
377 .change_queue_depth = ata_scsi_change_queue_depth,
378 .can_queue = SIL24_MAX_CMDS,
379 .this_id = ATA_SHT_THIS_ID,
380 .sg_tablesize = LIBATA_MAX_PRD,
381 .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
382 .emulated = ATA_SHT_EMULATED,
383 .use_clustering = ATA_SHT_USE_CLUSTERING,
384 .proc_name = DRV_NAME,
385 .dma_boundary = ATA_DMA_BOUNDARY,
386 .slave_configure = ata_scsi_slave_config,
387 .slave_destroy = ata_scsi_slave_destroy,
388 .bios_param = ata_std_bios_param,
390 .suspend = ata_scsi_device_suspend,
391 .resume = ata_scsi_device_resume,
395 static const struct ata_port_operations sil24_ops = {
396 .port_disable = ata_port_disable,
398 .dev_config = sil24_dev_config,
400 .check_status = sil24_check_status,
401 .check_altstatus = sil24_check_status,
402 .dev_select = ata_noop_dev_select,
404 .tf_read = sil24_tf_read,
406 .qc_prep = sil24_qc_prep,
407 .qc_issue = sil24_qc_issue,
409 .irq_handler = sil24_interrupt,
410 .irq_clear = sil24_irq_clear,
412 .scr_read = sil24_scr_read,
413 .scr_write = sil24_scr_write,
415 .freeze = sil24_freeze,
417 .error_handler = sil24_error_handler,
418 .post_internal_cmd = sil24_post_internal_cmd,
420 .port_start = sil24_port_start,
421 .port_stop = sil24_port_stop,
422 .host_stop = sil24_host_stop,
426 * Use bits 30-31 of port_flags to encode available port numbers.
427 * Current maxium is 4.
429 #define SIL24_NPORTS2FLAG(nports) ((((unsigned)(nports) - 1) & 0x3) << 30)
430 #define SIL24_FLAG2NPORTS(flag) ((((flag) >> 30) & 0x3) + 1)
432 static struct ata_port_info sil24_port_info[] = {
436 .flags = SIL24_COMMON_FLAGS | SIL24_NPORTS2FLAG(4) |
437 SIL24_FLAG_PCIX_IRQ_WOC,
438 .pio_mask = 0x1f, /* pio0-4 */
439 .mwdma_mask = 0x07, /* mwdma0-2 */
440 .udma_mask = 0x3f, /* udma0-5 */
441 .port_ops = &sil24_ops,
446 .flags = SIL24_COMMON_FLAGS | SIL24_NPORTS2FLAG(2),
447 .pio_mask = 0x1f, /* pio0-4 */
448 .mwdma_mask = 0x07, /* mwdma0-2 */
449 .udma_mask = 0x3f, /* udma0-5 */
450 .port_ops = &sil24_ops,
452 /* sil_3131/sil_3531 */
455 .flags = SIL24_COMMON_FLAGS | SIL24_NPORTS2FLAG(1),
456 .pio_mask = 0x1f, /* pio0-4 */
457 .mwdma_mask = 0x07, /* mwdma0-2 */
458 .udma_mask = 0x3f, /* udma0-5 */
459 .port_ops = &sil24_ops,
463 static int sil24_tag(int tag)
465 if (unlikely(ata_tag_internal(tag)))
470 static void sil24_dev_config(struct ata_port *ap, struct ata_device *dev)
472 void __iomem *port = (void __iomem *)ap->ioaddr.cmd_addr;
474 if (dev->cdb_len == 16)
475 writel(PORT_CS_CDB16, port + PORT_CTRL_STAT);
477 writel(PORT_CS_CDB16, port + PORT_CTRL_CLR);
480 static inline void sil24_update_tf(struct ata_port *ap)
482 struct sil24_port_priv *pp = ap->private_data;
483 void __iomem *port = (void __iomem *)ap->ioaddr.cmd_addr;
484 struct sil24_prb __iomem *prb = port;
487 memcpy_fromio(fis, prb->fis, 6 * 4);
488 ata_tf_from_fis(fis, &pp->tf);
491 static u8 sil24_check_status(struct ata_port *ap)
493 struct sil24_port_priv *pp = ap->private_data;
494 return pp->tf.command;
497 static int sil24_scr_map[] = {
504 static u32 sil24_scr_read(struct ata_port *ap, unsigned sc_reg)
506 void __iomem *scr_addr = (void __iomem *)ap->ioaddr.scr_addr;
507 if (sc_reg < ARRAY_SIZE(sil24_scr_map)) {
509 addr = scr_addr + sil24_scr_map[sc_reg] * 4;
510 return readl(scr_addr + sil24_scr_map[sc_reg] * 4);
515 static void sil24_scr_write(struct ata_port *ap, unsigned sc_reg, u32 val)
517 void __iomem *scr_addr = (void __iomem *)ap->ioaddr.scr_addr;
518 if (sc_reg < ARRAY_SIZE(sil24_scr_map)) {
520 addr = scr_addr + sil24_scr_map[sc_reg] * 4;
521 writel(val, scr_addr + sil24_scr_map[sc_reg] * 4);
525 static void sil24_tf_read(struct ata_port *ap, struct ata_taskfile *tf)
527 struct sil24_port_priv *pp = ap->private_data;
531 static int sil24_init_port(struct ata_port *ap)
533 void __iomem *port = (void __iomem *)ap->ioaddr.cmd_addr;
536 writel(PORT_CS_INIT, port + PORT_CTRL_STAT);
537 ata_wait_register(port + PORT_CTRL_STAT,
538 PORT_CS_INIT, PORT_CS_INIT, 10, 100);
539 tmp = ata_wait_register(port + PORT_CTRL_STAT,
540 PORT_CS_RDY, 0, 10, 100);
542 if ((tmp & (PORT_CS_INIT | PORT_CS_RDY)) != PORT_CS_RDY)
547 static int sil24_softreset(struct ata_port *ap, unsigned int *class)
549 void __iomem *port = (void __iomem *)ap->ioaddr.cmd_addr;
550 struct sil24_port_priv *pp = ap->private_data;
551 struct sil24_prb *prb = &pp->cmd_block[0].ata.prb;
552 dma_addr_t paddr = pp->cmd_block_dma;
558 if (ata_port_offline(ap)) {
559 DPRINTK("PHY reports no device\n");
560 *class = ATA_DEV_NONE;
564 /* put the port into known state */
565 if (sil24_init_port(ap)) {
566 reason ="port not ready";
571 prb->ctrl = cpu_to_le16(PRB_CTRL_SRST);
572 prb->fis[1] = 0; /* no PMP yet */
574 writel((u32)paddr, port + PORT_CMD_ACTIVATE);
575 writel((u64)paddr >> 32, port + PORT_CMD_ACTIVATE + 4);
577 mask = (PORT_IRQ_COMPLETE | PORT_IRQ_ERROR) << PORT_IRQ_RAW_SHIFT;
578 irq_stat = ata_wait_register(port + PORT_IRQ_STAT, mask, 0x0,
579 100, ATA_TMOUT_BOOT / HZ * 1000);
581 writel(irq_stat, port + PORT_IRQ_STAT); /* clear IRQs */
582 irq_stat >>= PORT_IRQ_RAW_SHIFT;
584 if (!(irq_stat & PORT_IRQ_COMPLETE)) {
585 if (irq_stat & PORT_IRQ_ERROR)
586 reason = "SRST command error";
593 *class = ata_dev_classify(&pp->tf);
595 if (*class == ATA_DEV_UNKNOWN)
596 *class = ATA_DEV_NONE;
599 DPRINTK("EXIT, class=%u\n", *class);
603 ata_port_printk(ap, KERN_ERR, "softreset failed (%s)\n", reason);
607 static int sil24_hardreset(struct ata_port *ap, unsigned int *class)
609 void __iomem *port = (void __iomem *)ap->ioaddr.cmd_addr;
614 /* sil24 does the right thing(tm) without any protection */
618 if (ata_port_online(ap))
621 writel(PORT_CS_DEV_RST, port + PORT_CTRL_STAT);
622 tmp = ata_wait_register(port + PORT_CTRL_STAT,
623 PORT_CS_DEV_RST, PORT_CS_DEV_RST, 10, tout_msec);
625 /* SStatus oscillates between zero and valid status after
626 * DEV_RST, debounce it.
628 rc = sata_phy_debounce(ap, sata_deb_timing_long);
630 reason = "PHY debouncing failed";
634 if (tmp & PORT_CS_DEV_RST) {
635 if (ata_port_offline(ap))
637 reason = "link not ready";
641 /* Sil24 doesn't store signature FIS after hardreset, so we
642 * can't wait for BSY to clear. Some devices take a long time
643 * to get ready and those devices will choke if we don't wait
644 * for BSY clearance here. Tell libata to perform follow-up
650 ata_port_printk(ap, KERN_ERR, "hardreset failed (%s)\n", reason);
654 static inline void sil24_fill_sg(struct ata_queued_cmd *qc,
655 struct sil24_sge *sge)
657 struct scatterlist *sg;
658 unsigned int idx = 0;
660 ata_for_each_sg(sg, qc) {
661 sge->addr = cpu_to_le64(sg_dma_address(sg));
662 sge->cnt = cpu_to_le32(sg_dma_len(sg));
663 if (ata_sg_is_last(sg, qc))
664 sge->flags = cpu_to_le32(SGE_TRM);
673 static void sil24_qc_prep(struct ata_queued_cmd *qc)
675 struct ata_port *ap = qc->ap;
676 struct sil24_port_priv *pp = ap->private_data;
677 union sil24_cmd_block *cb;
678 struct sil24_prb *prb;
679 struct sil24_sge *sge;
682 cb = &pp->cmd_block[sil24_tag(qc->tag)];
684 switch (qc->tf.protocol) {
688 case ATA_PROT_NODATA:
694 case ATA_PROT_ATAPI_DMA:
695 case ATA_PROT_ATAPI_NODATA:
696 prb = &cb->atapi.prb;
698 memset(cb->atapi.cdb, 0, 32);
699 memcpy(cb->atapi.cdb, qc->cdb, qc->dev->cdb_len);
701 if (qc->tf.protocol != ATA_PROT_ATAPI_NODATA) {
702 if (qc->tf.flags & ATA_TFLAG_WRITE)
703 ctrl = PRB_CTRL_PACKET_WRITE;
705 ctrl = PRB_CTRL_PACKET_READ;
710 prb = NULL; /* shut up, gcc */
715 prb->ctrl = cpu_to_le16(ctrl);
716 ata_tf_to_fis(&qc->tf, prb->fis, 0);
718 if (qc->flags & ATA_QCFLAG_DMAMAP)
719 sil24_fill_sg(qc, sge);
722 static unsigned int sil24_qc_issue(struct ata_queued_cmd *qc)
724 struct ata_port *ap = qc->ap;
725 struct sil24_port_priv *pp = ap->private_data;
726 void __iomem *port = (void __iomem *)ap->ioaddr.cmd_addr;
727 unsigned int tag = sil24_tag(qc->tag);
729 void __iomem *activate;
731 paddr = pp->cmd_block_dma + tag * sizeof(*pp->cmd_block);
732 activate = port + PORT_CMD_ACTIVATE + tag * 8;
734 writel((u32)paddr, activate);
735 writel((u64)paddr >> 32, activate + 4);
740 static void sil24_irq_clear(struct ata_port *ap)
745 static void sil24_freeze(struct ata_port *ap)
747 void __iomem *port = (void __iomem *)ap->ioaddr.cmd_addr;
749 /* Port-wide IRQ mask in HOST_CTRL doesn't really work, clear
750 * PORT_IRQ_ENABLE instead.
752 writel(0xffff, port + PORT_IRQ_ENABLE_CLR);
755 static void sil24_thaw(struct ata_port *ap)
757 void __iomem *port = (void __iomem *)ap->ioaddr.cmd_addr;
761 tmp = readl(port + PORT_IRQ_STAT);
762 writel(tmp, port + PORT_IRQ_STAT);
764 /* turn IRQ back on */
765 writel(DEF_PORT_IRQ, port + PORT_IRQ_ENABLE_SET);
768 static void sil24_error_intr(struct ata_port *ap)
770 void __iomem *port = (void __iomem *)ap->ioaddr.cmd_addr;
771 struct ata_eh_info *ehi = &ap->eh_info;
775 /* on error, we need to clear IRQ explicitly */
776 irq_stat = readl(port + PORT_IRQ_STAT);
777 writel(irq_stat, port + PORT_IRQ_STAT);
779 /* first, analyze and record host port events */
780 ata_ehi_clear_desc(ehi);
782 ata_ehi_push_desc(ehi, "irq_stat 0x%08x", irq_stat);
784 if (irq_stat & (PORT_IRQ_PHYRDY_CHG | PORT_IRQ_DEV_XCHG)) {
785 ata_ehi_hotplugged(ehi);
786 ata_ehi_push_desc(ehi, ", %s",
787 irq_stat & PORT_IRQ_PHYRDY_CHG ?
788 "PHY RDY changed" : "device exchanged");
792 if (irq_stat & PORT_IRQ_UNK_FIS) {
793 ehi->err_mask |= AC_ERR_HSM;
794 ehi->action |= ATA_EH_SOFTRESET;
795 ata_ehi_push_desc(ehi , ", unknown FIS");
799 /* deal with command error */
800 if (irq_stat & PORT_IRQ_ERROR) {
801 struct sil24_cerr_info *ci = NULL;
802 unsigned int err_mask = 0, action = 0;
803 struct ata_queued_cmd *qc;
806 /* analyze CMD_ERR */
807 cerr = readl(port + PORT_CMD_ERR);
808 if (cerr < ARRAY_SIZE(sil24_cerr_db))
809 ci = &sil24_cerr_db[cerr];
811 if (ci && ci->desc) {
812 err_mask |= ci->err_mask;
813 action |= ci->action;
814 ata_ehi_push_desc(ehi, ", %s", ci->desc);
816 err_mask |= AC_ERR_OTHER;
817 action |= ATA_EH_SOFTRESET;
818 ata_ehi_push_desc(ehi, ", unknown command error %d",
822 /* record error info */
823 qc = ata_qc_from_tag(ap, ap->active_tag);
826 qc->err_mask |= err_mask;
828 ehi->err_mask |= err_mask;
830 ehi->action |= action;
833 /* freeze or abort */
840 static void sil24_finish_qc(struct ata_queued_cmd *qc)
842 if (qc->flags & ATA_QCFLAG_RESULT_TF)
843 sil24_update_tf(qc->ap);
846 static inline void sil24_host_intr(struct ata_port *ap)
848 void __iomem *port = (void __iomem *)ap->ioaddr.cmd_addr;
849 u32 slot_stat, qc_active;
852 slot_stat = readl(port + PORT_SLOT_STAT);
854 if (unlikely(slot_stat & HOST_SSTAT_ATTN)) {
855 sil24_error_intr(ap);
859 if (ap->flags & SIL24_FLAG_PCIX_IRQ_WOC)
860 writel(PORT_IRQ_COMPLETE, port + PORT_IRQ_STAT);
862 qc_active = slot_stat & ~HOST_SSTAT_ATTN;
863 rc = ata_qc_complete_multiple(ap, qc_active, sil24_finish_qc);
867 struct ata_eh_info *ehi = &ap->eh_info;
868 ehi->err_mask |= AC_ERR_HSM;
869 ehi->action |= ATA_EH_SOFTRESET;
875 ata_port_printk(ap, KERN_INFO, "spurious interrupt "
876 "(slot_stat 0x%x active_tag %d sactive 0x%x)\n",
877 slot_stat, ap->active_tag, ap->sactive);
880 static irqreturn_t sil24_interrupt(int irq, void *dev_instance)
882 struct ata_host *host = dev_instance;
883 struct sil24_host_priv *hpriv = host->private_data;
884 unsigned handled = 0;
888 status = readl(hpriv->host_base + HOST_IRQ_STAT);
890 if (status == 0xffffffff) {
891 printk(KERN_ERR DRV_NAME ": IRQ status == 0xffffffff, "
892 "PCI fault or device removal?\n");
896 if (!(status & IRQ_STAT_4PORTS))
899 spin_lock(&host->lock);
901 for (i = 0; i < host->n_ports; i++)
902 if (status & (1 << i)) {
903 struct ata_port *ap = host->ports[i];
904 if (ap && !(ap->flags & ATA_FLAG_DISABLED)) {
905 sil24_host_intr(host->ports[i]);
908 printk(KERN_ERR DRV_NAME
909 ": interrupt from disabled port %d\n", i);
912 spin_unlock(&host->lock);
914 return IRQ_RETVAL(handled);
917 static void sil24_error_handler(struct ata_port *ap)
919 struct ata_eh_context *ehc = &ap->eh_context;
921 if (sil24_init_port(ap)) {
922 ata_eh_freeze_port(ap);
923 ehc->i.action |= ATA_EH_HARDRESET;
926 /* perform recovery */
927 ata_do_eh(ap, ata_std_prereset, sil24_softreset, sil24_hardreset,
931 static void sil24_post_internal_cmd(struct ata_queued_cmd *qc)
933 struct ata_port *ap = qc->ap;
935 if (qc->flags & ATA_QCFLAG_FAILED)
936 qc->err_mask |= AC_ERR_OTHER;
938 /* make DMA engine forget about the failed command */
943 static inline void sil24_cblk_free(struct sil24_port_priv *pp, struct device *dev)
945 const size_t cb_size = sizeof(*pp->cmd_block) * SIL24_MAX_CMDS;
947 dma_free_coherent(dev, cb_size, pp->cmd_block, pp->cmd_block_dma);
950 static int sil24_port_start(struct ata_port *ap)
952 struct device *dev = ap->host->dev;
953 struct sil24_port_priv *pp;
954 union sil24_cmd_block *cb;
955 size_t cb_size = sizeof(*cb) * SIL24_MAX_CMDS;
959 pp = kzalloc(sizeof(*pp), GFP_KERNEL);
963 pp->tf.command = ATA_DRDY;
965 cb = dma_alloc_coherent(dev, cb_size, &cb_dma, GFP_KERNEL);
968 memset(cb, 0, cb_size);
970 rc = ata_pad_alloc(ap, dev);
975 pp->cmd_block_dma = cb_dma;
977 ap->private_data = pp;
982 sil24_cblk_free(pp, dev);
989 static void sil24_port_stop(struct ata_port *ap)
991 struct device *dev = ap->host->dev;
992 struct sil24_port_priv *pp = ap->private_data;
994 sil24_cblk_free(pp, dev);
995 ata_pad_free(ap, dev);
999 static void sil24_host_stop(struct ata_host *host)
1001 struct sil24_host_priv *hpriv = host->private_data;
1002 struct pci_dev *pdev = to_pci_dev(host->dev);
1004 pci_iounmap(pdev, hpriv->host_base);
1005 pci_iounmap(pdev, hpriv->port_base);
1009 static void sil24_init_controller(struct pci_dev *pdev, int n_ports,
1010 unsigned long port_flags,
1011 void __iomem *host_base,
1012 void __iomem *port_base)
1018 writel(0, host_base + HOST_FLASH_CMD);
1020 /* clear global reset & mask interrupts during initialization */
1021 writel(0, host_base + HOST_CTRL);
1024 for (i = 0; i < n_ports; i++) {
1025 void __iomem *port = port_base + i * PORT_REGS_SIZE;
1027 /* Initial PHY setting */
1028 writel(0x20c, port + PORT_PHY_CFG);
1030 /* Clear port RST */
1031 tmp = readl(port + PORT_CTRL_STAT);
1032 if (tmp & PORT_CS_PORT_RST) {
1033 writel(PORT_CS_PORT_RST, port + PORT_CTRL_CLR);
1034 tmp = ata_wait_register(port + PORT_CTRL_STAT,
1036 PORT_CS_PORT_RST, 10, 100);
1037 if (tmp & PORT_CS_PORT_RST)
1038 dev_printk(KERN_ERR, &pdev->dev,
1039 "failed to clear port RST\n");
1042 /* Configure IRQ WoC */
1043 if (port_flags & SIL24_FLAG_PCIX_IRQ_WOC)
1044 writel(PORT_CS_IRQ_WOC, port + PORT_CTRL_STAT);
1046 writel(PORT_CS_IRQ_WOC, port + PORT_CTRL_CLR);
1048 /* Zero error counters. */
1049 writel(0x8000, port + PORT_DECODE_ERR_THRESH);
1050 writel(0x8000, port + PORT_CRC_ERR_THRESH);
1051 writel(0x8000, port + PORT_HSHK_ERR_THRESH);
1052 writel(0x0000, port + PORT_DECODE_ERR_CNT);
1053 writel(0x0000, port + PORT_CRC_ERR_CNT);
1054 writel(0x0000, port + PORT_HSHK_ERR_CNT);
1056 /* Always use 64bit activation */
1057 writel(PORT_CS_32BIT_ACTV, port + PORT_CTRL_CLR);
1059 /* Clear port multiplier enable and resume bits */
1060 writel(PORT_CS_PMP_EN | PORT_CS_PMP_RESUME,
1061 port + PORT_CTRL_CLR);
1064 /* Turn on interrupts */
1065 writel(IRQ_STAT_4PORTS, host_base + HOST_CTRL);
1068 static int sil24_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
1070 static int printed_version = 0;
1071 unsigned int board_id = (unsigned int)ent->driver_data;
1072 struct ata_port_info *pinfo = &sil24_port_info[board_id];
1073 struct ata_probe_ent *probe_ent = NULL;
1074 struct sil24_host_priv *hpriv = NULL;
1075 void __iomem *host_base = NULL;
1076 void __iomem *port_base = NULL;
1080 if (!printed_version++)
1081 dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n");
1083 rc = pci_enable_device(pdev);
1087 rc = pci_request_regions(pdev, DRV_NAME);
1092 /* map mmio registers */
1093 host_base = pci_iomap(pdev, 0, 0);
1096 port_base = pci_iomap(pdev, 2, 0);
1100 /* allocate & init probe_ent and hpriv */
1101 probe_ent = kzalloc(sizeof(*probe_ent), GFP_KERNEL);
1105 hpriv = kzalloc(sizeof(*hpriv), GFP_KERNEL);
1109 probe_ent->dev = pci_dev_to_dev(pdev);
1110 INIT_LIST_HEAD(&probe_ent->node);
1112 probe_ent->sht = pinfo->sht;
1113 probe_ent->port_flags = pinfo->flags;
1114 probe_ent->pio_mask = pinfo->pio_mask;
1115 probe_ent->mwdma_mask = pinfo->mwdma_mask;
1116 probe_ent->udma_mask = pinfo->udma_mask;
1117 probe_ent->port_ops = pinfo->port_ops;
1118 probe_ent->n_ports = SIL24_FLAG2NPORTS(pinfo->flags);
1120 probe_ent->irq = pdev->irq;
1121 probe_ent->irq_flags = IRQF_SHARED;
1122 probe_ent->private_data = hpriv;
1124 hpriv->host_base = host_base;
1125 hpriv->port_base = port_base;
1128 * Configure the device
1130 if (!pci_set_dma_mask(pdev, DMA_64BIT_MASK)) {
1131 rc = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
1133 rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
1135 dev_printk(KERN_ERR, &pdev->dev,
1136 "64-bit DMA enable failed\n");
1141 rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
1143 dev_printk(KERN_ERR, &pdev->dev,
1144 "32-bit DMA enable failed\n");
1147 rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
1149 dev_printk(KERN_ERR, &pdev->dev,
1150 "32-bit consistent DMA enable failed\n");
1155 /* Apply workaround for completion IRQ loss on PCI-X errata */
1156 if (probe_ent->port_flags & SIL24_FLAG_PCIX_IRQ_WOC) {
1157 tmp = readl(host_base + HOST_CTRL);
1158 if (tmp & (HOST_CTRL_TRDY | HOST_CTRL_STOP | HOST_CTRL_DEVSEL))
1159 dev_printk(KERN_INFO, &pdev->dev,
1160 "Applying completion IRQ loss on PCI-X "
1163 probe_ent->port_flags &= ~SIL24_FLAG_PCIX_IRQ_WOC;
1166 for (i = 0; i < probe_ent->n_ports; i++) {
1167 unsigned long portu =
1168 (unsigned long)port_base + i * PORT_REGS_SIZE;
1170 probe_ent->port[i].cmd_addr = portu;
1171 probe_ent->port[i].scr_addr = portu + PORT_SCONTROL;
1173 ata_std_ports(&probe_ent->port[i]);
1176 sil24_init_controller(pdev, probe_ent->n_ports, probe_ent->port_flags,
1177 host_base, port_base);
1179 pci_set_master(pdev);
1181 /* FIXME: check ata_device_add return value */
1182 ata_device_add(probe_ent);
1189 pci_iounmap(pdev, host_base);
1191 pci_iounmap(pdev, port_base);
1194 pci_release_regions(pdev);
1196 pci_disable_device(pdev);
1201 static int sil24_pci_device_resume(struct pci_dev *pdev)
1203 struct ata_host *host = dev_get_drvdata(&pdev->dev);
1204 struct sil24_host_priv *hpriv = host->private_data;
1206 ata_pci_device_do_resume(pdev);
1208 if (pdev->dev.power.power_state.event == PM_EVENT_SUSPEND)
1209 writel(HOST_CTRL_GLOBAL_RST, hpriv->host_base + HOST_CTRL);
1211 sil24_init_controller(pdev, host->n_ports, host->ports[0]->flags,
1212 hpriv->host_base, hpriv->port_base);
1214 ata_host_resume(host);
1220 static int __init sil24_init(void)
1222 return pci_register_driver(&sil24_pci_driver);
1225 static void __exit sil24_exit(void)
1227 pci_unregister_driver(&sil24_pci_driver);
1230 MODULE_AUTHOR("Tejun Heo");
1231 MODULE_DESCRIPTION("Silicon Image 3124/3132 SATA low-level driver");
1232 MODULE_LICENSE("GPL");
1233 MODULE_DEVICE_TABLE(pci, sil24_pci_tbl);
1235 module_init(sil24_init);
1236 module_exit(sil24_exit);