2 Madge Horizon ATM Adapter driver.
3 Copyright (C) 1995-1999 Madge Networks Ltd.
5 This program is free software; you can redistribute it and/or modify
6 it under the terms of the GNU General Public License as published by
7 the Free Software Foundation; either version 2 of the License, or
8 (at your option) any later version.
10 This program is distributed in the hope that it will be useful,
11 but WITHOUT ANY WARRANTY; without even the implied warranty of
12 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 GNU General Public License for more details.
15 You should have received a copy of the GNU General Public License
16 along with this program; if not, write to the Free Software
17 Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 The GNU GPL is contained in /usr/doc/copyright/GPL on a Debian
20 system and in the file COPYING in the Linux kernel source.
24 IMPORTANT NOTE: Madge Networks no longer makes the adapters
25 supported by this driver and makes no commitment to maintain it.
28 #include <linux/module.h>
29 #include <linux/kernel.h>
31 #include <linux/pci.h>
32 #include <linux/errno.h>
33 #include <linux/atm.h>
34 #include <linux/atmdev.h>
35 #include <linux/sonet.h>
36 #include <linux/skbuff.h>
37 #include <linux/time.h>
38 #include <linux/delay.h>
39 #include <linux/uio.h>
40 #include <linux/init.h>
41 #include <linux/ioport.h>
43 #include <asm/system.h>
45 #include <asm/atomic.h>
46 #include <asm/uaccess.h>
47 #include <asm/string.h>
48 #include <asm/byteorder.h>
52 #define maintainer_string "Giuliano Procida at Madge Networks <gprocida@madge.com>"
53 #define description_string "Madge ATM Horizon [Ultra] driver"
54 #define version_string "1.2.1"
56 static inline void __init show_version (void) {
57 printk ("%s version %s\n", description_string, version_string);
64 Driver and documentation by:
66 Chris Aston Madge Networks
67 Giuliano Procida Madge Networks
68 Simon Benham Madge Networks
69 Simon Johnson Madge Networks
70 Various Others Madge Networks
72 Some inspiration taken from other drivers by:
75 Kari Mettinen University of Helsinki
76 Werner Almesberger EPFL LRC
80 I Hardware, detection, initialisation and shutdown.
84 This driver should handle all variants of the PCI Madge ATM adapters
85 with the Horizon chipset. These are all PCI cards supporting PIO, BM
86 DMA and a form of MMIO (registers only, not internal RAM).
88 The driver is only known to work with SONET and UTP Horizon Ultra
89 cards at 155Mb/s. However, code is in place to deal with both the
90 original Horizon and 25Mb/s operation.
92 There are two revisions of the Horizon ASIC: the original and the
93 Ultra. Details of hardware bugs are in section III.
95 The ASIC version can be distinguished by chip markings but is NOT
96 indicated by the PCI revision (all adapters seem to have PCI rev 1).
100 Horizon => Collage 25 PCI Adapter (UTP and STP)
101 Horizon Ultra => Collage 155 PCI Client (UTP or SONET)
102 Ambassador x => Collage 155 PCI Server (completely different)
104 Horizon (25Mb/s) is fitted with UTP and STP connectors. It seems to
105 have a Madge B154 plus glue logic serializer. I have also found a
106 really ancient version of this with slightly different glue. It
107 comes with the revision 0 (140-025-01) ASIC.
109 Horizon Ultra (155Mb/s) is fitted with either a Pulse Medialink
110 output (UTP) or an HP HFBR 5205 output (SONET). It has either
111 Madge's SAMBA framer or a SUNI-lite device (early versions). It
112 comes with the revision 1 (140-027-01) ASIC.
116 All Horizon-based cards present with the same PCI Vendor and Device
117 IDs. The standard Linux 2.2 PCI API is used to locate any cards and
118 to enable bus-mastering (with appropriate latency).
120 ATM_LAYER_STATUS in the control register distinguishes between the
121 two possible physical layers (25 and 155). It is not clear whether
122 the 155 cards can also operate at 25Mbps. We rely on the fact that a
123 card operates at 155 if and only if it has the newer Horizon Ultra
126 For 155 cards the two possible framers are probed for and then set
131 The card is reset and then put into a known state. The physical
132 layer is configured for normal operation at the appropriate speed;
133 in the case of the 155 cards, the framer is initialised with
134 line-based timing; the internal RAM is zeroed and the allocation of
135 buffers for RX and TX is made; the Burnt In Address is read and
136 copied to the ATM ESI; various policy settings for RX (VPI bits,
137 unknown VCs, oam cells) are made. Ideally all policy items should be
138 configurable at module load (if not actually on-demand), however,
139 only the vpi vs vci bit allocation can be specified at insmod.
143 This is in response to module_cleaup. No VCs are in use and the card
144 should be idle; it is reset.
146 II Driver software (as it should be)
148 0. Traffic Parameters
150 The traffic classes (not an enumeration) are currently: ATM_NONE (no
151 traffic), ATM_UBR, ATM_CBR, ATM_VBR and ATM_ABR, ATM_ANYCLASS
152 (compatible with everything). Together with (perhaps only some of)
153 the following items they make up the traffic specification.
156 unsigned char traffic_class; traffic class (ATM_UBR, ...)
157 int max_pcr; maximum PCR in cells per second
158 int pcr; desired PCR in cells per second
159 int min_pcr; minimum PCR in cells per second
160 int max_cdv; maximum CDV in microseconds
161 int max_sdu; maximum SDU in bytes
164 Note that these denote bandwidth available not bandwidth used; the
165 possibilities according to ATMF are:
167 Real Time (cdv and max CDT given)
169 CBR(pcr) pcr bandwidth always available
170 rtVBR(pcr,scr,mbs) scr bandwidth always available, upto pcr at mbs too
174 nrtVBR(pcr,scr,mbs) scr bandwidth always available, upto pcr at mbs too
176 ABR(mcr,pcr) mcr bandwidth always available, upto pcr (depending) too
178 mbs is max burst size (bucket)
179 pcr and scr have associated cdvt values
180 mcr is like scr but has no cdtv
181 cdtv may differ at each hop
183 Some of the above items are qos items (as opposed to traffic
184 parameters). We have nothing to do with qos. All except ABR can have
185 their traffic parameters converted to GCRA parameters. The GCRA may
186 be implemented as a (real-number) leaky bucket. The GCRA can be used
187 in complicated ways by switches and in simpler ways by end-stations.
188 It can be used both to filter incoming cells and shape out-going
191 ATM Linux actually supports:
193 ATM_NONE() (no traffic in this direction)
194 ATM_UBR(max_frame_size)
195 ATM_CBR(max/min_pcr, max_cdv, max_frame_size)
197 0 or ATM_MAX_PCR are used to indicate maximum available PCR
199 A traffic specification consists of the AAL type and separate
200 traffic specifications for either direction. In ATM Linux it is:
203 struct atm_trafprm txtp;
204 struct atm_trafprm rxtp;
210 ATM_NO_AAL AAL not specified
211 ATM_AAL0 "raw" ATM cells
214 ATM_AAL34 AAL3/4 (data)
216 ATM_SAAL signaling AAL
218 The Horizon has support for AAL frame types: 0, 3/4 and 5. However,
219 it does not implement AAL 3/4 SAR and it has a different notion of
220 "raw cell" to ATM Linux's (48 bytes vs. 52 bytes) so neither are
221 supported by this driver.
223 The Horizon has limited support for ABR (including UBR), VBR and
224 CBR. Each TX channel has a bucket (containing up to 31 cell units)
225 and two timers (PCR and SCR) associated with it that can be used to
226 govern cell emissions and host notification (in the case of ABR this
227 is presumably so that RM cells may be emitted at appropriate times).
228 The timers may either be disabled or may be set to any of 240 values
229 (determined by the clock crystal, a fixed (?) per-device divider, a
230 configurable divider and a configurable timer preload value).
232 At the moment only UBR and CBR are supported by the driver. VBR will
233 be supported as soon as ATM for Linux supports it. ABR support is
234 very unlikely as RM cell handling is completely up to the driver.
236 1. TX (TX channel setup and TX transfer)
238 The TX half of the driver owns the TX Horizon registers. The TX
239 component in the IRQ handler is the BM completion handler. This can
240 only be entered when tx_busy is true (enforced by hardware). The
241 other TX component can only be entered when tx_busy is false
242 (enforced by driver). So TX is single-threaded.
244 Apart from a minor optimisation to not re-select the last channel,
245 the TX send component works as follows:
247 Atomic test and set tx_busy until we succeed; we should implement
248 some sort of timeout so that tx_busy will never be stuck at true.
250 If no TX channel is set up for this VC we wait for an idle one (if
251 necessary) and set it up.
253 At this point we have a TX channel ready for use. We wait for enough
254 buffers to become available then start a TX transmit (set the TX
255 descriptor, schedule transfer, exit).
257 The IRQ component handles TX completion (stats, free buffer, tx_busy
258 unset, exit). We also re-schedule further transfers for the same
261 TX setup in more detail:
263 TX open is a nop, the relevant information is held in the hrz_vcc
264 (vcc->dev_data) structure and is "cached" on the card.
266 TX close gets the TX lock and clears the channel from the "cache".
268 2. RX (Data Available and RX transfer)
270 The RX half of the driver owns the RX registers. There are two RX
271 components in the IRQ handler: the data available handler deals with
272 fresh data that has arrived on the card, the BM completion handler
273 is very similar to the TX completion handler. The data available
274 handler grabs the rx_lock and it is only released once the data has
275 been discarded or completely transferred to the host. The BM
276 completion handler only runs when the lock is held; the data
277 available handler is locked out over the same period.
279 Data available on the card triggers an interrupt. If the data is not
280 suitable for our existing RX channels or we cannot allocate a buffer
281 it is flushed. Otherwise an RX receive is scheduled. Multiple RX
282 transfers may be scheduled for the same frame.
284 RX setup in more detail:
291 0. Byte vs Word addressing of adapter RAM.
293 A design feature; see the .h file (especially the memory map).
295 1. Bus Master Data Transfers (original Horizon only, fixed in Ultra)
297 The host must not start a transmit direction transfer at a
298 non-four-byte boundary in host memory. Instead the host should
299 perform a byte, or a two byte, or one byte followed by two byte
300 transfer in order to start the rest of the transfer on a four byte
303 Simultaneous transmit and receive direction bus master transfers are
306 The simplest solution to these two is to always do PIO (never DMA)
307 in the TX direction on the original Horizon. More complicated
308 solutions are likely to hurt my brain.
310 2. Loss of buffer on close VC
312 When a VC is being closed, the buffer associated with it is not
313 returned to the pool. The host must store the reference to this
314 buffer and when opening a new VC then give it to that new VC.
316 The host intervention currently consists of stacking such a buffer
317 pointer at VC close and checking the stack at VC open.
319 3. Failure to close a VC
321 If a VC is currently receiving a frame then closing the VC may fail
322 and the frame continues to be received.
324 The solution is to make sure any received frames are flushed when
325 ready. This is currently done just before the solution to 2.
327 4. PCI bus (original Horizon only, fixed in Ultra)
329 Reading from the data port prior to initialisation will hang the PCI
330 bus. Just don't do that then! We don't.
334 . Timer code may be broken.
336 . Allow users to specify buffer allocation split for TX and RX.
338 . Deal once and for all with buggy VC close.
340 . Handle interrupted and/or non-blocking operations.
342 . Change some macros to functions and move from .h to .c.
344 . Try to limit the number of TX frames each VC may have queued, in
345 order to reduce the chances of TX buffer exhaustion.
347 . Implement VBR (bucket and timers not understood) and ABR (need to
348 do RM cells manually); also no Linux support for either.
350 . Implement QoS changes on open VCs (involves extracting parts of VC open
351 and close into separate functions and using them to make changes).
355 /********** globals **********/
357 static void do_housekeeping (unsigned long arg);
359 static unsigned short debug = 0;
360 static unsigned short vpi_bits = 0;
361 static int max_tx_size = 9000;
362 static int max_rx_size = 9000;
363 static unsigned char pci_lat = 0;
365 /********** access functions **********/
367 /* Read / Write Horizon registers */
368 static inline void wr_regl (const hrz_dev * dev, unsigned char reg, u32 data) {
369 outl (cpu_to_le32 (data), dev->iobase + reg);
372 static inline u32 rd_regl (const hrz_dev * dev, unsigned char reg) {
373 return le32_to_cpu (inl (dev->iobase + reg));
376 static inline void wr_regw (const hrz_dev * dev, unsigned char reg, u16 data) {
377 outw (cpu_to_le16 (data), dev->iobase + reg);
380 static inline u16 rd_regw (const hrz_dev * dev, unsigned char reg) {
381 return le16_to_cpu (inw (dev->iobase + reg));
384 static inline void wrs_regb (const hrz_dev * dev, unsigned char reg, void * addr, u32 len) {
385 outsb (dev->iobase + reg, addr, len);
388 static inline void rds_regb (const hrz_dev * dev, unsigned char reg, void * addr, u32 len) {
389 insb (dev->iobase + reg, addr, len);
392 /* Read / Write to a given address in Horizon buffer memory.
393 Interrupts must be disabled between the address register and data
394 port accesses as these must form an atomic operation. */
395 static inline void wr_mem (const hrz_dev * dev, HDW * addr, u32 data) {
396 // wr_regl (dev, MEM_WR_ADDR_REG_OFF, (u32) addr);
397 wr_regl (dev, MEM_WR_ADDR_REG_OFF, (addr - (HDW *) 0) * sizeof(HDW));
398 wr_regl (dev, MEMORY_PORT_OFF, data);
401 static inline u32 rd_mem (const hrz_dev * dev, HDW * addr) {
402 // wr_regl (dev, MEM_RD_ADDR_REG_OFF, (u32) addr);
403 wr_regl (dev, MEM_RD_ADDR_REG_OFF, (addr - (HDW *) 0) * sizeof(HDW));
404 return rd_regl (dev, MEMORY_PORT_OFF);
407 static inline void wr_framer (const hrz_dev * dev, u32 addr, u32 data) {
408 wr_regl (dev, MEM_WR_ADDR_REG_OFF, (u32) addr | 0x80000000);
409 wr_regl (dev, MEMORY_PORT_OFF, data);
412 static inline u32 rd_framer (const hrz_dev * dev, u32 addr) {
413 wr_regl (dev, MEM_RD_ADDR_REG_OFF, (u32) addr | 0x80000000);
414 return rd_regl (dev, MEMORY_PORT_OFF);
417 /********** specialised access functions **********/
421 static inline void FLUSH_RX_CHANNEL (hrz_dev * dev, u16 channel) {
422 wr_regw (dev, RX_CHANNEL_PORT_OFF, FLUSH_CHANNEL | channel);
426 static inline void WAIT_FLUSH_RX_COMPLETE (hrz_dev * dev) {
427 while (rd_regw (dev, RX_CHANNEL_PORT_OFF) & FLUSH_CHANNEL)
432 static inline void SELECT_RX_CHANNEL (hrz_dev * dev, u16 channel) {
433 wr_regw (dev, RX_CHANNEL_PORT_OFF, channel);
437 static inline void WAIT_UPDATE_COMPLETE (hrz_dev * dev) {
438 while (rd_regw (dev, RX_CHANNEL_PORT_OFF) & RX_CHANNEL_UPDATE_IN_PROGRESS)
445 static inline void SELECT_TX_CHANNEL (hrz_dev * dev, u16 tx_channel) {
446 wr_regl (dev, TX_CHANNEL_PORT_OFF, tx_channel);
450 /* Update or query one configuration parameter of a particular channel. */
452 static inline void update_tx_channel_config (hrz_dev * dev, short chan, u8 mode, u16 value) {
453 wr_regw (dev, TX_CHANNEL_CONFIG_COMMAND_OFF,
454 chan * TX_CHANNEL_CONFIG_MULT | mode);
455 wr_regw (dev, TX_CHANNEL_CONFIG_DATA_OFF, value);
459 static inline u16 query_tx_channel_config (hrz_dev * dev, short chan, u8 mode) {
460 wr_regw (dev, TX_CHANNEL_CONFIG_COMMAND_OFF,
461 chan * TX_CHANNEL_CONFIG_MULT | mode);
462 return rd_regw (dev, TX_CHANNEL_CONFIG_DATA_OFF);
465 /********** dump functions **********/
467 static inline void dump_skb (char * prefix, unsigned int vc, struct sk_buff * skb) {
470 unsigned char * data = skb->data;
471 PRINTDB (DBG_DATA, "%s(%u) ", prefix, vc);
472 for (i=0; i<skb->len && i < 256;i++)
473 PRINTDM (DBG_DATA, "%02x ", data[i]);
474 PRINTDE (DBG_DATA,"");
483 static inline void dump_regs (hrz_dev * dev) {
485 PRINTD (DBG_REGS, "CONTROL 0: %#x", rd_regl (dev, CONTROL_0_REG));
486 PRINTD (DBG_REGS, "RX CONFIG: %#x", rd_regw (dev, RX_CONFIG_OFF));
487 PRINTD (DBG_REGS, "TX CONFIG: %#x", rd_regw (dev, TX_CONFIG_OFF));
488 PRINTD (DBG_REGS, "TX STATUS: %#x", rd_regw (dev, TX_STATUS_OFF));
489 PRINTD (DBG_REGS, "IRQ ENBLE: %#x", rd_regl (dev, INT_ENABLE_REG_OFF));
490 PRINTD (DBG_REGS, "IRQ SORCE: %#x", rd_regl (dev, INT_SOURCE_REG_OFF));
497 static inline void dump_framer (hrz_dev * dev) {
500 PRINTDB (DBG_REGS, "framer registers:");
501 for (i = 0; i < 0x10; ++i)
502 PRINTDM (DBG_REGS, " %02x", rd_framer (dev, i));
503 PRINTDE (DBG_REGS,"");
510 /********** VPI/VCI <-> (RX) channel conversions **********/
512 /* RX channels are 10 bit integers, these fns are quite paranoid */
514 static inline int channel_to_vpivci (const u16 channel, short * vpi, int * vci) {
515 unsigned short vci_bits = 10 - vpi_bits;
516 if ((channel & RX_CHANNEL_MASK) == channel) {
517 *vci = channel & ((~0)<<vci_bits);
518 *vpi = channel >> vci_bits;
519 return channel ? 0 : -EINVAL;
524 static inline int vpivci_to_channel (u16 * channel, const short vpi, const int vci) {
525 unsigned short vci_bits = 10 - vpi_bits;
526 if (0 <= vpi && vpi < 1<<vpi_bits && 0 <= vci && vci < 1<<vci_bits) {
527 *channel = vpi<<vci_bits | vci;
528 return *channel ? 0 : -EINVAL;
533 /********** decode RX queue entries **********/
535 static inline u16 rx_q_entry_to_length (u32 x) {
536 return x & RX_Q_ENTRY_LENGTH_MASK;
539 static inline u16 rx_q_entry_to_rx_channel (u32 x) {
540 return (x>>RX_Q_ENTRY_CHANNEL_SHIFT) & RX_CHANNEL_MASK;
543 /* Cell Transmit Rate Values
545 * the cell transmit rate (cells per sec) can be set to a variety of
546 * different values by specifying two parameters: a timer preload from
547 * 1 to 16 (stored as 0 to 15) and a clock divider (2 to the power of
548 * an exponent from 0 to 14; the special value 15 disables the timer).
550 * cellrate = baserate / (preload * 2^divider)
552 * The maximum cell rate that can be specified is therefore just the
553 * base rate. Halving the preload is equivalent to adding 1 to the
554 * divider and so values 1 to 8 of the preload are redundant except
555 * in the case of a maximal divider (14).
557 * Given a desired cell rate, an algorithm to determine the preload
560 * a) x = baserate / cellrate, want p * 2^d = x (as far as possible)
561 * b) if x > 16 * 2^14 then set p = 16, d = 14 (min rate), done
562 * if x <= 16 then set p = x, d = 0 (high rates), done
563 * c) now have 16 < x <= 2^18, or 1 < x/16 <= 2^14 and we want to
564 * know n such that 2^(n-1) < x/16 <= 2^n, so slide a bit until
565 * we find the range (n will be between 1 and 14), set d = n
566 * d) Also have 8 < x/2^n <= 16, so set p nearest x/2^n
568 * The algorithm used below is a minor variant of the above.
570 * The base rate is derived from the oscillator frequency (Hz) using a
573 * baserate = freq / 32 in the case of some Unknown Card
574 * baserate = freq / 8 in the case of the Horizon 25
575 * baserate = freq / 8 in the case of the Horizon Ultra 155
577 * The Horizon cards have oscillators and base rates as follows:
579 * Card Oscillator Base Rate
580 * Unknown Card 33 MHz 1.03125 MHz (33 MHz = PCI freq)
581 * Horizon 25 32 MHz 4 MHz
582 * Horizon Ultra 155 40 MHz 5 MHz
584 * The following defines give the base rates in Hz. These were
585 * previously a factor of 100 larger, no doubt someone was using
589 #define BR_UKN 1031250l
590 #define BR_HRZ 4000000l
591 #define BR_ULT 5000000l
597 // p ranges from 1 to a power of 2
600 static int make_rate (const hrz_dev * dev, u32 c, rounding r,
601 u16 * bits, unsigned int * actual)
603 // note: rounding the rate down means rounding 'p' up
604 const unsigned long br = test_bit(ultra, &dev->flags) ? BR_ULT : BR_HRZ;
609 // br_exp and br_man are used to avoid overflowing (c*maxp*2^d) in
610 // the tests below. We could think harder about exact possibilities
613 unsigned long br_man = br;
614 unsigned int br_exp = 0;
616 PRINTD (DBG_QOS|DBG_FLOW, "make_rate b=%lu, c=%u, %s", br, c,
617 r == round_up ? "up" : r == round_down ? "down" : "nearest");
621 PRINTD (DBG_QOS|DBG_ERR, "zero rate is not allowed!");
625 while (br_exp < CR_MAXPEXP + CR_MIND && (br_man % 2 == 0)) {
626 br_man = br_man >> 1;
629 // (br >>br_exp) <<br_exp == br and
630 // br_exp <= CR_MAXPEXP+CR_MIND
632 if (br_man <= (c << (CR_MAXPEXP+CR_MIND-br_exp))) {
633 // Equivalent to: B <= (c << (MAXPEXP+MIND))
634 // take care of rounding
637 pre = (br+(c<<div)-1)/(c<<div);
638 // but p must be non-zero
643 pre = (br+(c<<div)/2)/(c<<div);
644 // but p must be non-zero
648 default: /* round_up */
650 // but p must be non-zero
654 PRINTD (DBG_QOS, "A: p=%u, d=%u", pre, div);
658 // at this point we have
659 // d == MIND and (c << (MAXPEXP+MIND)) < B
660 while (div < CR_MAXD) {
662 if (br_man <= (c << (CR_MAXPEXP+div-br_exp))) {
663 // Equivalent to: B <= (c << (MAXPEXP+d))
664 // c << (MAXPEXP+d-1) < B <= c << (MAXPEXP+d)
665 // 1 << (MAXPEXP-1) < B/2^d/c <= 1 << MAXPEXP
666 // MAXP/2 < B/c2^d <= MAXP
667 // take care of rounding
670 pre = (br+(c<<div)-1)/(c<<div);
673 pre = (br+(c<<div)/2)/(c<<div);
675 default: /* round_up */
678 PRINTD (DBG_QOS, "B: p=%u, d=%u", pre, div);
682 // at this point we have
683 // d == MAXD and (c << (MAXPEXP+MAXD)) < B
684 // but we cannot go any higher
685 // take care of rounding
688 pre = 1 << CR_MAXPEXP;
689 PRINTD (DBG_QOS, "C: p=%u, d=%u", pre, div);
692 if (div > CR_MAXD || (!pre) || pre > 1<<CR_MAXPEXP) {
693 PRINTD (DBG_QOS, "set_cr internal failure: d=%u p=%u",
698 *bits = (div<<CLOCK_SELECT_SHIFT) | (pre-1);
700 *actual = (br + (pre<<div) - 1) / (pre<<div);
701 PRINTD (DBG_QOS, "actual rate: %u", *actual);
707 static int make_rate_with_tolerance (const hrz_dev * dev, u32 c, rounding r, unsigned int tol,
708 u16 * bit_pattern, unsigned int * actual) {
709 unsigned int my_actual;
711 PRINTD (DBG_QOS|DBG_FLOW, "make_rate_with_tolerance c=%u, %s, tol=%u",
712 c, (r == round_up) ? "up" : (r == round_down) ? "down" : "nearest", tol);
715 // actual rate is not returned
718 if (make_rate (dev, c, round_nearest, bit_pattern, actual))
719 // should never happen as round_nearest always succeeds
722 if (c - tol <= *actual && *actual <= c + tol)
726 // intolerant, try rounding instead
727 return make_rate (dev, c, r, bit_pattern, actual);
730 /********** Listen on a VC **********/
732 static int hrz_open_rx (hrz_dev * dev, u16 channel) {
733 // is there any guarantee that we don't get two simulataneous
734 // identical calls of this function from different processes? yes
737 u32 channel_type; // u16?
739 u16 buf_ptr = RX_CHANNEL_IDLE;
741 rx_ch_desc * rx_desc = &memmap->rx_descs[channel];
743 PRINTD (DBG_FLOW, "hrz_open_rx %x", channel);
745 spin_lock_irqsave (&dev->mem_lock, flags);
746 channel_type = rd_mem (dev, &rx_desc->wr_buf_type) & BUFFER_PTR_MASK;
747 spin_unlock_irqrestore (&dev->mem_lock, flags);
749 // very serious error, should never occur
750 if (channel_type != RX_CHANNEL_DISABLED) {
751 PRINTD (DBG_ERR|DBG_VCC, "RX channel for VC already open");
752 return -EBUSY; // clean up?
755 // Give back spare buffer
756 if (dev->noof_spare_buffers) {
757 buf_ptr = dev->spare_buffers[--dev->noof_spare_buffers];
758 PRINTD (DBG_VCC, "using a spare buffer: %u", buf_ptr);
759 // should never occur
760 if (buf_ptr == RX_CHANNEL_DISABLED || buf_ptr == RX_CHANNEL_IDLE) {
761 // but easy to recover from
762 PRINTD (DBG_ERR|DBG_VCC, "bad spare buffer pointer, using IDLE");
763 buf_ptr = RX_CHANNEL_IDLE;
766 PRINTD (DBG_VCC, "using IDLE buffer pointer");
769 // Channel is currently disabled so change its status to idle
771 // do we really need to save the flags again?
772 spin_lock_irqsave (&dev->mem_lock, flags);
774 wr_mem (dev, &rx_desc->wr_buf_type,
775 buf_ptr | CHANNEL_TYPE_AAL5 | FIRST_CELL_OF_AAL5_FRAME);
776 if (buf_ptr != RX_CHANNEL_IDLE)
777 wr_mem (dev, &rx_desc->rd_buf_type, buf_ptr);
779 spin_unlock_irqrestore (&dev->mem_lock, flags);
781 // rxer->rate = make_rate (qos->peak_cells);
783 PRINTD (DBG_FLOW, "hrz_open_rx ok");
789 /********** change vc rate for a given vc **********/
791 static void hrz_change_vc_qos (ATM_RXER * rxer, MAAL_QOS * qos) {
792 rxer->rate = make_rate (qos->peak_cells);
796 /********** free an skb (as per ATM device driver documentation) **********/
798 static inline void hrz_kfree_skb (struct sk_buff * skb) {
799 if (ATM_SKB(skb)->vcc->pop) {
800 ATM_SKB(skb)->vcc->pop (ATM_SKB(skb)->vcc, skb);
802 dev_kfree_skb_any (skb);
806 /********** cancel listen on a VC **********/
808 static void hrz_close_rx (hrz_dev * dev, u16 vc) {
815 rx_ch_desc * rx_desc = &memmap->rx_descs[vc];
819 spin_lock_irqsave (&dev->mem_lock, flags);
820 value = rd_mem (dev, &rx_desc->wr_buf_type) & BUFFER_PTR_MASK;
821 spin_unlock_irqrestore (&dev->mem_lock, flags);
823 if (value == RX_CHANNEL_DISABLED) {
824 // I suppose this could happen once we deal with _NONE traffic properly
825 PRINTD (DBG_VCC, "closing VC: RX channel %u already disabled", vc);
828 if (value == RX_CHANNEL_IDLE)
831 spin_lock_irqsave (&dev->mem_lock, flags);
834 wr_mem (dev, &rx_desc->wr_buf_type, RX_CHANNEL_DISABLED);
836 if ((rd_mem (dev, &rx_desc->wr_buf_type) & BUFFER_PTR_MASK) == RX_CHANNEL_DISABLED)
843 spin_unlock_irqrestore (&dev->mem_lock, flags);
847 WAIT_FLUSH_RX_COMPLETE(dev);
849 // XXX Is this all really necessary? We can rely on the rx_data_av
850 // handler to discard frames that remain queued for delivery. If the
851 // worry is that immediately reopening the channel (perhaps by a
852 // different process) may cause some data to be mis-delivered then
853 // there may still be a simpler solution (such as busy-waiting on
854 // rx_busy once the channel is disabled or before a new one is
855 // opened - does this leave any holes?). Arguably setting up and
856 // tearing down the TX and RX halves of each virtual circuit could
857 // most safely be done within ?x_busy protected regions.
859 // OK, current changes are that Simon's marker is disabled and we DO
860 // look for NULL rxer elsewhere. The code here seems flush frames
861 // and then remember the last dead cell belonging to the channel
862 // just disabled - the cell gets relinked at the next vc_open.
863 // However, when all VCs are closed or only a few opened there are a
864 // handful of buffers that are unusable.
866 // Does anyone feel like documenting spare_buffers properly?
867 // Does anyone feel like fixing this in a nicer way?
869 // Flush any data which is left in the channel
871 // Change the rx channel port to something different to the RX
872 // channel we are trying to close to force Horizon to flush the rx
873 // channel read and write pointers.
875 u16 other = vc^(RX_CHANS/2);
877 SELECT_RX_CHANNEL (dev, other);
878 WAIT_UPDATE_COMPLETE (dev);
880 r1 = rd_mem (dev, &rx_desc->rd_buf_type);
882 // Select this RX channel. Flush doesn't seem to work unless we
883 // select an RX channel before hand
885 SELECT_RX_CHANNEL (dev, vc);
886 WAIT_UPDATE_COMPLETE (dev);
888 // Attempt to flush a frame on this RX channel
890 FLUSH_RX_CHANNEL (dev, vc);
891 WAIT_FLUSH_RX_COMPLETE (dev);
893 // Force Horizon to flush rx channel read and write pointers as before
895 SELECT_RX_CHANNEL (dev, other);
896 WAIT_UPDATE_COMPLETE (dev);
898 r2 = rd_mem (dev, &rx_desc->rd_buf_type);
900 PRINTD (DBG_VCC|DBG_RX, "r1 = %u, r2 = %u", r1, r2);
903 dev->spare_buffers[dev->noof_spare_buffers++] = (u16)r1;
910 rx_q_entry * wr_ptr = &memmap->rx_q_entries[rd_regw (dev, RX_QUEUE_WR_PTR_OFF)];
911 rx_q_entry * rd_ptr = dev->rx_q_entry;
913 PRINTD (DBG_VCC|DBG_RX, "rd_ptr = %u, wr_ptr = %u", rd_ptr, wr_ptr);
915 while (rd_ptr != wr_ptr) {
916 u32 x = rd_mem (dev, (HDW *) rd_ptr);
918 if (vc == rx_q_entry_to_rx_channel (x)) {
919 x |= SIMONS_DODGEY_MARKER;
921 PRINTD (DBG_RX|DBG_VCC|DBG_WARN, "marking a frame as dodgey");
923 wr_mem (dev, (HDW *) rd_ptr, x);
926 if (rd_ptr == dev->rx_q_wrap)
927 rd_ptr = dev->rx_q_reset;
934 spin_unlock_irqrestore (&dev->mem_lock, flags);
939 /********** schedule RX transfers **********/
941 // Note on tail recursion: a GCC developer said that it is not likely
942 // to be fixed soon, so do not define TAILRECUSRIONWORKS unless you
943 // are sure it does as you may otherwise overflow the kernel stack.
945 // giving this fn a return value would help GCC, alledgedly
947 static void rx_schedule (hrz_dev * dev, int irq) {
948 unsigned int rx_bytes;
951 #ifndef TAILRECURSIONWORKS
953 while (pio_instead) {
955 // bytes waiting for RX transfer
956 rx_bytes = dev->rx_bytes;
960 while (rd_regl (dev, MASTER_RX_COUNT_REG_OFF)) {
961 PRINTD (DBG_RX|DBG_WARN, "RX error: other PCI Bus Master RX still in progress!");
962 if (++spin_count > 10) {
963 PRINTD (DBG_RX|DBG_ERR, "spun out waiting PCI Bus Master RX completion");
964 wr_regl (dev, MASTER_RX_COUNT_REG_OFF, 0);
965 clear_bit (rx_busy, &dev->flags);
966 hrz_kfree_skb (dev->rx_skb);
972 // this code follows the TX code but (at the moment) there is only
973 // one region - the skb itself. I don't know if this will change,
974 // but it doesn't hurt to have the code here, disabled.
977 // start next transfer within same region
978 if (rx_bytes <= MAX_PIO_COUNT) {
979 PRINTD (DBG_RX|DBG_BUS, "(pio)");
982 if (rx_bytes <= MAX_TRANSFER_COUNT) {
983 PRINTD (DBG_RX|DBG_BUS, "(simple or last multi)");
986 PRINTD (DBG_RX|DBG_BUS, "(continuing multi)");
987 dev->rx_bytes = rx_bytes - MAX_TRANSFER_COUNT;
988 rx_bytes = MAX_TRANSFER_COUNT;
991 // rx_bytes == 0 -- we're between regions
992 // regions remaining to transfer
994 unsigned int rx_regions = dev->rx_regions;
996 unsigned int rx_regions = 0;
1001 // start a new region
1002 dev->rx_addr = dev->rx_iovec->iov_base;
1003 rx_bytes = dev->rx_iovec->iov_len;
1005 dev->rx_regions = rx_regions - 1;
1007 if (rx_bytes <= MAX_PIO_COUNT) {
1008 PRINTD (DBG_RX|DBG_BUS, "(pio)");
1011 if (rx_bytes <= MAX_TRANSFER_COUNT) {
1012 PRINTD (DBG_RX|DBG_BUS, "(full region)");
1015 PRINTD (DBG_RX|DBG_BUS, "(start multi region)");
1016 dev->rx_bytes = rx_bytes - MAX_TRANSFER_COUNT;
1017 rx_bytes = MAX_TRANSFER_COUNT;
1022 // that's all folks - end of frame
1023 struct sk_buff * skb = dev->rx_skb;
1024 // dev->rx_iovec = 0;
1026 FLUSH_RX_CHANNEL (dev, dev->rx_channel);
1028 dump_skb ("<<<", dev->rx_channel, skb);
1030 PRINTD (DBG_RX|DBG_SKB, "push %p %u", skb->data, skb->len);
1033 struct atm_vcc * vcc = ATM_SKB(skb)->vcc;
1035 atomic_inc(&vcc->stats->rx);
1036 do_gettimeofday(&skb->stamp);
1037 // end of our responsability
1038 vcc->push (vcc, skb);
1043 // note: writing RX_COUNT clears any interrupt condition
1047 wr_regl (dev, MASTER_RX_COUNT_REG_OFF, 0);
1048 rds_regb (dev, DATA_PORT_OFF, dev->rx_addr, rx_bytes);
1050 wr_regl (dev, MASTER_RX_ADDR_REG_OFF, virt_to_bus (dev->rx_addr));
1051 wr_regl (dev, MASTER_RX_COUNT_REG_OFF, rx_bytes);
1053 dev->rx_addr += rx_bytes;
1056 wr_regl (dev, MASTER_RX_COUNT_REG_OFF, 0);
1057 // allow another RX thread to start
1059 clear_bit (rx_busy, &dev->flags);
1060 PRINTD (DBG_RX, "cleared rx_busy for dev %p", dev);
1063 #ifdef TAILRECURSIONWORKS
1064 // and we all bless optimised tail calls
1066 return rx_schedule (dev, 0);
1076 /********** handle RX bus master complete events **********/
1078 static inline void rx_bus_master_complete_handler (hrz_dev * dev) {
1079 if (test_bit (rx_busy, &dev->flags)) {
1080 rx_schedule (dev, 1);
1082 PRINTD (DBG_RX|DBG_ERR, "unexpected RX bus master completion");
1083 // clear interrupt condition on adapter
1084 wr_regl (dev, MASTER_RX_COUNT_REG_OFF, 0);
1089 /********** (queue to) become the next TX thread **********/
1091 static inline int tx_hold (hrz_dev * dev) {
1092 while (test_and_set_bit (tx_busy, &dev->flags)) {
1093 PRINTD (DBG_TX, "sleeping at tx lock %p %lu", dev, dev->flags);
1094 interruptible_sleep_on (&dev->tx_queue);
1095 PRINTD (DBG_TX, "woken at tx lock %p %lu", dev, dev->flags);
1096 if (signal_pending (current))
1099 PRINTD (DBG_TX, "set tx_busy for dev %p", dev);
1103 /********** allow another TX thread to start **********/
1105 static inline void tx_release (hrz_dev * dev) {
1106 clear_bit (tx_busy, &dev->flags);
1107 PRINTD (DBG_TX, "cleared tx_busy for dev %p", dev);
1108 wake_up_interruptible (&dev->tx_queue);
1111 /********** schedule TX transfers **********/
1113 static void tx_schedule (hrz_dev * const dev, int irq) {
1114 unsigned int tx_bytes;
1116 int append_desc = 0;
1118 int pio_instead = 0;
1119 #ifndef TAILRECURSIONWORKS
1121 while (pio_instead) {
1123 // bytes in current region waiting for TX transfer
1124 tx_bytes = dev->tx_bytes;
1128 while (rd_regl (dev, MASTER_TX_COUNT_REG_OFF)) {
1129 PRINTD (DBG_TX|DBG_WARN, "TX error: other PCI Bus Master TX still in progress!");
1130 if (++spin_count > 10) {
1131 PRINTD (DBG_TX|DBG_ERR, "spun out waiting PCI Bus Master TX completion");
1132 wr_regl (dev, MASTER_TX_COUNT_REG_OFF, 0);
1134 hrz_kfree_skb (dev->tx_skb);
1141 // start next transfer within same region
1142 if (!test_bit (ultra, &dev->flags) || tx_bytes <= MAX_PIO_COUNT) {
1143 PRINTD (DBG_TX|DBG_BUS, "(pio)");
1146 if (tx_bytes <= MAX_TRANSFER_COUNT) {
1147 PRINTD (DBG_TX|DBG_BUS, "(simple or last multi)");
1148 if (!dev->tx_iovec) {
1149 // end of last region
1154 PRINTD (DBG_TX|DBG_BUS, "(continuing multi)");
1155 dev->tx_bytes = tx_bytes - MAX_TRANSFER_COUNT;
1156 tx_bytes = MAX_TRANSFER_COUNT;
1159 // tx_bytes == 0 -- we're between regions
1160 // regions remaining to transfer
1161 unsigned int tx_regions = dev->tx_regions;
1164 // start a new region
1165 dev->tx_addr = dev->tx_iovec->iov_base;
1166 tx_bytes = dev->tx_iovec->iov_len;
1168 dev->tx_regions = tx_regions - 1;
1170 if (!test_bit (ultra, &dev->flags) || tx_bytes <= MAX_PIO_COUNT) {
1171 PRINTD (DBG_TX|DBG_BUS, "(pio)");
1174 if (tx_bytes <= MAX_TRANSFER_COUNT) {
1175 PRINTD (DBG_TX|DBG_BUS, "(full region)");
1178 PRINTD (DBG_TX|DBG_BUS, "(start multi region)");
1179 dev->tx_bytes = tx_bytes - MAX_TRANSFER_COUNT;
1180 tx_bytes = MAX_TRANSFER_COUNT;
1184 // that's all folks - end of frame
1185 struct sk_buff * skb = dev->tx_skb;
1186 dev->tx_iovec = NULL;
1189 atomic_inc(&ATM_SKB(skb)->vcc->stats->tx);
1192 hrz_kfree_skb (skb);
1196 // note: writing TX_COUNT clears any interrupt condition
1200 wr_regl (dev, MASTER_TX_COUNT_REG_OFF, 0);
1201 wrs_regb (dev, DATA_PORT_OFF, dev->tx_addr, tx_bytes);
1203 wr_regl (dev, TX_DESCRIPTOR_PORT_OFF, cpu_to_be32 (dev->tx_skb->len));
1205 wr_regl (dev, MASTER_TX_ADDR_REG_OFF, virt_to_bus (dev->tx_addr));
1207 wr_regl (dev, TX_DESCRIPTOR_REG_OFF, cpu_to_be32 (dev->tx_skb->len));
1208 wr_regl (dev, MASTER_TX_COUNT_REG_OFF,
1210 ? tx_bytes | MASTER_TX_AUTO_APPEND_DESC
1213 dev->tx_addr += tx_bytes;
1216 wr_regl (dev, MASTER_TX_COUNT_REG_OFF, 0);
1221 #ifdef TAILRECURSIONWORKS
1222 // and we all bless optimised tail calls
1224 return tx_schedule (dev, 0);
1234 /********** handle TX bus master complete events **********/
1236 static inline void tx_bus_master_complete_handler (hrz_dev * dev) {
1237 if (test_bit (tx_busy, &dev->flags)) {
1238 tx_schedule (dev, 1);
1240 PRINTD (DBG_TX|DBG_ERR, "unexpected TX bus master completion");
1241 // clear interrupt condition on adapter
1242 wr_regl (dev, MASTER_TX_COUNT_REG_OFF, 0);
1247 /********** move RX Q pointer to next item in circular buffer **********/
1249 // called only from IRQ sub-handler
1250 static inline u32 rx_queue_entry_next (hrz_dev * dev) {
1252 spin_lock (&dev->mem_lock);
1253 rx_queue_entry = rd_mem (dev, &dev->rx_q_entry->entry);
1254 if (dev->rx_q_entry == dev->rx_q_wrap)
1255 dev->rx_q_entry = dev->rx_q_reset;
1258 wr_regw (dev, RX_QUEUE_RD_PTR_OFF, dev->rx_q_entry - dev->rx_q_reset);
1259 spin_unlock (&dev->mem_lock);
1260 return rx_queue_entry;
1263 /********** handle RX disabled by device **********/
1265 static inline void rx_disabled_handler (hrz_dev * dev) {
1266 wr_regw (dev, RX_CONFIG_OFF, rd_regw (dev, RX_CONFIG_OFF) | RX_ENABLE);
1268 PRINTK (KERN_WARNING, "RX was disabled!");
1271 /********** handle RX data received by device **********/
1273 // called from IRQ handler
1274 static inline void rx_data_av_handler (hrz_dev * dev) {
1276 u32 rx_queue_entry_flags;
1280 PRINTD (DBG_FLOW, "hrz_data_av_handler");
1282 // try to grab rx lock (not possible during RX bus mastering)
1283 if (test_and_set_bit (rx_busy, &dev->flags)) {
1284 PRINTD (DBG_RX, "locked out of rx lock");
1287 PRINTD (DBG_RX, "set rx_busy for dev %p", dev);
1288 // lock is cleared if we fail now, o/w after bus master completion
1290 YELLOW_LED_OFF(dev);
1292 rx_queue_entry = rx_queue_entry_next (dev);
1294 rx_len = rx_q_entry_to_length (rx_queue_entry);
1295 rx_channel = rx_q_entry_to_rx_channel (rx_queue_entry);
1297 WAIT_FLUSH_RX_COMPLETE (dev);
1299 SELECT_RX_CHANNEL (dev, rx_channel);
1301 PRINTD (DBG_RX, "rx_queue_entry is: %#x", rx_queue_entry);
1302 rx_queue_entry_flags = rx_queue_entry & (RX_CRC_32_OK|RX_COMPLETE_FRAME|SIMONS_DODGEY_MARKER);
1305 // (at least) bus-mastering breaks if we try to handle a
1306 // zero-length frame, besides AAL5 does not support them
1307 PRINTK (KERN_ERR, "zero-length frame!");
1308 rx_queue_entry_flags &= ~RX_COMPLETE_FRAME;
1311 if (rx_queue_entry_flags & SIMONS_DODGEY_MARKER) {
1312 PRINTD (DBG_RX|DBG_ERR, "Simon's marker detected!");
1314 if (rx_queue_entry_flags == (RX_CRC_32_OK | RX_COMPLETE_FRAME)) {
1315 struct atm_vcc * atm_vcc;
1317 PRINTD (DBG_RX, "got a frame on rx_channel %x len %u", rx_channel, rx_len);
1319 atm_vcc = dev->rxer[rx_channel];
1320 // if no vcc is assigned to this channel, we should drop the frame
1321 // (is this what SIMONS etc. was trying to achieve?)
1325 if (atm_vcc->qos.rxtp.traffic_class != ATM_NONE) {
1327 if (rx_len <= atm_vcc->qos.rxtp.max_sdu) {
1329 struct sk_buff * skb = atm_alloc_charge (atm_vcc, rx_len, GFP_ATOMIC);
1331 // remember this so we can push it later
1333 // remember this so we can flush it later
1334 dev->rx_channel = rx_channel;
1336 // prepare socket buffer
1337 skb_put (skb, rx_len);
1338 ATM_SKB(skb)->vcc = atm_vcc;
1341 // dev->rx_regions = 0;
1342 // dev->rx_iovec = 0;
1343 dev->rx_bytes = rx_len;
1344 dev->rx_addr = skb->data;
1345 PRINTD (DBG_RX, "RX start simple transfer (addr %p, len %d)",
1349 rx_schedule (dev, 0);
1353 PRINTD (DBG_SKB|DBG_WARN, "failed to get skb");
1357 PRINTK (KERN_INFO, "frame received on TX-only VC %x", rx_channel);
1358 // do we count this?
1362 PRINTK (KERN_WARNING, "dropped over-size frame");
1363 // do we count this?
1367 PRINTD (DBG_WARN|DBG_VCC|DBG_RX, "no VCC for this frame (VC closed)");
1368 // do we count this?
1372 // Wait update complete ? SPONG
1378 FLUSH_RX_CHANNEL (dev,rx_channel);
1379 clear_bit (rx_busy, &dev->flags);
1384 /********** interrupt handler **********/
1386 static irqreturn_t interrupt_handler(int irq, void *dev_id,
1387 struct pt_regs *pt_regs) {
1388 hrz_dev * dev = (hrz_dev *) dev_id;
1390 unsigned int irq_ok;
1393 PRINTD (DBG_FLOW, "interrupt_handler: %p", dev_id);
1396 PRINTD (DBG_IRQ|DBG_ERR, "irq with NULL dev_id: %d", irq);
1399 if (irq != dev->irq) {
1400 PRINTD (DBG_IRQ|DBG_ERR, "irq mismatch: %d", irq);
1404 // definitely for us
1406 while ((int_source = rd_regl (dev, INT_SOURCE_REG_OFF)
1407 & INTERESTING_INTERRUPTS)) {
1408 // In the interests of fairness, the (inline) handlers below are
1409 // called in sequence and without immediate return to the head of
1410 // the while loop. This is only of issue for slow hosts (or when
1411 // debugging messages are on). Really slow hosts may find a fast
1412 // sender keeps them permanently in the IRQ handler. :(
1414 // (only an issue for slow hosts) RX completion goes before
1415 // rx_data_av as the former implies rx_busy and so the latter
1416 // would just abort. If it reschedules another transfer
1417 // (continuing the same frame) then it will not clear rx_busy.
1419 // (only an issue for slow hosts) TX completion goes before RX
1420 // data available as it is a much shorter routine - there is the
1421 // chance that any further transfers it schedules will be complete
1422 // by the time of the return to the head of the while loop
1424 if (int_source & RX_BUS_MASTER_COMPLETE) {
1426 PRINTD (DBG_IRQ|DBG_BUS|DBG_RX, "rx_bus_master_complete asserted");
1427 rx_bus_master_complete_handler (dev);
1429 if (int_source & TX_BUS_MASTER_COMPLETE) {
1431 PRINTD (DBG_IRQ|DBG_BUS|DBG_TX, "tx_bus_master_complete asserted");
1432 tx_bus_master_complete_handler (dev);
1434 if (int_source & RX_DATA_AV) {
1436 PRINTD (DBG_IRQ|DBG_RX, "rx_data_av asserted");
1437 rx_data_av_handler (dev);
1441 PRINTD (DBG_IRQ, "work done: %u", irq_ok);
1443 PRINTD (DBG_IRQ|DBG_WARN, "spurious interrupt source: %#x", int_source);
1446 PRINTD (DBG_IRQ|DBG_FLOW, "interrupt_handler done: %p", dev_id);
1452 /********** housekeeping **********/
1454 static void do_housekeeping (unsigned long arg) {
1455 // just stats at the moment
1456 hrz_dev * dev = (hrz_dev *) arg;
1458 // collect device-specific (not driver/atm-linux) stats here
1459 dev->tx_cell_count += rd_regw (dev, TX_CELL_COUNT_OFF);
1460 dev->rx_cell_count += rd_regw (dev, RX_CELL_COUNT_OFF);
1461 dev->hec_error_count += rd_regw (dev, HEC_ERROR_COUNT_OFF);
1462 dev->unassigned_cell_count += rd_regw (dev, UNASSIGNED_CELL_COUNT_OFF);
1464 mod_timer (&dev->housekeeping, jiffies + HZ/10);
1469 /********** find an idle channel for TX and set it up **********/
1471 // called with tx_busy set
1472 static inline short setup_idle_tx_channel (hrz_dev * dev, hrz_vcc * vcc) {
1473 unsigned short idle_channels;
1474 short tx_channel = -1;
1475 unsigned int spin_count;
1476 PRINTD (DBG_FLOW|DBG_TX, "setup_idle_tx_channel %p", dev);
1478 // better would be to fail immediately, the caller can then decide whether
1479 // to wait or drop (depending on whether this is UBR etc.)
1481 while (!(idle_channels = rd_regw (dev, TX_STATUS_OFF) & IDLE_CHANNELS_MASK)) {
1482 PRINTD (DBG_TX|DBG_WARN, "waiting for idle TX channel");
1484 if (++spin_count > 100) {
1485 PRINTD (DBG_TX|DBG_ERR, "spun out waiting for idle TX channel");
1490 // got an idle channel
1492 // tx_idle ensures we look for idle channels in RR order
1493 int chan = dev->tx_idle;
1496 while (keep_going) {
1497 if (idle_channels & (1<<chan)) {
1502 if (chan == TX_CHANS)
1506 dev->tx_idle = chan;
1509 // set up the channel we found
1511 // Initialise the cell header in the transmit channel descriptor
1512 // a.k.a. prepare the channel and remember that we have done so.
1514 tx_ch_desc * tx_desc = &memmap->tx_descs[tx_channel];
1517 u16 channel = vcc->channel;
1519 unsigned long flags;
1520 spin_lock_irqsave (&dev->mem_lock, flags);
1522 // Update the transmit channel record.
1523 dev->tx_channel_record[tx_channel] = channel;
1526 update_tx_channel_config (dev, tx_channel, RATE_TYPE_ACCESS,
1529 // Update the PCR counter preload value etc.
1530 update_tx_channel_config (dev, tx_channel, PCR_TIMER_ACCESS,
1534 if (vcc->tx_xbr_bits == VBR_RATE_TYPE) {
1536 update_tx_channel_config (dev, tx_channel, SCR_TIMER_ACCESS,
1540 update_tx_channel_config (dev, tx_channel, BUCKET_CAPACITY_ACCESS,
1541 vcc->tx_bucket_bits);
1544 update_tx_channel_config (dev, tx_channel, BUCKET_FULLNESS_ACCESS,
1545 vcc->tx_bucket_bits);
1549 // Initialise the read and write buffer pointers
1550 rd_ptr = rd_mem (dev, &tx_desc->rd_buf_type) & BUFFER_PTR_MASK;
1551 wr_ptr = rd_mem (dev, &tx_desc->wr_buf_type) & BUFFER_PTR_MASK;
1553 // idle TX channels should have identical pointers
1554 if (rd_ptr != wr_ptr) {
1555 PRINTD (DBG_TX|DBG_ERR, "TX buffer pointers are broken!");
1556 // spin_unlock... return -E...
1557 // I wonder if gcc would get rid of one of the pointer aliases
1559 PRINTD (DBG_TX, "TX buffer pointers are: rd %x, wr %x.",
1564 PRINTD (DBG_QOS|DBG_TX, "tx_channel: aal0");
1565 rd_ptr |= CHANNEL_TYPE_RAW_CELLS;
1566 wr_ptr |= CHANNEL_TYPE_RAW_CELLS;
1569 PRINTD (DBG_QOS|DBG_TX, "tx_channel: aal34");
1570 rd_ptr |= CHANNEL_TYPE_AAL3_4;
1571 wr_ptr |= CHANNEL_TYPE_AAL3_4;
1574 rd_ptr |= CHANNEL_TYPE_AAL5;
1575 wr_ptr |= CHANNEL_TYPE_AAL5;
1576 // Initialise the CRC
1577 wr_mem (dev, &tx_desc->partial_crc, INITIAL_CRC);
1581 wr_mem (dev, &tx_desc->rd_buf_type, rd_ptr);
1582 wr_mem (dev, &tx_desc->wr_buf_type, wr_ptr);
1584 // Write the Cell Header
1585 // Payload Type, CLP and GFC would go here if non-zero
1586 wr_mem (dev, &tx_desc->cell_header, channel);
1588 spin_unlock_irqrestore (&dev->mem_lock, flags);
1594 /********** send a frame **********/
1596 static int hrz_send (struct atm_vcc * atm_vcc, struct sk_buff * skb) {
1597 unsigned int spin_count;
1599 hrz_dev * dev = HRZ_DEV(atm_vcc->dev);
1600 hrz_vcc * vcc = HRZ_VCC(atm_vcc);
1601 u16 channel = vcc->channel;
1603 u32 buffers_required;
1605 /* signed for error return */
1608 PRINTD (DBG_FLOW|DBG_TX, "hrz_send vc %x data %p len %u",
1609 channel, skb->data, skb->len);
1611 dump_skb (">>>", channel, skb);
1613 if (atm_vcc->qos.txtp.traffic_class == ATM_NONE) {
1614 PRINTK (KERN_ERR, "attempt to send on RX-only VC %x", channel);
1615 hrz_kfree_skb (skb);
1619 // don't understand this
1620 ATM_SKB(skb)->vcc = atm_vcc;
1622 if (skb->len > atm_vcc->qos.txtp.max_sdu) {
1623 PRINTK (KERN_ERR, "sk_buff length greater than agreed max_sdu, dropping...");
1624 hrz_kfree_skb (skb);
1629 PRINTD (DBG_ERR|DBG_TX, "attempt to transmit on zero (rx_)channel");
1630 hrz_kfree_skb (skb);
1636 // where would be a better place for this? housekeeping?
1638 pci_read_config_word (dev->pci_dev, PCI_STATUS, &status);
1639 if (status & PCI_STATUS_REC_MASTER_ABORT) {
1640 PRINTD (DBG_BUS|DBG_ERR, "Clearing PCI Master Abort (and cleaning up)");
1641 status &= ~PCI_STATUS_REC_MASTER_ABORT;
1642 pci_write_config_word (dev->pci_dev, PCI_STATUS, status);
1643 if (test_bit (tx_busy, &dev->flags)) {
1644 hrz_kfree_skb (dev->tx_skb);
1651 #ifdef DEBUG_HORIZON
1653 if (channel == 1023) {
1655 unsigned short d = 0;
1656 char * s = skb->data;
1658 for (i = 0; i < 4; ++i) {
1659 d = (d<<4) | ((*s <= '9') ? (*s - '0') : (*s - 'a' + 10));
1662 PRINTK (KERN_INFO, "debug bitmap is now %hx", debug = d);
1667 // wait until TX is free and grab lock
1668 if (tx_hold (dev)) {
1669 hrz_kfree_skb (skb);
1670 return -ERESTARTSYS;
1673 // Wait for enough space to be available in transmit buffer memory.
1675 // should be number of cells needed + 2 (according to hardware docs)
1676 // = ((framelen+8)+47) / 48 + 2
1677 // = (framelen+7) / 48 + 3, hmm... faster to put addition inside XXX
1678 buffers_required = (skb->len+(ATM_AAL5_TRAILER-1)) / ATM_CELL_PAYLOAD + 3;
1680 // replace with timer and sleep, add dev->tx_buffers_queue (max 1 entry)
1682 while ((free_buffers = rd_regw (dev, TX_FREE_BUFFER_COUNT_OFF)) < buffers_required) {
1683 PRINTD (DBG_TX, "waiting for free TX buffers, got %d of %d",
1684 free_buffers, buffers_required);
1685 // what is the appropriate delay? implement a timeout? (depending on line speed?)
1687 // what happens if we kill (current_pid, SIGKILL) ?
1689 if (++spin_count > 1000) {
1690 PRINTD (DBG_TX|DBG_ERR, "spun out waiting for tx buffers, got %d of %d",
1691 free_buffers, buffers_required);
1693 hrz_kfree_skb (skb);
1694 return -ERESTARTSYS;
1698 // Select a channel to transmit the frame on.
1699 if (channel == dev->last_vc) {
1700 PRINTD (DBG_TX, "last vc hack: hit");
1701 tx_channel = dev->tx_last;
1703 PRINTD (DBG_TX, "last vc hack: miss");
1704 // Are we currently transmitting this VC on one of the channels?
1705 for (tx_channel = 0; tx_channel < TX_CHANS; ++tx_channel)
1706 if (dev->tx_channel_record[tx_channel] == channel) {
1707 PRINTD (DBG_TX, "vc already on channel: hit");
1710 if (tx_channel == TX_CHANS) {
1711 PRINTD (DBG_TX, "vc already on channel: miss");
1712 // Find and set up an idle channel.
1713 tx_channel = setup_idle_tx_channel (dev, vcc);
1714 if (tx_channel < 0) {
1715 PRINTD (DBG_TX|DBG_ERR, "failed to get channel");
1721 PRINTD (DBG_TX, "got channel");
1722 SELECT_TX_CHANNEL(dev, tx_channel);
1724 dev->last_vc = channel;
1725 dev->tx_last = tx_channel;
1728 PRINTD (DBG_TX, "using channel %u", tx_channel);
1730 YELLOW_LED_OFF(dev);
1732 // TX start transfer
1735 unsigned int tx_len = skb->len;
1736 unsigned int tx_iovcnt = skb_shinfo(skb)->nr_frags;
1737 // remember this so we can free it later
1741 // scatter gather transfer
1742 dev->tx_regions = tx_iovcnt;
1743 dev->tx_iovec = NULL; /* @@@ needs rewritten */
1745 PRINTD (DBG_TX|DBG_BUS, "TX start scatter-gather transfer (iovec %p, len %d)",
1748 hrz_kfree_skb (skb);
1752 dev->tx_regions = 0;
1753 dev->tx_iovec = NULL;
1754 dev->tx_bytes = tx_len;
1755 dev->tx_addr = skb->data;
1756 PRINTD (DBG_TX|DBG_BUS, "TX start simple transfer (addr %p, len %d)",
1760 // and do the business
1761 tx_schedule (dev, 0);
1768 /********** reset a card **********/
1770 static void hrz_reset (const hrz_dev * dev) {
1771 u32 control_0_reg = rd_regl (dev, CONTROL_0_REG);
1773 // why not set RESET_HORIZON to one and wait for the card to
1774 // reassert that bit as zero? Like so:
1775 control_0_reg = control_0_reg & RESET_HORIZON;
1776 wr_regl (dev, CONTROL_0_REG, control_0_reg);
1777 while (control_0_reg & RESET_HORIZON)
1778 control_0_reg = rd_regl (dev, CONTROL_0_REG);
1780 // old reset code retained:
1781 wr_regl (dev, CONTROL_0_REG, control_0_reg |
1782 RESET_ATM | RESET_RX | RESET_TX | RESET_HOST);
1783 // just guessing here
1786 wr_regl (dev, CONTROL_0_REG, control_0_reg);
1789 /********** read the burnt in address **********/
1791 static inline void WRITE_IT_WAIT (const hrz_dev *dev, u32 ctrl)
1793 wr_regl (dev, CONTROL_0_REG, ctrl);
1797 static inline void CLOCK_IT (const hrz_dev *dev, u32 ctrl)
1799 // DI must be valid around rising SK edge
1800 WRITE_IT_WAIT(dev, ctrl & ~SEEPROM_SK);
1801 WRITE_IT_WAIT(dev, ctrl | SEEPROM_SK);
1804 static u16 __init read_bia (const hrz_dev * dev, u16 addr)
1806 u32 ctrl = rd_regl (dev, CONTROL_0_REG);
1808 const unsigned int addr_bits = 6;
1809 const unsigned int data_bits = 16;
1815 ctrl &= ~(SEEPROM_CS | SEEPROM_SK | SEEPROM_DI);
1816 WRITE_IT_WAIT(dev, ctrl);
1818 // wake Serial EEPROM and send 110 (READ) command
1819 ctrl |= (SEEPROM_CS | SEEPROM_DI);
1820 CLOCK_IT(dev, ctrl);
1823 CLOCK_IT(dev, ctrl);
1825 ctrl &= ~SEEPROM_DI;
1826 CLOCK_IT(dev, ctrl);
1828 for (i=0; i<addr_bits; i++) {
1829 if (addr & (1 << (addr_bits-1)))
1832 ctrl &= ~SEEPROM_DI;
1834 CLOCK_IT(dev, ctrl);
1839 // we could check that we have DO = 0 here
1840 ctrl &= ~SEEPROM_DI;
1843 for (i=0;i<data_bits;i++) {
1846 CLOCK_IT(dev, ctrl);
1848 if (rd_regl (dev, CONTROL_0_REG) & SEEPROM_DO)
1849 res |= (1 << (data_bits-1));
1852 ctrl &= ~(SEEPROM_SK | SEEPROM_CS);
1853 WRITE_IT_WAIT(dev, ctrl);
1858 /********** initialise a card **********/
1860 static int __init hrz_init (hrz_dev * dev) {
1874 ctrl = rd_regl (dev, CONTROL_0_REG);
1875 PRINTD (DBG_INFO, "ctrl0reg is %#x", ctrl);
1876 onefivefive = ctrl & ATM_LAYER_STATUS;
1879 printk (DEV_LABEL ": Horizon Ultra (at 155.52 MBps)");
1881 printk (DEV_LABEL ": Horizon (at 25 MBps)");
1884 // Reset the card to get everything in a known state
1889 // Clear all the buffer memory
1891 printk (" clearing memory");
1893 for (mem = (HDW *) memmap; mem < (HDW *) (memmap + 1); ++mem)
1894 wr_mem (dev, mem, 0);
1896 printk (" tx channels");
1898 // All transmit eight channels are set up as AAL5 ABR channels with
1899 // a 16us cell spacing. Why?
1901 // Channel 0 gets the free buffer at 100h, channel 1 gets the free
1902 // buffer at 110h etc.
1904 for (chan = 0; chan < TX_CHANS; ++chan) {
1905 tx_ch_desc * tx_desc = &memmap->tx_descs[chan];
1906 cell_buf * buf = &memmap->inittxbufs[chan];
1908 // initialise the read and write buffer pointers
1909 wr_mem (dev, &tx_desc->rd_buf_type, BUF_PTR(buf));
1910 wr_mem (dev, &tx_desc->wr_buf_type, BUF_PTR(buf));
1912 // set the status of the initial buffers to empty
1913 wr_mem (dev, &buf->next, BUFF_STATUS_EMPTY);
1916 // Use space bufn3 at the moment for tx buffers
1918 printk (" tx buffers");
1920 tx_desc = memmap->bufn3;
1922 wr_mem (dev, &memmap->txfreebufstart.next, BUF_PTR(tx_desc) | BUFF_STATUS_EMPTY);
1924 for (buff_count = 0; buff_count < BUFN3_SIZE-1; buff_count++) {
1925 wr_mem (dev, &tx_desc->next, BUF_PTR(tx_desc+1) | BUFF_STATUS_EMPTY);
1929 wr_mem (dev, &tx_desc->next, BUF_PTR(&memmap->txfreebufend) | BUFF_STATUS_EMPTY);
1931 // Initialise the transmit free buffer count
1932 wr_regw (dev, TX_FREE_BUFFER_COUNT_OFF, BUFN3_SIZE);
1934 printk (" rx channels");
1936 // Initialise all of the receive channels to be AAL5 disabled with
1937 // an interrupt threshold of 0
1939 for (chan = 0; chan < RX_CHANS; ++chan) {
1940 rx_ch_desc * rx_desc = &memmap->rx_descs[chan];
1942 wr_mem (dev, &rx_desc->wr_buf_type, CHANNEL_TYPE_AAL5 | RX_CHANNEL_DISABLED);
1945 printk (" rx buffers");
1947 // Use space bufn4 at the moment for rx buffers
1949 rx_desc = memmap->bufn4;
1951 wr_mem (dev, &memmap->rxfreebufstart.next, BUF_PTR(rx_desc) | BUFF_STATUS_EMPTY);
1953 for (buff_count = 0; buff_count < BUFN4_SIZE-1; buff_count++) {
1954 wr_mem (dev, &rx_desc->next, BUF_PTR(rx_desc+1) | BUFF_STATUS_EMPTY);
1959 wr_mem (dev, &rx_desc->next, BUF_PTR(&memmap->rxfreebufend) | BUFF_STATUS_EMPTY);
1961 // Initialise the receive free buffer count
1962 wr_regw (dev, RX_FREE_BUFFER_COUNT_OFF, BUFN4_SIZE);
1964 // Initialize Horizons registers
1967 wr_regw (dev, TX_CONFIG_OFF,
1968 ABR_ROUND_ROBIN | TX_NORMAL_OPERATION | DRVR_DRVRBAR_ENABLE);
1970 // RX config. Use 10-x VC bits, x VP bits, non user cells in channel 0.
1971 wr_regw (dev, RX_CONFIG_OFF,
1972 DISCARD_UNUSED_VPI_VCI_BITS_SET | NON_USER_CELLS_IN_ONE_CHANNEL | vpi_bits);
1975 wr_regw (dev, RX_LINE_CONFIG_OFF,
1976 LOCK_DETECT_ENABLE | FREQUENCY_DETECT_ENABLE | GXTALOUT_SELECT_DIV4);
1978 // Set the max AAL5 cell count to be just enough to contain the
1979 // largest AAL5 frame that the user wants to receive
1980 wr_regw (dev, MAX_AAL5_CELL_COUNT_OFF,
1981 (max_rx_size + ATM_AAL5_TRAILER + ATM_CELL_PAYLOAD - 1) / ATM_CELL_PAYLOAD);
1984 wr_regw (dev, RX_CONFIG_OFF, rd_regw (dev, RX_CONFIG_OFF) | RX_ENABLE);
1986 printk (" control");
1988 // Drive the OE of the LEDs then turn the green LED on
1989 ctrl |= GREEN_LED_OE | YELLOW_LED_OE | GREEN_LED | YELLOW_LED;
1990 wr_regl (dev, CONTROL_0_REG, ctrl);
1992 // Test for a 155-capable card
1995 // Select 155 mode... make this a choice (or: how do we detect
1996 // external line speed and switch?)
1997 ctrl |= ATM_LAYER_SELECT;
1998 wr_regl (dev, CONTROL_0_REG, ctrl);
2000 // test SUNI-lite vs SAMBA
2002 // Register 0x00 in the SUNI will have some of bits 3-7 set, and
2003 // they will always be zero for the SAMBA. Ha! Bloody hardware
2004 // engineers. It'll never work.
2006 if (rd_framer (dev, 0) & 0x00f0) {
2010 // Reset, just in case
2011 wr_framer (dev, 0x00, 0x0080);
2012 wr_framer (dev, 0x00, 0x0000);
2014 // Configure transmit FIFO
2015 wr_framer (dev, 0x63, rd_framer (dev, 0x63) | 0x0002);
2017 // Set line timed mode
2018 wr_framer (dev, 0x05, rd_framer (dev, 0x05) | 0x0001);
2023 // Reset, just in case
2024 wr_framer (dev, 0, rd_framer (dev, 0) | 0x0001);
2025 wr_framer (dev, 0, rd_framer (dev, 0) &~ 0x0001);
2027 // Turn off diagnostic loopback and enable line-timed mode
2028 wr_framer (dev, 0, 0x0002);
2030 // Turn on transmit outputs
2031 wr_framer (dev, 2, 0x0B80);
2035 ctrl &= ~ATM_LAYER_SELECT;
2051 u8 * esi = dev->atm_dev->esi;
2053 // in the card I have, EEPROM
2054 // addresses 0, 1, 2 contain 0
2055 // addresess 5, 6 etc. contain ffff
2056 // NB: Madge prefix is 00 00 f6 (which is 00 00 6f in Ethernet bit order)
2057 // the read_bia routine gets the BIA in Ethernet bit order
2059 for (i=0; i < ESI_LEN; ++i) {
2061 b = read_bia (dev, i/2 + 2);
2065 printk ("%02x", esi[i]);
2069 // Enable RX_Q and ?X_COMPLETE interrupts only
2070 wr_regl (dev, INT_ENABLE_REG_OFF, INTERESTING_INTERRUPTS);
2078 /********** check max_sdu **********/
2080 static int check_max_sdu (hrz_aal aal, struct atm_trafprm * tp, unsigned int max_frame_size) {
2081 PRINTD (DBG_FLOW|DBG_QOS, "check_max_sdu");
2085 if (!(tp->max_sdu)) {
2086 PRINTD (DBG_QOS, "defaulting max_sdu");
2087 tp->max_sdu = ATM_AAL0_SDU;
2088 } else if (tp->max_sdu != ATM_AAL0_SDU) {
2089 PRINTD (DBG_QOS|DBG_ERR, "rejecting max_sdu");
2094 if (tp->max_sdu == 0 || tp->max_sdu > ATM_MAX_AAL34_PDU) {
2095 PRINTD (DBG_QOS, "%sing max_sdu", tp->max_sdu ? "capp" : "default");
2096 tp->max_sdu = ATM_MAX_AAL34_PDU;
2100 if (tp->max_sdu == 0 || tp->max_sdu > max_frame_size) {
2101 PRINTD (DBG_QOS, "%sing max_sdu", tp->max_sdu ? "capp" : "default");
2102 tp->max_sdu = max_frame_size;
2109 /********** check pcr **********/
2111 // something like this should be part of ATM Linux
2112 static int atm_pcr_check (struct atm_trafprm * tp, unsigned int pcr) {
2113 // we are assuming non-UBR, and non-special values of pcr
2114 if (tp->min_pcr == ATM_MAX_PCR)
2115 PRINTD (DBG_QOS, "luser gave min_pcr = ATM_MAX_PCR");
2116 else if (tp->min_pcr < 0)
2117 PRINTD (DBG_QOS, "luser gave negative min_pcr");
2118 else if (tp->min_pcr && tp->min_pcr > pcr)
2119 PRINTD (DBG_QOS, "pcr less than min_pcr");
2121 // !! max_pcr = UNSPEC (0) is equivalent to max_pcr = MAX (-1)
2122 // easier to #define ATM_MAX_PCR 0 and have all rates unsigned?
2123 // [this would get rid of next two conditionals]
2124 if ((0) && tp->max_pcr == ATM_MAX_PCR)
2125 PRINTD (DBG_QOS, "luser gave max_pcr = ATM_MAX_PCR");
2126 else if ((tp->max_pcr != ATM_MAX_PCR) && tp->max_pcr < 0)
2127 PRINTD (DBG_QOS, "luser gave negative max_pcr");
2128 else if (tp->max_pcr && tp->max_pcr != ATM_MAX_PCR && tp->max_pcr < pcr)
2129 PRINTD (DBG_QOS, "pcr greater than max_pcr");
2131 // each limit unspecified or not violated
2132 PRINTD (DBG_QOS, "xBR(pcr) OK");
2135 PRINTD (DBG_QOS, "pcr=%u, tp: min_pcr=%d, pcr=%d, max_pcr=%d",
2136 pcr, tp->min_pcr, tp->pcr, tp->max_pcr);
2140 /********** open VC **********/
2142 static int hrz_open (struct atm_vcc *atm_vcc)
2147 struct atm_qos * qos;
2148 struct atm_trafprm * txtp;
2149 struct atm_trafprm * rxtp;
2151 hrz_dev * dev = HRZ_DEV(atm_vcc->dev);
2153 hrz_vcc * vccp; // allocated late
2154 short vpi = atm_vcc->vpi;
2155 int vci = atm_vcc->vci;
2156 PRINTD (DBG_FLOW|DBG_VCC, "hrz_open %x %x", vpi, vci);
2158 #ifdef ATM_VPI_UNSPEC
2159 // UNSPEC is deprecated, remove this code eventually
2160 if (vpi == ATM_VPI_UNSPEC || vci == ATM_VCI_UNSPEC) {
2161 PRINTK (KERN_WARNING, "rejecting open with unspecified VPI/VCI (deprecated)");
2166 error = vpivci_to_channel (&channel, vpi, vci);
2168 PRINTD (DBG_WARN|DBG_VCC, "VPI/VCI out of range: %hd/%d", vpi, vci);
2172 vcc.channel = channel;
2173 // max speed for the moment
2176 qos = &atm_vcc->qos;
2178 // check AAL and remember it
2181 // we would if it were 48 bytes and not 52!
2182 PRINTD (DBG_QOS|DBG_VCC, "AAL0");
2186 // we would if I knew how do the SAR!
2187 PRINTD (DBG_QOS|DBG_VCC, "AAL3/4");
2191 PRINTD (DBG_QOS|DBG_VCC, "AAL5");
2195 PRINTD (DBG_QOS|DBG_VCC, "Bad AAL!");
2200 // TX traffic parameters
2202 // there are two, interrelated problems here: 1. the reservation of
2203 // PCR is not a binary choice, we are given bounds and/or a
2204 // desirable value; 2. the device is only capable of certain values,
2205 // most of which are not integers. It is almost certainly acceptable
2206 // to be off by a maximum of 1 to 10 cps.
2208 // Pragmatic choice: always store an integral PCR as that which has
2209 // been allocated, even if we allocate a little (or a lot) less,
2210 // after rounding. The actual allocation depends on what we can
2211 // manage with our rate selection algorithm. The rate selection
2212 // algorithm is given an integral PCR and a tolerance and told
2213 // whether it should round the value up or down if the tolerance is
2214 // exceeded; it returns: a) the actual rate selected (rounded up to
2215 // the nearest integer), b) a bit pattern to feed to the timer
2216 // register, and c) a failure value if no applicable rate exists.
2218 // Part of the job is done by atm_pcr_goal which gives us a PCR
2219 // specification which says: EITHER grab the maximum available PCR
2220 // (and perhaps a lower bound which we musn't pass), OR grab this
2221 // amount, rounding down if you have to (and perhaps a lower bound
2222 // which we musn't pass) OR grab this amount, rounding up if you
2223 // have to (and perhaps an upper bound which we musn't pass). If any
2224 // bounds ARE passed we fail. Note that rounding is only rounding to
2225 // match device limitations, we do not round down to satisfy
2226 // bandwidth availability even if this would not violate any given
2229 // Note: telephony = 64kb/s = 48 byte cell payload @ 500/3 cells/s
2230 // (say) so this is not even a binary fixpoint cell rate (but this
2231 // device can do it). To avoid this sort of hassle we use a
2232 // tolerance parameter (currently fixed at 10 cps).
2234 PRINTD (DBG_QOS, "TX:");
2238 // set up defaults for no traffic
2240 // who knows what would actually happen if you try and send on this?
2241 vcc.tx_xbr_bits = IDLE_RATE_TYPE;
2242 vcc.tx_pcr_bits = CLOCK_DISABLE;
2244 vcc.tx_scr_bits = CLOCK_DISABLE;
2245 vcc.tx_bucket_bits = 0;
2248 if (txtp->traffic_class != ATM_NONE) {
2249 error = check_max_sdu (vcc.aal, txtp, max_tx_size);
2251 PRINTD (DBG_QOS, "TX max_sdu check failed");
2255 switch (txtp->traffic_class) {
2257 // we take "the PCR" as a rate-cap
2260 make_rate (dev, 1<<30, round_nearest, &vcc.tx_pcr_bits, NULL);
2261 vcc.tx_xbr_bits = ABR_RATE_TYPE;
2266 // reserve min, allow up to max
2267 vcc.tx_rate = 0; // ?
2268 make_rate (dev, 1<<30, round_nearest, &vcc.tx_pcr_bits, 0);
2269 vcc.tx_xbr_bits = ABR_RATE_TYPE;
2274 int pcr = atm_pcr_goal (txtp);
2277 // down vs. up, remaining bandwidth vs. unlimited bandwidth!!
2278 // should really have: once someone gets unlimited bandwidth
2279 // that no more non-UBR channels can be opened until the
2280 // unlimited one closes?? For the moment, round_down means
2281 // greedy people actually get something and not nothing
2283 // slight race (no locking) here so we may get -EAGAIN
2284 // later; the greedy bastards would deserve it :)
2285 PRINTD (DBG_QOS, "snatching all remaining TX bandwidth");
2286 pcr = dev->tx_avail;
2287 } else if (pcr < 0) {
2293 error = make_rate_with_tolerance (dev, pcr, r, 10,
2294 &vcc.tx_pcr_bits, &vcc.tx_rate);
2296 PRINTD (DBG_QOS, "could not make rate from TX PCR");
2299 // not really clear what further checking is needed
2300 error = atm_pcr_check (txtp, vcc.tx_rate);
2302 PRINTD (DBG_QOS, "TX PCR failed consistency check");
2305 vcc.tx_xbr_bits = CBR_RATE_TYPE;
2310 int pcr = atm_pcr_goal (txtp);
2311 // int scr = atm_scr_goal (txtp);
2312 int scr = pcr/2; // just for fun
2313 unsigned int mbs = 60; // just for fun
2316 unsigned int bucket;
2320 } else if (pcr < 0) {
2326 error = make_rate_with_tolerance (dev, pcr, pr, 10,
2327 &vcc.tx_pcr_bits, 0);
2329 // see comments for PCR with CBR above
2331 // slight race (no locking) here so we may get -EAGAIN
2332 // later; the greedy bastards would deserve it :)
2333 PRINTD (DBG_QOS, "snatching all remaining TX bandwidth");
2334 scr = dev->tx_avail;
2335 } else if (scr < 0) {
2341 error = make_rate_with_tolerance (dev, scr, sr, 10,
2342 &vcc.tx_scr_bits, &vcc.tx_rate);
2344 PRINTD (DBG_QOS, "could not make rate from TX SCR");
2347 // not really clear what further checking is needed
2348 // error = atm_scr_check (txtp, vcc.tx_rate);
2350 PRINTD (DBG_QOS, "TX SCR failed consistency check");
2353 // bucket calculations (from a piece of paper...) cell bucket
2354 // capacity must be largest integer smaller than m(p-s)/p + 1
2355 // where m = max burst size, p = pcr, s = scr
2356 bucket = mbs*(pcr-scr)/pcr;
2357 if (bucket*pcr != mbs*(pcr-scr))
2359 if (bucket > BUCKET_MAX_SIZE) {
2360 PRINTD (DBG_QOS, "shrinking bucket from %u to %u",
2361 bucket, BUCKET_MAX_SIZE);
2362 bucket = BUCKET_MAX_SIZE;
2364 vcc.tx_xbr_bits = VBR_RATE_TYPE;
2365 vcc.tx_bucket_bits = bucket;
2370 PRINTD (DBG_QOS, "unsupported TX traffic class");
2377 // RX traffic parameters
2379 PRINTD (DBG_QOS, "RX:");
2383 // set up defaults for no traffic
2386 if (rxtp->traffic_class != ATM_NONE) {
2387 error = check_max_sdu (vcc.aal, rxtp, max_rx_size);
2389 PRINTD (DBG_QOS, "RX max_sdu check failed");
2392 switch (rxtp->traffic_class) {
2400 vcc.rx_rate = 0; // ?
2405 int pcr = atm_pcr_goal (rxtp);
2407 // slight race (no locking) here so we may get -EAGAIN
2408 // later; the greedy bastards would deserve it :)
2409 PRINTD (DBG_QOS, "snatching all remaining RX bandwidth");
2410 pcr = dev->rx_avail;
2411 } else if (pcr < 0) {
2415 // not really clear what further checking is needed
2416 error = atm_pcr_check (rxtp, vcc.rx_rate);
2418 PRINTD (DBG_QOS, "RX PCR failed consistency check");
2425 // int scr = atm_scr_goal (rxtp);
2426 int scr = 1<<16; // just for fun
2428 // slight race (no locking) here so we may get -EAGAIN
2429 // later; the greedy bastards would deserve it :)
2430 PRINTD (DBG_QOS, "snatching all remaining RX bandwidth");
2431 scr = dev->rx_avail;
2432 } else if (scr < 0) {
2436 // not really clear what further checking is needed
2437 // error = atm_scr_check (rxtp, vcc.rx_rate);
2439 PRINTD (DBG_QOS, "RX SCR failed consistency check");
2446 PRINTD (DBG_QOS, "unsupported RX traffic class");
2454 // late abort useful for diagnostics
2455 if (vcc.aal != aal5) {
2456 PRINTD (DBG_QOS, "AAL not supported");
2460 // get space for our vcc stuff and copy parameters into it
2461 vccp = kmalloc (sizeof(hrz_vcc), GFP_KERNEL);
2463 PRINTK (KERN_ERR, "out of memory!");
2468 // clear error and grab cell rate resource lock
2470 spin_lock (&dev->rate_lock);
2472 if (vcc.tx_rate > dev->tx_avail) {
2473 PRINTD (DBG_QOS, "not enough TX PCR left");
2477 if (vcc.rx_rate > dev->rx_avail) {
2478 PRINTD (DBG_QOS, "not enough RX PCR left");
2483 // really consume cell rates
2484 dev->tx_avail -= vcc.tx_rate;
2485 dev->rx_avail -= vcc.rx_rate;
2486 PRINTD (DBG_QOS|DBG_VCC, "reserving %u TX PCR and %u RX PCR",
2487 vcc.tx_rate, vcc.rx_rate);
2490 // release lock and exit on error
2491 spin_unlock (&dev->rate_lock);
2493 PRINTD (DBG_QOS|DBG_VCC, "insufficient cell rate resources");
2498 // this is "immediately before allocating the connection identifier
2499 // in hardware" - so long as the next call does not fail :)
2500 set_bit(ATM_VF_ADDR,&atm_vcc->flags);
2502 // any errors here are very serious and should never occur
2504 if (rxtp->traffic_class != ATM_NONE) {
2505 if (dev->rxer[channel]) {
2506 PRINTD (DBG_ERR|DBG_VCC, "VC already open for RX");
2510 error = hrz_open_rx (dev, channel);
2515 // this link allows RX frames through
2516 dev->rxer[channel] = atm_vcc;
2519 // success, set elements of atm_vcc
2520 atm_vcc->dev_data = (void *) vccp;
2522 // indicate readiness
2523 set_bit(ATM_VF_READY,&atm_vcc->flags);
2528 /********** close VC **********/
2530 static void hrz_close (struct atm_vcc * atm_vcc) {
2531 hrz_dev * dev = HRZ_DEV(atm_vcc->dev);
2532 hrz_vcc * vcc = HRZ_VCC(atm_vcc);
2533 u16 channel = vcc->channel;
2534 PRINTD (DBG_VCC|DBG_FLOW, "hrz_close");
2536 // indicate unreadiness
2537 clear_bit(ATM_VF_READY,&atm_vcc->flags);
2539 if (atm_vcc->qos.txtp.traffic_class != ATM_NONE) {
2542 // let any TX on this channel that has started complete
2543 // no restart, just keep trying
2544 while (tx_hold (dev))
2546 // remove record of any tx_channel having been setup for this channel
2547 for (i = 0; i < TX_CHANS; ++i)
2548 if (dev->tx_channel_record[i] == channel) {
2549 dev->tx_channel_record[i] = -1;
2552 if (dev->last_vc == channel)
2557 if (atm_vcc->qos.rxtp.traffic_class != ATM_NONE) {
2558 // disable RXing - it tries quite hard
2559 hrz_close_rx (dev, channel);
2560 // forget the vcc - no more skbs will be pushed
2561 if (atm_vcc != dev->rxer[channel])
2562 PRINTK (KERN_ERR, "%s atm_vcc=%p rxer[channel]=%p",
2563 "arghhh! we're going to die!",
2564 atm_vcc, dev->rxer[channel]);
2565 dev->rxer[channel] = NULL;
2568 // atomically release our rate reservation
2569 spin_lock (&dev->rate_lock);
2570 PRINTD (DBG_QOS|DBG_VCC, "releasing %u TX PCR and %u RX PCR",
2571 vcc->tx_rate, vcc->rx_rate);
2572 dev->tx_avail += vcc->tx_rate;
2573 dev->rx_avail += vcc->rx_rate;
2574 spin_unlock (&dev->rate_lock);
2576 // free our structure
2578 // say the VPI/VCI is free again
2579 clear_bit(ATM_VF_ADDR,&atm_vcc->flags);
2583 static int hrz_getsockopt (struct atm_vcc * atm_vcc, int level, int optname,
2584 void *optval, int optlen) {
2585 hrz_dev * dev = HRZ_DEV(atm_vcc->dev);
2586 PRINTD (DBG_FLOW|DBG_VCC, "hrz_getsockopt");
2595 return -ENOPROTOOPT;
2603 static int hrz_setsockopt (struct atm_vcc * atm_vcc, int level, int optname,
2604 void *optval, int optlen) {
2605 hrz_dev * dev = HRZ_DEV(atm_vcc->dev);
2606 PRINTD (DBG_FLOW|DBG_VCC, "hrz_setsockopt");
2615 return -ENOPROTOOPT;
2625 static int hrz_ioctl (struct atm_dev * atm_dev, unsigned int cmd, void *arg) {
2626 hrz_dev * dev = HRZ_DEV(atm_dev);
2627 PRINTD (DBG_FLOW, "hrz_ioctl");
2631 unsigned char hrz_phy_get (struct atm_dev * atm_dev, unsigned long addr) {
2632 hrz_dev * dev = HRZ_DEV(atm_dev);
2633 PRINTD (DBG_FLOW, "hrz_phy_get");
2637 static void hrz_phy_put (struct atm_dev * atm_dev, unsigned char value,
2638 unsigned long addr) {
2639 hrz_dev * dev = HRZ_DEV(atm_dev);
2640 PRINTD (DBG_FLOW, "hrz_phy_put");
2643 static int hrz_change_qos (struct atm_vcc * atm_vcc, struct atm_qos *qos, int flgs) {
2644 hrz_dev * dev = HRZ_DEV(vcc->dev);
2645 PRINTD (DBG_FLOW, "hrz_change_qos");
2650 /********** proc file contents **********/
2652 static int hrz_proc_read (struct atm_dev * atm_dev, loff_t * pos, char * page) {
2653 hrz_dev * dev = HRZ_DEV(atm_dev);
2655 PRINTD (DBG_FLOW, "hrz_proc_read");
2657 /* more diagnostics here? */
2661 unsigned int count = sprintf (page, "vbr buckets:");
2663 for (i = 0; i < TX_CHANS; ++i)
2664 count += sprintf (page, " %u/%u",
2665 query_tx_channel_config (dev, i, BUCKET_FULLNESS_ACCESS),
2666 query_tx_channel_config (dev, i, BUCKET_CAPACITY_ACCESS));
2667 count += sprintf (page+count, ".\n");
2673 return sprintf (page,
2674 "cells: TX %lu, RX %lu, HEC errors %lu, unassigned %lu.\n",
2675 dev->tx_cell_count, dev->rx_cell_count,
2676 dev->hec_error_count, dev->unassigned_cell_count);
2679 return sprintf (page,
2680 "free cell buffers: TX %hu, RX %hu+%hu.\n",
2681 rd_regw (dev, TX_FREE_BUFFER_COUNT_OFF),
2682 rd_regw (dev, RX_FREE_BUFFER_COUNT_OFF),
2683 dev->noof_spare_buffers);
2686 return sprintf (page,
2687 "cps remaining: TX %u, RX %u\n",
2688 dev->tx_avail, dev->rx_avail);
2693 static const struct atmdev_ops hrz_ops = {
2697 .proc_read = hrz_proc_read,
2698 .owner = THIS_MODULE,
2701 static int __devinit hrz_probe(struct pci_dev *pci_dev, const struct pci_device_id *pci_ent)
2706 // adapter slot free, read resources from PCI configuration space
2707 u32 iobase = pci_resource_start (pci_dev, 0);
2708 u32 * membase = bus_to_virt (pci_resource_start (pci_dev, 1));
2709 u8 irq = pci_dev->irq;
2712 PRINTD (DBG_FLOW, "hrz_probe");
2714 /* XXX DEV_LABEL is a guess */
2715 if (!request_region(iobase, HRZ_IO_EXTENT, DEV_LABEL))
2718 if (pci_enable_device(pci_dev)) {
2723 dev = kmalloc(sizeof(hrz_dev), GFP_KERNEL);
2725 // perhaps we should be nice: deregister all adapters and abort?
2726 PRINTD(DBG_ERR, "out of memory");
2731 memset(dev, 0, sizeof(hrz_dev));
2733 pci_set_drvdata(pci_dev, dev);
2735 // grab IRQ and install handler - move this someplace more sensible
2736 if (request_irq(irq,
2738 SA_SHIRQ, /* irqflags guess */
2739 DEV_LABEL, /* name guess */
2741 PRINTD(DBG_WARN, "request IRQ failed!");
2746 PRINTD(DBG_INFO, "found Madge ATM adapter (hrz) at: IO %x, IRQ %u, MEM %p",
2747 iobase, irq, membase);
2749 dev->atm_dev = atm_dev_register(DEV_LABEL, &hrz_ops, -1, NULL);
2750 if (!(dev->atm_dev)) {
2751 PRINTD(DBG_ERR, "failed to register Madge ATM adapter");
2756 PRINTD(DBG_INFO, "registered Madge ATM adapter (no. %d) (%p) at %p",
2757 dev->atm_dev->number, dev, dev->atm_dev);
2758 dev->atm_dev->dev_data = (void *) dev;
2759 dev->pci_dev = pci_dev;
2761 // enable bus master accesses
2762 pci_set_master(pci_dev);
2764 // frobnicate latency (upwards, usually)
2765 pci_read_config_byte(pci_dev, PCI_LATENCY_TIMER, &lat);
2767 PRINTD(DBG_INFO, "%s PCI latency timer from %hu to %hu",
2768 "changing", lat, pci_lat);
2769 pci_write_config_byte(pci_dev, PCI_LATENCY_TIMER, pci_lat);
2770 } else if (lat < MIN_PCI_LATENCY) {
2771 PRINTK(KERN_INFO, "%s PCI latency timer from %hu to %hu",
2772 "increasing", lat, MIN_PCI_LATENCY);
2773 pci_write_config_byte(pci_dev, PCI_LATENCY_TIMER, MIN_PCI_LATENCY);
2776 dev->iobase = iobase;
2778 dev->membase = membase;
2780 dev->rx_q_entry = dev->rx_q_reset = &memmap->rx_q_entries[0];
2781 dev->rx_q_wrap = &memmap->rx_q_entries[RX_CHANS-1];
2783 // these next three are performance hacks
2788 dev->tx_regions = 0;
2791 dev->tx_iovec = NULL;
2793 dev->tx_cell_count = 0;
2794 dev->rx_cell_count = 0;
2795 dev->hec_error_count = 0;
2796 dev->unassigned_cell_count = 0;
2798 dev->noof_spare_buffers = 0;
2802 for (i = 0; i < TX_CHANS; ++i)
2803 dev->tx_channel_record[i] = -1;
2808 // Allocate cell rates and remember ASIC version
2809 // Fibre: ATM_OC3_PCR = 1555200000/8/270*260/53 - 29/53
2810 // Copper: (WRONG) we want 6 into the above, close to 25Mb/s
2811 // Copper: (plagarise!) 25600000/8/270*260/53 - n/53
2813 if (hrz_init(dev)) {
2814 // to be really pedantic, this should be ATM_OC3c_PCR
2815 dev->tx_avail = ATM_OC3_PCR;
2816 dev->rx_avail = ATM_OC3_PCR;
2817 set_bit(ultra, &dev->flags); // NOT "|= ultra" !
2819 dev->tx_avail = ((25600000/8)*26)/(27*53);
2820 dev->rx_avail = ((25600000/8)*26)/(27*53);
2821 PRINTD(DBG_WARN, "Buggy ASIC: no TX bus-mastering.");
2824 // rate changes spinlock
2825 spin_lock_init(&dev->rate_lock);
2827 // on-board memory access spinlock; we want atomic reads and
2828 // writes to adapter memory (handles IRQ and SMP)
2829 spin_lock_init(&dev->mem_lock);
2831 init_waitqueue_head(&dev->tx_queue);
2833 // vpi in 0..4, vci in 6..10
2834 dev->atm_dev->ci_range.vpi_bits = vpi_bits;
2835 dev->atm_dev->ci_range.vci_bits = 10-vpi_bits;
2837 init_timer(&dev->housekeeping);
2838 dev->housekeeping.function = do_housekeeping;
2839 dev->housekeeping.data = (unsigned long) dev;
2840 mod_timer(&dev->housekeeping, jiffies);
2846 free_irq(dev->irq, dev);
2850 pci_disable_device(pci_dev);
2852 release_region(iobase, HRZ_IO_EXTENT);
2856 static void __devexit hrz_remove_one(struct pci_dev *pci_dev)
2860 dev = pci_get_drvdata(pci_dev);
2862 PRINTD(DBG_INFO, "closing %p (atm_dev = %p)", dev, dev->atm_dev);
2863 del_timer_sync(&dev->housekeeping);
2865 atm_dev_deregister(dev->atm_dev);
2866 free_irq(dev->irq, dev);
2867 release_region(dev->iobase, HRZ_IO_EXTENT);
2870 pci_disable_device(pci_dev);
2873 static void __init hrz_check_args (void) {
2874 #ifdef DEBUG_HORIZON
2875 PRINTK (KERN_NOTICE, "debug bitmap is %hx", debug &= DBG_MASK);
2878 PRINTK (KERN_NOTICE, "no debug support in this image");
2881 if (vpi_bits > HRZ_MAX_VPI)
2882 PRINTK (KERN_ERR, "vpi_bits has been limited to %hu",
2883 vpi_bits = HRZ_MAX_VPI);
2885 if (max_tx_size < 0 || max_tx_size > TX_AAL5_LIMIT)
2886 PRINTK (KERN_NOTICE, "max_tx_size has been limited to %hu",
2887 max_tx_size = TX_AAL5_LIMIT);
2889 if (max_rx_size < 0 || max_rx_size > RX_AAL5_LIMIT)
2890 PRINTK (KERN_NOTICE, "max_rx_size has been limited to %hu",
2891 max_rx_size = RX_AAL5_LIMIT);
2896 MODULE_AUTHOR(maintainer_string);
2897 MODULE_DESCRIPTION(description_string);
2898 MODULE_LICENSE("GPL");
2899 module_param(debug, ushort, 0644);
2900 module_param(vpi_bits, ushort, 0);
2901 module_param(max_tx_size, int, 0);
2902 module_param(max_rx_size, int, 0);
2903 module_param(pci_lat, byte, 0);
2904 MODULE_PARM_DESC(debug, "debug bitmap, see .h file");
2905 MODULE_PARM_DESC(vpi_bits, "number of bits (0..4) to allocate to VPIs");
2906 MODULE_PARM_DESC(max_tx_size, "maximum size of TX AAL5 frames");
2907 MODULE_PARM_DESC(max_rx_size, "maximum size of RX AAL5 frames");
2908 MODULE_PARM_DESC(pci_lat, "PCI latency in bus cycles");
2910 static struct pci_device_id hrz_pci_tbl[] = {
2911 { PCI_VENDOR_ID_MADGE, PCI_DEVICE_ID_MADGE_HORIZON, PCI_ANY_ID, PCI_ANY_ID,
2916 MODULE_DEVICE_TABLE(pci, hrz_pci_tbl);
2918 static struct pci_driver hrz_driver = {
2921 .remove = __devexit_p(hrz_remove_one),
2922 .id_table = hrz_pci_tbl,
2925 /********** module entry **********/
2927 static int __init hrz_module_init (void) {
2928 // sanity check - cast is needed since printk does not support %Zu
2929 if (sizeof(struct MEMMAP) != 128*1024/4) {
2930 PRINTK (KERN_ERR, "Fix struct MEMMAP (is %lu fakewords).",
2931 (unsigned long) sizeof(struct MEMMAP));
2941 return pci_module_init(&hrz_driver);
2944 /********** module exit **********/
2946 static void __exit hrz_module_exit (void) {
2947 PRINTD (DBG_FLOW, "cleanup_module");
2949 return pci_unregister_driver(&hrz_driver);
2952 module_init(hrz_module_init);
2953 module_exit(hrz_module_exit);