2 Madge Horizon ATM Adapter driver.
3 Copyright (C) 1995-1999 Madge Networks Ltd.
5 This program is free software; you can redistribute it and/or modify
6 it under the terms of the GNU General Public License as published by
7 the Free Software Foundation; either version 2 of the License, or
8 (at your option) any later version.
10 This program is distributed in the hope that it will be useful,
11 but WITHOUT ANY WARRANTY; without even the implied warranty of
12 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 GNU General Public License for more details.
15 You should have received a copy of the GNU General Public License
16 along with this program; if not, write to the Free Software
17 Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 The GNU GPL is contained in /usr/doc/copyright/GPL on a Debian
20 system and in the file COPYING in the Linux kernel source.
24 IMPORTANT NOTE: Madge Networks no longer makes the adapters
25 supported by this driver and makes no commitment to maintain it.
28 #include <linux/module.h>
29 #include <linux/kernel.h>
31 #include <linux/pci.h>
32 #include <linux/errno.h>
33 #include <linux/atm.h>
34 #include <linux/atmdev.h>
35 #include <linux/sonet.h>
36 #include <linux/skbuff.h>
37 #include <linux/time.h>
38 #include <linux/delay.h>
39 #include <linux/uio.h>
40 #include <linux/init.h>
41 #include <linux/ioport.h>
43 #include <asm/system.h>
45 #include <asm/atomic.h>
46 #include <asm/uaccess.h>
47 #include <asm/string.h>
48 #include <asm/byteorder.h>
52 #define maintainer_string "Giuliano Procida at Madge Networks <gprocida@madge.com>"
53 #define description_string "Madge ATM Horizon [Ultra] driver"
54 #define version_string "1.2.1"
56 static inline void __init show_version (void) {
57 printk ("%s version %s\n", description_string, version_string);
64 Driver and documentation by:
66 Chris Aston Madge Networks
67 Giuliano Procida Madge Networks
68 Simon Benham Madge Networks
69 Simon Johnson Madge Networks
70 Various Others Madge Networks
72 Some inspiration taken from other drivers by:
75 Kari Mettinen University of Helsinki
76 Werner Almesberger EPFL LRC
80 I Hardware, detection, initialisation and shutdown.
84 This driver should handle all variants of the PCI Madge ATM adapters
85 with the Horizon chipset. These are all PCI cards supporting PIO, BM
86 DMA and a form of MMIO (registers only, not internal RAM).
88 The driver is only known to work with SONET and UTP Horizon Ultra
89 cards at 155Mb/s. However, code is in place to deal with both the
90 original Horizon and 25Mb/s operation.
92 There are two revisions of the Horizon ASIC: the original and the
93 Ultra. Details of hardware bugs are in section III.
95 The ASIC version can be distinguished by chip markings but is NOT
96 indicated by the PCI revision (all adapters seem to have PCI rev 1).
100 Horizon => Collage 25 PCI Adapter (UTP and STP)
101 Horizon Ultra => Collage 155 PCI Client (UTP or SONET)
102 Ambassador x => Collage 155 PCI Server (completely different)
104 Horizon (25Mb/s) is fitted with UTP and STP connectors. It seems to
105 have a Madge B154 plus glue logic serializer. I have also found a
106 really ancient version of this with slightly different glue. It
107 comes with the revision 0 (140-025-01) ASIC.
109 Horizon Ultra (155Mb/s) is fitted with either a Pulse Medialink
110 output (UTP) or an HP HFBR 5205 output (SONET). It has either
111 Madge's SAMBA framer or a SUNI-lite device (early versions). It
112 comes with the revision 1 (140-027-01) ASIC.
116 All Horizon-based cards present with the same PCI Vendor and Device
117 IDs. The standard Linux 2.2 PCI API is used to locate any cards and
118 to enable bus-mastering (with appropriate latency).
120 ATM_LAYER_STATUS in the control register distinguishes between the
121 two possible physical layers (25 and 155). It is not clear whether
122 the 155 cards can also operate at 25Mbps. We rely on the fact that a
123 card operates at 155 if and only if it has the newer Horizon Ultra
126 For 155 cards the two possible framers are probed for and then set
131 The card is reset and then put into a known state. The physical
132 layer is configured for normal operation at the appropriate speed;
133 in the case of the 155 cards, the framer is initialised with
134 line-based timing; the internal RAM is zeroed and the allocation of
135 buffers for RX and TX is made; the Burnt In Address is read and
136 copied to the ATM ESI; various policy settings for RX (VPI bits,
137 unknown VCs, oam cells) are made. Ideally all policy items should be
138 configurable at module load (if not actually on-demand), however,
139 only the vpi vs vci bit allocation can be specified at insmod.
143 This is in response to module_cleaup. No VCs are in use and the card
144 should be idle; it is reset.
146 II Driver software (as it should be)
148 0. Traffic Parameters
150 The traffic classes (not an enumeration) are currently: ATM_NONE (no
151 traffic), ATM_UBR, ATM_CBR, ATM_VBR and ATM_ABR, ATM_ANYCLASS
152 (compatible with everything). Together with (perhaps only some of)
153 the following items they make up the traffic specification.
156 unsigned char traffic_class; traffic class (ATM_UBR, ...)
157 int max_pcr; maximum PCR in cells per second
158 int pcr; desired PCR in cells per second
159 int min_pcr; minimum PCR in cells per second
160 int max_cdv; maximum CDV in microseconds
161 int max_sdu; maximum SDU in bytes
164 Note that these denote bandwidth available not bandwidth used; the
165 possibilities according to ATMF are:
167 Real Time (cdv and max CDT given)
169 CBR(pcr) pcr bandwidth always available
170 rtVBR(pcr,scr,mbs) scr bandwidth always available, upto pcr at mbs too
174 nrtVBR(pcr,scr,mbs) scr bandwidth always available, upto pcr at mbs too
176 ABR(mcr,pcr) mcr bandwidth always available, upto pcr (depending) too
178 mbs is max burst size (bucket)
179 pcr and scr have associated cdvt values
180 mcr is like scr but has no cdtv
181 cdtv may differ at each hop
183 Some of the above items are qos items (as opposed to traffic
184 parameters). We have nothing to do with qos. All except ABR can have
185 their traffic parameters converted to GCRA parameters. The GCRA may
186 be implemented as a (real-number) leaky bucket. The GCRA can be used
187 in complicated ways by switches and in simpler ways by end-stations.
188 It can be used both to filter incoming cells and shape out-going
191 ATM Linux actually supports:
193 ATM_NONE() (no traffic in this direction)
194 ATM_UBR(max_frame_size)
195 ATM_CBR(max/min_pcr, max_cdv, max_frame_size)
197 0 or ATM_MAX_PCR are used to indicate maximum available PCR
199 A traffic specification consists of the AAL type and separate
200 traffic specifications for either direction. In ATM Linux it is:
203 struct atm_trafprm txtp;
204 struct atm_trafprm rxtp;
210 ATM_NO_AAL AAL not specified
211 ATM_AAL0 "raw" ATM cells
214 ATM_AAL34 AAL3/4 (data)
216 ATM_SAAL signaling AAL
218 The Horizon has support for AAL frame types: 0, 3/4 and 5. However,
219 it does not implement AAL 3/4 SAR and it has a different notion of
220 "raw cell" to ATM Linux's (48 bytes vs. 52 bytes) so neither are
221 supported by this driver.
223 The Horizon has limited support for ABR (including UBR), VBR and
224 CBR. Each TX channel has a bucket (containing up to 31 cell units)
225 and two timers (PCR and SCR) associated with it that can be used to
226 govern cell emissions and host notification (in the case of ABR this
227 is presumably so that RM cells may be emitted at appropriate times).
228 The timers may either be disabled or may be set to any of 240 values
229 (determined by the clock crystal, a fixed (?) per-device divider, a
230 configurable divider and a configurable timer preload value).
232 At the moment only UBR and CBR are supported by the driver. VBR will
233 be supported as soon as ATM for Linux supports it. ABR support is
234 very unlikely as RM cell handling is completely up to the driver.
236 1. TX (TX channel setup and TX transfer)
238 The TX half of the driver owns the TX Horizon registers. The TX
239 component in the IRQ handler is the BM completion handler. This can
240 only be entered when tx_busy is true (enforced by hardware). The
241 other TX component can only be entered when tx_busy is false
242 (enforced by driver). So TX is single-threaded.
244 Apart from a minor optimisation to not re-select the last channel,
245 the TX send component works as follows:
247 Atomic test and set tx_busy until we succeed; we should implement
248 some sort of timeout so that tx_busy will never be stuck at true.
250 If no TX channel is set up for this VC we wait for an idle one (if
251 necessary) and set it up.
253 At this point we have a TX channel ready for use. We wait for enough
254 buffers to become available then start a TX transmit (set the TX
255 descriptor, schedule transfer, exit).
257 The IRQ component handles TX completion (stats, free buffer, tx_busy
258 unset, exit). We also re-schedule further transfers for the same
261 TX setup in more detail:
263 TX open is a nop, the relevant information is held in the hrz_vcc
264 (vcc->dev_data) structure and is "cached" on the card.
266 TX close gets the TX lock and clears the channel from the "cache".
268 2. RX (Data Available and RX transfer)
270 The RX half of the driver owns the RX registers. There are two RX
271 components in the IRQ handler: the data available handler deals with
272 fresh data that has arrived on the card, the BM completion handler
273 is very similar to the TX completion handler. The data available
274 handler grabs the rx_lock and it is only released once the data has
275 been discarded or completely transferred to the host. The BM
276 completion handler only runs when the lock is held; the data
277 available handler is locked out over the same period.
279 Data available on the card triggers an interrupt. If the data is not
280 suitable for our existing RX channels or we cannot allocate a buffer
281 it is flushed. Otherwise an RX receive is scheduled. Multiple RX
282 transfers may be scheduled for the same frame.
284 RX setup in more detail:
291 0. Byte vs Word addressing of adapter RAM.
293 A design feature; see the .h file (especially the memory map).
295 1. Bus Master Data Transfers (original Horizon only, fixed in Ultra)
297 The host must not start a transmit direction transfer at a
298 non-four-byte boundary in host memory. Instead the host should
299 perform a byte, or a two byte, or one byte followed by two byte
300 transfer in order to start the rest of the transfer on a four byte
303 Simultaneous transmit and receive direction bus master transfers are
306 The simplest solution to these two is to always do PIO (never DMA)
307 in the TX direction on the original Horizon. More complicated
308 solutions are likely to hurt my brain.
310 2. Loss of buffer on close VC
312 When a VC is being closed, the buffer associated with it is not
313 returned to the pool. The host must store the reference to this
314 buffer and when opening a new VC then give it to that new VC.
316 The host intervention currently consists of stacking such a buffer
317 pointer at VC close and checking the stack at VC open.
319 3. Failure to close a VC
321 If a VC is currently receiving a frame then closing the VC may fail
322 and the frame continues to be received.
324 The solution is to make sure any received frames are flushed when
325 ready. This is currently done just before the solution to 2.
327 4. PCI bus (original Horizon only, fixed in Ultra)
329 Reading from the data port prior to initialisation will hang the PCI
330 bus. Just don't do that then! We don't.
334 . Timer code may be broken.
336 . Allow users to specify buffer allocation split for TX and RX.
338 . Deal once and for all with buggy VC close.
340 . Handle interrupted and/or non-blocking operations.
342 . Change some macros to functions and move from .h to .c.
344 . Try to limit the number of TX frames each VC may have queued, in
345 order to reduce the chances of TX buffer exhaustion.
347 . Implement VBR (bucket and timers not understood) and ABR (need to
348 do RM cells manually); also no Linux support for either.
350 . Implement QoS changes on open VCs (involves extracting parts of VC open
351 and close into separate functions and using them to make changes).
355 /********** globals **********/
357 static hrz_dev * hrz_devs = NULL;
358 static struct timer_list housekeeping;
360 static unsigned short debug = 0;
361 static unsigned short vpi_bits = 0;
362 static int max_tx_size = 9000;
363 static int max_rx_size = 9000;
364 static unsigned char pci_lat = 0;
366 /********** access functions **********/
368 /* Read / Write Horizon registers */
369 static inline void wr_regl (const hrz_dev * dev, unsigned char reg, u32 data) {
370 outl (cpu_to_le32 (data), dev->iobase + reg);
373 static inline u32 rd_regl (const hrz_dev * dev, unsigned char reg) {
374 return le32_to_cpu (inl (dev->iobase + reg));
377 static inline void wr_regw (const hrz_dev * dev, unsigned char reg, u16 data) {
378 outw (cpu_to_le16 (data), dev->iobase + reg);
381 static inline u16 rd_regw (const hrz_dev * dev, unsigned char reg) {
382 return le16_to_cpu (inw (dev->iobase + reg));
385 static inline void wrs_regb (const hrz_dev * dev, unsigned char reg, void * addr, u32 len) {
386 outsb (dev->iobase + reg, addr, len);
389 static inline void rds_regb (const hrz_dev * dev, unsigned char reg, void * addr, u32 len) {
390 insb (dev->iobase + reg, addr, len);
393 /* Read / Write to a given address in Horizon buffer memory.
394 Interrupts must be disabled between the address register and data
395 port accesses as these must form an atomic operation. */
396 static inline void wr_mem (const hrz_dev * dev, HDW * addr, u32 data) {
397 // wr_regl (dev, MEM_WR_ADDR_REG_OFF, (u32) addr);
398 wr_regl (dev, MEM_WR_ADDR_REG_OFF, (addr - (HDW *) 0) * sizeof(HDW));
399 wr_regl (dev, MEMORY_PORT_OFF, data);
402 static inline u32 rd_mem (const hrz_dev * dev, HDW * addr) {
403 // wr_regl (dev, MEM_RD_ADDR_REG_OFF, (u32) addr);
404 wr_regl (dev, MEM_RD_ADDR_REG_OFF, (addr - (HDW *) 0) * sizeof(HDW));
405 return rd_regl (dev, MEMORY_PORT_OFF);
408 static inline void wr_framer (const hrz_dev * dev, u32 addr, u32 data) {
409 wr_regl (dev, MEM_WR_ADDR_REG_OFF, (u32) addr | 0x80000000);
410 wr_regl (dev, MEMORY_PORT_OFF, data);
413 static inline u32 rd_framer (const hrz_dev * dev, u32 addr) {
414 wr_regl (dev, MEM_RD_ADDR_REG_OFF, (u32) addr | 0x80000000);
415 return rd_regl (dev, MEMORY_PORT_OFF);
418 /********** specialised access functions **********/
422 static inline void FLUSH_RX_CHANNEL (hrz_dev * dev, u16 channel) {
423 wr_regw (dev, RX_CHANNEL_PORT_OFF, FLUSH_CHANNEL | channel);
427 static inline void WAIT_FLUSH_RX_COMPLETE (hrz_dev * dev) {
428 while (rd_regw (dev, RX_CHANNEL_PORT_OFF) & FLUSH_CHANNEL)
433 static inline void SELECT_RX_CHANNEL (hrz_dev * dev, u16 channel) {
434 wr_regw (dev, RX_CHANNEL_PORT_OFF, channel);
438 static inline void WAIT_UPDATE_COMPLETE (hrz_dev * dev) {
439 while (rd_regw (dev, RX_CHANNEL_PORT_OFF) & RX_CHANNEL_UPDATE_IN_PROGRESS)
446 static inline void SELECT_TX_CHANNEL (hrz_dev * dev, u16 tx_channel) {
447 wr_regl (dev, TX_CHANNEL_PORT_OFF, tx_channel);
451 /* Update or query one configuration parameter of a particular channel. */
453 static inline void update_tx_channel_config (hrz_dev * dev, short chan, u8 mode, u16 value) {
454 wr_regw (dev, TX_CHANNEL_CONFIG_COMMAND_OFF,
455 chan * TX_CHANNEL_CONFIG_MULT | mode);
456 wr_regw (dev, TX_CHANNEL_CONFIG_DATA_OFF, value);
460 static inline u16 query_tx_channel_config (hrz_dev * dev, short chan, u8 mode) {
461 wr_regw (dev, TX_CHANNEL_CONFIG_COMMAND_OFF,
462 chan * TX_CHANNEL_CONFIG_MULT | mode);
463 return rd_regw (dev, TX_CHANNEL_CONFIG_DATA_OFF);
466 /********** dump functions **********/
468 static inline void dump_skb (char * prefix, unsigned int vc, struct sk_buff * skb) {
471 unsigned char * data = skb->data;
472 PRINTDB (DBG_DATA, "%s(%u) ", prefix, vc);
473 for (i=0; i<skb->len && i < 256;i++)
474 PRINTDM (DBG_DATA, "%02x ", data[i]);
475 PRINTDE (DBG_DATA,"");
484 static inline void dump_regs (hrz_dev * dev) {
486 PRINTD (DBG_REGS, "CONTROL 0: %#x", rd_regl (dev, CONTROL_0_REG));
487 PRINTD (DBG_REGS, "RX CONFIG: %#x", rd_regw (dev, RX_CONFIG_OFF));
488 PRINTD (DBG_REGS, "TX CONFIG: %#x", rd_regw (dev, TX_CONFIG_OFF));
489 PRINTD (DBG_REGS, "TX STATUS: %#x", rd_regw (dev, TX_STATUS_OFF));
490 PRINTD (DBG_REGS, "IRQ ENBLE: %#x", rd_regl (dev, INT_ENABLE_REG_OFF));
491 PRINTD (DBG_REGS, "IRQ SORCE: %#x", rd_regl (dev, INT_SOURCE_REG_OFF));
498 static inline void dump_framer (hrz_dev * dev) {
501 PRINTDB (DBG_REGS, "framer registers:");
502 for (i = 0; i < 0x10; ++i)
503 PRINTDM (DBG_REGS, " %02x", rd_framer (dev, i));
504 PRINTDE (DBG_REGS,"");
511 /********** VPI/VCI <-> (RX) channel conversions **********/
513 /* RX channels are 10 bit integers, these fns are quite paranoid */
515 static inline int channel_to_vpivci (const u16 channel, short * vpi, int * vci) {
516 unsigned short vci_bits = 10 - vpi_bits;
517 if ((channel & RX_CHANNEL_MASK) == channel) {
518 *vci = channel & ((~0)<<vci_bits);
519 *vpi = channel >> vci_bits;
520 return channel ? 0 : -EINVAL;
525 static inline int vpivci_to_channel (u16 * channel, const short vpi, const int vci) {
526 unsigned short vci_bits = 10 - vpi_bits;
527 if (0 <= vpi && vpi < 1<<vpi_bits && 0 <= vci && vci < 1<<vci_bits) {
528 *channel = vpi<<vci_bits | vci;
529 return *channel ? 0 : -EINVAL;
534 /********** decode RX queue entries **********/
536 static inline u16 rx_q_entry_to_length (u32 x) {
537 return x & RX_Q_ENTRY_LENGTH_MASK;
540 static inline u16 rx_q_entry_to_rx_channel (u32 x) {
541 return (x>>RX_Q_ENTRY_CHANNEL_SHIFT) & RX_CHANNEL_MASK;
544 /* Cell Transmit Rate Values
546 * the cell transmit rate (cells per sec) can be set to a variety of
547 * different values by specifying two parameters: a timer preload from
548 * 1 to 16 (stored as 0 to 15) and a clock divider (2 to the power of
549 * an exponent from 0 to 14; the special value 15 disables the timer).
551 * cellrate = baserate / (preload * 2^divider)
553 * The maximum cell rate that can be specified is therefore just the
554 * base rate. Halving the preload is equivalent to adding 1 to the
555 * divider and so values 1 to 8 of the preload are redundant except
556 * in the case of a maximal divider (14).
558 * Given a desired cell rate, an algorithm to determine the preload
561 * a) x = baserate / cellrate, want p * 2^d = x (as far as possible)
562 * b) if x > 16 * 2^14 then set p = 16, d = 14 (min rate), done
563 * if x <= 16 then set p = x, d = 0 (high rates), done
564 * c) now have 16 < x <= 2^18, or 1 < x/16 <= 2^14 and we want to
565 * know n such that 2^(n-1) < x/16 <= 2^n, so slide a bit until
566 * we find the range (n will be between 1 and 14), set d = n
567 * d) Also have 8 < x/2^n <= 16, so set p nearest x/2^n
569 * The algorithm used below is a minor variant of the above.
571 * The base rate is derived from the oscillator frequency (Hz) using a
574 * baserate = freq / 32 in the case of some Unknown Card
575 * baserate = freq / 8 in the case of the Horizon 25
576 * baserate = freq / 8 in the case of the Horizon Ultra 155
578 * The Horizon cards have oscillators and base rates as follows:
580 * Card Oscillator Base Rate
581 * Unknown Card 33 MHz 1.03125 MHz (33 MHz = PCI freq)
582 * Horizon 25 32 MHz 4 MHz
583 * Horizon Ultra 155 40 MHz 5 MHz
585 * The following defines give the base rates in Hz. These were
586 * previously a factor of 100 larger, no doubt someone was using
590 #define BR_UKN 1031250l
591 #define BR_HRZ 4000000l
592 #define BR_ULT 5000000l
598 // p ranges from 1 to a power of 2
601 static int make_rate (const hrz_dev * dev, u32 c, rounding r,
602 u16 * bits, unsigned int * actual)
604 // note: rounding the rate down means rounding 'p' up
605 const unsigned long br = test_bit(ultra, &dev->flags) ? BR_ULT : BR_HRZ;
610 // br_exp and br_man are used to avoid overflowing (c*maxp*2^d) in
611 // the tests below. We could think harder about exact possibilities
614 unsigned long br_man = br;
615 unsigned int br_exp = 0;
617 PRINTD (DBG_QOS|DBG_FLOW, "make_rate b=%lu, c=%u, %s", br, c,
618 r == round_up ? "up" : r == round_down ? "down" : "nearest");
622 PRINTD (DBG_QOS|DBG_ERR, "zero rate is not allowed!");
626 while (br_exp < CR_MAXPEXP + CR_MIND && (br_man % 2 == 0)) {
627 br_man = br_man >> 1;
630 // (br >>br_exp) <<br_exp == br and
631 // br_exp <= CR_MAXPEXP+CR_MIND
633 if (br_man <= (c << (CR_MAXPEXP+CR_MIND-br_exp))) {
634 // Equivalent to: B <= (c << (MAXPEXP+MIND))
635 // take care of rounding
638 pre = (br+(c<<div)-1)/(c<<div);
639 // but p must be non-zero
644 pre = (br+(c<<div)/2)/(c<<div);
645 // but p must be non-zero
649 default: /* round_up */
651 // but p must be non-zero
655 PRINTD (DBG_QOS, "A: p=%u, d=%u", pre, div);
659 // at this point we have
660 // d == MIND and (c << (MAXPEXP+MIND)) < B
661 while (div < CR_MAXD) {
663 if (br_man <= (c << (CR_MAXPEXP+div-br_exp))) {
664 // Equivalent to: B <= (c << (MAXPEXP+d))
665 // c << (MAXPEXP+d-1) < B <= c << (MAXPEXP+d)
666 // 1 << (MAXPEXP-1) < B/2^d/c <= 1 << MAXPEXP
667 // MAXP/2 < B/c2^d <= MAXP
668 // take care of rounding
671 pre = (br+(c<<div)-1)/(c<<div);
674 pre = (br+(c<<div)/2)/(c<<div);
676 default: /* round_up */
679 PRINTD (DBG_QOS, "B: p=%u, d=%u", pre, div);
683 // at this point we have
684 // d == MAXD and (c << (MAXPEXP+MAXD)) < B
685 // but we cannot go any higher
686 // take care of rounding
689 pre = 1 << CR_MAXPEXP;
690 PRINTD (DBG_QOS, "C: p=%u, d=%u", pre, div);
693 if (div > CR_MAXD || (!pre) || pre > 1<<CR_MAXPEXP) {
694 PRINTD (DBG_QOS, "set_cr internal failure: d=%u p=%u",
699 *bits = (div<<CLOCK_SELECT_SHIFT) | (pre-1);
701 *actual = (br + (pre<<div) - 1) / (pre<<div);
702 PRINTD (DBG_QOS, "actual rate: %u", *actual);
708 static int make_rate_with_tolerance (const hrz_dev * dev, u32 c, rounding r, unsigned int tol,
709 u16 * bit_pattern, unsigned int * actual) {
710 unsigned int my_actual;
712 PRINTD (DBG_QOS|DBG_FLOW, "make_rate_with_tolerance c=%u, %s, tol=%u",
713 c, (r == round_up) ? "up" : (r == round_down) ? "down" : "nearest", tol);
716 // actual rate is not returned
719 if (make_rate (dev, c, round_nearest, bit_pattern, actual))
720 // should never happen as round_nearest always succeeds
723 if (c - tol <= *actual && *actual <= c + tol)
727 // intolerant, try rounding instead
728 return make_rate (dev, c, r, bit_pattern, actual);
731 /********** Listen on a VC **********/
733 static int hrz_open_rx (hrz_dev * dev, u16 channel) {
734 // is there any guarantee that we don't get two simulataneous
735 // identical calls of this function from different processes? yes
738 u32 channel_type; // u16?
740 u16 buf_ptr = RX_CHANNEL_IDLE;
742 rx_ch_desc * rx_desc = &memmap->rx_descs[channel];
744 PRINTD (DBG_FLOW, "hrz_open_rx %x", channel);
746 spin_lock_irqsave (&dev->mem_lock, flags);
747 channel_type = rd_mem (dev, &rx_desc->wr_buf_type) & BUFFER_PTR_MASK;
748 spin_unlock_irqrestore (&dev->mem_lock, flags);
750 // very serious error, should never occur
751 if (channel_type != RX_CHANNEL_DISABLED) {
752 PRINTD (DBG_ERR|DBG_VCC, "RX channel for VC already open");
753 return -EBUSY; // clean up?
756 // Give back spare buffer
757 if (dev->noof_spare_buffers) {
758 buf_ptr = dev->spare_buffers[--dev->noof_spare_buffers];
759 PRINTD (DBG_VCC, "using a spare buffer: %u", buf_ptr);
760 // should never occur
761 if (buf_ptr == RX_CHANNEL_DISABLED || buf_ptr == RX_CHANNEL_IDLE) {
762 // but easy to recover from
763 PRINTD (DBG_ERR|DBG_VCC, "bad spare buffer pointer, using IDLE");
764 buf_ptr = RX_CHANNEL_IDLE;
767 PRINTD (DBG_VCC, "using IDLE buffer pointer");
770 // Channel is currently disabled so change its status to idle
772 // do we really need to save the flags again?
773 spin_lock_irqsave (&dev->mem_lock, flags);
775 wr_mem (dev, &rx_desc->wr_buf_type,
776 buf_ptr | CHANNEL_TYPE_AAL5 | FIRST_CELL_OF_AAL5_FRAME);
777 if (buf_ptr != RX_CHANNEL_IDLE)
778 wr_mem (dev, &rx_desc->rd_buf_type, buf_ptr);
780 spin_unlock_irqrestore (&dev->mem_lock, flags);
782 // rxer->rate = make_rate (qos->peak_cells);
784 PRINTD (DBG_FLOW, "hrz_open_rx ok");
790 /********** change vc rate for a given vc **********/
792 static void hrz_change_vc_qos (ATM_RXER * rxer, MAAL_QOS * qos) {
793 rxer->rate = make_rate (qos->peak_cells);
797 /********** free an skb (as per ATM device driver documentation) **********/
799 static inline void hrz_kfree_skb (struct sk_buff * skb) {
800 if (ATM_SKB(skb)->vcc->pop) {
801 ATM_SKB(skb)->vcc->pop (ATM_SKB(skb)->vcc, skb);
803 dev_kfree_skb_any (skb);
807 /********** cancel listen on a VC **********/
809 static void hrz_close_rx (hrz_dev * dev, u16 vc) {
816 rx_ch_desc * rx_desc = &memmap->rx_descs[vc];
820 spin_lock_irqsave (&dev->mem_lock, flags);
821 value = rd_mem (dev, &rx_desc->wr_buf_type) & BUFFER_PTR_MASK;
822 spin_unlock_irqrestore (&dev->mem_lock, flags);
824 if (value == RX_CHANNEL_DISABLED) {
825 // I suppose this could happen once we deal with _NONE traffic properly
826 PRINTD (DBG_VCC, "closing VC: RX channel %u already disabled", vc);
829 if (value == RX_CHANNEL_IDLE)
832 spin_lock_irqsave (&dev->mem_lock, flags);
835 wr_mem (dev, &rx_desc->wr_buf_type, RX_CHANNEL_DISABLED);
837 if ((rd_mem (dev, &rx_desc->wr_buf_type) & BUFFER_PTR_MASK) == RX_CHANNEL_DISABLED)
844 spin_unlock_irqrestore (&dev->mem_lock, flags);
848 WAIT_FLUSH_RX_COMPLETE(dev);
850 // XXX Is this all really necessary? We can rely on the rx_data_av
851 // handler to discard frames that remain queued for delivery. If the
852 // worry is that immediately reopening the channel (perhaps by a
853 // different process) may cause some data to be mis-delivered then
854 // there may still be a simpler solution (such as busy-waiting on
855 // rx_busy once the channel is disabled or before a new one is
856 // opened - does this leave any holes?). Arguably setting up and
857 // tearing down the TX and RX halves of each virtual circuit could
858 // most safely be done within ?x_busy protected regions.
860 // OK, current changes are that Simon's marker is disabled and we DO
861 // look for NULL rxer elsewhere. The code here seems flush frames
862 // and then remember the last dead cell belonging to the channel
863 // just disabled - the cell gets relinked at the next vc_open.
864 // However, when all VCs are closed or only a few opened there are a
865 // handful of buffers that are unusable.
867 // Does anyone feel like documenting spare_buffers properly?
868 // Does anyone feel like fixing this in a nicer way?
870 // Flush any data which is left in the channel
872 // Change the rx channel port to something different to the RX
873 // channel we are trying to close to force Horizon to flush the rx
874 // channel read and write pointers.
876 u16 other = vc^(RX_CHANS/2);
878 SELECT_RX_CHANNEL (dev, other);
879 WAIT_UPDATE_COMPLETE (dev);
881 r1 = rd_mem (dev, &rx_desc->rd_buf_type);
883 // Select this RX channel. Flush doesn't seem to work unless we
884 // select an RX channel before hand
886 SELECT_RX_CHANNEL (dev, vc);
887 WAIT_UPDATE_COMPLETE (dev);
889 // Attempt to flush a frame on this RX channel
891 FLUSH_RX_CHANNEL (dev, vc);
892 WAIT_FLUSH_RX_COMPLETE (dev);
894 // Force Horizon to flush rx channel read and write pointers as before
896 SELECT_RX_CHANNEL (dev, other);
897 WAIT_UPDATE_COMPLETE (dev);
899 r2 = rd_mem (dev, &rx_desc->rd_buf_type);
901 PRINTD (DBG_VCC|DBG_RX, "r1 = %u, r2 = %u", r1, r2);
904 dev->spare_buffers[dev->noof_spare_buffers++] = (u16)r1;
911 rx_q_entry * wr_ptr = &memmap->rx_q_entries[rd_regw (dev, RX_QUEUE_WR_PTR_OFF)];
912 rx_q_entry * rd_ptr = dev->rx_q_entry;
914 PRINTD (DBG_VCC|DBG_RX, "rd_ptr = %u, wr_ptr = %u", rd_ptr, wr_ptr);
916 while (rd_ptr != wr_ptr) {
917 u32 x = rd_mem (dev, (HDW *) rd_ptr);
919 if (vc == rx_q_entry_to_rx_channel (x)) {
920 x |= SIMONS_DODGEY_MARKER;
922 PRINTD (DBG_RX|DBG_VCC|DBG_WARN, "marking a frame as dodgey");
924 wr_mem (dev, (HDW *) rd_ptr, x);
927 if (rd_ptr == dev->rx_q_wrap)
928 rd_ptr = dev->rx_q_reset;
935 spin_unlock_irqrestore (&dev->mem_lock, flags);
940 /********** schedule RX transfers **********/
942 // Note on tail recursion: a GCC developer said that it is not likely
943 // to be fixed soon, so do not define TAILRECUSRIONWORKS unless you
944 // are sure it does as you may otherwise overflow the kernel stack.
946 // giving this fn a return value would help GCC, alledgedly
948 static void rx_schedule (hrz_dev * dev, int irq) {
949 unsigned int rx_bytes;
952 #ifndef TAILRECURSIONWORKS
954 while (pio_instead) {
956 // bytes waiting for RX transfer
957 rx_bytes = dev->rx_bytes;
961 while (rd_regl (dev, MASTER_RX_COUNT_REG_OFF)) {
962 PRINTD (DBG_RX|DBG_WARN, "RX error: other PCI Bus Master RX still in progress!");
963 if (++spin_count > 10) {
964 PRINTD (DBG_RX|DBG_ERR, "spun out waiting PCI Bus Master RX completion");
965 wr_regl (dev, MASTER_RX_COUNT_REG_OFF, 0);
966 clear_bit (rx_busy, &dev->flags);
967 hrz_kfree_skb (dev->rx_skb);
973 // this code follows the TX code but (at the moment) there is only
974 // one region - the skb itself. I don't know if this will change,
975 // but it doesn't hurt to have the code here, disabled.
978 // start next transfer within same region
979 if (rx_bytes <= MAX_PIO_COUNT) {
980 PRINTD (DBG_RX|DBG_BUS, "(pio)");
983 if (rx_bytes <= MAX_TRANSFER_COUNT) {
984 PRINTD (DBG_RX|DBG_BUS, "(simple or last multi)");
987 PRINTD (DBG_RX|DBG_BUS, "(continuing multi)");
988 dev->rx_bytes = rx_bytes - MAX_TRANSFER_COUNT;
989 rx_bytes = MAX_TRANSFER_COUNT;
992 // rx_bytes == 0 -- we're between regions
993 // regions remaining to transfer
995 unsigned int rx_regions = dev->rx_regions;
997 unsigned int rx_regions = 0;
1002 // start a new region
1003 dev->rx_addr = dev->rx_iovec->iov_base;
1004 rx_bytes = dev->rx_iovec->iov_len;
1006 dev->rx_regions = rx_regions - 1;
1008 if (rx_bytes <= MAX_PIO_COUNT) {
1009 PRINTD (DBG_RX|DBG_BUS, "(pio)");
1012 if (rx_bytes <= MAX_TRANSFER_COUNT) {
1013 PRINTD (DBG_RX|DBG_BUS, "(full region)");
1016 PRINTD (DBG_RX|DBG_BUS, "(start multi region)");
1017 dev->rx_bytes = rx_bytes - MAX_TRANSFER_COUNT;
1018 rx_bytes = MAX_TRANSFER_COUNT;
1023 // that's all folks - end of frame
1024 struct sk_buff * skb = dev->rx_skb;
1025 // dev->rx_iovec = 0;
1027 FLUSH_RX_CHANNEL (dev, dev->rx_channel);
1029 dump_skb ("<<<", dev->rx_channel, skb);
1031 PRINTD (DBG_RX|DBG_SKB, "push %p %u", skb->data, skb->len);
1034 struct atm_vcc * vcc = ATM_SKB(skb)->vcc;
1036 atomic_inc(&vcc->stats->rx);
1037 do_gettimeofday(&skb->stamp);
1038 // end of our responsability
1039 vcc->push (vcc, skb);
1044 // note: writing RX_COUNT clears any interrupt condition
1048 wr_regl (dev, MASTER_RX_COUNT_REG_OFF, 0);
1049 rds_regb (dev, DATA_PORT_OFF, dev->rx_addr, rx_bytes);
1051 wr_regl (dev, MASTER_RX_ADDR_REG_OFF, virt_to_bus (dev->rx_addr));
1052 wr_regl (dev, MASTER_RX_COUNT_REG_OFF, rx_bytes);
1054 dev->rx_addr += rx_bytes;
1057 wr_regl (dev, MASTER_RX_COUNT_REG_OFF, 0);
1058 // allow another RX thread to start
1060 clear_bit (rx_busy, &dev->flags);
1061 PRINTD (DBG_RX, "cleared rx_busy for dev %p", dev);
1064 #ifdef TAILRECURSIONWORKS
1065 // and we all bless optimised tail calls
1067 return rx_schedule (dev, 0);
1077 /********** handle RX bus master complete events **********/
1079 static inline void rx_bus_master_complete_handler (hrz_dev * dev) {
1080 if (test_bit (rx_busy, &dev->flags)) {
1081 rx_schedule (dev, 1);
1083 PRINTD (DBG_RX|DBG_ERR, "unexpected RX bus master completion");
1084 // clear interrupt condition on adapter
1085 wr_regl (dev, MASTER_RX_COUNT_REG_OFF, 0);
1090 /********** (queue to) become the next TX thread **********/
1092 static inline int tx_hold (hrz_dev * dev) {
1093 while (test_and_set_bit (tx_busy, &dev->flags)) {
1094 PRINTD (DBG_TX, "sleeping at tx lock %p %lu", dev, dev->flags);
1095 interruptible_sleep_on (&dev->tx_queue);
1096 PRINTD (DBG_TX, "woken at tx lock %p %lu", dev, dev->flags);
1097 if (signal_pending (current))
1100 PRINTD (DBG_TX, "set tx_busy for dev %p", dev);
1104 /********** allow another TX thread to start **********/
1106 static inline void tx_release (hrz_dev * dev) {
1107 clear_bit (tx_busy, &dev->flags);
1108 PRINTD (DBG_TX, "cleared tx_busy for dev %p", dev);
1109 wake_up_interruptible (&dev->tx_queue);
1112 /********** schedule TX transfers **********/
1114 static void tx_schedule (hrz_dev * const dev, int irq) {
1115 unsigned int tx_bytes;
1117 int append_desc = 0;
1119 int pio_instead = 0;
1120 #ifndef TAILRECURSIONWORKS
1122 while (pio_instead) {
1124 // bytes in current region waiting for TX transfer
1125 tx_bytes = dev->tx_bytes;
1129 while (rd_regl (dev, MASTER_TX_COUNT_REG_OFF)) {
1130 PRINTD (DBG_TX|DBG_WARN, "TX error: other PCI Bus Master TX still in progress!");
1131 if (++spin_count > 10) {
1132 PRINTD (DBG_TX|DBG_ERR, "spun out waiting PCI Bus Master TX completion");
1133 wr_regl (dev, MASTER_TX_COUNT_REG_OFF, 0);
1135 hrz_kfree_skb (dev->tx_skb);
1142 // start next transfer within same region
1143 if (!test_bit (ultra, &dev->flags) || tx_bytes <= MAX_PIO_COUNT) {
1144 PRINTD (DBG_TX|DBG_BUS, "(pio)");
1147 if (tx_bytes <= MAX_TRANSFER_COUNT) {
1148 PRINTD (DBG_TX|DBG_BUS, "(simple or last multi)");
1149 if (!dev->tx_iovec) {
1150 // end of last region
1155 PRINTD (DBG_TX|DBG_BUS, "(continuing multi)");
1156 dev->tx_bytes = tx_bytes - MAX_TRANSFER_COUNT;
1157 tx_bytes = MAX_TRANSFER_COUNT;
1160 // tx_bytes == 0 -- we're between regions
1161 // regions remaining to transfer
1162 unsigned int tx_regions = dev->tx_regions;
1165 // start a new region
1166 dev->tx_addr = dev->tx_iovec->iov_base;
1167 tx_bytes = dev->tx_iovec->iov_len;
1169 dev->tx_regions = tx_regions - 1;
1171 if (!test_bit (ultra, &dev->flags) || tx_bytes <= MAX_PIO_COUNT) {
1172 PRINTD (DBG_TX|DBG_BUS, "(pio)");
1175 if (tx_bytes <= MAX_TRANSFER_COUNT) {
1176 PRINTD (DBG_TX|DBG_BUS, "(full region)");
1179 PRINTD (DBG_TX|DBG_BUS, "(start multi region)");
1180 dev->tx_bytes = tx_bytes - MAX_TRANSFER_COUNT;
1181 tx_bytes = MAX_TRANSFER_COUNT;
1185 // that's all folks - end of frame
1186 struct sk_buff * skb = dev->tx_skb;
1187 dev->tx_iovec = NULL;
1190 atomic_inc(&ATM_SKB(skb)->vcc->stats->tx);
1193 hrz_kfree_skb (skb);
1197 // note: writing TX_COUNT clears any interrupt condition
1201 wr_regl (dev, MASTER_TX_COUNT_REG_OFF, 0);
1202 wrs_regb (dev, DATA_PORT_OFF, dev->tx_addr, tx_bytes);
1204 wr_regl (dev, TX_DESCRIPTOR_PORT_OFF, cpu_to_be32 (dev->tx_skb->len));
1206 wr_regl (dev, MASTER_TX_ADDR_REG_OFF, virt_to_bus (dev->tx_addr));
1208 wr_regl (dev, TX_DESCRIPTOR_REG_OFF, cpu_to_be32 (dev->tx_skb->len));
1209 wr_regl (dev, MASTER_TX_COUNT_REG_OFF,
1211 ? tx_bytes | MASTER_TX_AUTO_APPEND_DESC
1214 dev->tx_addr += tx_bytes;
1217 wr_regl (dev, MASTER_TX_COUNT_REG_OFF, 0);
1222 #ifdef TAILRECURSIONWORKS
1223 // and we all bless optimised tail calls
1225 return tx_schedule (dev, 0);
1235 /********** handle TX bus master complete events **********/
1237 static inline void tx_bus_master_complete_handler (hrz_dev * dev) {
1238 if (test_bit (tx_busy, &dev->flags)) {
1239 tx_schedule (dev, 1);
1241 PRINTD (DBG_TX|DBG_ERR, "unexpected TX bus master completion");
1242 // clear interrupt condition on adapter
1243 wr_regl (dev, MASTER_TX_COUNT_REG_OFF, 0);
1248 /********** move RX Q pointer to next item in circular buffer **********/
1250 // called only from IRQ sub-handler
1251 static inline u32 rx_queue_entry_next (hrz_dev * dev) {
1253 spin_lock (&dev->mem_lock);
1254 rx_queue_entry = rd_mem (dev, &dev->rx_q_entry->entry);
1255 if (dev->rx_q_entry == dev->rx_q_wrap)
1256 dev->rx_q_entry = dev->rx_q_reset;
1259 wr_regw (dev, RX_QUEUE_RD_PTR_OFF, dev->rx_q_entry - dev->rx_q_reset);
1260 spin_unlock (&dev->mem_lock);
1261 return rx_queue_entry;
1264 /********** handle RX disabled by device **********/
1266 static inline void rx_disabled_handler (hrz_dev * dev) {
1267 wr_regw (dev, RX_CONFIG_OFF, rd_regw (dev, RX_CONFIG_OFF) | RX_ENABLE);
1269 PRINTK (KERN_WARNING, "RX was disabled!");
1272 /********** handle RX data received by device **********/
1274 // called from IRQ handler
1275 static inline void rx_data_av_handler (hrz_dev * dev) {
1277 u32 rx_queue_entry_flags;
1281 PRINTD (DBG_FLOW, "hrz_data_av_handler");
1283 // try to grab rx lock (not possible during RX bus mastering)
1284 if (test_and_set_bit (rx_busy, &dev->flags)) {
1285 PRINTD (DBG_RX, "locked out of rx lock");
1288 PRINTD (DBG_RX, "set rx_busy for dev %p", dev);
1289 // lock is cleared if we fail now, o/w after bus master completion
1291 YELLOW_LED_OFF(dev);
1293 rx_queue_entry = rx_queue_entry_next (dev);
1295 rx_len = rx_q_entry_to_length (rx_queue_entry);
1296 rx_channel = rx_q_entry_to_rx_channel (rx_queue_entry);
1298 WAIT_FLUSH_RX_COMPLETE (dev);
1300 SELECT_RX_CHANNEL (dev, rx_channel);
1302 PRINTD (DBG_RX, "rx_queue_entry is: %#x", rx_queue_entry);
1303 rx_queue_entry_flags = rx_queue_entry & (RX_CRC_32_OK|RX_COMPLETE_FRAME|SIMONS_DODGEY_MARKER);
1306 // (at least) bus-mastering breaks if we try to handle a
1307 // zero-length frame, besides AAL5 does not support them
1308 PRINTK (KERN_ERR, "zero-length frame!");
1309 rx_queue_entry_flags &= ~RX_COMPLETE_FRAME;
1312 if (rx_queue_entry_flags & SIMONS_DODGEY_MARKER) {
1313 PRINTD (DBG_RX|DBG_ERR, "Simon's marker detected!");
1315 if (rx_queue_entry_flags == (RX_CRC_32_OK | RX_COMPLETE_FRAME)) {
1316 struct atm_vcc * atm_vcc;
1318 PRINTD (DBG_RX, "got a frame on rx_channel %x len %u", rx_channel, rx_len);
1320 atm_vcc = dev->rxer[rx_channel];
1321 // if no vcc is assigned to this channel, we should drop the frame
1322 // (is this what SIMONS etc. was trying to achieve?)
1326 if (atm_vcc->qos.rxtp.traffic_class != ATM_NONE) {
1328 if (rx_len <= atm_vcc->qos.rxtp.max_sdu) {
1330 struct sk_buff * skb = atm_alloc_charge (atm_vcc, rx_len, GFP_ATOMIC);
1332 // remember this so we can push it later
1334 // remember this so we can flush it later
1335 dev->rx_channel = rx_channel;
1337 // prepare socket buffer
1338 skb_put (skb, rx_len);
1339 ATM_SKB(skb)->vcc = atm_vcc;
1342 // dev->rx_regions = 0;
1343 // dev->rx_iovec = 0;
1344 dev->rx_bytes = rx_len;
1345 dev->rx_addr = skb->data;
1346 PRINTD (DBG_RX, "RX start simple transfer (addr %p, len %d)",
1350 rx_schedule (dev, 0);
1354 PRINTD (DBG_SKB|DBG_WARN, "failed to get skb");
1358 PRINTK (KERN_INFO, "frame received on TX-only VC %x", rx_channel);
1359 // do we count this?
1363 PRINTK (KERN_WARNING, "dropped over-size frame");
1364 // do we count this?
1368 PRINTD (DBG_WARN|DBG_VCC|DBG_RX, "no VCC for this frame (VC closed)");
1369 // do we count this?
1373 // Wait update complete ? SPONG
1379 FLUSH_RX_CHANNEL (dev,rx_channel);
1380 clear_bit (rx_busy, &dev->flags);
1385 /********** interrupt handler **********/
1387 static irqreturn_t interrupt_handler(int irq, void *dev_id,
1388 struct pt_regs *pt_regs) {
1389 hrz_dev * dev = hrz_devs;
1391 unsigned int irq_ok;
1394 PRINTD (DBG_FLOW, "interrupt_handler: %p", dev_id);
1397 PRINTD (DBG_IRQ|DBG_ERR, "irq with NULL dev_id: %d", irq);
1400 // Did one of our cards generate the interrupt?
1407 PRINTD (DBG_IRQ, "irq not for me: %d", irq);
1410 if (irq != dev->irq) {
1411 PRINTD (DBG_IRQ|DBG_ERR, "irq mismatch: %d", irq);
1415 // definitely for us
1417 while ((int_source = rd_regl (dev, INT_SOURCE_REG_OFF)
1418 & INTERESTING_INTERRUPTS)) {
1419 // In the interests of fairness, the (inline) handlers below are
1420 // called in sequence and without immediate return to the head of
1421 // the while loop. This is only of issue for slow hosts (or when
1422 // debugging messages are on). Really slow hosts may find a fast
1423 // sender keeps them permanently in the IRQ handler. :(
1425 // (only an issue for slow hosts) RX completion goes before
1426 // rx_data_av as the former implies rx_busy and so the latter
1427 // would just abort. If it reschedules another transfer
1428 // (continuing the same frame) then it will not clear rx_busy.
1430 // (only an issue for slow hosts) TX completion goes before RX
1431 // data available as it is a much shorter routine - there is the
1432 // chance that any further transfers it schedules will be complete
1433 // by the time of the return to the head of the while loop
1435 if (int_source & RX_BUS_MASTER_COMPLETE) {
1437 PRINTD (DBG_IRQ|DBG_BUS|DBG_RX, "rx_bus_master_complete asserted");
1438 rx_bus_master_complete_handler (dev);
1440 if (int_source & TX_BUS_MASTER_COMPLETE) {
1442 PRINTD (DBG_IRQ|DBG_BUS|DBG_TX, "tx_bus_master_complete asserted");
1443 tx_bus_master_complete_handler (dev);
1445 if (int_source & RX_DATA_AV) {
1447 PRINTD (DBG_IRQ|DBG_RX, "rx_data_av asserted");
1448 rx_data_av_handler (dev);
1452 PRINTD (DBG_IRQ, "work done: %u", irq_ok);
1454 PRINTD (DBG_IRQ|DBG_WARN, "spurious interrupt source: %#x", int_source);
1457 PRINTD (DBG_IRQ|DBG_FLOW, "interrupt_handler done: %p", dev_id);
1463 /********** housekeeping **********/
1465 static void set_timer (struct timer_list * timer, unsigned int delay) {
1466 timer->expires = jiffies + delay;
1471 static void do_housekeeping (unsigned long arg) {
1472 // just stats at the moment
1473 hrz_dev * dev = hrz_devs;
1475 // data is set to zero at module unload
1476 if (housekeeping.data) {
1478 // collect device-specific (not driver/atm-linux) stats here
1479 dev->tx_cell_count += rd_regw (dev, TX_CELL_COUNT_OFF);
1480 dev->rx_cell_count += rd_regw (dev, RX_CELL_COUNT_OFF);
1481 dev->hec_error_count += rd_regw (dev, HEC_ERROR_COUNT_OFF);
1482 dev->unassigned_cell_count += rd_regw (dev, UNASSIGNED_CELL_COUNT_OFF);
1485 set_timer (&housekeeping, HZ/10);
1490 /********** find an idle channel for TX and set it up **********/
1492 // called with tx_busy set
1493 static inline short setup_idle_tx_channel (hrz_dev * dev, hrz_vcc * vcc) {
1494 unsigned short idle_channels;
1495 short tx_channel = -1;
1496 unsigned int spin_count;
1497 PRINTD (DBG_FLOW|DBG_TX, "setup_idle_tx_channel %p", dev);
1499 // better would be to fail immediately, the caller can then decide whether
1500 // to wait or drop (depending on whether this is UBR etc.)
1502 while (!(idle_channels = rd_regw (dev, TX_STATUS_OFF) & IDLE_CHANNELS_MASK)) {
1503 PRINTD (DBG_TX|DBG_WARN, "waiting for idle TX channel");
1505 if (++spin_count > 100) {
1506 PRINTD (DBG_TX|DBG_ERR, "spun out waiting for idle TX channel");
1511 // got an idle channel
1513 // tx_idle ensures we look for idle channels in RR order
1514 int chan = dev->tx_idle;
1517 while (keep_going) {
1518 if (idle_channels & (1<<chan)) {
1523 if (chan == TX_CHANS)
1527 dev->tx_idle = chan;
1530 // set up the channel we found
1532 // Initialise the cell header in the transmit channel descriptor
1533 // a.k.a. prepare the channel and remember that we have done so.
1535 tx_ch_desc * tx_desc = &memmap->tx_descs[tx_channel];
1538 u16 channel = vcc->channel;
1540 unsigned long flags;
1541 spin_lock_irqsave (&dev->mem_lock, flags);
1543 // Update the transmit channel record.
1544 dev->tx_channel_record[tx_channel] = channel;
1547 update_tx_channel_config (dev, tx_channel, RATE_TYPE_ACCESS,
1550 // Update the PCR counter preload value etc.
1551 update_tx_channel_config (dev, tx_channel, PCR_TIMER_ACCESS,
1555 if (vcc->tx_xbr_bits == VBR_RATE_TYPE) {
1557 update_tx_channel_config (dev, tx_channel, SCR_TIMER_ACCESS,
1561 update_tx_channel_config (dev, tx_channel, BUCKET_CAPACITY_ACCESS,
1562 vcc->tx_bucket_bits);
1565 update_tx_channel_config (dev, tx_channel, BUCKET_FULLNESS_ACCESS,
1566 vcc->tx_bucket_bits);
1570 // Initialise the read and write buffer pointers
1571 rd_ptr = rd_mem (dev, &tx_desc->rd_buf_type) & BUFFER_PTR_MASK;
1572 wr_ptr = rd_mem (dev, &tx_desc->wr_buf_type) & BUFFER_PTR_MASK;
1574 // idle TX channels should have identical pointers
1575 if (rd_ptr != wr_ptr) {
1576 PRINTD (DBG_TX|DBG_ERR, "TX buffer pointers are broken!");
1577 // spin_unlock... return -E...
1578 // I wonder if gcc would get rid of one of the pointer aliases
1580 PRINTD (DBG_TX, "TX buffer pointers are: rd %x, wr %x.",
1585 PRINTD (DBG_QOS|DBG_TX, "tx_channel: aal0");
1586 rd_ptr |= CHANNEL_TYPE_RAW_CELLS;
1587 wr_ptr |= CHANNEL_TYPE_RAW_CELLS;
1590 PRINTD (DBG_QOS|DBG_TX, "tx_channel: aal34");
1591 rd_ptr |= CHANNEL_TYPE_AAL3_4;
1592 wr_ptr |= CHANNEL_TYPE_AAL3_4;
1595 rd_ptr |= CHANNEL_TYPE_AAL5;
1596 wr_ptr |= CHANNEL_TYPE_AAL5;
1597 // Initialise the CRC
1598 wr_mem (dev, &tx_desc->partial_crc, INITIAL_CRC);
1602 wr_mem (dev, &tx_desc->rd_buf_type, rd_ptr);
1603 wr_mem (dev, &tx_desc->wr_buf_type, wr_ptr);
1605 // Write the Cell Header
1606 // Payload Type, CLP and GFC would go here if non-zero
1607 wr_mem (dev, &tx_desc->cell_header, channel);
1609 spin_unlock_irqrestore (&dev->mem_lock, flags);
1615 /********** send a frame **********/
1617 static int hrz_send (struct atm_vcc * atm_vcc, struct sk_buff * skb) {
1618 unsigned int spin_count;
1620 hrz_dev * dev = HRZ_DEV(atm_vcc->dev);
1621 hrz_vcc * vcc = HRZ_VCC(atm_vcc);
1622 u16 channel = vcc->channel;
1624 u32 buffers_required;
1626 /* signed for error return */
1629 PRINTD (DBG_FLOW|DBG_TX, "hrz_send vc %x data %p len %u",
1630 channel, skb->data, skb->len);
1632 dump_skb (">>>", channel, skb);
1634 if (atm_vcc->qos.txtp.traffic_class == ATM_NONE) {
1635 PRINTK (KERN_ERR, "attempt to send on RX-only VC %x", channel);
1636 hrz_kfree_skb (skb);
1640 // don't understand this
1641 ATM_SKB(skb)->vcc = atm_vcc;
1643 if (skb->len > atm_vcc->qos.txtp.max_sdu) {
1644 PRINTK (KERN_ERR, "sk_buff length greater than agreed max_sdu, dropping...");
1645 hrz_kfree_skb (skb);
1650 PRINTD (DBG_ERR|DBG_TX, "attempt to transmit on zero (rx_)channel");
1651 hrz_kfree_skb (skb);
1657 // where would be a better place for this? housekeeping?
1659 pci_read_config_word (dev->pci_dev, PCI_STATUS, &status);
1660 if (status & PCI_STATUS_REC_MASTER_ABORT) {
1661 PRINTD (DBG_BUS|DBG_ERR, "Clearing PCI Master Abort (and cleaning up)");
1662 status &= ~PCI_STATUS_REC_MASTER_ABORT;
1663 pci_write_config_word (dev->pci_dev, PCI_STATUS, status);
1664 if (test_bit (tx_busy, &dev->flags)) {
1665 hrz_kfree_skb (dev->tx_skb);
1672 #ifdef DEBUG_HORIZON
1674 if (channel == 1023) {
1676 unsigned short d = 0;
1677 char * s = skb->data;
1679 for (i = 0; i < 4; ++i) {
1680 d = (d<<4) | ((*s <= '9') ? (*s - '0') : (*s - 'a' + 10));
1683 PRINTK (KERN_INFO, "debug bitmap is now %hx", debug = d);
1688 // wait until TX is free and grab lock
1689 if (tx_hold (dev)) {
1690 hrz_kfree_skb (skb);
1691 return -ERESTARTSYS;
1694 // Wait for enough space to be available in transmit buffer memory.
1696 // should be number of cells needed + 2 (according to hardware docs)
1697 // = ((framelen+8)+47) / 48 + 2
1698 // = (framelen+7) / 48 + 3, hmm... faster to put addition inside XXX
1699 buffers_required = (skb->len+(ATM_AAL5_TRAILER-1)) / ATM_CELL_PAYLOAD + 3;
1701 // replace with timer and sleep, add dev->tx_buffers_queue (max 1 entry)
1703 while ((free_buffers = rd_regw (dev, TX_FREE_BUFFER_COUNT_OFF)) < buffers_required) {
1704 PRINTD (DBG_TX, "waiting for free TX buffers, got %d of %d",
1705 free_buffers, buffers_required);
1706 // what is the appropriate delay? implement a timeout? (depending on line speed?)
1708 // what happens if we kill (current_pid, SIGKILL) ?
1710 if (++spin_count > 1000) {
1711 PRINTD (DBG_TX|DBG_ERR, "spun out waiting for tx buffers, got %d of %d",
1712 free_buffers, buffers_required);
1714 hrz_kfree_skb (skb);
1715 return -ERESTARTSYS;
1719 // Select a channel to transmit the frame on.
1720 if (channel == dev->last_vc) {
1721 PRINTD (DBG_TX, "last vc hack: hit");
1722 tx_channel = dev->tx_last;
1724 PRINTD (DBG_TX, "last vc hack: miss");
1725 // Are we currently transmitting this VC on one of the channels?
1726 for (tx_channel = 0; tx_channel < TX_CHANS; ++tx_channel)
1727 if (dev->tx_channel_record[tx_channel] == channel) {
1728 PRINTD (DBG_TX, "vc already on channel: hit");
1731 if (tx_channel == TX_CHANS) {
1732 PRINTD (DBG_TX, "vc already on channel: miss");
1733 // Find and set up an idle channel.
1734 tx_channel = setup_idle_tx_channel (dev, vcc);
1735 if (tx_channel < 0) {
1736 PRINTD (DBG_TX|DBG_ERR, "failed to get channel");
1742 PRINTD (DBG_TX, "got channel");
1743 SELECT_TX_CHANNEL(dev, tx_channel);
1745 dev->last_vc = channel;
1746 dev->tx_last = tx_channel;
1749 PRINTD (DBG_TX, "using channel %u", tx_channel);
1751 YELLOW_LED_OFF(dev);
1753 // TX start transfer
1756 unsigned int tx_len = skb->len;
1757 unsigned int tx_iovcnt = skb_shinfo(skb)->nr_frags;
1758 // remember this so we can free it later
1762 // scatter gather transfer
1763 dev->tx_regions = tx_iovcnt;
1764 dev->tx_iovec = NULL; /* @@@ needs rewritten */
1766 PRINTD (DBG_TX|DBG_BUS, "TX start scatter-gather transfer (iovec %p, len %d)",
1769 hrz_kfree_skb (skb);
1773 dev->tx_regions = 0;
1774 dev->tx_iovec = NULL;
1775 dev->tx_bytes = tx_len;
1776 dev->tx_addr = skb->data;
1777 PRINTD (DBG_TX|DBG_BUS, "TX start simple transfer (addr %p, len %d)",
1781 // and do the business
1782 tx_schedule (dev, 0);
1789 /********** reset a card **********/
1791 static void hrz_reset (const hrz_dev * dev) {
1792 u32 control_0_reg = rd_regl (dev, CONTROL_0_REG);
1794 // why not set RESET_HORIZON to one and wait for the card to
1795 // reassert that bit as zero? Like so:
1796 control_0_reg = control_0_reg & RESET_HORIZON;
1797 wr_regl (dev, CONTROL_0_REG, control_0_reg);
1798 while (control_0_reg & RESET_HORIZON)
1799 control_0_reg = rd_regl (dev, CONTROL_0_REG);
1801 // old reset code retained:
1802 wr_regl (dev, CONTROL_0_REG, control_0_reg |
1803 RESET_ATM | RESET_RX | RESET_TX | RESET_HOST);
1804 // just guessing here
1807 wr_regl (dev, CONTROL_0_REG, control_0_reg);
1810 /********** read the burnt in address **********/
1812 static inline void WRITE_IT_WAIT (const hrz_dev *dev, u32 ctrl)
1814 wr_regl (dev, CONTROL_0_REG, ctrl);
1818 static inline void CLOCK_IT (const hrz_dev *dev, u32 ctrl)
1820 // DI must be valid around rising SK edge
1821 WRITE_IT_WAIT(dev, ctrl & ~SEEPROM_SK);
1822 WRITE_IT_WAIT(dev, ctrl | SEEPROM_SK);
1825 static u16 __init read_bia (const hrz_dev * dev, u16 addr)
1827 u32 ctrl = rd_regl (dev, CONTROL_0_REG);
1829 const unsigned int addr_bits = 6;
1830 const unsigned int data_bits = 16;
1836 ctrl &= ~(SEEPROM_CS | SEEPROM_SK | SEEPROM_DI);
1837 WRITE_IT_WAIT(dev, ctrl);
1839 // wake Serial EEPROM and send 110 (READ) command
1840 ctrl |= (SEEPROM_CS | SEEPROM_DI);
1841 CLOCK_IT(dev, ctrl);
1844 CLOCK_IT(dev, ctrl);
1846 ctrl &= ~SEEPROM_DI;
1847 CLOCK_IT(dev, ctrl);
1849 for (i=0; i<addr_bits; i++) {
1850 if (addr & (1 << (addr_bits-1)))
1853 ctrl &= ~SEEPROM_DI;
1855 CLOCK_IT(dev, ctrl);
1860 // we could check that we have DO = 0 here
1861 ctrl &= ~SEEPROM_DI;
1864 for (i=0;i<data_bits;i++) {
1867 CLOCK_IT(dev, ctrl);
1869 if (rd_regl (dev, CONTROL_0_REG) & SEEPROM_DO)
1870 res |= (1 << (data_bits-1));
1873 ctrl &= ~(SEEPROM_SK | SEEPROM_CS);
1874 WRITE_IT_WAIT(dev, ctrl);
1879 /********** initialise a card **********/
1881 static int __init hrz_init (hrz_dev * dev) {
1895 ctrl = rd_regl (dev, CONTROL_0_REG);
1896 PRINTD (DBG_INFO, "ctrl0reg is %#x", ctrl);
1897 onefivefive = ctrl & ATM_LAYER_STATUS;
1900 printk (DEV_LABEL ": Horizon Ultra (at 155.52 MBps)");
1902 printk (DEV_LABEL ": Horizon (at 25 MBps)");
1905 // Reset the card to get everything in a known state
1910 // Clear all the buffer memory
1912 printk (" clearing memory");
1914 for (mem = (HDW *) memmap; mem < (HDW *) (memmap + 1); ++mem)
1915 wr_mem (dev, mem, 0);
1917 printk (" tx channels");
1919 // All transmit eight channels are set up as AAL5 ABR channels with
1920 // a 16us cell spacing. Why?
1922 // Channel 0 gets the free buffer at 100h, channel 1 gets the free
1923 // buffer at 110h etc.
1925 for (chan = 0; chan < TX_CHANS; ++chan) {
1926 tx_ch_desc * tx_desc = &memmap->tx_descs[chan];
1927 cell_buf * buf = &memmap->inittxbufs[chan];
1929 // initialise the read and write buffer pointers
1930 wr_mem (dev, &tx_desc->rd_buf_type, BUF_PTR(buf));
1931 wr_mem (dev, &tx_desc->wr_buf_type, BUF_PTR(buf));
1933 // set the status of the initial buffers to empty
1934 wr_mem (dev, &buf->next, BUFF_STATUS_EMPTY);
1937 // Use space bufn3 at the moment for tx buffers
1939 printk (" tx buffers");
1941 tx_desc = memmap->bufn3;
1943 wr_mem (dev, &memmap->txfreebufstart.next, BUF_PTR(tx_desc) | BUFF_STATUS_EMPTY);
1945 for (buff_count = 0; buff_count < BUFN3_SIZE-1; buff_count++) {
1946 wr_mem (dev, &tx_desc->next, BUF_PTR(tx_desc+1) | BUFF_STATUS_EMPTY);
1950 wr_mem (dev, &tx_desc->next, BUF_PTR(&memmap->txfreebufend) | BUFF_STATUS_EMPTY);
1952 // Initialise the transmit free buffer count
1953 wr_regw (dev, TX_FREE_BUFFER_COUNT_OFF, BUFN3_SIZE);
1955 printk (" rx channels");
1957 // Initialise all of the receive channels to be AAL5 disabled with
1958 // an interrupt threshold of 0
1960 for (chan = 0; chan < RX_CHANS; ++chan) {
1961 rx_ch_desc * rx_desc = &memmap->rx_descs[chan];
1963 wr_mem (dev, &rx_desc->wr_buf_type, CHANNEL_TYPE_AAL5 | RX_CHANNEL_DISABLED);
1966 printk (" rx buffers");
1968 // Use space bufn4 at the moment for rx buffers
1970 rx_desc = memmap->bufn4;
1972 wr_mem (dev, &memmap->rxfreebufstart.next, BUF_PTR(rx_desc) | BUFF_STATUS_EMPTY);
1974 for (buff_count = 0; buff_count < BUFN4_SIZE-1; buff_count++) {
1975 wr_mem (dev, &rx_desc->next, BUF_PTR(rx_desc+1) | BUFF_STATUS_EMPTY);
1980 wr_mem (dev, &rx_desc->next, BUF_PTR(&memmap->rxfreebufend) | BUFF_STATUS_EMPTY);
1982 // Initialise the receive free buffer count
1983 wr_regw (dev, RX_FREE_BUFFER_COUNT_OFF, BUFN4_SIZE);
1985 // Initialize Horizons registers
1988 wr_regw (dev, TX_CONFIG_OFF,
1989 ABR_ROUND_ROBIN | TX_NORMAL_OPERATION | DRVR_DRVRBAR_ENABLE);
1991 // RX config. Use 10-x VC bits, x VP bits, non user cells in channel 0.
1992 wr_regw (dev, RX_CONFIG_OFF,
1993 DISCARD_UNUSED_VPI_VCI_BITS_SET | NON_USER_CELLS_IN_ONE_CHANNEL | vpi_bits);
1996 wr_regw (dev, RX_LINE_CONFIG_OFF,
1997 LOCK_DETECT_ENABLE | FREQUENCY_DETECT_ENABLE | GXTALOUT_SELECT_DIV4);
1999 // Set the max AAL5 cell count to be just enough to contain the
2000 // largest AAL5 frame that the user wants to receive
2001 wr_regw (dev, MAX_AAL5_CELL_COUNT_OFF,
2002 (max_rx_size + ATM_AAL5_TRAILER + ATM_CELL_PAYLOAD - 1) / ATM_CELL_PAYLOAD);
2005 wr_regw (dev, RX_CONFIG_OFF, rd_regw (dev, RX_CONFIG_OFF) | RX_ENABLE);
2007 printk (" control");
2009 // Drive the OE of the LEDs then turn the green LED on
2010 ctrl |= GREEN_LED_OE | YELLOW_LED_OE | GREEN_LED | YELLOW_LED;
2011 wr_regl (dev, CONTROL_0_REG, ctrl);
2013 // Test for a 155-capable card
2016 // Select 155 mode... make this a choice (or: how do we detect
2017 // external line speed and switch?)
2018 ctrl |= ATM_LAYER_SELECT;
2019 wr_regl (dev, CONTROL_0_REG, ctrl);
2021 // test SUNI-lite vs SAMBA
2023 // Register 0x00 in the SUNI will have some of bits 3-7 set, and
2024 // they will always be zero for the SAMBA. Ha! Bloody hardware
2025 // engineers. It'll never work.
2027 if (rd_framer (dev, 0) & 0x00f0) {
2031 // Reset, just in case
2032 wr_framer (dev, 0x00, 0x0080);
2033 wr_framer (dev, 0x00, 0x0000);
2035 // Configure transmit FIFO
2036 wr_framer (dev, 0x63, rd_framer (dev, 0x63) | 0x0002);
2038 // Set line timed mode
2039 wr_framer (dev, 0x05, rd_framer (dev, 0x05) | 0x0001);
2044 // Reset, just in case
2045 wr_framer (dev, 0, rd_framer (dev, 0) | 0x0001);
2046 wr_framer (dev, 0, rd_framer (dev, 0) &~ 0x0001);
2048 // Turn off diagnostic loopback and enable line-timed mode
2049 wr_framer (dev, 0, 0x0002);
2051 // Turn on transmit outputs
2052 wr_framer (dev, 2, 0x0B80);
2056 ctrl &= ~ATM_LAYER_SELECT;
2072 u8 * esi = dev->atm_dev->esi;
2074 // in the card I have, EEPROM
2075 // addresses 0, 1, 2 contain 0
2076 // addresess 5, 6 etc. contain ffff
2077 // NB: Madge prefix is 00 00 f6 (which is 00 00 6f in Ethernet bit order)
2078 // the read_bia routine gets the BIA in Ethernet bit order
2080 for (i=0; i < ESI_LEN; ++i) {
2082 b = read_bia (dev, i/2 + 2);
2086 printk ("%02x", esi[i]);
2090 // Enable RX_Q and ?X_COMPLETE interrupts only
2091 wr_regl (dev, INT_ENABLE_REG_OFF, INTERESTING_INTERRUPTS);
2099 /********** check max_sdu **********/
2101 static int check_max_sdu (hrz_aal aal, struct atm_trafprm * tp, unsigned int max_frame_size) {
2102 PRINTD (DBG_FLOW|DBG_QOS, "check_max_sdu");
2106 if (!(tp->max_sdu)) {
2107 PRINTD (DBG_QOS, "defaulting max_sdu");
2108 tp->max_sdu = ATM_AAL0_SDU;
2109 } else if (tp->max_sdu != ATM_AAL0_SDU) {
2110 PRINTD (DBG_QOS|DBG_ERR, "rejecting max_sdu");
2115 if (tp->max_sdu == 0 || tp->max_sdu > ATM_MAX_AAL34_PDU) {
2116 PRINTD (DBG_QOS, "%sing max_sdu", tp->max_sdu ? "capp" : "default");
2117 tp->max_sdu = ATM_MAX_AAL34_PDU;
2121 if (tp->max_sdu == 0 || tp->max_sdu > max_frame_size) {
2122 PRINTD (DBG_QOS, "%sing max_sdu", tp->max_sdu ? "capp" : "default");
2123 tp->max_sdu = max_frame_size;
2130 /********** check pcr **********/
2132 // something like this should be part of ATM Linux
2133 static int atm_pcr_check (struct atm_trafprm * tp, unsigned int pcr) {
2134 // we are assuming non-UBR, and non-special values of pcr
2135 if (tp->min_pcr == ATM_MAX_PCR)
2136 PRINTD (DBG_QOS, "luser gave min_pcr = ATM_MAX_PCR");
2137 else if (tp->min_pcr < 0)
2138 PRINTD (DBG_QOS, "luser gave negative min_pcr");
2139 else if (tp->min_pcr && tp->min_pcr > pcr)
2140 PRINTD (DBG_QOS, "pcr less than min_pcr");
2142 // !! max_pcr = UNSPEC (0) is equivalent to max_pcr = MAX (-1)
2143 // easier to #define ATM_MAX_PCR 0 and have all rates unsigned?
2144 // [this would get rid of next two conditionals]
2145 if ((0) && tp->max_pcr == ATM_MAX_PCR)
2146 PRINTD (DBG_QOS, "luser gave max_pcr = ATM_MAX_PCR");
2147 else if ((tp->max_pcr != ATM_MAX_PCR) && tp->max_pcr < 0)
2148 PRINTD (DBG_QOS, "luser gave negative max_pcr");
2149 else if (tp->max_pcr && tp->max_pcr != ATM_MAX_PCR && tp->max_pcr < pcr)
2150 PRINTD (DBG_QOS, "pcr greater than max_pcr");
2152 // each limit unspecified or not violated
2153 PRINTD (DBG_QOS, "xBR(pcr) OK");
2156 PRINTD (DBG_QOS, "pcr=%u, tp: min_pcr=%d, pcr=%d, max_pcr=%d",
2157 pcr, tp->min_pcr, tp->pcr, tp->max_pcr);
2161 /********** open VC **********/
2163 static int hrz_open (struct atm_vcc *atm_vcc)
2168 struct atm_qos * qos;
2169 struct atm_trafprm * txtp;
2170 struct atm_trafprm * rxtp;
2172 hrz_dev * dev = HRZ_DEV(atm_vcc->dev);
2174 hrz_vcc * vccp; // allocated late
2175 short vpi = atm_vcc->vpi;
2176 int vci = atm_vcc->vci;
2177 PRINTD (DBG_FLOW|DBG_VCC, "hrz_open %x %x", vpi, vci);
2179 #ifdef ATM_VPI_UNSPEC
2180 // UNSPEC is deprecated, remove this code eventually
2181 if (vpi == ATM_VPI_UNSPEC || vci == ATM_VCI_UNSPEC) {
2182 PRINTK (KERN_WARNING, "rejecting open with unspecified VPI/VCI (deprecated)");
2187 error = vpivci_to_channel (&channel, vpi, vci);
2189 PRINTD (DBG_WARN|DBG_VCC, "VPI/VCI out of range: %hd/%d", vpi, vci);
2193 vcc.channel = channel;
2194 // max speed for the moment
2197 qos = &atm_vcc->qos;
2199 // check AAL and remember it
2202 // we would if it were 48 bytes and not 52!
2203 PRINTD (DBG_QOS|DBG_VCC, "AAL0");
2207 // we would if I knew how do the SAR!
2208 PRINTD (DBG_QOS|DBG_VCC, "AAL3/4");
2212 PRINTD (DBG_QOS|DBG_VCC, "AAL5");
2216 PRINTD (DBG_QOS|DBG_VCC, "Bad AAL!");
2221 // TX traffic parameters
2223 // there are two, interrelated problems here: 1. the reservation of
2224 // PCR is not a binary choice, we are given bounds and/or a
2225 // desirable value; 2. the device is only capable of certain values,
2226 // most of which are not integers. It is almost certainly acceptable
2227 // to be off by a maximum of 1 to 10 cps.
2229 // Pragmatic choice: always store an integral PCR as that which has
2230 // been allocated, even if we allocate a little (or a lot) less,
2231 // after rounding. The actual allocation depends on what we can
2232 // manage with our rate selection algorithm. The rate selection
2233 // algorithm is given an integral PCR and a tolerance and told
2234 // whether it should round the value up or down if the tolerance is
2235 // exceeded; it returns: a) the actual rate selected (rounded up to
2236 // the nearest integer), b) a bit pattern to feed to the timer
2237 // register, and c) a failure value if no applicable rate exists.
2239 // Part of the job is done by atm_pcr_goal which gives us a PCR
2240 // specification which says: EITHER grab the maximum available PCR
2241 // (and perhaps a lower bound which we musn't pass), OR grab this
2242 // amount, rounding down if you have to (and perhaps a lower bound
2243 // which we musn't pass) OR grab this amount, rounding up if you
2244 // have to (and perhaps an upper bound which we musn't pass). If any
2245 // bounds ARE passed we fail. Note that rounding is only rounding to
2246 // match device limitations, we do not round down to satisfy
2247 // bandwidth availability even if this would not violate any given
2250 // Note: telephony = 64kb/s = 48 byte cell payload @ 500/3 cells/s
2251 // (say) so this is not even a binary fixpoint cell rate (but this
2252 // device can do it). To avoid this sort of hassle we use a
2253 // tolerance parameter (currently fixed at 10 cps).
2255 PRINTD (DBG_QOS, "TX:");
2259 // set up defaults for no traffic
2261 // who knows what would actually happen if you try and send on this?
2262 vcc.tx_xbr_bits = IDLE_RATE_TYPE;
2263 vcc.tx_pcr_bits = CLOCK_DISABLE;
2265 vcc.tx_scr_bits = CLOCK_DISABLE;
2266 vcc.tx_bucket_bits = 0;
2269 if (txtp->traffic_class != ATM_NONE) {
2270 error = check_max_sdu (vcc.aal, txtp, max_tx_size);
2272 PRINTD (DBG_QOS, "TX max_sdu check failed");
2276 switch (txtp->traffic_class) {
2278 // we take "the PCR" as a rate-cap
2281 make_rate (dev, 1<<30, round_nearest, &vcc.tx_pcr_bits, NULL);
2282 vcc.tx_xbr_bits = ABR_RATE_TYPE;
2287 // reserve min, allow up to max
2288 vcc.tx_rate = 0; // ?
2289 make_rate (dev, 1<<30, round_nearest, &vcc.tx_pcr_bits, 0);
2290 vcc.tx_xbr_bits = ABR_RATE_TYPE;
2295 int pcr = atm_pcr_goal (txtp);
2298 // down vs. up, remaining bandwidth vs. unlimited bandwidth!!
2299 // should really have: once someone gets unlimited bandwidth
2300 // that no more non-UBR channels can be opened until the
2301 // unlimited one closes?? For the moment, round_down means
2302 // greedy people actually get something and not nothing
2304 // slight race (no locking) here so we may get -EAGAIN
2305 // later; the greedy bastards would deserve it :)
2306 PRINTD (DBG_QOS, "snatching all remaining TX bandwidth");
2307 pcr = dev->tx_avail;
2308 } else if (pcr < 0) {
2314 error = make_rate_with_tolerance (dev, pcr, r, 10,
2315 &vcc.tx_pcr_bits, &vcc.tx_rate);
2317 PRINTD (DBG_QOS, "could not make rate from TX PCR");
2320 // not really clear what further checking is needed
2321 error = atm_pcr_check (txtp, vcc.tx_rate);
2323 PRINTD (DBG_QOS, "TX PCR failed consistency check");
2326 vcc.tx_xbr_bits = CBR_RATE_TYPE;
2331 int pcr = atm_pcr_goal (txtp);
2332 // int scr = atm_scr_goal (txtp);
2333 int scr = pcr/2; // just for fun
2334 unsigned int mbs = 60; // just for fun
2337 unsigned int bucket;
2341 } else if (pcr < 0) {
2347 error = make_rate_with_tolerance (dev, pcr, pr, 10,
2348 &vcc.tx_pcr_bits, 0);
2350 // see comments for PCR with CBR above
2352 // slight race (no locking) here so we may get -EAGAIN
2353 // later; the greedy bastards would deserve it :)
2354 PRINTD (DBG_QOS, "snatching all remaining TX bandwidth");
2355 scr = dev->tx_avail;
2356 } else if (scr < 0) {
2362 error = make_rate_with_tolerance (dev, scr, sr, 10,
2363 &vcc.tx_scr_bits, &vcc.tx_rate);
2365 PRINTD (DBG_QOS, "could not make rate from TX SCR");
2368 // not really clear what further checking is needed
2369 // error = atm_scr_check (txtp, vcc.tx_rate);
2371 PRINTD (DBG_QOS, "TX SCR failed consistency check");
2374 // bucket calculations (from a piece of paper...) cell bucket
2375 // capacity must be largest integer smaller than m(p-s)/p + 1
2376 // where m = max burst size, p = pcr, s = scr
2377 bucket = mbs*(pcr-scr)/pcr;
2378 if (bucket*pcr != mbs*(pcr-scr))
2380 if (bucket > BUCKET_MAX_SIZE) {
2381 PRINTD (DBG_QOS, "shrinking bucket from %u to %u",
2382 bucket, BUCKET_MAX_SIZE);
2383 bucket = BUCKET_MAX_SIZE;
2385 vcc.tx_xbr_bits = VBR_RATE_TYPE;
2386 vcc.tx_bucket_bits = bucket;
2391 PRINTD (DBG_QOS, "unsupported TX traffic class");
2398 // RX traffic parameters
2400 PRINTD (DBG_QOS, "RX:");
2404 // set up defaults for no traffic
2407 if (rxtp->traffic_class != ATM_NONE) {
2408 error = check_max_sdu (vcc.aal, rxtp, max_rx_size);
2410 PRINTD (DBG_QOS, "RX max_sdu check failed");
2413 switch (rxtp->traffic_class) {
2421 vcc.rx_rate = 0; // ?
2426 int pcr = atm_pcr_goal (rxtp);
2428 // slight race (no locking) here so we may get -EAGAIN
2429 // later; the greedy bastards would deserve it :)
2430 PRINTD (DBG_QOS, "snatching all remaining RX bandwidth");
2431 pcr = dev->rx_avail;
2432 } else if (pcr < 0) {
2436 // not really clear what further checking is needed
2437 error = atm_pcr_check (rxtp, vcc.rx_rate);
2439 PRINTD (DBG_QOS, "RX PCR failed consistency check");
2446 // int scr = atm_scr_goal (rxtp);
2447 int scr = 1<<16; // just for fun
2449 // slight race (no locking) here so we may get -EAGAIN
2450 // later; the greedy bastards would deserve it :)
2451 PRINTD (DBG_QOS, "snatching all remaining RX bandwidth");
2452 scr = dev->rx_avail;
2453 } else if (scr < 0) {
2457 // not really clear what further checking is needed
2458 // error = atm_scr_check (rxtp, vcc.rx_rate);
2460 PRINTD (DBG_QOS, "RX SCR failed consistency check");
2467 PRINTD (DBG_QOS, "unsupported RX traffic class");
2475 // late abort useful for diagnostics
2476 if (vcc.aal != aal5) {
2477 PRINTD (DBG_QOS, "AAL not supported");
2481 // get space for our vcc stuff and copy parameters into it
2482 vccp = kmalloc (sizeof(hrz_vcc), GFP_KERNEL);
2484 PRINTK (KERN_ERR, "out of memory!");
2489 // clear error and grab cell rate resource lock
2491 spin_lock (&dev->rate_lock);
2493 if (vcc.tx_rate > dev->tx_avail) {
2494 PRINTD (DBG_QOS, "not enough TX PCR left");
2498 if (vcc.rx_rate > dev->rx_avail) {
2499 PRINTD (DBG_QOS, "not enough RX PCR left");
2504 // really consume cell rates
2505 dev->tx_avail -= vcc.tx_rate;
2506 dev->rx_avail -= vcc.rx_rate;
2507 PRINTD (DBG_QOS|DBG_VCC, "reserving %u TX PCR and %u RX PCR",
2508 vcc.tx_rate, vcc.rx_rate);
2511 // release lock and exit on error
2512 spin_unlock (&dev->rate_lock);
2514 PRINTD (DBG_QOS|DBG_VCC, "insufficient cell rate resources");
2519 // this is "immediately before allocating the connection identifier
2520 // in hardware" - so long as the next call does not fail :)
2521 set_bit(ATM_VF_ADDR,&atm_vcc->flags);
2523 // any errors here are very serious and should never occur
2525 if (rxtp->traffic_class != ATM_NONE) {
2526 if (dev->rxer[channel]) {
2527 PRINTD (DBG_ERR|DBG_VCC, "VC already open for RX");
2531 error = hrz_open_rx (dev, channel);
2536 // this link allows RX frames through
2537 dev->rxer[channel] = atm_vcc;
2540 // success, set elements of atm_vcc
2541 atm_vcc->dev_data = (void *) vccp;
2543 // indicate readiness
2544 set_bit(ATM_VF_READY,&atm_vcc->flags);
2549 /********** close VC **********/
2551 static void hrz_close (struct atm_vcc * atm_vcc) {
2552 hrz_dev * dev = HRZ_DEV(atm_vcc->dev);
2553 hrz_vcc * vcc = HRZ_VCC(atm_vcc);
2554 u16 channel = vcc->channel;
2555 PRINTD (DBG_VCC|DBG_FLOW, "hrz_close");
2557 // indicate unreadiness
2558 clear_bit(ATM_VF_READY,&atm_vcc->flags);
2560 if (atm_vcc->qos.txtp.traffic_class != ATM_NONE) {
2563 // let any TX on this channel that has started complete
2564 // no restart, just keep trying
2565 while (tx_hold (dev))
2567 // remove record of any tx_channel having been setup for this channel
2568 for (i = 0; i < TX_CHANS; ++i)
2569 if (dev->tx_channel_record[i] == channel) {
2570 dev->tx_channel_record[i] = -1;
2573 if (dev->last_vc == channel)
2578 if (atm_vcc->qos.rxtp.traffic_class != ATM_NONE) {
2579 // disable RXing - it tries quite hard
2580 hrz_close_rx (dev, channel);
2581 // forget the vcc - no more skbs will be pushed
2582 if (atm_vcc != dev->rxer[channel])
2583 PRINTK (KERN_ERR, "%s atm_vcc=%p rxer[channel]=%p",
2584 "arghhh! we're going to die!",
2585 atm_vcc, dev->rxer[channel]);
2586 dev->rxer[channel] = NULL;
2589 // atomically release our rate reservation
2590 spin_lock (&dev->rate_lock);
2591 PRINTD (DBG_QOS|DBG_VCC, "releasing %u TX PCR and %u RX PCR",
2592 vcc->tx_rate, vcc->rx_rate);
2593 dev->tx_avail += vcc->tx_rate;
2594 dev->rx_avail += vcc->rx_rate;
2595 spin_unlock (&dev->rate_lock);
2597 // free our structure
2599 // say the VPI/VCI is free again
2600 clear_bit(ATM_VF_ADDR,&atm_vcc->flags);
2604 static int hrz_getsockopt (struct atm_vcc * atm_vcc, int level, int optname,
2605 void *optval, int optlen) {
2606 hrz_dev * dev = HRZ_DEV(atm_vcc->dev);
2607 PRINTD (DBG_FLOW|DBG_VCC, "hrz_getsockopt");
2616 return -ENOPROTOOPT;
2624 static int hrz_setsockopt (struct atm_vcc * atm_vcc, int level, int optname,
2625 void *optval, int optlen) {
2626 hrz_dev * dev = HRZ_DEV(atm_vcc->dev);
2627 PRINTD (DBG_FLOW|DBG_VCC, "hrz_setsockopt");
2636 return -ENOPROTOOPT;
2646 static int hrz_ioctl (struct atm_dev * atm_dev, unsigned int cmd, void *arg) {
2647 hrz_dev * dev = HRZ_DEV(atm_dev);
2648 PRINTD (DBG_FLOW, "hrz_ioctl");
2652 unsigned char hrz_phy_get (struct atm_dev * atm_dev, unsigned long addr) {
2653 hrz_dev * dev = HRZ_DEV(atm_dev);
2654 PRINTD (DBG_FLOW, "hrz_phy_get");
2658 static void hrz_phy_put (struct atm_dev * atm_dev, unsigned char value,
2659 unsigned long addr) {
2660 hrz_dev * dev = HRZ_DEV(atm_dev);
2661 PRINTD (DBG_FLOW, "hrz_phy_put");
2664 static int hrz_change_qos (struct atm_vcc * atm_vcc, struct atm_qos *qos, int flgs) {
2665 hrz_dev * dev = HRZ_DEV(vcc->dev);
2666 PRINTD (DBG_FLOW, "hrz_change_qos");
2671 /********** proc file contents **********/
2673 static int hrz_proc_read (struct atm_dev * atm_dev, loff_t * pos, char * page) {
2674 hrz_dev * dev = HRZ_DEV(atm_dev);
2676 PRINTD (DBG_FLOW, "hrz_proc_read");
2678 /* more diagnostics here? */
2682 unsigned int count = sprintf (page, "vbr buckets:");
2684 for (i = 0; i < TX_CHANS; ++i)
2685 count += sprintf (page, " %u/%u",
2686 query_tx_channel_config (dev, i, BUCKET_FULLNESS_ACCESS),
2687 query_tx_channel_config (dev, i, BUCKET_CAPACITY_ACCESS));
2688 count += sprintf (page+count, ".\n");
2694 return sprintf (page,
2695 "cells: TX %lu, RX %lu, HEC errors %lu, unassigned %lu.\n",
2696 dev->tx_cell_count, dev->rx_cell_count,
2697 dev->hec_error_count, dev->unassigned_cell_count);
2700 return sprintf (page,
2701 "free cell buffers: TX %hu, RX %hu+%hu.\n",
2702 rd_regw (dev, TX_FREE_BUFFER_COUNT_OFF),
2703 rd_regw (dev, RX_FREE_BUFFER_COUNT_OFF),
2704 dev->noof_spare_buffers);
2707 return sprintf (page,
2708 "cps remaining: TX %u, RX %u\n",
2709 dev->tx_avail, dev->rx_avail);
2714 static const struct atmdev_ops hrz_ops = {
2718 .proc_read = hrz_proc_read,
2719 .owner = THIS_MODULE,
2722 static int __init hrz_probe (void) {
2723 struct pci_dev * pci_dev;
2726 PRINTD (DBG_FLOW, "hrz_probe");
2730 while ((pci_dev = pci_find_device
2731 (PCI_VENDOR_ID_MADGE, PCI_DEVICE_ID_MADGE_HORIZON, pci_dev)
2735 // adapter slot free, read resources from PCI configuration space
2736 u32 iobase = pci_resource_start (pci_dev, 0);
2737 u32 * membase = bus_to_virt (pci_resource_start (pci_dev, 1));
2738 u8 irq = pci_dev->irq;
2740 /* XXX DEV_LABEL is a guess */
2741 if (!request_region (iobase, HRZ_IO_EXTENT, DEV_LABEL))
2744 if (pci_enable_device (pci_dev))
2747 dev = kmalloc (sizeof(hrz_dev), GFP_KERNEL);
2749 // perhaps we should be nice: deregister all adapters and abort?
2750 PRINTD (DBG_ERR, "out of memory");
2754 memset (dev, 0, sizeof(hrz_dev));
2756 // grab IRQ and install handler - move this someplace more sensible
2757 if (request_irq (irq,
2759 SA_SHIRQ, /* irqflags guess */
2760 DEV_LABEL, /* name guess */
2762 PRINTD (DBG_WARN, "request IRQ failed!");
2763 // free_irq is at "endif"
2766 PRINTD (DBG_INFO, "found Madge ATM adapter (hrz) at: IO %x, IRQ %u, MEM %p",
2767 iobase, irq, membase);
2769 dev->atm_dev = atm_dev_register (DEV_LABEL, &hrz_ops, -1, NULL);
2770 if (!(dev->atm_dev)) {
2771 PRINTD (DBG_ERR, "failed to register Madge ATM adapter");
2775 PRINTD (DBG_INFO, "registered Madge ATM adapter (no. %d) (%p) at %p",
2776 dev->atm_dev->number, dev, dev->atm_dev);
2777 dev->atm_dev->dev_data = (void *) dev;
2778 dev->pci_dev = pci_dev;
2780 // enable bus master accesses
2781 pci_set_master (pci_dev);
2783 // frobnicate latency (upwards, usually)
2784 pci_read_config_byte (pci_dev, PCI_LATENCY_TIMER, &lat);
2786 PRINTD (DBG_INFO, "%s PCI latency timer from %hu to %hu",
2787 "changing", lat, pci_lat);
2788 pci_write_config_byte (pci_dev, PCI_LATENCY_TIMER, pci_lat);
2789 } else if (lat < MIN_PCI_LATENCY) {
2790 PRINTK (KERN_INFO, "%s PCI latency timer from %hu to %hu",
2791 "increasing", lat, MIN_PCI_LATENCY);
2792 pci_write_config_byte (pci_dev, PCI_LATENCY_TIMER, MIN_PCI_LATENCY);
2795 dev->iobase = iobase;
2797 dev->membase = membase;
2799 dev->rx_q_entry = dev->rx_q_reset = &memmap->rx_q_entries[0];
2800 dev->rx_q_wrap = &memmap->rx_q_entries[RX_CHANS-1];
2802 // these next three are performance hacks
2807 dev->tx_regions = 0;
2810 dev->tx_iovec = NULL;
2812 dev->tx_cell_count = 0;
2813 dev->rx_cell_count = 0;
2814 dev->hec_error_count = 0;
2815 dev->unassigned_cell_count = 0;
2817 dev->noof_spare_buffers = 0;
2821 for (i = 0; i < TX_CHANS; ++i)
2822 dev->tx_channel_record[i] = -1;
2827 // Allocate cell rates and remember ASIC version
2828 // Fibre: ATM_OC3_PCR = 1555200000/8/270*260/53 - 29/53
2829 // Copper: (WRONG) we want 6 into the above, close to 25Mb/s
2830 // Copper: (plagarise!) 25600000/8/270*260/53 - n/53
2832 if (hrz_init (dev)) {
2833 // to be really pedantic, this should be ATM_OC3c_PCR
2834 dev->tx_avail = ATM_OC3_PCR;
2835 dev->rx_avail = ATM_OC3_PCR;
2836 set_bit (ultra, &dev->flags); // NOT "|= ultra" !
2838 dev->tx_avail = ((25600000/8)*26)/(27*53);
2839 dev->rx_avail = ((25600000/8)*26)/(27*53);
2840 PRINTD (DBG_WARN, "Buggy ASIC: no TX bus-mastering.");
2843 // rate changes spinlock
2844 spin_lock_init (&dev->rate_lock);
2846 // on-board memory access spinlock; we want atomic reads and
2847 // writes to adapter memory (handles IRQ and SMP)
2848 spin_lock_init (&dev->mem_lock);
2850 init_waitqueue_head (&dev->tx_queue);
2852 // vpi in 0..4, vci in 6..10
2853 dev->atm_dev->ci_range.vpi_bits = vpi_bits;
2854 dev->atm_dev->ci_range.vci_bits = 10-vpi_bits;
2856 // update count and linked list
2858 dev->prev = hrz_devs;
2863 /* not currently reached */
2864 atm_dev_deregister (dev->atm_dev);
2865 } /* atm_dev_register */
2866 free_irq (irq, dev);
2870 release_region(iobase, HRZ_IO_EXTENT);
2871 } /* kmalloc and while */
2875 static void __init hrz_check_args (void) {
2876 #ifdef DEBUG_HORIZON
2877 PRINTK (KERN_NOTICE, "debug bitmap is %hx", debug &= DBG_MASK);
2880 PRINTK (KERN_NOTICE, "no debug support in this image");
2883 if (vpi_bits > HRZ_MAX_VPI)
2884 PRINTK (KERN_ERR, "vpi_bits has been limited to %hu",
2885 vpi_bits = HRZ_MAX_VPI);
2887 if (max_tx_size < 0 || max_tx_size > TX_AAL5_LIMIT)
2888 PRINTK (KERN_NOTICE, "max_tx_size has been limited to %hu",
2889 max_tx_size = TX_AAL5_LIMIT);
2891 if (max_rx_size < 0 || max_rx_size > RX_AAL5_LIMIT)
2892 PRINTK (KERN_NOTICE, "max_rx_size has been limited to %hu",
2893 max_rx_size = RX_AAL5_LIMIT);
2898 MODULE_AUTHOR(maintainer_string);
2899 MODULE_DESCRIPTION(description_string);
2900 MODULE_LICENSE("GPL");
2901 MODULE_PARM(debug, "h");
2902 MODULE_PARM(vpi_bits, "h");
2903 MODULE_PARM(max_tx_size, "i");
2904 MODULE_PARM(max_rx_size, "i");
2905 MODULE_PARM(pci_lat, "b");
2906 MODULE_PARM_DESC(debug, "debug bitmap, see .h file");
2907 MODULE_PARM_DESC(vpi_bits, "number of bits (0..4) to allocate to VPIs");
2908 MODULE_PARM_DESC(max_tx_size, "maximum size of TX AAL5 frames");
2909 MODULE_PARM_DESC(max_rx_size, "maximum size of RX AAL5 frames");
2910 MODULE_PARM_DESC(pci_lat, "PCI latency in bus cycles");
2912 /********** module entry **********/
2914 static int __init hrz_module_init (void) {
2917 // sanity check - cast is needed since printk does not support %Zu
2918 if (sizeof(struct MEMMAP) != 128*1024/4) {
2919 PRINTK (KERN_ERR, "Fix struct MEMMAP (is %lu fakewords).",
2920 (unsigned long) sizeof(struct MEMMAP));
2933 init_timer (&housekeeping);
2934 housekeeping.function = do_housekeeping;
2936 housekeeping.data = 1;
2937 set_timer (&housekeeping, 0);
2939 PRINTK (KERN_ERR, "no (usable) adapters found");
2942 return devs ? 0 : -ENODEV;
2945 /********** module exit **********/
2947 static void __exit hrz_module_exit (void) {
2949 PRINTD (DBG_FLOW, "cleanup_module");
2952 housekeeping.data = 0;
2953 del_timer (&housekeeping);
2957 hrz_devs = dev->prev;
2959 PRINTD (DBG_INFO, "closing %p (atm_dev = %p)", dev, dev->atm_dev);
2961 atm_dev_deregister (dev->atm_dev);
2962 free_irq (dev->irq, dev);
2963 release_region (dev->iobase, HRZ_IO_EXTENT);
2970 module_init(hrz_module_init);
2971 module_exit(hrz_module_exit);