1 /*******************************************************************
2 * ident "$Id: idt77252.c,v 1.2 2001/11/11 08:13:54 ecd Exp $"
5 * $Date: 2001/11/11 08:13:54 $
7 * Copyright (c) 2000 ATecoM GmbH
9 * The author may be reached at ecd@atecom.com.
11 * This program is free software; you can redistribute it and/or modify it
12 * under the terms of the GNU General Public License as published by the
13 * Free Software Foundation; either version 2 of the License, or (at your
14 * option) any later version.
16 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
17 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
18 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
19 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
21 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
22 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
23 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
24 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
25 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 * You should have received a copy of the GNU General Public License along
28 * with this program; if not, write to the Free Software Foundation, Inc.,
29 * 675 Mass Ave, Cambridge, MA 02139, USA.
31 *******************************************************************/
32 static char const rcsid[] =
33 "$Id: idt77252.c,v 1.2 2001/11/11 08:13:54 ecd Exp $";
36 #include <linux/module.h>
37 #include <linux/config.h>
38 #include <linux/pci.h>
39 #include <linux/skbuff.h>
40 #include <linux/kernel.h>
41 #include <linux/vmalloc.h>
42 #include <linux/netdevice.h>
43 #include <linux/atmdev.h>
44 #include <linux/atm.h>
45 #include <linux/delay.h>
46 #include <linux/init.h>
47 #include <linux/bitops.h>
48 #include <linux/wait.h>
49 #include <asm/semaphore.h>
51 #include <asm/uaccess.h>
52 #include <asm/atomic.h>
53 #include <asm/byteorder.h>
55 #ifdef CONFIG_ATM_IDT77252_USE_SUNI
57 #endif /* CONFIG_ATM_IDT77252_USE_SUNI */
61 #include "idt77252_tables.h"
63 static unsigned int vpibits = 1;
66 #define CONFIG_ATM_IDT77252_SEND_IDLE 1
72 #define DEBUG_MODULE 1
73 #undef HAVE_EEPROM /* does not work, yet. */
75 #ifdef CONFIG_ATM_IDT77252_DEBUG
76 static unsigned long debug = DBG_GENERAL;
80 #define SAR_RX_DELAY (SAR_CFG_RXINT_NODELAY)
86 static struct scq_info *alloc_scq(struct idt77252_dev *, int);
87 static void free_scq(struct idt77252_dev *, struct scq_info *);
88 static int queue_skb(struct idt77252_dev *, struct vc_map *,
89 struct sk_buff *, int oam);
90 static void drain_scq(struct idt77252_dev *, struct vc_map *);
91 static unsigned long get_free_scd(struct idt77252_dev *, struct vc_map *);
92 static void fill_scd(struct idt77252_dev *, struct scq_info *, int);
97 static int push_rx_skb(struct idt77252_dev *,
98 struct sk_buff *, int queue);
99 static void recycle_rx_skb(struct idt77252_dev *, struct sk_buff *);
100 static void flush_rx_pool(struct idt77252_dev *, struct rx_pool *);
101 static void recycle_rx_pool_skb(struct idt77252_dev *,
103 static void add_rx_skb(struct idt77252_dev *, int queue,
104 unsigned int size, unsigned int count);
109 static int init_rsq(struct idt77252_dev *);
110 static void deinit_rsq(struct idt77252_dev *);
111 static void idt77252_rx(struct idt77252_dev *);
116 static int init_tsq(struct idt77252_dev *);
117 static void deinit_tsq(struct idt77252_dev *);
118 static void idt77252_tx(struct idt77252_dev *);
124 static void idt77252_dev_close(struct atm_dev *dev);
125 static int idt77252_open(struct atm_vcc *vcc);
126 static void idt77252_close(struct atm_vcc *vcc);
127 static int idt77252_send(struct atm_vcc *vcc, struct sk_buff *skb);
128 static int idt77252_send_oam(struct atm_vcc *vcc, void *cell,
130 static void idt77252_phy_put(struct atm_dev *dev, unsigned char value,
132 static unsigned char idt77252_phy_get(struct atm_dev *dev, unsigned long addr);
133 static int idt77252_change_qos(struct atm_vcc *vcc, struct atm_qos *qos,
135 static int idt77252_proc_read(struct atm_dev *dev, loff_t * pos,
137 static void idt77252_softint(void *dev_id);
140 static struct atmdev_ops idt77252_ops =
142 .dev_close = idt77252_dev_close,
143 .open = idt77252_open,
144 .close = idt77252_close,
145 .send = idt77252_send,
146 .send_oam = idt77252_send_oam,
147 .phy_put = idt77252_phy_put,
148 .phy_get = idt77252_phy_get,
149 .change_qos = idt77252_change_qos,
150 .proc_read = idt77252_proc_read,
154 static struct idt77252_dev *idt77252_chain = NULL;
155 static unsigned int idt77252_sram_write_errors = 0;
157 /*****************************************************************************/
159 /* I/O and Utility Bus */
161 /*****************************************************************************/
164 waitfor_idle(struct idt77252_dev *card)
168 stat = readl(SAR_REG_STAT);
169 while (stat & SAR_STAT_CMDBZ)
170 stat = readl(SAR_REG_STAT);
174 read_sram(struct idt77252_dev *card, unsigned long addr)
179 spin_lock_irqsave(&card->cmd_lock, flags);
180 writel(SAR_CMD_READ_SRAM | (addr << 2), SAR_REG_CMD);
182 value = readl(SAR_REG_DR0);
183 spin_unlock_irqrestore(&card->cmd_lock, flags);
188 write_sram(struct idt77252_dev *card, unsigned long addr, u32 value)
192 if ((idt77252_sram_write_errors == 0) &&
193 (((addr > card->tst[0] + card->tst_size - 2) &&
194 (addr < card->tst[0] + card->tst_size)) ||
195 ((addr > card->tst[1] + card->tst_size - 2) &&
196 (addr < card->tst[1] + card->tst_size)))) {
197 printk("%s: ERROR: TST JMP section at %08lx written: %08x\n",
198 card->name, addr, value);
201 spin_lock_irqsave(&card->cmd_lock, flags);
202 writel(value, SAR_REG_DR0);
203 writel(SAR_CMD_WRITE_SRAM | (addr << 2), SAR_REG_CMD);
205 spin_unlock_irqrestore(&card->cmd_lock, flags);
209 read_utility(void *dev, unsigned long ubus_addr)
211 struct idt77252_dev *card = dev;
216 printk("Error: No such device.\n");
220 spin_lock_irqsave(&card->cmd_lock, flags);
221 writel(SAR_CMD_READ_UTILITY + ubus_addr, SAR_REG_CMD);
223 value = readl(SAR_REG_DR0);
224 spin_unlock_irqrestore(&card->cmd_lock, flags);
229 write_utility(void *dev, unsigned long ubus_addr, u8 value)
231 struct idt77252_dev *card = dev;
235 printk("Error: No such device.\n");
239 spin_lock_irqsave(&card->cmd_lock, flags);
240 writel((u32) value, SAR_REG_DR0);
241 writel(SAR_CMD_WRITE_UTILITY + ubus_addr, SAR_REG_CMD);
243 spin_unlock_irqrestore(&card->cmd_lock, flags);
247 static u32 rdsrtab[] =
249 SAR_GP_EECS | SAR_GP_EESCLK,
251 SAR_GP_EESCLK, /* 0 */
253 SAR_GP_EESCLK, /* 0 */
255 SAR_GP_EESCLK, /* 0 */
257 SAR_GP_EESCLK, /* 0 */
259 SAR_GP_EESCLK, /* 0 */
261 SAR_GP_EESCLK | SAR_GP_EEDO, /* 1 */
263 SAR_GP_EESCLK, /* 0 */
265 SAR_GP_EESCLK | SAR_GP_EEDO /* 1 */
268 static u32 wrentab[] =
270 SAR_GP_EECS | SAR_GP_EESCLK,
272 SAR_GP_EESCLK, /* 0 */
274 SAR_GP_EESCLK, /* 0 */
276 SAR_GP_EESCLK, /* 0 */
278 SAR_GP_EESCLK, /* 0 */
280 SAR_GP_EESCLK | SAR_GP_EEDO, /* 1 */
282 SAR_GP_EESCLK | SAR_GP_EEDO, /* 1 */
284 SAR_GP_EESCLK, /* 0 */
286 SAR_GP_EESCLK /* 0 */
291 SAR_GP_EECS | SAR_GP_EESCLK,
293 SAR_GP_EESCLK, /* 0 */
295 SAR_GP_EESCLK, /* 0 */
297 SAR_GP_EESCLK, /* 0 */
299 SAR_GP_EESCLK, /* 0 */
301 SAR_GP_EESCLK, /* 0 */
303 SAR_GP_EESCLK, /* 0 */
305 SAR_GP_EESCLK | SAR_GP_EEDO, /* 1 */
307 SAR_GP_EESCLK | SAR_GP_EEDO /* 1 */
312 SAR_GP_EECS | SAR_GP_EESCLK,
314 SAR_GP_EESCLK, /* 0 */
316 SAR_GP_EESCLK, /* 0 */
318 SAR_GP_EESCLK, /* 0 */
320 SAR_GP_EESCLK, /* 0 */
322 SAR_GP_EESCLK, /* 0 */
324 SAR_GP_EESCLK, /* 0 */
326 SAR_GP_EESCLK | SAR_GP_EEDO, /* 1 */
328 SAR_GP_EESCLK /* 0 */
331 static u32 clktab[] =
353 idt77252_read_gp(struct idt77252_dev *card)
357 gp = readl(SAR_REG_GP);
359 printk("RD: %s\n", gp & SAR_GP_EEDI ? "1" : "0");
365 idt77252_write_gp(struct idt77252_dev *card, u32 value)
370 printk("WR: %s %s %s\n", value & SAR_GP_EECS ? " " : "/CS",
371 value & SAR_GP_EESCLK ? "HIGH" : "LOW ",
372 value & SAR_GP_EEDO ? "1" : "0");
375 spin_lock_irqsave(&card->cmd_lock, flags);
377 writel(value, SAR_REG_GP);
378 spin_unlock_irqrestore(&card->cmd_lock, flags);
382 idt77252_eeprom_read_status(struct idt77252_dev *card)
388 gp = idt77252_read_gp(card) & ~(SAR_GP_EESCLK|SAR_GP_EECS|SAR_GP_EEDO);
390 for (i = 0; i < sizeof(rdsrtab)/sizeof(rdsrtab[0]); i++) {
391 idt77252_write_gp(card, gp | rdsrtab[i]);
394 idt77252_write_gp(card, gp | SAR_GP_EECS);
398 for (i = 0, j = 0; i < 8; i++) {
401 idt77252_write_gp(card, gp | clktab[j++]);
404 byte |= idt77252_read_gp(card) & SAR_GP_EEDI ? 1 : 0;
406 idt77252_write_gp(card, gp | clktab[j++]);
409 idt77252_write_gp(card, gp | SAR_GP_EECS);
416 idt77252_eeprom_read_byte(struct idt77252_dev *card, u8 offset)
422 gp = idt77252_read_gp(card) & ~(SAR_GP_EESCLK|SAR_GP_EECS|SAR_GP_EEDO);
424 for (i = 0; i < sizeof(rdtab)/sizeof(rdtab[0]); i++) {
425 idt77252_write_gp(card, gp | rdtab[i]);
428 idt77252_write_gp(card, gp | SAR_GP_EECS);
431 for (i = 0, j = 0; i < 8; i++) {
432 idt77252_write_gp(card, gp | clktab[j++] |
433 (offset & 1 ? SAR_GP_EEDO : 0));
436 idt77252_write_gp(card, gp | clktab[j++] |
437 (offset & 1 ? SAR_GP_EEDO : 0));
442 idt77252_write_gp(card, gp | SAR_GP_EECS);
446 for (i = 0, j = 0; i < 8; i++) {
449 idt77252_write_gp(card, gp | clktab[j++]);
452 byte |= idt77252_read_gp(card) & SAR_GP_EEDI ? 1 : 0;
454 idt77252_write_gp(card, gp | clktab[j++]);
457 idt77252_write_gp(card, gp | SAR_GP_EECS);
464 idt77252_eeprom_write_byte(struct idt77252_dev *card, u8 offset, u8 data)
469 gp = idt77252_read_gp(card) & ~(SAR_GP_EESCLK|SAR_GP_EECS|SAR_GP_EEDO);
471 for (i = 0; i < sizeof(wrentab)/sizeof(wrentab[0]); i++) {
472 idt77252_write_gp(card, gp | wrentab[i]);
475 idt77252_write_gp(card, gp | SAR_GP_EECS);
478 for (i = 0; i < sizeof(wrtab)/sizeof(wrtab[0]); i++) {
479 idt77252_write_gp(card, gp | wrtab[i]);
482 idt77252_write_gp(card, gp | SAR_GP_EECS);
485 for (i = 0, j = 0; i < 8; i++) {
486 idt77252_write_gp(card, gp | clktab[j++] |
487 (offset & 1 ? SAR_GP_EEDO : 0));
490 idt77252_write_gp(card, gp | clktab[j++] |
491 (offset & 1 ? SAR_GP_EEDO : 0));
496 idt77252_write_gp(card, gp | SAR_GP_EECS);
499 for (i = 0, j = 0; i < 8; i++) {
500 idt77252_write_gp(card, gp | clktab[j++] |
501 (data & 1 ? SAR_GP_EEDO : 0));
504 idt77252_write_gp(card, gp | clktab[j++] |
505 (data & 1 ? SAR_GP_EEDO : 0));
510 idt77252_write_gp(card, gp | SAR_GP_EECS);
515 idt77252_eeprom_init(struct idt77252_dev *card)
519 gp = idt77252_read_gp(card) & ~(SAR_GP_EESCLK|SAR_GP_EECS|SAR_GP_EEDO);
521 idt77252_write_gp(card, gp | SAR_GP_EECS | SAR_GP_EESCLK);
523 idt77252_write_gp(card, gp | SAR_GP_EECS);
525 idt77252_write_gp(card, gp | SAR_GP_EECS | SAR_GP_EESCLK);
527 idt77252_write_gp(card, gp | SAR_GP_EECS);
530 #endif /* HAVE_EEPROM */
533 #ifdef CONFIG_ATM_IDT77252_DEBUG
535 dump_tct(struct idt77252_dev *card, int index)
540 tct = (unsigned long) (card->tct_base + index * SAR_SRAM_TCT_SIZE);
542 printk("%s: TCT %x:", card->name, index);
543 for (i = 0; i < 8; i++) {
544 printk(" %08x", read_sram(card, tct + i));
550 idt77252_tx_dump(struct idt77252_dev *card)
556 printk("%s\n", __FUNCTION__);
557 for (i = 0; i < card->tct_size; i++) {
571 printk("%s: Connection %d:\n", card->name, vc->index);
572 dump_tct(card, vc->index);
578 /*****************************************************************************/
582 /*****************************************************************************/
585 sb_pool_add(struct idt77252_dev *card, struct sk_buff *skb, int queue)
587 struct sb_pool *pool = &card->sbpool[queue];
591 while (pool->skb[index]) {
592 index = (index + 1) & FBQ_MASK;
593 if (index == pool->index)
597 pool->skb[index] = skb;
598 IDT77252_PRV_POOL(skb) = POOL_HANDLE(queue, index);
600 pool->index = (index + 1) & FBQ_MASK;
605 sb_pool_remove(struct idt77252_dev *card, struct sk_buff *skb)
607 unsigned int queue, index;
610 handle = IDT77252_PRV_POOL(skb);
612 queue = POOL_QUEUE(handle);
616 index = POOL_INDEX(handle);
617 if (index > FBQ_SIZE - 1)
620 card->sbpool[queue].skb[index] = NULL;
623 static struct sk_buff *
624 sb_pool_skb(struct idt77252_dev *card, u32 handle)
626 unsigned int queue, index;
628 queue = POOL_QUEUE(handle);
632 index = POOL_INDEX(handle);
633 if (index > FBQ_SIZE - 1)
636 return card->sbpool[queue].skb[index];
639 static struct scq_info *
640 alloc_scq(struct idt77252_dev *card, int class)
642 struct scq_info *scq;
644 scq = (struct scq_info *) kmalloc(sizeof(struct scq_info), GFP_KERNEL);
647 memset(scq, 0, sizeof(struct scq_info));
649 scq->base = pci_alloc_consistent(card->pcidev, SCQ_SIZE,
651 if (scq->base == NULL) {
655 memset(scq->base, 0, SCQ_SIZE);
657 scq->next = scq->base;
658 scq->last = scq->base + (SCQ_ENTRIES - 1);
659 atomic_set(&scq->used, 0);
661 spin_lock_init(&scq->lock);
662 spin_lock_init(&scq->skblock);
664 skb_queue_head_init(&scq->transmit);
665 skb_queue_head_init(&scq->pending);
667 TXPRINTK("idt77252: SCQ: base 0x%p, next 0x%p, last 0x%p, paddr %08llx\n",
668 scq->base, scq->next, scq->last, (unsigned long long)scq->paddr);
674 free_scq(struct idt77252_dev *card, struct scq_info *scq)
679 pci_free_consistent(card->pcidev, SCQ_SIZE,
680 scq->base, scq->paddr);
682 while ((skb = skb_dequeue(&scq->transmit))) {
683 pci_unmap_single(card->pcidev, IDT77252_PRV_PADDR(skb),
684 skb->len, PCI_DMA_TODEVICE);
686 vcc = ATM_SKB(skb)->vcc;
693 while ((skb = skb_dequeue(&scq->pending))) {
694 pci_unmap_single(card->pcidev, IDT77252_PRV_PADDR(skb),
695 skb->len, PCI_DMA_TODEVICE);
697 vcc = ATM_SKB(skb)->vcc;
709 push_on_scq(struct idt77252_dev *card, struct vc_map *vc, struct sk_buff *skb)
711 struct scq_info *scq = vc->scq;
716 TXPRINTK("%s: SCQ: next 0x%p\n", card->name, scq->next);
718 atomic_inc(&scq->used);
719 entries = atomic_read(&scq->used);
720 if (entries > (SCQ_ENTRIES - 1)) {
721 atomic_dec(&scq->used);
725 skb_queue_tail(&scq->transmit, skb);
727 spin_lock_irqsave(&vc->lock, flags);
729 struct atm_vcc *vcc = vc->tx_vcc;
731 vc->estimator->cells += (skb->len + 47) / 48;
732 if (atomic_read(&vcc->sk->sk_wmem_alloc) >
733 (vcc->sk->sk_sndbuf >> 1)) {
734 u32 cps = vc->estimator->maxcps;
736 vc->estimator->cps = cps;
737 vc->estimator->avcps = cps << 5;
738 if (vc->lacr < vc->init_er) {
739 vc->lacr = vc->init_er;
740 writel(TCMDQ_LACR | (vc->lacr << 16) |
741 vc->index, SAR_REG_TCMDQ);
745 spin_unlock_irqrestore(&vc->lock, flags);
747 tbd = &IDT77252_PRV_TBD(skb);
749 spin_lock_irqsave(&scq->lock, flags);
750 scq->next->word_1 = cpu_to_le32(tbd->word_1 |
751 SAR_TBD_TSIF | SAR_TBD_GTSI);
752 scq->next->word_2 = cpu_to_le32(tbd->word_2);
753 scq->next->word_3 = cpu_to_le32(tbd->word_3);
754 scq->next->word_4 = cpu_to_le32(tbd->word_4);
756 if (scq->next == scq->last)
757 scq->next = scq->base;
761 write_sram(card, scq->scd,
763 (u32)((unsigned long)scq->next - (unsigned long)scq->base));
764 spin_unlock_irqrestore(&scq->lock, flags);
766 scq->trans_start = jiffies;
768 if (test_and_clear_bit(VCF_IDLE, &vc->flags)) {
769 writel(TCMDQ_START_LACR | (vc->lacr << 16) | vc->index,
773 TXPRINTK("%d entries in SCQ used (push).\n", atomic_read(&scq->used));
775 XPRINTK("%s: SCQ (after push %2d) head = 0x%x, next = 0x%p.\n",
776 card->name, atomic_read(&scq->used),
777 read_sram(card, scq->scd + 1), scq->next);
782 if (jiffies - scq->trans_start > HZ) {
783 printk("%s: Error pushing TBD for %d.%d\n",
784 card->name, vc->tx_vcc->vpi, vc->tx_vcc->vci);
785 #ifdef CONFIG_ATM_IDT77252_DEBUG
786 idt77252_tx_dump(card);
788 scq->trans_start = jiffies;
796 drain_scq(struct idt77252_dev *card, struct vc_map *vc)
798 struct scq_info *scq = vc->scq;
802 TXPRINTK("%s: SCQ (before drain %2d) next = 0x%p.\n",
803 card->name, atomic_read(&scq->used), scq->next);
805 skb = skb_dequeue(&scq->transmit);
807 TXPRINTK("%s: freeing skb at %p.\n", card->name, skb);
809 pci_unmap_single(card->pcidev, IDT77252_PRV_PADDR(skb),
810 skb->len, PCI_DMA_TODEVICE);
812 vcc = ATM_SKB(skb)->vcc;
819 atomic_inc(&vcc->stats->tx);
822 atomic_dec(&scq->used);
824 spin_lock(&scq->skblock);
825 while ((skb = skb_dequeue(&scq->pending))) {
826 if (push_on_scq(card, vc, skb)) {
827 skb_queue_head(&vc->scq->pending, skb);
831 spin_unlock(&scq->skblock);
835 queue_skb(struct idt77252_dev *card, struct vc_map *vc,
836 struct sk_buff *skb, int oam)
845 printk("%s: invalid skb->len (%d)\n", card->name, skb->len);
849 TXPRINTK("%s: Sending %d bytes of data.\n",
850 card->name, skb->len);
852 tbd = &IDT77252_PRV_TBD(skb);
853 vcc = ATM_SKB(skb)->vcc;
855 IDT77252_PRV_PADDR(skb) = pci_map_single(card->pcidev, skb->data,
856 skb->len, PCI_DMA_TODEVICE);
864 tbd->word_1 = SAR_TBD_OAM | ATM_CELL_PAYLOAD | SAR_TBD_EPDU;
865 tbd->word_2 = IDT77252_PRV_PADDR(skb) + 4;
866 tbd->word_3 = 0x00000000;
867 tbd->word_4 = (skb->data[0] << 24) | (skb->data[1] << 16) |
868 (skb->data[2] << 8) | (skb->data[3] << 0);
870 if (test_bit(VCF_RSV, &vc->flags))
876 if (test_bit(VCF_RSV, &vc->flags)) {
877 printk("%s: Trying to transmit on reserved VC\n", card->name);
890 tbd->word_1 = SAR_TBD_EPDU | SAR_TBD_AAL0 |
893 tbd->word_1 = SAR_TBD_EPDU | SAR_TBD_AAL34 |
896 tbd->word_2 = IDT77252_PRV_PADDR(skb) + 4;
897 tbd->word_3 = 0x00000000;
898 tbd->word_4 = (skb->data[0] << 24) | (skb->data[1] << 16) |
899 (skb->data[2] << 8) | (skb->data[3] << 0);
903 tbd->word_1 = SAR_TBD_EPDU | SAR_TBD_AAL5 | skb->len;
904 tbd->word_2 = IDT77252_PRV_PADDR(skb);
905 tbd->word_3 = skb->len;
906 tbd->word_4 = (vcc->vpi << SAR_TBD_VPI_SHIFT) |
907 (vcc->vci << SAR_TBD_VCI_SHIFT);
913 printk("%s: Traffic type not supported.\n", card->name);
914 error = -EPROTONOSUPPORT;
919 spin_lock_irqsave(&vc->scq->skblock, flags);
920 skb_queue_tail(&vc->scq->pending, skb);
922 while ((skb = skb_dequeue(&vc->scq->pending))) {
923 if (push_on_scq(card, vc, skb)) {
924 skb_queue_head(&vc->scq->pending, skb);
928 spin_unlock_irqrestore(&vc->scq->skblock, flags);
933 pci_unmap_single(card->pcidev, IDT77252_PRV_PADDR(skb),
934 skb->len, PCI_DMA_TODEVICE);
939 get_free_scd(struct idt77252_dev *card, struct vc_map *vc)
943 for (i = 0; i < card->scd_size; i++) {
944 if (!card->scd2vc[i]) {
945 card->scd2vc[i] = vc;
947 return card->scd_base + i * SAR_SRAM_SCD_SIZE;
954 fill_scd(struct idt77252_dev *card, struct scq_info *scq, int class)
956 write_sram(card, scq->scd, scq->paddr);
957 write_sram(card, scq->scd + 1, 0x00000000);
958 write_sram(card, scq->scd + 2, 0xffffffff);
959 write_sram(card, scq->scd + 3, 0x00000000);
963 clear_scd(struct idt77252_dev *card, struct scq_info *scq, int class)
968 /*****************************************************************************/
972 /*****************************************************************************/
975 init_rsq(struct idt77252_dev *card)
977 struct rsq_entry *rsqe;
979 card->rsq.base = pci_alloc_consistent(card->pcidev, RSQSIZE,
981 if (card->rsq.base == NULL) {
982 printk("%s: can't allocate RSQ.\n", card->name);
985 memset(card->rsq.base, 0, RSQSIZE);
987 card->rsq.last = card->rsq.base + RSQ_NUM_ENTRIES - 1;
988 card->rsq.next = card->rsq.last;
989 for (rsqe = card->rsq.base; rsqe <= card->rsq.last; rsqe++)
992 writel((unsigned long) card->rsq.last - (unsigned long) card->rsq.base,
994 writel(card->rsq.paddr, SAR_REG_RSQB);
996 IPRINTK("%s: RSQ base at 0x%lx (0x%x).\n", card->name,
997 (unsigned long) card->rsq.base,
998 readl(SAR_REG_RSQB));
999 IPRINTK("%s: RSQ head = 0x%x, base = 0x%x, tail = 0x%x.\n",
1001 readl(SAR_REG_RSQH),
1002 readl(SAR_REG_RSQB),
1003 readl(SAR_REG_RSQT));
1009 deinit_rsq(struct idt77252_dev *card)
1011 pci_free_consistent(card->pcidev, RSQSIZE,
1012 card->rsq.base, card->rsq.paddr);
1016 dequeue_rx(struct idt77252_dev *card, struct rsq_entry *rsqe)
1018 struct atm_vcc *vcc;
1019 struct sk_buff *skb;
1020 struct rx_pool *rpp;
1022 u32 header, vpi, vci;
1026 stat = le32_to_cpu(rsqe->word_4);
1028 if (stat & SAR_RSQE_IDLE) {
1029 RXPRINTK("%s: message about inactive connection.\n",
1034 skb = sb_pool_skb(card, le32_to_cpu(rsqe->word_2));
1036 printk("%s: NULL skb in %s, rsqe: %08x %08x %08x %08x\n",
1037 card->name, __FUNCTION__,
1038 le32_to_cpu(rsqe->word_1), le32_to_cpu(rsqe->word_2),
1039 le32_to_cpu(rsqe->word_3), le32_to_cpu(rsqe->word_4));
1043 header = le32_to_cpu(rsqe->word_1);
1044 vpi = (header >> 16) & 0x00ff;
1045 vci = (header >> 0) & 0xffff;
1047 RXPRINTK("%s: SDU for %d.%d received in buffer 0x%p (data 0x%p).\n",
1048 card->name, vpi, vci, skb, skb->data);
1050 if ((vpi >= (1 << card->vpibits)) || (vci != (vci & card->vcimask))) {
1051 printk("%s: SDU received for out-of-range vc %u.%u\n",
1052 card->name, vpi, vci);
1053 recycle_rx_skb(card, skb);
1057 vc = card->vcs[VPCI2VC(card, vpi, vci)];
1058 if (!vc || !test_bit(VCF_RX, &vc->flags)) {
1059 printk("%s: SDU received on non RX vc %u.%u\n",
1060 card->name, vpi, vci);
1061 recycle_rx_skb(card, skb);
1067 pci_dma_sync_single_for_cpu(card->pcidev, IDT77252_PRV_PADDR(skb),
1068 skb->end - skb->data, PCI_DMA_FROMDEVICE);
1070 if ((vcc->qos.aal == ATM_AAL0) ||
1071 (vcc->qos.aal == ATM_AAL34)) {
1073 unsigned char *cell;
1077 for (i = (stat & SAR_RSQE_CELLCNT); i; i--) {
1078 if ((sb = dev_alloc_skb(64)) == NULL) {
1079 printk("%s: Can't allocate buffers for aal0.\n",
1081 atomic_add(i, &vcc->stats->rx_drop);
1084 if (!atm_charge(vcc, sb->truesize)) {
1085 RXPRINTK("%s: atm_charge() dropped aal0 packets.\n",
1087 atomic_add(i - 1, &vcc->stats->rx_drop);
1091 aal0 = (vpi << ATM_HDR_VPI_SHIFT) |
1092 (vci << ATM_HDR_VCI_SHIFT);
1093 aal0 |= (stat & SAR_RSQE_EPDU) ? 0x00000002 : 0;
1094 aal0 |= (stat & SAR_RSQE_CLP) ? 0x00000001 : 0;
1096 *((u32 *) sb->data) = aal0;
1097 skb_put(sb, sizeof(u32));
1098 memcpy(skb_put(sb, ATM_CELL_PAYLOAD),
1099 cell, ATM_CELL_PAYLOAD);
1101 ATM_SKB(sb)->vcc = vcc;
1102 do_gettimeofday(&sb->stamp);
1104 atomic_inc(&vcc->stats->rx);
1106 cell += ATM_CELL_PAYLOAD;
1109 recycle_rx_skb(card, skb);
1112 if (vcc->qos.aal != ATM_AAL5) {
1113 printk("%s: Unexpected AAL type in dequeue_rx(): %d.\n",
1114 card->name, vcc->qos.aal);
1115 recycle_rx_skb(card, skb);
1118 skb->len = (stat & SAR_RSQE_CELLCNT) * ATM_CELL_PAYLOAD;
1120 rpp = &vc->rcv.rx_pool;
1122 rpp->len += skb->len;
1126 rpp->last = &skb->next;
1128 if (stat & SAR_RSQE_EPDU) {
1129 unsigned char *l1l2;
1132 l1l2 = (unsigned char *) ((unsigned long) skb->data + skb->len - 6);
1134 len = (l1l2[0] << 8) | l1l2[1];
1135 len = len ? len : 0x10000;
1137 RXPRINTK("%s: PDU has %d bytes.\n", card->name, len);
1139 if ((len + 8 > rpp->len) || (len + (47 + 8) < rpp->len)) {
1140 RXPRINTK("%s: AAL5 PDU size mismatch: %d != %d. "
1142 card->name, len, rpp->len, readl(SAR_REG_CDC));
1143 recycle_rx_pool_skb(card, rpp);
1144 atomic_inc(&vcc->stats->rx_err);
1147 if (stat & SAR_RSQE_CRC) {
1148 RXPRINTK("%s: AAL5 CRC error.\n", card->name);
1149 recycle_rx_pool_skb(card, rpp);
1150 atomic_inc(&vcc->stats->rx_err);
1153 if (rpp->count > 1) {
1156 skb = dev_alloc_skb(rpp->len);
1158 RXPRINTK("%s: Can't alloc RX skb.\n",
1160 recycle_rx_pool_skb(card, rpp);
1161 atomic_inc(&vcc->stats->rx_err);
1164 if (!atm_charge(vcc, skb->truesize)) {
1165 recycle_rx_pool_skb(card, rpp);
1170 for (i = 0; i < rpp->count; i++) {
1171 memcpy(skb_put(skb, sb->len),
1176 recycle_rx_pool_skb(card, rpp);
1179 ATM_SKB(skb)->vcc = vcc;
1180 do_gettimeofday(&skb->stamp);
1182 vcc->push(vcc, skb);
1183 atomic_inc(&vcc->stats->rx);
1189 flush_rx_pool(card, rpp);
1191 if (!atm_charge(vcc, skb->truesize)) {
1192 recycle_rx_skb(card, skb);
1196 pci_unmap_single(card->pcidev, IDT77252_PRV_PADDR(skb),
1197 skb->end - skb->data, PCI_DMA_FROMDEVICE);
1198 sb_pool_remove(card, skb);
1201 ATM_SKB(skb)->vcc = vcc;
1202 do_gettimeofday(&skb->stamp);
1204 vcc->push(vcc, skb);
1205 atomic_inc(&vcc->stats->rx);
1207 if (skb->truesize > SAR_FB_SIZE_3)
1208 add_rx_skb(card, 3, SAR_FB_SIZE_3, 1);
1209 else if (skb->truesize > SAR_FB_SIZE_2)
1210 add_rx_skb(card, 2, SAR_FB_SIZE_2, 1);
1211 else if (skb->truesize > SAR_FB_SIZE_1)
1212 add_rx_skb(card, 1, SAR_FB_SIZE_1, 1);
1214 add_rx_skb(card, 0, SAR_FB_SIZE_0, 1);
1220 idt77252_rx(struct idt77252_dev *card)
1222 struct rsq_entry *rsqe;
1224 if (card->rsq.next == card->rsq.last)
1225 rsqe = card->rsq.base;
1227 rsqe = card->rsq.next + 1;
1229 if (!(le32_to_cpu(rsqe->word_4) & SAR_RSQE_VALID)) {
1230 RXPRINTK("%s: no entry in RSQ.\n", card->name);
1235 dequeue_rx(card, rsqe);
1237 card->rsq.next = rsqe;
1238 if (card->rsq.next == card->rsq.last)
1239 rsqe = card->rsq.base;
1241 rsqe = card->rsq.next + 1;
1242 } while (le32_to_cpu(rsqe->word_4) & SAR_RSQE_VALID);
1244 writel((unsigned long) card->rsq.next - (unsigned long) card->rsq.base,
1249 idt77252_rx_raw(struct idt77252_dev *card)
1251 struct sk_buff *queue;
1253 struct atm_vcc *vcc;
1257 if (card->raw_cell_head == NULL) {
1258 u32 handle = le32_to_cpu(*(card->raw_cell_hnd + 1));
1259 card->raw_cell_head = sb_pool_skb(card, handle);
1262 queue = card->raw_cell_head;
1266 head = IDT77252_PRV_PADDR(queue) + (queue->data - queue->head - 16);
1267 tail = readl(SAR_REG_RAWCT);
1269 pci_dma_sync_single_for_cpu(card->pcidev, IDT77252_PRV_PADDR(queue),
1270 queue->end - queue->head - 16,
1271 PCI_DMA_FROMDEVICE);
1273 while (head != tail) {
1274 unsigned int vpi, vci, pti;
1277 header = le32_to_cpu(*(u32 *) &queue->data[0]);
1279 vpi = (header & ATM_HDR_VPI_MASK) >> ATM_HDR_VPI_SHIFT;
1280 vci = (header & ATM_HDR_VCI_MASK) >> ATM_HDR_VCI_SHIFT;
1281 pti = (header & ATM_HDR_PTI_MASK) >> ATM_HDR_PTI_SHIFT;
1283 #ifdef CONFIG_ATM_IDT77252_DEBUG
1284 if (debug & DBG_RAW_CELL) {
1287 printk("%s: raw cell %x.%02x.%04x.%x.%x\n",
1288 card->name, (header >> 28) & 0x000f,
1289 (header >> 20) & 0x00ff,
1290 (header >> 4) & 0xffff,
1291 (header >> 1) & 0x0007,
1292 (header >> 0) & 0x0001);
1293 for (i = 16; i < 64; i++)
1294 printk(" %02x", queue->data[i]);
1299 if (vpi >= (1<<card->vpibits) || vci >= (1<<card->vcibits)) {
1300 RPRINTK("%s: SDU received for out-of-range vc %u.%u\n",
1301 card->name, vpi, vci);
1305 vc = card->vcs[VPCI2VC(card, vpi, vci)];
1306 if (!vc || !test_bit(VCF_RX, &vc->flags)) {
1307 RPRINTK("%s: SDU received on non RX vc %u.%u\n",
1308 card->name, vpi, vci);
1314 if (vcc->qos.aal != ATM_AAL0) {
1315 RPRINTK("%s: raw cell for non AAL0 vc %u.%u\n",
1316 card->name, vpi, vci);
1317 atomic_inc(&vcc->stats->rx_drop);
1321 if ((sb = dev_alloc_skb(64)) == NULL) {
1322 printk("%s: Can't allocate buffers for AAL0.\n",
1324 atomic_inc(&vcc->stats->rx_err);
1328 if ((vcc->sk != NULL) && !atm_charge(vcc, sb->truesize)) {
1329 RXPRINTK("%s: atm_charge() dropped AAL0 packets.\n",
1335 *((u32 *) sb->data) = header;
1336 skb_put(sb, sizeof(u32));
1337 memcpy(skb_put(sb, ATM_CELL_PAYLOAD), &(queue->data[16]),
1340 ATM_SKB(sb)->vcc = vcc;
1341 do_gettimeofday(&sb->stamp);
1343 atomic_inc(&vcc->stats->rx);
1346 skb_pull(queue, 64);
1348 head = IDT77252_PRV_PADDR(queue)
1349 + (queue->data - queue->head - 16);
1351 if (queue->len < 128) {
1352 struct sk_buff *next;
1355 head = le32_to_cpu(*(u32 *) &queue->data[0]);
1356 handle = le32_to_cpu(*(u32 *) &queue->data[4]);
1358 next = sb_pool_skb(card, handle);
1359 recycle_rx_skb(card, queue);
1362 card->raw_cell_head = next;
1363 queue = card->raw_cell_head;
1364 pci_dma_sync_single_for_cpu(card->pcidev,
1365 IDT77252_PRV_PADDR(queue),
1366 queue->end - queue->data,
1367 PCI_DMA_FROMDEVICE);
1369 card->raw_cell_head = NULL;
1370 printk("%s: raw cell queue overrun\n",
1379 /*****************************************************************************/
1383 /*****************************************************************************/
1386 init_tsq(struct idt77252_dev *card)
1388 struct tsq_entry *tsqe;
1390 card->tsq.base = pci_alloc_consistent(card->pcidev, RSQSIZE,
1392 if (card->tsq.base == NULL) {
1393 printk("%s: can't allocate TSQ.\n", card->name);
1396 memset(card->tsq.base, 0, TSQSIZE);
1398 card->tsq.last = card->tsq.base + TSQ_NUM_ENTRIES - 1;
1399 card->tsq.next = card->tsq.last;
1400 for (tsqe = card->tsq.base; tsqe <= card->tsq.last; tsqe++)
1401 tsqe->word_2 = cpu_to_le32(SAR_TSQE_INVALID);
1403 writel(card->tsq.paddr, SAR_REG_TSQB);
1404 writel((unsigned long) card->tsq.next - (unsigned long) card->tsq.base,
1411 deinit_tsq(struct idt77252_dev *card)
1413 pci_free_consistent(card->pcidev, TSQSIZE,
1414 card->tsq.base, card->tsq.paddr);
1418 idt77252_tx(struct idt77252_dev *card)
1420 struct tsq_entry *tsqe;
1421 unsigned int vpi, vci;
1425 if (card->tsq.next == card->tsq.last)
1426 tsqe = card->tsq.base;
1428 tsqe = card->tsq.next + 1;
1430 TXPRINTK("idt77252_tx: tsq %p: base %p, next %p, last %p\n", tsqe,
1431 card->tsq.base, card->tsq.next, card->tsq.last);
1432 TXPRINTK("idt77252_tx: tsqb %08x, tsqt %08x, tsqh %08x, \n",
1433 readl(SAR_REG_TSQB),
1434 readl(SAR_REG_TSQT),
1435 readl(SAR_REG_TSQH));
1437 stat = le32_to_cpu(tsqe->word_2);
1439 if (stat & SAR_TSQE_INVALID)
1443 TXPRINTK("tsqe: 0x%p [0x%08x 0x%08x]\n", tsqe,
1444 le32_to_cpu(tsqe->word_1),
1445 le32_to_cpu(tsqe->word_2));
1447 switch (stat & SAR_TSQE_TYPE) {
1448 case SAR_TSQE_TYPE_TIMER:
1449 TXPRINTK("%s: Timer RollOver detected.\n", card->name);
1452 case SAR_TSQE_TYPE_IDLE:
1454 conn = le32_to_cpu(tsqe->word_1);
1456 if (SAR_TSQE_TAG(stat) == 0x10) {
1458 printk("%s: Connection %d halted.\n",
1460 le32_to_cpu(tsqe->word_1) & 0x1fff);
1465 vc = card->vcs[conn & 0x1fff];
1467 printk("%s: could not find VC from conn %d\n",
1468 card->name, conn & 0x1fff);
1472 printk("%s: Connection %d IDLE.\n",
1473 card->name, vc->index);
1475 set_bit(VCF_IDLE, &vc->flags);
1478 case SAR_TSQE_TYPE_TSR:
1480 conn = le32_to_cpu(tsqe->word_1);
1482 vc = card->vcs[conn & 0x1fff];
1484 printk("%s: no VC at index %d\n",
1486 le32_to_cpu(tsqe->word_1) & 0x1fff);
1490 drain_scq(card, vc);
1493 case SAR_TSQE_TYPE_TBD_COMP:
1495 conn = le32_to_cpu(tsqe->word_1);
1497 vpi = (conn >> SAR_TBD_VPI_SHIFT) & 0x00ff;
1498 vci = (conn >> SAR_TBD_VCI_SHIFT) & 0xffff;
1500 if (vpi >= (1 << card->vpibits) ||
1501 vci >= (1 << card->vcibits)) {
1502 printk("%s: TBD complete: "
1503 "out of range VPI.VCI %u.%u\n",
1504 card->name, vpi, vci);
1508 vc = card->vcs[VPCI2VC(card, vpi, vci)];
1510 printk("%s: TBD complete: "
1511 "no VC at VPI.VCI %u.%u\n",
1512 card->name, vpi, vci);
1516 drain_scq(card, vc);
1520 tsqe->word_2 = cpu_to_le32(SAR_TSQE_INVALID);
1522 card->tsq.next = tsqe;
1523 if (card->tsq.next == card->tsq.last)
1524 tsqe = card->tsq.base;
1526 tsqe = card->tsq.next + 1;
1528 TXPRINTK("tsqe: %p: base %p, next %p, last %p\n", tsqe,
1529 card->tsq.base, card->tsq.next, card->tsq.last);
1531 stat = le32_to_cpu(tsqe->word_2);
1533 } while (!(stat & SAR_TSQE_INVALID));
1535 writel((unsigned long)card->tsq.next - (unsigned long)card->tsq.base,
1538 XPRINTK("idt77252_tx-after writel%d: TSQ head = 0x%x, tail = 0x%x, next = 0x%p.\n",
1539 card->index, readl(SAR_REG_TSQH),
1540 readl(SAR_REG_TSQT), card->tsq.next);
1545 tst_timer(unsigned long data)
1547 struct idt77252_dev *card = (struct idt77252_dev *)data;
1548 unsigned long base, idle, jump;
1549 unsigned long flags;
1553 spin_lock_irqsave(&card->tst_lock, flags);
1555 base = card->tst[card->tst_index];
1556 idle = card->tst[card->tst_index ^ 1];
1558 if (test_bit(TST_SWITCH_WAIT, &card->tst_state)) {
1559 jump = base + card->tst_size - 2;
1561 pc = readl(SAR_REG_NOW) >> 2;
1562 if ((pc ^ idle) & ~(card->tst_size - 1)) {
1563 mod_timer(&card->tst_timer, jiffies + 1);
1567 clear_bit(TST_SWITCH_WAIT, &card->tst_state);
1569 card->tst_index ^= 1;
1570 write_sram(card, jump, TSTE_OPC_JMP | (base << 2));
1572 base = card->tst[card->tst_index];
1573 idle = card->tst[card->tst_index ^ 1];
1575 for (e = 0; e < card->tst_size - 2; e++) {
1576 if (card->soft_tst[e].tste & TSTE_PUSH_IDLE) {
1577 write_sram(card, idle + e,
1578 card->soft_tst[e].tste & TSTE_MASK);
1579 card->soft_tst[e].tste &= ~(TSTE_PUSH_IDLE);
1584 if (test_and_clear_bit(TST_SWITCH_PENDING, &card->tst_state)) {
1586 for (e = 0; e < card->tst_size - 2; e++) {
1587 if (card->soft_tst[e].tste & TSTE_PUSH_ACTIVE) {
1588 write_sram(card, idle + e,
1589 card->soft_tst[e].tste & TSTE_MASK);
1590 card->soft_tst[e].tste &= ~(TSTE_PUSH_ACTIVE);
1591 card->soft_tst[e].tste |= TSTE_PUSH_IDLE;
1595 jump = base + card->tst_size - 2;
1597 write_sram(card, jump, TSTE_OPC_NULL);
1598 set_bit(TST_SWITCH_WAIT, &card->tst_state);
1600 mod_timer(&card->tst_timer, jiffies + 1);
1604 spin_unlock_irqrestore(&card->tst_lock, flags);
1608 __fill_tst(struct idt77252_dev *card, struct vc_map *vc,
1609 int n, unsigned int opc)
1611 unsigned long cl, avail;
1616 avail = card->tst_size - 2;
1617 for (e = 0; e < avail; e++) {
1618 if (card->soft_tst[e].vc == NULL)
1622 printk("%s: No free TST entries found\n", card->name);
1626 NPRINTK("%s: conn %d: first TST entry at %d.\n",
1627 card->name, vc ? vc->index : -1, e);
1631 data = opc & TSTE_OPC_MASK;
1632 if (vc && (opc != TSTE_OPC_NULL))
1633 data = opc | vc->index;
1635 idle = card->tst[card->tst_index ^ 1];
1641 if ((cl >= avail) && (card->soft_tst[e].vc == NULL)) {
1643 card->soft_tst[e].vc = vc;
1645 card->soft_tst[e].vc = (void *)-1;
1647 card->soft_tst[e].tste = data;
1648 if (timer_pending(&card->tst_timer))
1649 card->soft_tst[e].tste |= TSTE_PUSH_ACTIVE;
1651 write_sram(card, idle + e, data);
1652 card->soft_tst[e].tste |= TSTE_PUSH_IDLE;
1655 cl -= card->tst_size;
1668 fill_tst(struct idt77252_dev *card, struct vc_map *vc, int n, unsigned int opc)
1670 unsigned long flags;
1673 spin_lock_irqsave(&card->tst_lock, flags);
1675 res = __fill_tst(card, vc, n, opc);
1677 set_bit(TST_SWITCH_PENDING, &card->tst_state);
1678 if (!timer_pending(&card->tst_timer))
1679 mod_timer(&card->tst_timer, jiffies + 1);
1681 spin_unlock_irqrestore(&card->tst_lock, flags);
1686 __clear_tst(struct idt77252_dev *card, struct vc_map *vc)
1691 idle = card->tst[card->tst_index ^ 1];
1693 for (e = 0; e < card->tst_size - 2; e++) {
1694 if (card->soft_tst[e].vc == vc) {
1695 card->soft_tst[e].vc = NULL;
1697 card->soft_tst[e].tste = TSTE_OPC_VAR;
1698 if (timer_pending(&card->tst_timer))
1699 card->soft_tst[e].tste |= TSTE_PUSH_ACTIVE;
1701 write_sram(card, idle + e, TSTE_OPC_VAR);
1702 card->soft_tst[e].tste |= TSTE_PUSH_IDLE;
1711 clear_tst(struct idt77252_dev *card, struct vc_map *vc)
1713 unsigned long flags;
1716 spin_lock_irqsave(&card->tst_lock, flags);
1718 res = __clear_tst(card, vc);
1720 set_bit(TST_SWITCH_PENDING, &card->tst_state);
1721 if (!timer_pending(&card->tst_timer))
1722 mod_timer(&card->tst_timer, jiffies + 1);
1724 spin_unlock_irqrestore(&card->tst_lock, flags);
1729 change_tst(struct idt77252_dev *card, struct vc_map *vc,
1730 int n, unsigned int opc)
1732 unsigned long flags;
1735 spin_lock_irqsave(&card->tst_lock, flags);
1737 __clear_tst(card, vc);
1738 res = __fill_tst(card, vc, n, opc);
1740 set_bit(TST_SWITCH_PENDING, &card->tst_state);
1741 if (!timer_pending(&card->tst_timer))
1742 mod_timer(&card->tst_timer, jiffies + 1);
1744 spin_unlock_irqrestore(&card->tst_lock, flags);
1750 set_tct(struct idt77252_dev *card, struct vc_map *vc)
1754 tct = (unsigned long) (card->tct_base + vc->index * SAR_SRAM_TCT_SIZE);
1756 switch (vc->class) {
1758 OPRINTK("%s: writing TCT at 0x%lx, SCD 0x%lx.\n",
1759 card->name, tct, vc->scq->scd);
1761 write_sram(card, tct + 0, TCT_CBR | vc->scq->scd);
1762 write_sram(card, tct + 1, 0);
1763 write_sram(card, tct + 2, 0);
1764 write_sram(card, tct + 3, 0);
1765 write_sram(card, tct + 4, 0);
1766 write_sram(card, tct + 5, 0);
1767 write_sram(card, tct + 6, 0);
1768 write_sram(card, tct + 7, 0);
1772 OPRINTK("%s: writing TCT at 0x%lx, SCD 0x%lx.\n",
1773 card->name, tct, vc->scq->scd);
1775 write_sram(card, tct + 0, TCT_UBR | vc->scq->scd);
1776 write_sram(card, tct + 1, 0);
1777 write_sram(card, tct + 2, TCT_TSIF);
1778 write_sram(card, tct + 3, TCT_HALT | TCT_IDLE);
1779 write_sram(card, tct + 4, 0);
1780 write_sram(card, tct + 5, vc->init_er);
1781 write_sram(card, tct + 6, 0);
1782 write_sram(card, tct + 7, TCT_FLAG_UBR);
1794 /*****************************************************************************/
1798 /*****************************************************************************/
1800 static __inline__ int
1801 idt77252_fbq_level(struct idt77252_dev *card, int queue)
1803 return (readl(SAR_REG_STAT) >> (16 + (queue << 2))) & 0x0f;
1806 static __inline__ int
1807 idt77252_fbq_full(struct idt77252_dev *card, int queue)
1809 return (readl(SAR_REG_STAT) >> (16 + (queue << 2))) == 0x0f;
1813 push_rx_skb(struct idt77252_dev *card, struct sk_buff *skb, int queue)
1815 unsigned long flags;
1819 skb->data = skb->tail = skb->head;
1822 skb_reserve(skb, 16);
1826 skb_put(skb, SAR_FB_SIZE_0);
1829 skb_put(skb, SAR_FB_SIZE_1);
1832 skb_put(skb, SAR_FB_SIZE_2);
1835 skb_put(skb, SAR_FB_SIZE_3);
1842 if (idt77252_fbq_full(card, queue))
1845 memset(&skb->data[(skb->len & ~(0x3f)) - 64], 0, 2 * sizeof(u32));
1847 handle = IDT77252_PRV_POOL(skb);
1848 addr = IDT77252_PRV_PADDR(skb);
1850 spin_lock_irqsave(&card->cmd_lock, flags);
1851 writel(handle, card->fbq[queue]);
1852 writel(addr, card->fbq[queue]);
1853 spin_unlock_irqrestore(&card->cmd_lock, flags);
1859 add_rx_skb(struct idt77252_dev *card, int queue,
1860 unsigned int size, unsigned int count)
1862 struct sk_buff *skb;
1867 skb = dev_alloc_skb(size);
1871 if (sb_pool_add(card, skb, queue)) {
1872 printk("%s: SB POOL full\n", __FUNCTION__);
1876 paddr = pci_map_single(card->pcidev, skb->data,
1877 skb->end - skb->data,
1878 PCI_DMA_FROMDEVICE);
1879 IDT77252_PRV_PADDR(skb) = paddr;
1881 if (push_rx_skb(card, skb, queue)) {
1882 printk("%s: FB QUEUE full\n", __FUNCTION__);
1890 pci_unmap_single(card->pcidev, IDT77252_PRV_PADDR(skb),
1891 skb->end - skb->data, PCI_DMA_FROMDEVICE);
1893 handle = IDT77252_PRV_POOL(skb);
1894 card->sbpool[POOL_QUEUE(handle)].skb[POOL_INDEX(handle)] = NULL;
1902 recycle_rx_skb(struct idt77252_dev *card, struct sk_buff *skb)
1904 u32 handle = IDT77252_PRV_POOL(skb);
1907 pci_dma_sync_single_for_device(card->pcidev, IDT77252_PRV_PADDR(skb),
1908 skb->end - skb->data, PCI_DMA_FROMDEVICE);
1910 err = push_rx_skb(card, skb, POOL_QUEUE(handle));
1912 pci_unmap_single(card->pcidev, IDT77252_PRV_PADDR(skb),
1913 skb->end - skb->data, PCI_DMA_FROMDEVICE);
1914 sb_pool_remove(card, skb);
1920 flush_rx_pool(struct idt77252_dev *card, struct rx_pool *rpp)
1925 rpp->last = &rpp->first;
1929 recycle_rx_pool_skb(struct idt77252_dev *card, struct rx_pool *rpp)
1931 struct sk_buff *skb, *next;
1935 for (i = 0; i < rpp->count; i++) {
1938 recycle_rx_skb(card, skb);
1941 flush_rx_pool(card, rpp);
1944 /*****************************************************************************/
1948 /*****************************************************************************/
1951 idt77252_phy_put(struct atm_dev *dev, unsigned char value, unsigned long addr)
1953 write_utility(dev->dev_data, 0x100 + (addr & 0x1ff), value);
1956 static unsigned char
1957 idt77252_phy_get(struct atm_dev *dev, unsigned long addr)
1959 return read_utility(dev->dev_data, 0x100 + (addr & 0x1ff));
1963 idt77252_send_skb(struct atm_vcc *vcc, struct sk_buff *skb, int oam)
1965 struct atm_dev *dev = vcc->dev;
1966 struct idt77252_dev *card = dev->dev_data;
1967 struct vc_map *vc = vcc->dev_data;
1971 printk("%s: NULL connection in send().\n", card->name);
1972 atomic_inc(&vcc->stats->tx_err);
1976 if (!test_bit(VCF_TX, &vc->flags)) {
1977 printk("%s: Trying to transmit on a non-tx VC.\n", card->name);
1978 atomic_inc(&vcc->stats->tx_err);
1983 switch (vcc->qos.aal) {
1989 printk("%s: Unsupported AAL: %d\n", card->name, vcc->qos.aal);
1990 atomic_inc(&vcc->stats->tx_err);
1995 if (skb_shinfo(skb)->nr_frags != 0) {
1996 printk("%s: No scatter-gather yet.\n", card->name);
1997 atomic_inc(&vcc->stats->tx_err);
2001 ATM_SKB(skb)->vcc = vcc;
2003 err = queue_skb(card, vc, skb, oam);
2005 atomic_inc(&vcc->stats->tx_err);
2014 idt77252_send(struct atm_vcc *vcc, struct sk_buff *skb)
2016 return idt77252_send_skb(vcc, skb, 0);
2020 idt77252_send_oam(struct atm_vcc *vcc, void *cell, int flags)
2022 struct atm_dev *dev = vcc->dev;
2023 struct idt77252_dev *card = dev->dev_data;
2024 struct sk_buff *skb;
2026 skb = dev_alloc_skb(64);
2028 printk("%s: Out of memory in send_oam().\n", card->name);
2029 atomic_inc(&vcc->stats->tx_err);
2032 atomic_add(skb->truesize, &vcc->sk->sk_wmem_alloc);
2034 memcpy(skb_put(skb, 52), cell, 52);
2036 return idt77252_send_skb(vcc, skb, 1);
2039 static __inline__ unsigned int
2040 idt77252_fls(unsigned int x)
2046 if (x & 0xffff0000) {
2068 idt77252_int_to_atmfp(unsigned int rate)
2074 e = idt77252_fls(rate) - 1;
2076 m = (rate - (1 << e)) << (9 - e);
2078 m = (rate - (1 << e));
2080 m = (rate - (1 << e)) >> (e - 9);
2081 return 0x4000 | (e << 9) | m;
2085 idt77252_rate_logindex(struct idt77252_dev *card, int pcr)
2089 afp = idt77252_int_to_atmfp(pcr < 0 ? -pcr : pcr);
2091 return rate_to_log[(afp >> 5) & 0x1ff];
2092 return rate_to_log[((afp >> 5) + 1) & 0x1ff];
2096 idt77252_est_timer(unsigned long data)
2098 struct vc_map *vc = (struct vc_map *)data;
2099 struct idt77252_dev *card = vc->card;
2100 struct rate_estimator *est;
2101 unsigned long flags;
2106 spin_lock_irqsave(&vc->lock, flags);
2107 est = vc->estimator;
2111 ncells = est->cells;
2113 rate = ((u32)(ncells - est->last_cells)) << (7 - est->interval);
2114 est->last_cells = ncells;
2115 est->avcps += ((long)rate - (long)est->avcps) >> est->ewma_log;
2116 est->cps = (est->avcps + 0x1f) >> 5;
2119 if (cps < (est->maxcps >> 4))
2120 cps = est->maxcps >> 4;
2122 lacr = idt77252_rate_logindex(card, cps);
2123 if (lacr > vc->max_er)
2126 if (lacr != vc->lacr) {
2128 writel(TCMDQ_LACR|(vc->lacr << 16)|vc->index, SAR_REG_TCMDQ);
2131 est->timer.expires = jiffies + ((HZ / 4) << est->interval);
2132 add_timer(&est->timer);
2135 spin_unlock_irqrestore(&vc->lock, flags);
2138 static struct rate_estimator *
2139 idt77252_init_est(struct vc_map *vc, int pcr)
2141 struct rate_estimator *est;
2143 est = kmalloc(sizeof(struct rate_estimator), GFP_KERNEL);
2146 memset(est, 0, sizeof(*est));
2148 est->maxcps = pcr < 0 ? -pcr : pcr;
2149 est->cps = est->maxcps;
2150 est->avcps = est->cps << 5;
2152 est->interval = 2; /* XXX: make this configurable */
2153 est->ewma_log = 2; /* XXX: make this configurable */
2154 init_timer(&est->timer);
2155 est->timer.data = (unsigned long)vc;
2156 est->timer.function = idt77252_est_timer;
2158 est->timer.expires = jiffies + ((HZ / 4) << est->interval);
2159 add_timer(&est->timer);
2165 idt77252_init_cbr(struct idt77252_dev *card, struct vc_map *vc,
2166 struct atm_vcc *vcc, struct atm_qos *qos)
2168 int tst_free, tst_used, tst_entries;
2169 unsigned long tmpl, modl;
2172 if ((qos->txtp.max_pcr == 0) &&
2173 (qos->txtp.pcr == 0) && (qos->txtp.min_pcr == 0)) {
2174 printk("%s: trying to open a CBR VC with cell rate = 0\n",
2180 tst_free = card->tst_free;
2181 if (test_bit(VCF_TX, &vc->flags))
2182 tst_used = vc->ntste;
2183 tst_free += tst_used;
2185 tcr = atm_pcr_goal(&qos->txtp);
2186 tcra = tcr >= 0 ? tcr : -tcr;
2188 TXPRINTK("%s: CBR target cell rate = %d\n", card->name, tcra);
2190 tmpl = (unsigned long) tcra * ((unsigned long) card->tst_size - 2);
2191 modl = tmpl % (unsigned long)card->utopia_pcr;
2193 tst_entries = (int) (tmpl / card->utopia_pcr);
2197 } else if (tcr == 0) {
2198 tst_entries = tst_free - SAR_TST_RESERVED;
2199 if (tst_entries <= 0) {
2200 printk("%s: no CBR bandwidth free.\n", card->name);
2205 if (tst_entries == 0) {
2206 printk("%s: selected CBR bandwidth < granularity.\n",
2211 if (tst_entries > (tst_free - SAR_TST_RESERVED)) {
2212 printk("%s: not enough CBR bandwidth free.\n", card->name);
2216 vc->ntste = tst_entries;
2218 card->tst_free = tst_free - tst_entries;
2219 if (test_bit(VCF_TX, &vc->flags)) {
2220 if (tst_used == tst_entries)
2223 OPRINTK("%s: modify %d -> %d entries in TST.\n",
2224 card->name, tst_used, tst_entries);
2225 change_tst(card, vc, tst_entries, TSTE_OPC_CBR);
2229 OPRINTK("%s: setting %d entries in TST.\n", card->name, tst_entries);
2230 fill_tst(card, vc, tst_entries, TSTE_OPC_CBR);
2235 idt77252_init_ubr(struct idt77252_dev *card, struct vc_map *vc,
2236 struct atm_vcc *vcc, struct atm_qos *qos)
2238 unsigned long flags;
2241 spin_lock_irqsave(&vc->lock, flags);
2242 if (vc->estimator) {
2243 del_timer(&vc->estimator->timer);
2244 kfree(vc->estimator);
2245 vc->estimator = NULL;
2247 spin_unlock_irqrestore(&vc->lock, flags);
2249 tcr = atm_pcr_goal(&qos->txtp);
2251 tcr = card->link_pcr;
2253 vc->estimator = idt77252_init_est(vc, tcr);
2255 vc->class = SCHED_UBR;
2256 vc->init_er = idt77252_rate_logindex(card, tcr);
2257 vc->lacr = vc->init_er;
2259 vc->max_er = vc->init_er;
2267 idt77252_init_tx(struct idt77252_dev *card, struct vc_map *vc,
2268 struct atm_vcc *vcc, struct atm_qos *qos)
2272 if (test_bit(VCF_TX, &vc->flags))
2275 switch (qos->txtp.traffic_class) {
2277 vc->class = SCHED_CBR;
2281 vc->class = SCHED_UBR;
2287 return -EPROTONOSUPPORT;
2290 vc->scq = alloc_scq(card, vc->class);
2292 printk("%s: can't get SCQ.\n", card->name);
2296 vc->scq->scd = get_free_scd(card, vc);
2297 if (vc->scq->scd == 0) {
2298 printk("%s: no SCD available.\n", card->name);
2299 free_scq(card, vc->scq);
2303 fill_scd(card, vc->scq, vc->class);
2305 if (set_tct(card, vc)) {
2306 printk("%s: class %d not supported.\n",
2307 card->name, qos->txtp.traffic_class);
2309 card->scd2vc[vc->scd_index] = NULL;
2310 free_scq(card, vc->scq);
2311 return -EPROTONOSUPPORT;
2314 switch (vc->class) {
2316 error = idt77252_init_cbr(card, vc, vcc, qos);
2318 card->scd2vc[vc->scd_index] = NULL;
2319 free_scq(card, vc->scq);
2323 clear_bit(VCF_IDLE, &vc->flags);
2324 writel(TCMDQ_START | vc->index, SAR_REG_TCMDQ);
2328 error = idt77252_init_ubr(card, vc, vcc, qos);
2330 card->scd2vc[vc->scd_index] = NULL;
2331 free_scq(card, vc->scq);
2335 set_bit(VCF_IDLE, &vc->flags);
2340 set_bit(VCF_TX, &vc->flags);
2345 idt77252_init_rx(struct idt77252_dev *card, struct vc_map *vc,
2346 struct atm_vcc *vcc, struct atm_qos *qos)
2348 unsigned long flags;
2352 if (test_bit(VCF_RX, &vc->flags))
2356 set_bit(VCF_RX, &vc->flags);
2358 if ((vcc->vci == 3) || (vcc->vci == 4))
2361 flush_rx_pool(card, &vc->rcv.rx_pool);
2363 rcte |= SAR_RCTE_CONNECTOPEN;
2364 rcte |= SAR_RCTE_RAWCELLINTEN;
2368 rcte |= SAR_RCTE_RCQ;
2371 rcte |= SAR_RCTE_OAM; /* Let SAR drop Video */
2374 rcte |= SAR_RCTE_AAL34;
2377 rcte |= SAR_RCTE_AAL5;
2380 rcte |= SAR_RCTE_RCQ;
2384 if (qos->aal != ATM_AAL5)
2385 rcte |= SAR_RCTE_FBP_1;
2386 else if (qos->rxtp.max_sdu > SAR_FB_SIZE_2)
2387 rcte |= SAR_RCTE_FBP_3;
2388 else if (qos->rxtp.max_sdu > SAR_FB_SIZE_1)
2389 rcte |= SAR_RCTE_FBP_2;
2390 else if (qos->rxtp.max_sdu > SAR_FB_SIZE_0)
2391 rcte |= SAR_RCTE_FBP_1;
2393 rcte |= SAR_RCTE_FBP_01;
2395 addr = card->rct_base + (vc->index << 2);
2397 OPRINTK("%s: writing RCT at 0x%lx\n", card->name, addr);
2398 write_sram(card, addr, rcte);
2400 spin_lock_irqsave(&card->cmd_lock, flags);
2401 writel(SAR_CMD_OPEN_CONNECTION | (addr << 2), SAR_REG_CMD);
2403 spin_unlock_irqrestore(&card->cmd_lock, flags);
2409 idt77252_open(struct atm_vcc *vcc)
2411 struct atm_dev *dev = vcc->dev;
2412 struct idt77252_dev *card = dev->dev_data;
2418 short vpi = vcc->vpi;
2420 if (vpi == ATM_VPI_UNSPEC || vci == ATM_VCI_UNSPEC)
2423 if (vpi >= (1 << card->vpibits)) {
2424 printk("%s: unsupported VPI: %d\n", card->name, vpi);
2428 if (vci >= (1 << card->vcibits)) {
2429 printk("%s: unsupported VCI: %d\n", card->name, vci);
2433 set_bit(ATM_VF_ADDR, &vcc->flags);
2437 OPRINTK("%s: opening vpi.vci: %d.%d\n", card->name, vpi, vci);
2439 switch (vcc->qos.aal) {
2445 printk("%s: Unsupported AAL: %d\n", card->name, vcc->qos.aal);
2447 return -EPROTONOSUPPORT;
2450 index = VPCI2VC(card, vpi, vci);
2451 if (!card->vcs[index]) {
2452 card->vcs[index] = kmalloc(sizeof(struct vc_map), GFP_KERNEL);
2453 if (!card->vcs[index]) {
2454 printk("%s: can't alloc vc in open()\n", card->name);
2458 memset(card->vcs[index], 0, sizeof(struct vc_map));
2460 card->vcs[index]->card = card;
2461 card->vcs[index]->index = index;
2463 spin_lock_init(&card->vcs[index]->lock);
2465 vc = card->vcs[index];
2469 IPRINTK("%s: idt77252_open: vc = %d (%d.%d) %s/%s (max RX SDU: %u)\n",
2470 card->name, vc->index, vcc->vpi, vcc->vci,
2471 vcc->qos.rxtp.traffic_class != ATM_NONE ? "rx" : "--",
2472 vcc->qos.txtp.traffic_class != ATM_NONE ? "tx" : "--",
2473 vcc->qos.rxtp.max_sdu);
2476 if (vcc->qos.txtp.traffic_class != ATM_NONE &&
2477 test_bit(VCF_TX, &vc->flags))
2479 if (vcc->qos.rxtp.traffic_class != ATM_NONE &&
2480 test_bit(VCF_RX, &vc->flags))
2484 printk("%s: %s vci already in use.\n", card->name,
2485 inuse == 1 ? "tx" : inuse == 2 ? "rx" : "tx and rx");
2490 if (vcc->qos.txtp.traffic_class != ATM_NONE) {
2491 error = idt77252_init_tx(card, vc, vcc, &vcc->qos);
2498 if (vcc->qos.rxtp.traffic_class != ATM_NONE) {
2499 error = idt77252_init_rx(card, vc, vcc, &vcc->qos);
2506 set_bit(ATM_VF_READY, &vcc->flags);
2513 idt77252_close(struct atm_vcc *vcc)
2515 struct atm_dev *dev = vcc->dev;
2516 struct idt77252_dev *card = dev->dev_data;
2517 struct vc_map *vc = vcc->dev_data;
2518 unsigned long flags;
2520 unsigned long timeout;
2524 IPRINTK("%s: idt77252_close: vc = %d (%d.%d)\n",
2525 card->name, vc->index, vcc->vpi, vcc->vci);
2527 clear_bit(ATM_VF_READY, &vcc->flags);
2529 if (vcc->qos.rxtp.traffic_class != ATM_NONE) {
2531 spin_lock_irqsave(&vc->lock, flags);
2532 clear_bit(VCF_RX, &vc->flags);
2534 spin_unlock_irqrestore(&vc->lock, flags);
2536 if ((vcc->vci == 3) || (vcc->vci == 4))
2539 addr = card->rct_base + vc->index * SAR_SRAM_RCT_SIZE;
2541 spin_lock_irqsave(&card->cmd_lock, flags);
2542 writel(SAR_CMD_CLOSE_CONNECTION | (addr << 2), SAR_REG_CMD);
2544 spin_unlock_irqrestore(&card->cmd_lock, flags);
2546 if (vc->rcv.rx_pool.count) {
2547 DPRINTK("%s: closing a VC with pending rx buffers.\n",
2550 recycle_rx_pool_skb(card, &vc->rcv.rx_pool);
2555 if (vcc->qos.txtp.traffic_class != ATM_NONE) {
2557 spin_lock_irqsave(&vc->lock, flags);
2558 clear_bit(VCF_TX, &vc->flags);
2559 clear_bit(VCF_IDLE, &vc->flags);
2560 clear_bit(VCF_RSV, &vc->flags);
2563 if (vc->estimator) {
2564 del_timer(&vc->estimator->timer);
2565 kfree(vc->estimator);
2566 vc->estimator = NULL;
2568 spin_unlock_irqrestore(&vc->lock, flags);
2571 while (atomic_read(&vc->scq->used) > 0) {
2572 timeout = msleep_interruptible(timeout);
2577 printk("%s: SCQ drain timeout: %u used\n",
2578 card->name, atomic_read(&vc->scq->used));
2580 writel(TCMDQ_HALT | vc->index, SAR_REG_TCMDQ);
2581 clear_scd(card, vc->scq, vc->class);
2583 if (vc->class == SCHED_CBR) {
2584 clear_tst(card, vc);
2585 card->tst_free += vc->ntste;
2589 card->scd2vc[vc->scd_index] = NULL;
2590 free_scq(card, vc->scq);
2597 idt77252_change_qos(struct atm_vcc *vcc, struct atm_qos *qos, int flags)
2599 struct atm_dev *dev = vcc->dev;
2600 struct idt77252_dev *card = dev->dev_data;
2601 struct vc_map *vc = vcc->dev_data;
2606 if (qos->txtp.traffic_class != ATM_NONE) {
2607 if (!test_bit(VCF_TX, &vc->flags)) {
2608 error = idt77252_init_tx(card, vc, vcc, qos);
2612 switch (qos->txtp.traffic_class) {
2614 error = idt77252_init_cbr(card, vc, vcc, qos);
2620 error = idt77252_init_ubr(card, vc, vcc, qos);
2624 if (!test_bit(VCF_IDLE, &vc->flags)) {
2625 writel(TCMDQ_LACR | (vc->lacr << 16) |
2626 vc->index, SAR_REG_TCMDQ);
2632 error = -EOPNOTSUPP;
2638 if ((qos->rxtp.traffic_class != ATM_NONE) &&
2639 !test_bit(VCF_RX, &vc->flags)) {
2640 error = idt77252_init_rx(card, vc, vcc, qos);
2645 memcpy(&vcc->qos, qos, sizeof(struct atm_qos));
2647 set_bit(ATM_VF_HASQOS, &vcc->flags);
2655 idt77252_proc_read(struct atm_dev *dev, loff_t * pos, char *page)
2657 struct idt77252_dev *card = dev->dev_data;
2662 return sprintf(page, "IDT77252 Interrupts:\n");
2664 return sprintf(page, "TSIF: %lu\n", card->irqstat[15]);
2666 return sprintf(page, "TXICP: %lu\n", card->irqstat[14]);
2668 return sprintf(page, "TSQF: %lu\n", card->irqstat[12]);
2670 return sprintf(page, "TMROF: %lu\n", card->irqstat[11]);
2672 return sprintf(page, "PHYI: %lu\n", card->irqstat[10]);
2674 return sprintf(page, "FBQ3A: %lu\n", card->irqstat[8]);
2676 return sprintf(page, "FBQ2A: %lu\n", card->irqstat[7]);
2678 return sprintf(page, "RSQF: %lu\n", card->irqstat[6]);
2680 return sprintf(page, "EPDU: %lu\n", card->irqstat[5]);
2682 return sprintf(page, "RAWCF: %lu\n", card->irqstat[4]);
2684 return sprintf(page, "FBQ1A: %lu\n", card->irqstat[3]);
2686 return sprintf(page, "FBQ0A: %lu\n", card->irqstat[2]);
2688 return sprintf(page, "RSQAF: %lu\n", card->irqstat[1]);
2690 return sprintf(page, "IDT77252 Transmit Connection Table:\n");
2692 for (i = 0; i < card->tct_size; i++) {
2694 struct atm_vcc *vcc;
2711 p += sprintf(p, " %4u: %u.%u: ", i, vcc->vpi, vcc->vci);
2712 tct = (unsigned long) (card->tct_base + i * SAR_SRAM_TCT_SIZE);
2714 for (i = 0; i < 8; i++)
2715 p += sprintf(p, " %08x", read_sram(card, tct + i));
2716 p += sprintf(p, "\n");
2722 /*****************************************************************************/
2724 /* Interrupt handler */
2726 /*****************************************************************************/
2729 idt77252_collect_stat(struct idt77252_dev *card)
2733 cdc = readl(SAR_REG_CDC);
2734 vpec = readl(SAR_REG_VPEC);
2735 icc = readl(SAR_REG_ICC);
2738 printk("%s:", card->name);
2740 if (cdc & 0x7f0000) {
2744 if (cdc & (1 << 22)) {
2745 printk("%sRM ID", s);
2748 if (cdc & (1 << 21)) {
2749 printk("%sCON TAB", s);
2752 if (cdc & (1 << 20)) {
2753 printk("%sNO FB", s);
2756 if (cdc & (1 << 19)) {
2757 printk("%sOAM CRC", s);
2760 if (cdc & (1 << 18)) {
2761 printk("%sRM CRC", s);
2764 if (cdc & (1 << 17)) {
2765 printk("%sRM FIFO", s);
2768 if (cdc & (1 << 16)) {
2769 printk("%sRX FIFO", s);
2775 printk(" CDC %04x, VPEC %04x, ICC: %04x\n",
2776 cdc & 0xffff, vpec & 0xffff, icc & 0xffff);
2781 idt77252_interrupt(int irq, void *dev_id, struct pt_regs *ptregs)
2783 struct idt77252_dev *card = dev_id;
2786 stat = readl(SAR_REG_STAT) & 0xffff;
2787 if (!stat) /* no interrupt for us */
2790 if (test_and_set_bit(IDT77252_BIT_INTERRUPT, &card->flags)) {
2791 printk("%s: Re-entering irq_handler()\n", card->name);
2795 writel(stat, SAR_REG_STAT); /* reset interrupt */
2797 if (stat & SAR_STAT_TSIF) { /* entry written to TSQ */
2798 INTPRINTK("%s: TSIF\n", card->name);
2799 card->irqstat[15]++;
2802 if (stat & SAR_STAT_TXICP) { /* Incomplete CS-PDU has */
2803 INTPRINTK("%s: TXICP\n", card->name);
2804 card->irqstat[14]++;
2805 #ifdef CONFIG_ATM_IDT77252_DEBUG
2806 idt77252_tx_dump(card);
2809 if (stat & SAR_STAT_TSQF) { /* TSQ 7/8 full */
2810 INTPRINTK("%s: TSQF\n", card->name);
2811 card->irqstat[12]++;
2814 if (stat & SAR_STAT_TMROF) { /* Timer overflow */
2815 INTPRINTK("%s: TMROF\n", card->name);
2816 card->irqstat[11]++;
2817 idt77252_collect_stat(card);
2820 if (stat & SAR_STAT_EPDU) { /* Got complete CS-PDU */
2821 INTPRINTK("%s: EPDU\n", card->name);
2825 if (stat & SAR_STAT_RSQAF) { /* RSQ is 7/8 full */
2826 INTPRINTK("%s: RSQAF\n", card->name);
2830 if (stat & SAR_STAT_RSQF) { /* RSQ is full */
2831 INTPRINTK("%s: RSQF\n", card->name);
2835 if (stat & SAR_STAT_RAWCF) { /* Raw cell received */
2836 INTPRINTK("%s: RAWCF\n", card->name);
2838 idt77252_rx_raw(card);
2841 if (stat & SAR_STAT_PHYI) { /* PHY device interrupt */
2842 INTPRINTK("%s: PHYI", card->name);
2843 card->irqstat[10]++;
2844 if (card->atmdev->phy && card->atmdev->phy->interrupt)
2845 card->atmdev->phy->interrupt(card->atmdev);
2848 if (stat & (SAR_STAT_FBQ0A | SAR_STAT_FBQ1A |
2849 SAR_STAT_FBQ2A | SAR_STAT_FBQ3A)) {
2851 writel(readl(SAR_REG_CFG) & ~(SAR_CFG_FBIE), SAR_REG_CFG);
2853 INTPRINTK("%s: FBQA: %04x\n", card->name, stat);
2855 if (stat & SAR_STAT_FBQ0A)
2857 if (stat & SAR_STAT_FBQ1A)
2859 if (stat & SAR_STAT_FBQ2A)
2861 if (stat & SAR_STAT_FBQ3A)
2864 schedule_work(&card->tqueue);
2868 clear_bit(IDT77252_BIT_INTERRUPT, &card->flags);
2873 idt77252_softint(void *dev_id)
2875 struct idt77252_dev *card = dev_id;
2879 for (done = 1; ; done = 1) {
2880 stat = readl(SAR_REG_STAT) >> 16;
2882 if ((stat & 0x0f) < SAR_FBQ0_HIGH) {
2883 add_rx_skb(card, 0, SAR_FB_SIZE_0, 32);
2888 if ((stat & 0x0f) < SAR_FBQ1_HIGH) {
2889 add_rx_skb(card, 1, SAR_FB_SIZE_1, 32);
2894 if ((stat & 0x0f) < SAR_FBQ2_HIGH) {
2895 add_rx_skb(card, 2, SAR_FB_SIZE_2, 32);
2900 if ((stat & 0x0f) < SAR_FBQ3_HIGH) {
2901 add_rx_skb(card, 3, SAR_FB_SIZE_3, 32);
2909 writel(readl(SAR_REG_CFG) | SAR_CFG_FBIE, SAR_REG_CFG);
2914 open_card_oam(struct idt77252_dev *card)
2916 unsigned long flags;
2923 for (vpi = 0; vpi < (1 << card->vpibits); vpi++) {
2924 for (vci = 3; vci < 5; vci++) {
2925 index = VPCI2VC(card, vpi, vci);
2927 vc = kmalloc(sizeof(struct vc_map), GFP_KERNEL);
2929 printk("%s: can't alloc vc\n", card->name);
2932 memset(vc, 0, sizeof(struct vc_map));
2935 card->vcs[index] = vc;
2937 flush_rx_pool(card, &vc->rcv.rx_pool);
2939 rcte = SAR_RCTE_CONNECTOPEN |
2940 SAR_RCTE_RAWCELLINTEN |
2944 addr = card->rct_base + (vc->index << 2);
2945 write_sram(card, addr, rcte);
2947 spin_lock_irqsave(&card->cmd_lock, flags);
2948 writel(SAR_CMD_OPEN_CONNECTION | (addr << 2),
2951 spin_unlock_irqrestore(&card->cmd_lock, flags);
2959 close_card_oam(struct idt77252_dev *card)
2961 unsigned long flags;
2967 for (vpi = 0; vpi < (1 << card->vpibits); vpi++) {
2968 for (vci = 3; vci < 5; vci++) {
2969 index = VPCI2VC(card, vpi, vci);
2970 vc = card->vcs[index];
2972 addr = card->rct_base + vc->index * SAR_SRAM_RCT_SIZE;
2974 spin_lock_irqsave(&card->cmd_lock, flags);
2975 writel(SAR_CMD_CLOSE_CONNECTION | (addr << 2),
2978 spin_unlock_irqrestore(&card->cmd_lock, flags);
2980 if (vc->rcv.rx_pool.count) {
2981 DPRINTK("%s: closing a VC "
2982 "with pending rx buffers.\n",
2985 recycle_rx_pool_skb(card, &vc->rcv.rx_pool);
2992 open_card_ubr0(struct idt77252_dev *card)
2996 vc = kmalloc(sizeof(struct vc_map), GFP_KERNEL);
2998 printk("%s: can't alloc vc\n", card->name);
3001 memset(vc, 0, sizeof(struct vc_map));
3003 vc->class = SCHED_UBR0;
3005 vc->scq = alloc_scq(card, vc->class);
3007 printk("%s: can't get SCQ.\n", card->name);
3011 card->scd2vc[0] = vc;
3013 vc->scq->scd = card->scd_base;
3015 fill_scd(card, vc->scq, vc->class);
3017 write_sram(card, card->tct_base + 0, TCT_UBR | card->scd_base);
3018 write_sram(card, card->tct_base + 1, 0);
3019 write_sram(card, card->tct_base + 2, 0);
3020 write_sram(card, card->tct_base + 3, 0);
3021 write_sram(card, card->tct_base + 4, 0);
3022 write_sram(card, card->tct_base + 5, 0);
3023 write_sram(card, card->tct_base + 6, 0);
3024 write_sram(card, card->tct_base + 7, TCT_FLAG_UBR);
3026 clear_bit(VCF_IDLE, &vc->flags);
3027 writel(TCMDQ_START | 0, SAR_REG_TCMDQ);
3032 idt77252_dev_open(struct idt77252_dev *card)
3036 if (!test_bit(IDT77252_BIT_INIT, &card->flags)) {
3037 printk("%s: SAR not yet initialized.\n", card->name);
3041 conf = SAR_CFG_RXPTH| /* enable receive path */
3042 SAR_RX_DELAY | /* interrupt on complete PDU */
3043 SAR_CFG_RAWIE | /* interrupt enable on raw cells */
3044 SAR_CFG_RQFIE | /* interrupt on RSQ almost full */
3045 SAR_CFG_TMOIE | /* interrupt on timer overflow */
3046 SAR_CFG_FBIE | /* interrupt on low free buffers */
3047 SAR_CFG_TXEN | /* transmit operation enable */
3048 SAR_CFG_TXINT | /* interrupt on transmit status */
3049 SAR_CFG_TXUIE | /* interrupt on transmit underrun */
3050 SAR_CFG_TXSFI | /* interrupt on TSQ almost full */
3051 SAR_CFG_PHYIE /* enable PHY interrupts */
3054 #ifdef CONFIG_ATM_IDT77252_RCV_ALL
3055 /* Test RAW cell receive. */
3056 conf |= SAR_CFG_VPECA;
3059 writel(readl(SAR_REG_CFG) | conf, SAR_REG_CFG);
3061 if (open_card_oam(card)) {
3062 printk("%s: Error initializing OAM.\n", card->name);
3066 if (open_card_ubr0(card)) {
3067 printk("%s: Error initializing UBR0.\n", card->name);
3071 IPRINTK("%s: opened IDT77252 ABR SAR.\n", card->name);
3076 idt77252_dev_close(struct atm_dev *dev)
3078 struct idt77252_dev *card = dev->dev_data;
3081 close_card_oam(card);
3083 conf = SAR_CFG_RXPTH | /* enable receive path */
3084 SAR_RX_DELAY | /* interrupt on complete PDU */
3085 SAR_CFG_RAWIE | /* interrupt enable on raw cells */
3086 SAR_CFG_RQFIE | /* interrupt on RSQ almost full */
3087 SAR_CFG_TMOIE | /* interrupt on timer overflow */
3088 SAR_CFG_FBIE | /* interrupt on low free buffers */
3089 SAR_CFG_TXEN | /* transmit operation enable */
3090 SAR_CFG_TXINT | /* interrupt on transmit status */
3091 SAR_CFG_TXUIE | /* interrupt on xmit underrun */
3092 SAR_CFG_TXSFI /* interrupt on TSQ almost full */
3095 writel(readl(SAR_REG_CFG) & ~(conf), SAR_REG_CFG);
3097 DIPRINTK("%s: closed IDT77252 ABR SAR.\n", card->name);
3101 /*****************************************************************************/
3103 /* Initialisation and Deinitialization of IDT77252 */
3105 /*****************************************************************************/
3109 deinit_card(struct idt77252_dev *card)
3111 struct sk_buff *skb;
3114 if (!test_bit(IDT77252_BIT_INIT, &card->flags)) {
3115 printk("%s: SAR not yet initialized.\n", card->name);
3118 DIPRINTK("idt77252: deinitialize card %u\n", card->index);
3120 writel(0, SAR_REG_CFG);
3123 atm_dev_deregister(card->atmdev);
3125 for (i = 0; i < 4; i++) {
3126 for (j = 0; j < FBQ_SIZE; j++) {
3127 skb = card->sbpool[i].skb[j];
3129 pci_unmap_single(card->pcidev,
3130 IDT77252_PRV_PADDR(skb),
3131 skb->end - skb->data,
3132 PCI_DMA_FROMDEVICE);
3133 card->sbpool[i].skb[j] = NULL;
3139 vfree(card->soft_tst);
3141 vfree(card->scd2vc);
3145 if (card->raw_cell_hnd) {
3146 pci_free_consistent(card->pcidev, 2 * sizeof(u32),
3147 card->raw_cell_hnd, card->raw_cell_paddr);
3150 if (card->rsq.base) {
3151 DIPRINTK("%s: Release RSQ ...\n", card->name);
3155 if (card->tsq.base) {
3156 DIPRINTK("%s: Release TSQ ...\n", card->name);
3160 DIPRINTK("idt77252: Release IRQ.\n");
3161 free_irq(card->pcidev->irq, card);
3163 for (i = 0; i < 4; i++) {
3165 iounmap(card->fbq[i]);
3169 iounmap(card->membase);
3171 clear_bit(IDT77252_BIT_INIT, &card->flags);
3172 DIPRINTK("%s: Card deinitialized.\n", card->name);
3176 static int __devinit
3177 init_sram(struct idt77252_dev *card)
3181 for (i = 0; i < card->sramsize; i += 4)
3182 write_sram(card, (i >> 2), 0);
3184 /* set SRAM layout for THIS card */
3185 if (card->sramsize == (512 * 1024)) {
3186 card->tct_base = SAR_SRAM_TCT_128_BASE;
3187 card->tct_size = (SAR_SRAM_TCT_128_TOP - card->tct_base + 1)
3188 / SAR_SRAM_TCT_SIZE;
3189 card->rct_base = SAR_SRAM_RCT_128_BASE;
3190 card->rct_size = (SAR_SRAM_RCT_128_TOP - card->rct_base + 1)
3191 / SAR_SRAM_RCT_SIZE;
3192 card->rt_base = SAR_SRAM_RT_128_BASE;
3193 card->scd_base = SAR_SRAM_SCD_128_BASE;
3194 card->scd_size = (SAR_SRAM_SCD_128_TOP - card->scd_base + 1)
3195 / SAR_SRAM_SCD_SIZE;
3196 card->tst[0] = SAR_SRAM_TST1_128_BASE;
3197 card->tst[1] = SAR_SRAM_TST2_128_BASE;
3198 card->tst_size = SAR_SRAM_TST1_128_TOP - card->tst[0] + 1;
3199 card->abrst_base = SAR_SRAM_ABRSTD_128_BASE;
3200 card->abrst_size = SAR_ABRSTD_SIZE_8K;
3201 card->fifo_base = SAR_SRAM_FIFO_128_BASE;
3202 card->fifo_size = SAR_RXFD_SIZE_32K;
3204 card->tct_base = SAR_SRAM_TCT_32_BASE;
3205 card->tct_size = (SAR_SRAM_TCT_32_TOP - card->tct_base + 1)
3206 / SAR_SRAM_TCT_SIZE;
3207 card->rct_base = SAR_SRAM_RCT_32_BASE;
3208 card->rct_size = (SAR_SRAM_RCT_32_TOP - card->rct_base + 1)
3209 / SAR_SRAM_RCT_SIZE;
3210 card->rt_base = SAR_SRAM_RT_32_BASE;
3211 card->scd_base = SAR_SRAM_SCD_32_BASE;
3212 card->scd_size = (SAR_SRAM_SCD_32_TOP - card->scd_base + 1)
3213 / SAR_SRAM_SCD_SIZE;
3214 card->tst[0] = SAR_SRAM_TST1_32_BASE;
3215 card->tst[1] = SAR_SRAM_TST2_32_BASE;
3216 card->tst_size = (SAR_SRAM_TST1_32_TOP - card->tst[0] + 1);
3217 card->abrst_base = SAR_SRAM_ABRSTD_32_BASE;
3218 card->abrst_size = SAR_ABRSTD_SIZE_1K;
3219 card->fifo_base = SAR_SRAM_FIFO_32_BASE;
3220 card->fifo_size = SAR_RXFD_SIZE_4K;
3223 /* Initialize TCT */
3224 for (i = 0; i < card->tct_size; i++) {
3225 write_sram(card, i * SAR_SRAM_TCT_SIZE + 0, 0);
3226 write_sram(card, i * SAR_SRAM_TCT_SIZE + 1, 0);
3227 write_sram(card, i * SAR_SRAM_TCT_SIZE + 2, 0);
3228 write_sram(card, i * SAR_SRAM_TCT_SIZE + 3, 0);
3229 write_sram(card, i * SAR_SRAM_TCT_SIZE + 4, 0);
3230 write_sram(card, i * SAR_SRAM_TCT_SIZE + 5, 0);
3231 write_sram(card, i * SAR_SRAM_TCT_SIZE + 6, 0);
3232 write_sram(card, i * SAR_SRAM_TCT_SIZE + 7, 0);
3235 /* Initialize RCT */
3236 for (i = 0; i < card->rct_size; i++) {
3237 write_sram(card, card->rct_base + i * SAR_SRAM_RCT_SIZE,
3238 (u32) SAR_RCTE_RAWCELLINTEN);
3239 write_sram(card, card->rct_base + i * SAR_SRAM_RCT_SIZE + 1,
3241 write_sram(card, card->rct_base + i * SAR_SRAM_RCT_SIZE + 2,
3243 write_sram(card, card->rct_base + i * SAR_SRAM_RCT_SIZE + 3,
3247 writel((SAR_FBQ0_LOW << 28) | 0x00000000 | 0x00000000 |
3248 (SAR_FB_SIZE_0 / 48), SAR_REG_FBQS0);
3249 writel((SAR_FBQ1_LOW << 28) | 0x00000000 | 0x00000000 |
3250 (SAR_FB_SIZE_1 / 48), SAR_REG_FBQS1);
3251 writel((SAR_FBQ2_LOW << 28) | 0x00000000 | 0x00000000 |
3252 (SAR_FB_SIZE_2 / 48), SAR_REG_FBQS2);
3253 writel((SAR_FBQ3_LOW << 28) | 0x00000000 | 0x00000000 |
3254 (SAR_FB_SIZE_3 / 48), SAR_REG_FBQS3);
3256 /* Initialize rate table */
3257 for (i = 0; i < 256; i++) {
3258 write_sram(card, card->rt_base + i, log_to_rate[i]);
3261 for (i = 0; i < 128; i++) {
3264 tmp = rate_to_log[(i << 2) + 0] << 0;
3265 tmp |= rate_to_log[(i << 2) + 1] << 8;
3266 tmp |= rate_to_log[(i << 2) + 2] << 16;
3267 tmp |= rate_to_log[(i << 2) + 3] << 24;
3268 write_sram(card, card->rt_base + 256 + i, tmp);
3271 #if 0 /* Fill RDF and AIR tables. */
3272 for (i = 0; i < 128; i++) {
3275 tmp = RDF[0][(i << 1) + 0] << 16;
3276 tmp |= RDF[0][(i << 1) + 1] << 0;
3277 write_sram(card, card->rt_base + 512 + i, tmp);
3280 for (i = 0; i < 128; i++) {
3283 tmp = AIR[0][(i << 1) + 0] << 16;
3284 tmp |= AIR[0][(i << 1) + 1] << 0;
3285 write_sram(card, card->rt_base + 640 + i, tmp);
3289 IPRINTK("%s: initialize rate table ...\n", card->name);
3290 writel(card->rt_base << 2, SAR_REG_RTBL);
3292 /* Initialize TSTs */
3293 IPRINTK("%s: initialize TST ...\n", card->name);
3294 card->tst_free = card->tst_size - 2; /* last two are jumps */
3296 for (i = card->tst[0]; i < card->tst[0] + card->tst_size - 2; i++)
3297 write_sram(card, i, TSTE_OPC_VAR);
3298 write_sram(card, i++, TSTE_OPC_JMP | (card->tst[0] << 2));
3299 idt77252_sram_write_errors = 1;
3300 write_sram(card, i++, TSTE_OPC_JMP | (card->tst[1] << 2));
3301 idt77252_sram_write_errors = 0;
3302 for (i = card->tst[1]; i < card->tst[1] + card->tst_size - 2; i++)
3303 write_sram(card, i, TSTE_OPC_VAR);
3304 write_sram(card, i++, TSTE_OPC_JMP | (card->tst[1] << 2));
3305 idt77252_sram_write_errors = 1;
3306 write_sram(card, i++, TSTE_OPC_JMP | (card->tst[0] << 2));
3307 idt77252_sram_write_errors = 0;
3309 card->tst_index = 0;
3310 writel(card->tst[0] << 2, SAR_REG_TSTB);
3312 /* Initialize ABRSTD and Receive FIFO */
3313 IPRINTK("%s: initialize ABRSTD ...\n", card->name);
3314 writel(card->abrst_size | (card->abrst_base << 2),
3317 IPRINTK("%s: initialize receive fifo ...\n", card->name);
3318 writel(card->fifo_size | (card->fifo_base << 2),
3321 IPRINTK("%s: SRAM initialization complete.\n", card->name);
3325 static int __devinit
3326 init_card(struct atm_dev *dev)
3328 struct idt77252_dev *card = dev->dev_data;
3329 struct pci_dev *pcidev = card->pcidev;
3330 unsigned long tmpl, modl;
3331 unsigned int linkrate, rsvdcr;
3332 unsigned int tst_entries;
3333 struct net_device *tmp;
3341 if (test_bit(IDT77252_BIT_INIT, &card->flags)) {
3342 printk("Error: SAR already initialized.\n");
3346 /*****************************************************************/
3347 /* P C I C O N F I G U R A T I O N */
3348 /*****************************************************************/
3350 /* Set PCI Retry-Timeout and TRDY timeout */
3351 IPRINTK("%s: Checking PCI retries.\n", card->name);
3352 if (pci_read_config_byte(pcidev, 0x40, &pci_byte) != 0) {
3353 printk("%s: can't read PCI retry timeout.\n", card->name);
3357 if (pci_byte != 0) {
3358 IPRINTK("%s: PCI retry timeout: %d, set to 0.\n",
3359 card->name, pci_byte);
3360 if (pci_write_config_byte(pcidev, 0x40, 0) != 0) {
3361 printk("%s: can't set PCI retry timeout.\n",
3367 IPRINTK("%s: Checking PCI TRDY.\n", card->name);
3368 if (pci_read_config_byte(pcidev, 0x41, &pci_byte) != 0) {
3369 printk("%s: can't read PCI TRDY timeout.\n", card->name);
3373 if (pci_byte != 0) {
3374 IPRINTK("%s: PCI TRDY timeout: %d, set to 0.\n",
3375 card->name, pci_byte);
3376 if (pci_write_config_byte(pcidev, 0x41, 0) != 0) {
3377 printk("%s: can't set PCI TRDY timeout.\n", card->name);
3382 /* Reset Timer register */
3383 if (readl(SAR_REG_STAT) & SAR_STAT_TMROF) {
3384 printk("%s: resetting timer overflow.\n", card->name);
3385 writel(SAR_STAT_TMROF, SAR_REG_STAT);
3387 IPRINTK("%s: Request IRQ ... ", card->name);
3388 if (request_irq(pcidev->irq, idt77252_interrupt, SA_INTERRUPT|SA_SHIRQ,
3389 card->name, card) != 0) {
3390 printk("%s: can't allocate IRQ.\n", card->name);
3394 IPRINTK("got %d.\n", pcidev->irq);
3396 /*****************************************************************/
3397 /* C H E C K A N D I N I T S R A M */
3398 /*****************************************************************/
3400 IPRINTK("%s: Initializing SRAM\n", card->name);
3402 /* preset size of connecton table, so that init_sram() knows about it */
3403 conf = SAR_CFG_TX_FIFO_SIZE_9 | /* Use maximum fifo size */
3404 SAR_CFG_RXSTQ_SIZE_8k | /* Receive Status Queue is 8k */
3405 SAR_CFG_IDLE_CLP | /* Set CLP on idle cells */
3406 #ifndef CONFIG_ATM_IDT77252_SEND_IDLE
3407 SAR_CFG_NO_IDLE | /* Do not send idle cells */
3411 if (card->sramsize == (512 * 1024))
3412 conf |= SAR_CFG_CNTBL_1k;
3414 conf |= SAR_CFG_CNTBL_512;
3418 conf |= SAR_CFG_VPVCS_0;
3422 conf |= SAR_CFG_VPVCS_1;
3425 conf |= SAR_CFG_VPVCS_2;
3428 conf |= SAR_CFG_VPVCS_8;
3432 writel(readl(SAR_REG_CFG) | conf, SAR_REG_CFG);
3434 if (init_sram(card) < 0)
3437 /********************************************************************/
3438 /* A L L O C R A M A N D S E T V A R I O U S T H I N G S */
3439 /********************************************************************/
3440 /* Initialize TSQ */
3441 if (0 != init_tsq(card)) {
3445 /* Initialize RSQ */
3446 if (0 != init_rsq(card)) {
3451 card->vpibits = vpibits;
3452 if (card->sramsize == (512 * 1024)) {
3453 card->vcibits = 10 - card->vpibits;
3455 card->vcibits = 9 - card->vpibits;
3459 for (k = 0, i = 1; k < card->vcibits; k++) {
3464 IPRINTK("%s: Setting VPI/VCI mask to zero.\n", card->name);
3465 writel(0, SAR_REG_VPM);
3467 /* Little Endian Order */
3468 writel(0, SAR_REG_GP);
3470 /* Initialize RAW Cell Handle Register */
3471 card->raw_cell_hnd = pci_alloc_consistent(card->pcidev, 2 * sizeof(u32),
3472 &card->raw_cell_paddr);
3473 if (!card->raw_cell_hnd) {
3474 printk("%s: memory allocation failure.\n", card->name);
3478 memset(card->raw_cell_hnd, 0, 2 * sizeof(u32));
3479 writel(card->raw_cell_paddr, SAR_REG_RAWHND);
3480 IPRINTK("%s: raw cell handle is at 0x%p.\n", card->name,
3481 card->raw_cell_hnd);
3483 size = sizeof(struct vc_map *) * card->tct_size;
3484 IPRINTK("%s: allocate %d byte for VC map.\n", card->name, size);
3485 if (NULL == (card->vcs = vmalloc(size))) {
3486 printk("%s: memory allocation failure.\n", card->name);
3490 memset(card->vcs, 0, size);
3492 size = sizeof(struct vc_map *) * card->scd_size;
3493 IPRINTK("%s: allocate %d byte for SCD to VC mapping.\n",
3495 if (NULL == (card->scd2vc = vmalloc(size))) {
3496 printk("%s: memory allocation failure.\n", card->name);
3500 memset(card->scd2vc, 0, size);
3502 size = sizeof(struct tst_info) * (card->tst_size - 2);
3503 IPRINTK("%s: allocate %d byte for TST to VC mapping.\n",
3505 if (NULL == (card->soft_tst = vmalloc(size))) {
3506 printk("%s: memory allocation failure.\n", card->name);
3510 for (i = 0; i < card->tst_size - 2; i++) {
3511 card->soft_tst[i].tste = TSTE_OPC_VAR;
3512 card->soft_tst[i].vc = NULL;
3515 if (dev->phy == NULL) {
3516 printk("%s: No LT device defined.\n", card->name);
3520 if (dev->phy->ioctl == NULL) {
3521 printk("%s: LT had no IOCTL funtion defined.\n", card->name);
3526 #ifdef CONFIG_ATM_IDT77252_USE_SUNI
3528 * this is a jhs hack to get around special functionality in the
3529 * phy driver for the atecom hardware; the functionality doesn't
3530 * exist in the linux atm suni driver
3532 * it isn't the right way to do things, but as the guy from NIST
3533 * said, talking about their measurement of the fine structure
3534 * constant, "it's good enough for government work."
3536 linkrate = 149760000;
3539 card->link_pcr = (linkrate / 8 / 53);
3540 printk("%s: Linkrate on ATM line : %u bit/s, %u cell/s.\n",
3541 card->name, linkrate, card->link_pcr);
3543 #ifdef CONFIG_ATM_IDT77252_SEND_IDLE
3544 card->utopia_pcr = card->link_pcr;
3546 card->utopia_pcr = (160000000 / 8 / 54);
3550 if (card->utopia_pcr > card->link_pcr)
3551 rsvdcr = card->utopia_pcr - card->link_pcr;
3553 tmpl = (unsigned long) rsvdcr * ((unsigned long) card->tst_size - 2);
3554 modl = tmpl % (unsigned long)card->utopia_pcr;
3555 tst_entries = (int) (tmpl / (unsigned long)card->utopia_pcr);
3558 card->tst_free -= tst_entries;
3559 fill_tst(card, NULL, tst_entries, TSTE_OPC_NULL);
3562 idt77252_eeprom_init(card);
3563 printk("%s: EEPROM: %02x:", card->name,
3564 idt77252_eeprom_read_status(card));
3566 for (i = 0; i < 0x80; i++) {
3568 idt77252_eeprom_read_byte(card, i)
3572 #endif /* HAVE_EEPROM */
3577 sprintf(tname, "eth%d", card->index);
3578 tmp = dev_get_by_name(tname); /* jhs: was "tmp = dev_get(tname);" */
3580 memcpy(card->atmdev->esi, tmp->dev_addr, 6);
3582 printk("%s: ESI %02x:%02x:%02x:%02x:%02x:%02x\n",
3583 card->name, card->atmdev->esi[0], card->atmdev->esi[1],
3584 card->atmdev->esi[2], card->atmdev->esi[3],
3585 card->atmdev->esi[4], card->atmdev->esi[5]);
3591 /* Set Maximum Deficit Count for now. */
3592 writel(0xffff, SAR_REG_MDFCT);
3594 set_bit(IDT77252_BIT_INIT, &card->flags);
3596 XPRINTK("%s: IDT77252 ABR SAR initialization complete.\n", card->name);
3601 /*****************************************************************************/
3603 /* Probing of IDT77252 ABR SAR */
3605 /*****************************************************************************/
3608 static int __devinit
3609 idt77252_preset(struct idt77252_dev *card)
3613 /*****************************************************************/
3614 /* P C I C O N F I G U R A T I O N */
3615 /*****************************************************************/
3617 XPRINTK("%s: Enable PCI master and memory access for SAR.\n",
3619 if (pci_read_config_word(card->pcidev, PCI_COMMAND, &pci_command)) {
3620 printk("%s: can't read PCI_COMMAND.\n", card->name);
3624 if (!(pci_command & PCI_COMMAND_IO)) {
3625 printk("%s: PCI_COMMAND: %04x (???)\n",
3626 card->name, pci_command);
3630 pci_command |= (PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
3631 if (pci_write_config_word(card->pcidev, PCI_COMMAND, pci_command)) {
3632 printk("%s: can't write PCI_COMMAND.\n", card->name);
3636 /*****************************************************************/
3637 /* G E N E R I C R E S E T */
3638 /*****************************************************************/
3640 /* Software reset */
3641 writel(SAR_CFG_SWRST, SAR_REG_CFG);
3643 writel(0, SAR_REG_CFG);
3645 IPRINTK("%s: Software resetted.\n", card->name);
3650 static unsigned long __devinit
3651 probe_sram(struct idt77252_dev *card)
3655 writel(0, SAR_REG_DR0);
3656 writel(SAR_CMD_WRITE_SRAM | (0 << 2), SAR_REG_CMD);
3658 for (addr = 0x4000; addr < 0x80000; addr += 0x4000) {
3659 writel(0xdeadbeef, SAR_REG_DR0);
3660 writel(SAR_CMD_WRITE_SRAM | (addr << 2), SAR_REG_CMD);
3662 writel(SAR_CMD_READ_SRAM | (0 << 2), SAR_REG_CMD);
3663 data = readl(SAR_REG_DR0);
3669 return addr * sizeof(u32);
3672 static int __devinit
3673 idt77252_init_one(struct pci_dev *pcidev, const struct pci_device_id *id)
3675 static struct idt77252_dev **last = &idt77252_chain;
3676 static int index = 0;
3678 unsigned long membase, srambase;
3679 struct idt77252_dev *card;
3680 struct atm_dev *dev;
3681 ushort revision = 0;
3685 if ((err = pci_enable_device(pcidev))) {
3686 printk("idt77252: can't enable PCI device at %s\n", pci_name(pcidev));
3690 if (pci_read_config_word(pcidev, PCI_REVISION_ID, &revision)) {
3691 printk("idt77252-%d: can't read PCI_REVISION_ID\n", index);
3693 goto err_out_disable_pdev;
3696 card = kmalloc(sizeof(struct idt77252_dev), GFP_KERNEL);
3698 printk("idt77252-%d: can't allocate private data\n", index);
3700 goto err_out_disable_pdev;
3702 memset(card, 0, sizeof(struct idt77252_dev));
3704 card->revision = revision;
3705 card->index = index;
3706 card->pcidev = pcidev;
3707 sprintf(card->name, "idt77252-%d", card->index);
3709 INIT_WORK(&card->tqueue, idt77252_softint, (void *)card);
3711 membase = pci_resource_start(pcidev, 1);
3712 srambase = pci_resource_start(pcidev, 2);
3714 init_MUTEX(&card->mutex);
3715 spin_lock_init(&card->cmd_lock);
3716 spin_lock_init(&card->tst_lock);
3718 init_timer(&card->tst_timer);
3719 card->tst_timer.data = (unsigned long)card;
3720 card->tst_timer.function = tst_timer;
3722 /* Do the I/O remapping... */
3723 card->membase = ioremap(membase, 1024);
3724 if (!card->membase) {
3725 printk("%s: can't ioremap() membase\n", card->name);
3727 goto err_out_free_card;
3730 if (idt77252_preset(card)) {
3731 printk("%s: preset failed\n", card->name);
3733 goto err_out_iounmap;
3736 dev = atm_dev_register("idt77252", &idt77252_ops, -1, NULL);
3738 printk("%s: can't register atm device\n", card->name);
3740 goto err_out_iounmap;
3742 dev->dev_data = card;
3745 #ifdef CONFIG_ATM_IDT77252_USE_SUNI
3748 printk("%s: can't init SUNI\n", card->name);
3750 goto err_out_deinit_card;
3752 #endif /* CONFIG_ATM_IDT77252_USE_SUNI */
3754 card->sramsize = probe_sram(card);
3756 for (i = 0; i < 4; i++) {
3757 card->fbq[i] = ioremap(srambase | 0x200000 | (i << 18), 4);
3758 if (!card->fbq[i]) {
3759 printk("%s: can't ioremap() FBQ%d\n", card->name, i);
3761 goto err_out_deinit_card;
3765 printk("%s: ABR SAR (Rev %c): MEM %08lx SRAM %08lx [%u KB]\n",
3766 card->name, ((revision > 1) && (revision < 25)) ?
3767 'A' + revision - 1 : '?', membase, srambase,
3768 card->sramsize / 1024);
3770 if (init_card(dev)) {
3771 printk("%s: init_card failed\n", card->name);
3773 goto err_out_deinit_card;
3776 dev->ci_range.vpi_bits = card->vpibits;
3777 dev->ci_range.vci_bits = card->vcibits;
3778 dev->link_rate = card->link_pcr;
3780 if (dev->phy->start)
3781 dev->phy->start(dev);
3783 if (idt77252_dev_open(card)) {
3784 printk("%s: dev_open failed\n", card->name);
3797 dev->phy->stop(dev);
3799 err_out_deinit_card:
3803 iounmap(card->membase);
3808 err_out_disable_pdev:
3809 pci_disable_device(pcidev);
3813 static struct pci_device_id idt77252_pci_tbl[] =
3815 { PCI_VENDOR_ID_IDT, PCI_DEVICE_ID_IDT_IDT77252,
3816 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
3820 MODULE_DEVICE_TABLE(pci, idt77252_pci_tbl);
3822 static struct pci_driver idt77252_driver = {
3824 .id_table = idt77252_pci_tbl,
3825 .probe = idt77252_init_one,
3828 static int __init idt77252_init(void)
3830 struct sk_buff *skb;
3832 printk("%s: at %p\n", __FUNCTION__, idt77252_init);
3834 if (sizeof(skb->cb) < sizeof(struct atm_skb_data) +
3835 sizeof(struct idt77252_skb_prv)) {
3836 printk(KERN_ERR "%s: skb->cb is too small (%lu < %lu)\n",
3837 __FUNCTION__, (unsigned long) sizeof(skb->cb),
3838 (unsigned long) sizeof(struct atm_skb_data) +
3839 sizeof(struct idt77252_skb_prv));
3843 return pci_register_driver(&idt77252_driver);
3846 static void __exit idt77252_exit(void)
3848 struct idt77252_dev *card;
3849 struct atm_dev *dev;
3851 pci_unregister_driver(&idt77252_driver);
3853 while (idt77252_chain) {
3854 card = idt77252_chain;
3856 idt77252_chain = card->next;
3859 dev->phy->stop(dev);
3861 pci_disable_device(card->pcidev);
3865 DIPRINTK("idt77252: finished cleanup-module().\n");
3868 module_init(idt77252_init);
3869 module_exit(idt77252_exit);
3871 MODULE_LICENSE("GPL");
3873 module_param(vpibits, uint, 0);
3874 MODULE_PARM_DESC(vpibits, "number of VPI bits supported (0, 1, or 2)");
3875 #ifdef CONFIG_ATM_IDT77252_DEBUG
3876 module_param(debug, ulong, 0644);
3877 MODULE_PARM_DESC(debug, "debug bitmap, see drivers/atm/idt77252.h");
3880 MODULE_AUTHOR("Eddie C. Dost <ecd@atecom.com>");
3881 MODULE_DESCRIPTION("IDT77252 ABR SAR Driver");