1 /*******************************************************************
2 * ident "$Id: idt77252.c,v 1.2 2001/11/11 08:13:54 ecd Exp $"
5 * $Date: 2001/11/11 08:13:54 $
7 * Copyright (c) 2000 ATecoM GmbH
9 * The author may be reached at ecd@atecom.com.
11 * This program is free software; you can redistribute it and/or modify it
12 * under the terms of the GNU General Public License as published by the
13 * Free Software Foundation; either version 2 of the License, or (at your
14 * option) any later version.
16 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
17 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
18 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
19 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
21 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
22 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
23 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
24 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
25 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 * You should have received a copy of the GNU General Public License along
28 * with this program; if not, write to the Free Software Foundation, Inc.,
29 * 675 Mass Ave, Cambridge, MA 02139, USA.
31 *******************************************************************/
32 static char const rcsid[] =
33 "$Id: idt77252.c,v 1.2 2001/11/11 08:13:54 ecd Exp $";
36 #include <linux/module.h>
37 #include <linux/config.h>
38 #include <linux/pci.h>
39 #include <linux/skbuff.h>
40 #include <linux/kernel.h>
41 #include <linux/vmalloc.h>
42 #include <linux/netdevice.h>
43 #include <linux/atmdev.h>
44 #include <linux/atm.h>
45 #include <linux/delay.h>
46 #include <linux/init.h>
47 #include <linux/bitops.h>
48 #include <linux/wait.h>
49 #include <asm/semaphore.h>
51 #include <asm/uaccess.h>
52 #include <asm/atomic.h>
53 #include <asm/byteorder.h>
55 #ifdef CONFIG_ATM_IDT77252_USE_SUNI
57 #endif /* CONFIG_ATM_IDT77252_USE_SUNI */
61 #include "idt77252_tables.h"
63 static unsigned int vpibits = 1;
66 #define CONFIG_ATM_IDT77252_SEND_IDLE 1
72 #define DEBUG_MODULE 1
73 #undef HAVE_EEPROM /* does not work, yet. */
75 #ifdef CONFIG_ATM_IDT77252_DEBUG
76 static unsigned long debug = DBG_GENERAL;
80 #define SAR_RX_DELAY (SAR_CFG_RXINT_NODELAY)
86 static struct scq_info *alloc_scq(struct idt77252_dev *, int);
87 static void free_scq(struct idt77252_dev *, struct scq_info *);
88 static int queue_skb(struct idt77252_dev *, struct vc_map *,
89 struct sk_buff *, int oam);
90 static void drain_scq(struct idt77252_dev *, struct vc_map *);
91 static unsigned long get_free_scd(struct idt77252_dev *, struct vc_map *);
92 static void fill_scd(struct idt77252_dev *, struct scq_info *, int);
97 static int push_rx_skb(struct idt77252_dev *,
98 struct sk_buff *, int queue);
99 static void recycle_rx_skb(struct idt77252_dev *, struct sk_buff *);
100 static void flush_rx_pool(struct idt77252_dev *, struct rx_pool *);
101 static void recycle_rx_pool_skb(struct idt77252_dev *,
103 static void add_rx_skb(struct idt77252_dev *, int queue,
104 unsigned int size, unsigned int count);
109 static int init_rsq(struct idt77252_dev *);
110 static void deinit_rsq(struct idt77252_dev *);
111 static void idt77252_rx(struct idt77252_dev *);
116 static int init_tsq(struct idt77252_dev *);
117 static void deinit_tsq(struct idt77252_dev *);
118 static void idt77252_tx(struct idt77252_dev *);
124 static void idt77252_dev_close(struct atm_dev *dev);
125 static int idt77252_open(struct atm_vcc *vcc);
126 static void idt77252_close(struct atm_vcc *vcc);
127 static int idt77252_send(struct atm_vcc *vcc, struct sk_buff *skb);
128 static int idt77252_send_oam(struct atm_vcc *vcc, void *cell,
130 static void idt77252_phy_put(struct atm_dev *dev, unsigned char value,
132 static unsigned char idt77252_phy_get(struct atm_dev *dev, unsigned long addr);
133 static int idt77252_change_qos(struct atm_vcc *vcc, struct atm_qos *qos,
135 static int idt77252_proc_read(struct atm_dev *dev, loff_t * pos,
137 static void idt77252_softint(void *dev_id);
140 static struct atmdev_ops idt77252_ops =
142 .dev_close = idt77252_dev_close,
143 .open = idt77252_open,
144 .close = idt77252_close,
145 .send = idt77252_send,
146 .send_oam = idt77252_send_oam,
147 .phy_put = idt77252_phy_put,
148 .phy_get = idt77252_phy_get,
149 .change_qos = idt77252_change_qos,
150 .proc_read = idt77252_proc_read,
154 static struct idt77252_dev *idt77252_chain = NULL;
155 static unsigned int idt77252_sram_write_errors = 0;
157 /*****************************************************************************/
159 /* I/O and Utility Bus */
161 /*****************************************************************************/
164 waitfor_idle(struct idt77252_dev *card)
168 stat = readl(SAR_REG_STAT);
169 while (stat & SAR_STAT_CMDBZ)
170 stat = readl(SAR_REG_STAT);
174 read_sram(struct idt77252_dev *card, unsigned long addr)
179 spin_lock_irqsave(&card->cmd_lock, flags);
180 writel(SAR_CMD_READ_SRAM | (addr << 2), SAR_REG_CMD);
182 value = readl(SAR_REG_DR0);
183 spin_unlock_irqrestore(&card->cmd_lock, flags);
188 write_sram(struct idt77252_dev *card, unsigned long addr, u32 value)
192 if ((idt77252_sram_write_errors == 0) &&
193 (((addr > card->tst[0] + card->tst_size - 2) &&
194 (addr < card->tst[0] + card->tst_size)) ||
195 ((addr > card->tst[1] + card->tst_size - 2) &&
196 (addr < card->tst[1] + card->tst_size)))) {
197 printk("%s: ERROR: TST JMP section at %08lx written: %08x\n",
198 card->name, addr, value);
201 spin_lock_irqsave(&card->cmd_lock, flags);
202 writel(value, SAR_REG_DR0);
203 writel(SAR_CMD_WRITE_SRAM | (addr << 2), SAR_REG_CMD);
205 spin_unlock_irqrestore(&card->cmd_lock, flags);
209 read_utility(void *dev, unsigned long ubus_addr)
211 struct idt77252_dev *card = dev;
216 printk("Error: No such device.\n");
220 spin_lock_irqsave(&card->cmd_lock, flags);
221 writel(SAR_CMD_READ_UTILITY + ubus_addr, SAR_REG_CMD);
223 value = readl(SAR_REG_DR0);
224 spin_unlock_irqrestore(&card->cmd_lock, flags);
229 write_utility(void *dev, unsigned long ubus_addr, u8 value)
231 struct idt77252_dev *card = dev;
235 printk("Error: No such device.\n");
239 spin_lock_irqsave(&card->cmd_lock, flags);
240 writel((u32) value, SAR_REG_DR0);
241 writel(SAR_CMD_WRITE_UTILITY + ubus_addr, SAR_REG_CMD);
243 spin_unlock_irqrestore(&card->cmd_lock, flags);
247 static u32 rdsrtab[] =
249 SAR_GP_EECS | SAR_GP_EESCLK,
251 SAR_GP_EESCLK, /* 0 */
253 SAR_GP_EESCLK, /* 0 */
255 SAR_GP_EESCLK, /* 0 */
257 SAR_GP_EESCLK, /* 0 */
259 SAR_GP_EESCLK, /* 0 */
261 SAR_GP_EESCLK | SAR_GP_EEDO, /* 1 */
263 SAR_GP_EESCLK, /* 0 */
265 SAR_GP_EESCLK | SAR_GP_EEDO /* 1 */
268 static u32 wrentab[] =
270 SAR_GP_EECS | SAR_GP_EESCLK,
272 SAR_GP_EESCLK, /* 0 */
274 SAR_GP_EESCLK, /* 0 */
276 SAR_GP_EESCLK, /* 0 */
278 SAR_GP_EESCLK, /* 0 */
280 SAR_GP_EESCLK | SAR_GP_EEDO, /* 1 */
282 SAR_GP_EESCLK | SAR_GP_EEDO, /* 1 */
284 SAR_GP_EESCLK, /* 0 */
286 SAR_GP_EESCLK /* 0 */
291 SAR_GP_EECS | SAR_GP_EESCLK,
293 SAR_GP_EESCLK, /* 0 */
295 SAR_GP_EESCLK, /* 0 */
297 SAR_GP_EESCLK, /* 0 */
299 SAR_GP_EESCLK, /* 0 */
301 SAR_GP_EESCLK, /* 0 */
303 SAR_GP_EESCLK, /* 0 */
305 SAR_GP_EESCLK | SAR_GP_EEDO, /* 1 */
307 SAR_GP_EESCLK | SAR_GP_EEDO /* 1 */
312 SAR_GP_EECS | SAR_GP_EESCLK,
314 SAR_GP_EESCLK, /* 0 */
316 SAR_GP_EESCLK, /* 0 */
318 SAR_GP_EESCLK, /* 0 */
320 SAR_GP_EESCLK, /* 0 */
322 SAR_GP_EESCLK, /* 0 */
324 SAR_GP_EESCLK, /* 0 */
326 SAR_GP_EESCLK | SAR_GP_EEDO, /* 1 */
328 SAR_GP_EESCLK /* 0 */
331 static u32 clktab[] =
353 idt77252_read_gp(struct idt77252_dev *card)
357 gp = readl(SAR_REG_GP);
359 printk("RD: %s\n", gp & SAR_GP_EEDI ? "1" : "0");
365 idt77252_write_gp(struct idt77252_dev *card, u32 value)
370 printk("WR: %s %s %s\n", value & SAR_GP_EECS ? " " : "/CS",
371 value & SAR_GP_EESCLK ? "HIGH" : "LOW ",
372 value & SAR_GP_EEDO ? "1" : "0");
375 spin_lock_irqsave(&card->cmd_lock, flags);
377 writel(value, SAR_REG_GP);
378 spin_unlock_irqrestore(&card->cmd_lock, flags);
382 idt77252_eeprom_read_status(struct idt77252_dev *card)
388 gp = idt77252_read_gp(card) & ~(SAR_GP_EESCLK|SAR_GP_EECS|SAR_GP_EEDO);
390 for (i = 0; i < sizeof(rdsrtab)/sizeof(rdsrtab[0]); i++) {
391 idt77252_write_gp(card, gp | rdsrtab[i]);
394 idt77252_write_gp(card, gp | SAR_GP_EECS);
398 for (i = 0, j = 0; i < 8; i++) {
401 idt77252_write_gp(card, gp | clktab[j++]);
404 byte |= idt77252_read_gp(card) & SAR_GP_EEDI ? 1 : 0;
406 idt77252_write_gp(card, gp | clktab[j++]);
409 idt77252_write_gp(card, gp | SAR_GP_EECS);
416 idt77252_eeprom_read_byte(struct idt77252_dev *card, u8 offset)
422 gp = idt77252_read_gp(card) & ~(SAR_GP_EESCLK|SAR_GP_EECS|SAR_GP_EEDO);
424 for (i = 0; i < sizeof(rdtab)/sizeof(rdtab[0]); i++) {
425 idt77252_write_gp(card, gp | rdtab[i]);
428 idt77252_write_gp(card, gp | SAR_GP_EECS);
431 for (i = 0, j = 0; i < 8; i++) {
432 idt77252_write_gp(card, gp | clktab[j++] |
433 (offset & 1 ? SAR_GP_EEDO : 0));
436 idt77252_write_gp(card, gp | clktab[j++] |
437 (offset & 1 ? SAR_GP_EEDO : 0));
442 idt77252_write_gp(card, gp | SAR_GP_EECS);
446 for (i = 0, j = 0; i < 8; i++) {
449 idt77252_write_gp(card, gp | clktab[j++]);
452 byte |= idt77252_read_gp(card) & SAR_GP_EEDI ? 1 : 0;
454 idt77252_write_gp(card, gp | clktab[j++]);
457 idt77252_write_gp(card, gp | SAR_GP_EECS);
464 idt77252_eeprom_write_byte(struct idt77252_dev *card, u8 offset, u8 data)
469 gp = idt77252_read_gp(card) & ~(SAR_GP_EESCLK|SAR_GP_EECS|SAR_GP_EEDO);
471 for (i = 0; i < sizeof(wrentab)/sizeof(wrentab[0]); i++) {
472 idt77252_write_gp(card, gp | wrentab[i]);
475 idt77252_write_gp(card, gp | SAR_GP_EECS);
478 for (i = 0; i < sizeof(wrtab)/sizeof(wrtab[0]); i++) {
479 idt77252_write_gp(card, gp | wrtab[i]);
482 idt77252_write_gp(card, gp | SAR_GP_EECS);
485 for (i = 0, j = 0; i < 8; i++) {
486 idt77252_write_gp(card, gp | clktab[j++] |
487 (offset & 1 ? SAR_GP_EEDO : 0));
490 idt77252_write_gp(card, gp | clktab[j++] |
491 (offset & 1 ? SAR_GP_EEDO : 0));
496 idt77252_write_gp(card, gp | SAR_GP_EECS);
499 for (i = 0, j = 0; i < 8; i++) {
500 idt77252_write_gp(card, gp | clktab[j++] |
501 (data & 1 ? SAR_GP_EEDO : 0));
504 idt77252_write_gp(card, gp | clktab[j++] |
505 (data & 1 ? SAR_GP_EEDO : 0));
510 idt77252_write_gp(card, gp | SAR_GP_EECS);
515 idt77252_eeprom_init(struct idt77252_dev *card)
519 gp = idt77252_read_gp(card) & ~(SAR_GP_EESCLK|SAR_GP_EECS|SAR_GP_EEDO);
521 idt77252_write_gp(card, gp | SAR_GP_EECS | SAR_GP_EESCLK);
523 idt77252_write_gp(card, gp | SAR_GP_EECS);
525 idt77252_write_gp(card, gp | SAR_GP_EECS | SAR_GP_EESCLK);
527 idt77252_write_gp(card, gp | SAR_GP_EECS);
530 #endif /* HAVE_EEPROM */
533 #ifdef CONFIG_ATM_IDT77252_DEBUG
535 dump_tct(struct idt77252_dev *card, int index)
540 tct = (unsigned long) (card->tct_base + index * SAR_SRAM_TCT_SIZE);
542 printk("%s: TCT %x:", card->name, index);
543 for (i = 0; i < 8; i++) {
544 printk(" %08x", read_sram(card, tct + i));
550 idt77252_tx_dump(struct idt77252_dev *card)
556 printk("%s\n", __FUNCTION__);
557 for (i = 0; i < card->tct_size; i++) {
571 printk("%s: Connection %d:\n", card->name, vc->index);
572 dump_tct(card, vc->index);
578 /*****************************************************************************/
582 /*****************************************************************************/
585 sb_pool_add(struct idt77252_dev *card, struct sk_buff *skb, int queue)
587 struct sb_pool *pool = &card->sbpool[queue];
591 while (pool->skb[index]) {
592 index = (index + 1) & FBQ_MASK;
593 if (index == pool->index)
597 pool->skb[index] = skb;
598 IDT77252_PRV_POOL(skb) = POOL_HANDLE(queue, index);
600 pool->index = (index + 1) & FBQ_MASK;
605 sb_pool_remove(struct idt77252_dev *card, struct sk_buff *skb)
607 unsigned int queue, index;
610 handle = IDT77252_PRV_POOL(skb);
612 queue = POOL_QUEUE(handle);
616 index = POOL_INDEX(handle);
617 if (index > FBQ_SIZE - 1)
620 card->sbpool[queue].skb[index] = NULL;
623 static struct sk_buff *
624 sb_pool_skb(struct idt77252_dev *card, u32 handle)
626 unsigned int queue, index;
628 queue = POOL_QUEUE(handle);
632 index = POOL_INDEX(handle);
633 if (index > FBQ_SIZE - 1)
636 return card->sbpool[queue].skb[index];
639 static struct scq_info *
640 alloc_scq(struct idt77252_dev *card, int class)
642 struct scq_info *scq;
644 scq = (struct scq_info *) kmalloc(sizeof(struct scq_info), GFP_KERNEL);
647 memset(scq, 0, sizeof(struct scq_info));
649 scq->base = pci_alloc_consistent(card->pcidev, SCQ_SIZE,
651 if (scq->base == NULL) {
655 memset(scq->base, 0, SCQ_SIZE);
657 scq->next = scq->base;
658 scq->last = scq->base + (SCQ_ENTRIES - 1);
659 atomic_set(&scq->used, 0);
661 spin_lock_init(&scq->lock);
662 spin_lock_init(&scq->skblock);
664 skb_queue_head_init(&scq->transmit);
665 skb_queue_head_init(&scq->pending);
667 TXPRINTK("idt77252: SCQ: base 0x%p, next 0x%p, last 0x%p, paddr %08llx\n",
668 scq->base, scq->next, scq->last, (unsigned long long)scq->paddr);
674 free_scq(struct idt77252_dev *card, struct scq_info *scq)
679 pci_free_consistent(card->pcidev, SCQ_SIZE,
680 scq->base, scq->paddr);
682 while ((skb = skb_dequeue(&scq->transmit))) {
683 pci_unmap_single(card->pcidev, IDT77252_PRV_PADDR(skb),
684 skb->len, PCI_DMA_TODEVICE);
686 vcc = ATM_SKB(skb)->vcc;
693 while ((skb = skb_dequeue(&scq->pending))) {
694 pci_unmap_single(card->pcidev, IDT77252_PRV_PADDR(skb),
695 skb->len, PCI_DMA_TODEVICE);
697 vcc = ATM_SKB(skb)->vcc;
709 push_on_scq(struct idt77252_dev *card, struct vc_map *vc, struct sk_buff *skb)
711 struct scq_info *scq = vc->scq;
716 TXPRINTK("%s: SCQ: next 0x%p\n", card->name, scq->next);
718 atomic_inc(&scq->used);
719 entries = atomic_read(&scq->used);
720 if (entries > (SCQ_ENTRIES - 1)) {
721 atomic_dec(&scq->used);
725 skb_queue_tail(&scq->transmit, skb);
727 spin_lock_irqsave(&vc->lock, flags);
729 struct atm_vcc *vcc = vc->tx_vcc;
731 vc->estimator->cells += (skb->len + 47) / 48;
732 if (atomic_read(&vcc->sk->sk_wmem_alloc) >
733 (vcc->sk->sk_sndbuf >> 1)) {
734 u32 cps = vc->estimator->maxcps;
736 vc->estimator->cps = cps;
737 vc->estimator->avcps = cps << 5;
738 if (vc->lacr < vc->init_er) {
739 vc->lacr = vc->init_er;
740 writel(TCMDQ_LACR | (vc->lacr << 16) |
741 vc->index, SAR_REG_TCMDQ);
745 spin_unlock_irqrestore(&vc->lock, flags);
747 tbd = &IDT77252_PRV_TBD(skb);
749 spin_lock_irqsave(&scq->lock, flags);
750 scq->next->word_1 = cpu_to_le32(tbd->word_1 |
751 SAR_TBD_TSIF | SAR_TBD_GTSI);
752 scq->next->word_2 = cpu_to_le32(tbd->word_2);
753 scq->next->word_3 = cpu_to_le32(tbd->word_3);
754 scq->next->word_4 = cpu_to_le32(tbd->word_4);
756 if (scq->next == scq->last)
757 scq->next = scq->base;
761 write_sram(card, scq->scd,
763 (u32)((unsigned long)scq->next - (unsigned long)scq->base));
764 spin_unlock_irqrestore(&scq->lock, flags);
766 scq->trans_start = jiffies;
768 if (test_and_clear_bit(VCF_IDLE, &vc->flags)) {
769 writel(TCMDQ_START_LACR | (vc->lacr << 16) | vc->index,
773 TXPRINTK("%d entries in SCQ used (push).\n", atomic_read(&scq->used));
775 XPRINTK("%s: SCQ (after push %2d) head = 0x%x, next = 0x%p.\n",
776 card->name, atomic_read(&scq->used),
777 read_sram(card, scq->scd + 1), scq->next);
782 if (jiffies - scq->trans_start > HZ) {
783 printk("%s: Error pushing TBD for %d.%d\n",
784 card->name, vc->tx_vcc->vpi, vc->tx_vcc->vci);
785 #ifdef CONFIG_ATM_IDT77252_DEBUG
786 idt77252_tx_dump(card);
788 scq->trans_start = jiffies;
796 drain_scq(struct idt77252_dev *card, struct vc_map *vc)
798 struct scq_info *scq = vc->scq;
802 TXPRINTK("%s: SCQ (before drain %2d) next = 0x%p.\n",
803 card->name, atomic_read(&scq->used), scq->next);
805 skb = skb_dequeue(&scq->transmit);
807 TXPRINTK("%s: freeing skb at %p.\n", card->name, skb);
809 pci_unmap_single(card->pcidev, IDT77252_PRV_PADDR(skb),
810 skb->len, PCI_DMA_TODEVICE);
812 vcc = ATM_SKB(skb)->vcc;
819 atomic_inc(&vcc->stats->tx);
822 atomic_dec(&scq->used);
824 spin_lock(&scq->skblock);
825 while ((skb = skb_dequeue(&scq->pending))) {
826 if (push_on_scq(card, vc, skb)) {
827 skb_queue_head(&vc->scq->pending, skb);
831 spin_unlock(&scq->skblock);
835 queue_skb(struct idt77252_dev *card, struct vc_map *vc,
836 struct sk_buff *skb, int oam)
845 printk("%s: invalid skb->len (%d)\n", card->name, skb->len);
849 TXPRINTK("%s: Sending %d bytes of data.\n",
850 card->name, skb->len);
852 tbd = &IDT77252_PRV_TBD(skb);
853 vcc = ATM_SKB(skb)->vcc;
855 IDT77252_PRV_PADDR(skb) = pci_map_single(card->pcidev, skb->data,
856 skb->len, PCI_DMA_TODEVICE);
864 tbd->word_1 = SAR_TBD_OAM | ATM_CELL_PAYLOAD | SAR_TBD_EPDU;
865 tbd->word_2 = IDT77252_PRV_PADDR(skb) + 4;
866 tbd->word_3 = 0x00000000;
867 tbd->word_4 = (skb->data[0] << 24) | (skb->data[1] << 16) |
868 (skb->data[2] << 8) | (skb->data[3] << 0);
870 if (test_bit(VCF_RSV, &vc->flags))
876 if (test_bit(VCF_RSV, &vc->flags)) {
877 printk("%s: Trying to transmit on reserved VC\n", card->name);
890 tbd->word_1 = SAR_TBD_EPDU | SAR_TBD_AAL0 |
893 tbd->word_1 = SAR_TBD_EPDU | SAR_TBD_AAL34 |
896 tbd->word_2 = IDT77252_PRV_PADDR(skb) + 4;
897 tbd->word_3 = 0x00000000;
898 tbd->word_4 = (skb->data[0] << 24) | (skb->data[1] << 16) |
899 (skb->data[2] << 8) | (skb->data[3] << 0);
903 tbd->word_1 = SAR_TBD_EPDU | SAR_TBD_AAL5 | skb->len;
904 tbd->word_2 = IDT77252_PRV_PADDR(skb);
905 tbd->word_3 = skb->len;
906 tbd->word_4 = (vcc->vpi << SAR_TBD_VPI_SHIFT) |
907 (vcc->vci << SAR_TBD_VCI_SHIFT);
913 printk("%s: Traffic type not supported.\n", card->name);
914 error = -EPROTONOSUPPORT;
919 spin_lock_irqsave(&vc->scq->skblock, flags);
920 skb_queue_tail(&vc->scq->pending, skb);
922 while ((skb = skb_dequeue(&vc->scq->pending))) {
923 if (push_on_scq(card, vc, skb)) {
924 skb_queue_head(&vc->scq->pending, skb);
928 spin_unlock_irqrestore(&vc->scq->skblock, flags);
933 pci_unmap_single(card->pcidev, IDT77252_PRV_PADDR(skb),
934 skb->len, PCI_DMA_TODEVICE);
939 get_free_scd(struct idt77252_dev *card, struct vc_map *vc)
943 for (i = 0; i < card->scd_size; i++) {
944 if (!card->scd2vc[i]) {
945 card->scd2vc[i] = vc;
947 return card->scd_base + i * SAR_SRAM_SCD_SIZE;
954 fill_scd(struct idt77252_dev *card, struct scq_info *scq, int class)
956 write_sram(card, scq->scd, scq->paddr);
957 write_sram(card, scq->scd + 1, 0x00000000);
958 write_sram(card, scq->scd + 2, 0xffffffff);
959 write_sram(card, scq->scd + 3, 0x00000000);
963 clear_scd(struct idt77252_dev *card, struct scq_info *scq, int class)
968 /*****************************************************************************/
972 /*****************************************************************************/
975 init_rsq(struct idt77252_dev *card)
977 struct rsq_entry *rsqe;
979 card->rsq.base = pci_alloc_consistent(card->pcidev, RSQSIZE,
981 if (card->rsq.base == NULL) {
982 printk("%s: can't allocate RSQ.\n", card->name);
985 memset(card->rsq.base, 0, RSQSIZE);
987 card->rsq.last = card->rsq.base + RSQ_NUM_ENTRIES - 1;
988 card->rsq.next = card->rsq.last;
989 for (rsqe = card->rsq.base; rsqe <= card->rsq.last; rsqe++)
992 writel((unsigned long) card->rsq.last - (unsigned long) card->rsq.base,
994 writel(card->rsq.paddr, SAR_REG_RSQB);
996 IPRINTK("%s: RSQ base at 0x%lx (0x%x).\n", card->name,
997 (unsigned long) card->rsq.base,
998 readl(SAR_REG_RSQB));
999 IPRINTK("%s: RSQ head = 0x%x, base = 0x%x, tail = 0x%x.\n",
1001 readl(SAR_REG_RSQH),
1002 readl(SAR_REG_RSQB),
1003 readl(SAR_REG_RSQT));
1009 deinit_rsq(struct idt77252_dev *card)
1011 pci_free_consistent(card->pcidev, RSQSIZE,
1012 card->rsq.base, card->rsq.paddr);
1016 dequeue_rx(struct idt77252_dev *card, struct rsq_entry *rsqe)
1018 struct atm_vcc *vcc;
1019 struct sk_buff *skb;
1020 struct rx_pool *rpp;
1022 u32 header, vpi, vci;
1026 stat = le32_to_cpu(rsqe->word_4);
1028 if (stat & SAR_RSQE_IDLE) {
1029 RXPRINTK("%s: message about inactive connection.\n",
1034 skb = sb_pool_skb(card, le32_to_cpu(rsqe->word_2));
1036 printk("%s: NULL skb in %s, rsqe: %08x %08x %08x %08x\n",
1037 card->name, __FUNCTION__,
1038 le32_to_cpu(rsqe->word_1), le32_to_cpu(rsqe->word_2),
1039 le32_to_cpu(rsqe->word_3), le32_to_cpu(rsqe->word_4));
1043 header = le32_to_cpu(rsqe->word_1);
1044 vpi = (header >> 16) & 0x00ff;
1045 vci = (header >> 0) & 0xffff;
1047 RXPRINTK("%s: SDU for %d.%d received in buffer 0x%p (data 0x%p).\n",
1048 card->name, vpi, vci, skb, skb->data);
1050 if ((vpi >= (1 << card->vpibits)) || (vci != (vci & card->vcimask))) {
1051 printk("%s: SDU received for out-of-range vc %u.%u\n",
1052 card->name, vpi, vci);
1053 recycle_rx_skb(card, skb);
1057 vc = card->vcs[VPCI2VC(card, vpi, vci)];
1058 if (!vc || !test_bit(VCF_RX, &vc->flags)) {
1059 printk("%s: SDU received on non RX vc %u.%u\n",
1060 card->name, vpi, vci);
1061 recycle_rx_skb(card, skb);
1067 pci_dma_sync_single_for_cpu(card->pcidev, IDT77252_PRV_PADDR(skb),
1068 skb->end - skb->data, PCI_DMA_FROMDEVICE);
1070 if ((vcc->qos.aal == ATM_AAL0) ||
1071 (vcc->qos.aal == ATM_AAL34)) {
1073 unsigned char *cell;
1077 for (i = (stat & SAR_RSQE_CELLCNT); i; i--) {
1078 if ((sb = dev_alloc_skb(64)) == NULL) {
1079 printk("%s: Can't allocate buffers for aal0.\n",
1081 atomic_add(i, &vcc->stats->rx_drop);
1084 if (!atm_charge(vcc, sb->truesize)) {
1085 RXPRINTK("%s: atm_charge() dropped aal0 packets.\n",
1087 atomic_add(i - 1, &vcc->stats->rx_drop);
1091 aal0 = (vpi << ATM_HDR_VPI_SHIFT) |
1092 (vci << ATM_HDR_VCI_SHIFT);
1093 aal0 |= (stat & SAR_RSQE_EPDU) ? 0x00000002 : 0;
1094 aal0 |= (stat & SAR_RSQE_CLP) ? 0x00000001 : 0;
1096 *((u32 *) sb->data) = aal0;
1097 skb_put(sb, sizeof(u32));
1098 memcpy(skb_put(sb, ATM_CELL_PAYLOAD),
1099 cell, ATM_CELL_PAYLOAD);
1101 ATM_SKB(sb)->vcc = vcc;
1102 do_gettimeofday(&sb->stamp);
1104 atomic_inc(&vcc->stats->rx);
1106 cell += ATM_CELL_PAYLOAD;
1109 recycle_rx_skb(card, skb);
1112 if (vcc->qos.aal != ATM_AAL5) {
1113 printk("%s: Unexpected AAL type in dequeue_rx(): %d.\n",
1114 card->name, vcc->qos.aal);
1115 recycle_rx_skb(card, skb);
1118 skb->len = (stat & SAR_RSQE_CELLCNT) * ATM_CELL_PAYLOAD;
1120 rpp = &vc->rcv.rx_pool;
1122 rpp->len += skb->len;
1126 rpp->last = &skb->next;
1128 if (stat & SAR_RSQE_EPDU) {
1129 unsigned char *l1l2;
1132 l1l2 = (unsigned char *) ((unsigned long) skb->data + skb->len - 6);
1134 len = (l1l2[0] << 8) | l1l2[1];
1135 len = len ? len : 0x10000;
1137 RXPRINTK("%s: PDU has %d bytes.\n", card->name, len);
1139 if ((len + 8 > rpp->len) || (len + (47 + 8) < rpp->len)) {
1140 RXPRINTK("%s: AAL5 PDU size mismatch: %d != %d. "
1142 card->name, len, rpp->len, readl(SAR_REG_CDC));
1143 recycle_rx_pool_skb(card, rpp);
1144 atomic_inc(&vcc->stats->rx_err);
1147 if (stat & SAR_RSQE_CRC) {
1148 RXPRINTK("%s: AAL5 CRC error.\n", card->name);
1149 recycle_rx_pool_skb(card, rpp);
1150 atomic_inc(&vcc->stats->rx_err);
1153 if (rpp->count > 1) {
1156 skb = dev_alloc_skb(rpp->len);
1158 RXPRINTK("%s: Can't alloc RX skb.\n",
1160 recycle_rx_pool_skb(card, rpp);
1161 atomic_inc(&vcc->stats->rx_err);
1164 if (!atm_charge(vcc, skb->truesize)) {
1165 recycle_rx_pool_skb(card, rpp);
1170 for (i = 0; i < rpp->count; i++) {
1171 memcpy(skb_put(skb, sb->len),
1176 recycle_rx_pool_skb(card, rpp);
1179 ATM_SKB(skb)->vcc = vcc;
1180 do_gettimeofday(&skb->stamp);
1182 vcc->push(vcc, skb);
1183 atomic_inc(&vcc->stats->rx);
1189 flush_rx_pool(card, rpp);
1191 if (!atm_charge(vcc, skb->truesize)) {
1192 recycle_rx_skb(card, skb);
1196 pci_unmap_single(card->pcidev, IDT77252_PRV_PADDR(skb),
1197 skb->end - skb->data, PCI_DMA_FROMDEVICE);
1198 sb_pool_remove(card, skb);
1201 ATM_SKB(skb)->vcc = vcc;
1202 do_gettimeofday(&skb->stamp);
1204 vcc->push(vcc, skb);
1205 atomic_inc(&vcc->stats->rx);
1207 if (skb->truesize > SAR_FB_SIZE_3)
1208 add_rx_skb(card, 3, SAR_FB_SIZE_3, 1);
1209 else if (skb->truesize > SAR_FB_SIZE_2)
1210 add_rx_skb(card, 2, SAR_FB_SIZE_2, 1);
1211 else if (skb->truesize > SAR_FB_SIZE_1)
1212 add_rx_skb(card, 1, SAR_FB_SIZE_1, 1);
1214 add_rx_skb(card, 0, SAR_FB_SIZE_0, 1);
1220 idt77252_rx(struct idt77252_dev *card)
1222 struct rsq_entry *rsqe;
1224 if (card->rsq.next == card->rsq.last)
1225 rsqe = card->rsq.base;
1227 rsqe = card->rsq.next + 1;
1229 if (!(le32_to_cpu(rsqe->word_4) & SAR_RSQE_VALID)) {
1230 RXPRINTK("%s: no entry in RSQ.\n", card->name);
1235 dequeue_rx(card, rsqe);
1237 card->rsq.next = rsqe;
1238 if (card->rsq.next == card->rsq.last)
1239 rsqe = card->rsq.base;
1241 rsqe = card->rsq.next + 1;
1242 } while (le32_to_cpu(rsqe->word_4) & SAR_RSQE_VALID);
1244 writel((unsigned long) card->rsq.next - (unsigned long) card->rsq.base,
1249 idt77252_rx_raw(struct idt77252_dev *card)
1251 struct sk_buff *queue;
1253 struct atm_vcc *vcc;
1257 if (card->raw_cell_head == NULL) {
1258 u32 handle = le32_to_cpu(*(card->raw_cell_hnd + 1));
1259 card->raw_cell_head = sb_pool_skb(card, handle);
1262 queue = card->raw_cell_head;
1266 head = IDT77252_PRV_PADDR(queue) + (queue->data - queue->head - 16);
1267 tail = readl(SAR_REG_RAWCT);
1269 pci_dma_sync_single(card->pcidev, IDT77252_PRV_PADDR(queue),
1270 queue->end - queue->head - 16, PCI_DMA_FROMDEVICE);
1272 while (head != tail) {
1273 unsigned int vpi, vci, pti;
1276 header = le32_to_cpu(*(u32 *) &queue->data[0]);
1278 vpi = (header & ATM_HDR_VPI_MASK) >> ATM_HDR_VPI_SHIFT;
1279 vci = (header & ATM_HDR_VCI_MASK) >> ATM_HDR_VCI_SHIFT;
1280 pti = (header & ATM_HDR_PTI_MASK) >> ATM_HDR_PTI_SHIFT;
1282 #ifdef CONFIG_ATM_IDT77252_DEBUG
1283 if (debug & DBG_RAW_CELL) {
1286 printk("%s: raw cell %x.%02x.%04x.%x.%x\n",
1287 card->name, (header >> 28) & 0x000f,
1288 (header >> 20) & 0x00ff,
1289 (header >> 4) & 0xffff,
1290 (header >> 1) & 0x0007,
1291 (header >> 0) & 0x0001);
1292 for (i = 16; i < 64; i++)
1293 printk(" %02x", queue->data[i]);
1298 if (vpi >= (1<<card->vpibits) || vci >= (1<<card->vcibits)) {
1299 RPRINTK("%s: SDU received for out-of-range vc %u.%u\n",
1300 card->name, vpi, vci);
1304 vc = card->vcs[VPCI2VC(card, vpi, vci)];
1305 if (!vc || !test_bit(VCF_RX, &vc->flags)) {
1306 RPRINTK("%s: SDU received on non RX vc %u.%u\n",
1307 card->name, vpi, vci);
1313 if (vcc->qos.aal != ATM_AAL0) {
1314 RPRINTK("%s: raw cell for non AAL0 vc %u.%u\n",
1315 card->name, vpi, vci);
1316 atomic_inc(&vcc->stats->rx_drop);
1320 if ((sb = dev_alloc_skb(64)) == NULL) {
1321 printk("%s: Can't allocate buffers for AAL0.\n",
1323 atomic_inc(&vcc->stats->rx_err);
1327 if ((vcc->sk != NULL) && !atm_charge(vcc, sb->truesize)) {
1328 RXPRINTK("%s: atm_charge() dropped AAL0 packets.\n",
1334 *((u32 *) sb->data) = header;
1335 skb_put(sb, sizeof(u32));
1336 memcpy(skb_put(sb, ATM_CELL_PAYLOAD), &(queue->data[16]),
1339 ATM_SKB(sb)->vcc = vcc;
1340 do_gettimeofday(&sb->stamp);
1342 atomic_inc(&vcc->stats->rx);
1345 skb_pull(queue, 64);
1347 head = IDT77252_PRV_PADDR(queue)
1348 + (queue->data - queue->head - 16);
1350 if (queue->len < 128) {
1351 struct sk_buff *next;
1354 head = le32_to_cpu(*(u32 *) &queue->data[0]);
1355 handle = le32_to_cpu(*(u32 *) &queue->data[4]);
1357 next = sb_pool_skb(card, handle);
1358 recycle_rx_skb(card, queue);
1361 card->raw_cell_head = next;
1362 queue = card->raw_cell_head;
1363 pci_dma_sync_single(card->pcidev,
1364 IDT77252_PRV_PADDR(queue),
1365 queue->end - queue->data,
1366 PCI_DMA_FROMDEVICE);
1368 card->raw_cell_head = NULL;
1369 printk("%s: raw cell queue overrun\n",
1378 /*****************************************************************************/
1382 /*****************************************************************************/
1385 init_tsq(struct idt77252_dev *card)
1387 struct tsq_entry *tsqe;
1389 card->tsq.base = pci_alloc_consistent(card->pcidev, RSQSIZE,
1391 if (card->tsq.base == NULL) {
1392 printk("%s: can't allocate TSQ.\n", card->name);
1395 memset(card->tsq.base, 0, TSQSIZE);
1397 card->tsq.last = card->tsq.base + TSQ_NUM_ENTRIES - 1;
1398 card->tsq.next = card->tsq.last;
1399 for (tsqe = card->tsq.base; tsqe <= card->tsq.last; tsqe++)
1400 tsqe->word_2 = cpu_to_le32(SAR_TSQE_INVALID);
1402 writel(card->tsq.paddr, SAR_REG_TSQB);
1403 writel((unsigned long) card->tsq.next - (unsigned long) card->tsq.base,
1410 deinit_tsq(struct idt77252_dev *card)
1412 pci_free_consistent(card->pcidev, TSQSIZE,
1413 card->tsq.base, card->tsq.paddr);
1417 idt77252_tx(struct idt77252_dev *card)
1419 struct tsq_entry *tsqe;
1420 unsigned int vpi, vci;
1424 if (card->tsq.next == card->tsq.last)
1425 tsqe = card->tsq.base;
1427 tsqe = card->tsq.next + 1;
1429 TXPRINTK("idt77252_tx: tsq %p: base %p, next %p, last %p\n", tsqe,
1430 card->tsq.base, card->tsq.next, card->tsq.last);
1431 TXPRINTK("idt77252_tx: tsqb %08x, tsqt %08x, tsqh %08x, \n",
1432 readl(SAR_REG_TSQB),
1433 readl(SAR_REG_TSQT),
1434 readl(SAR_REG_TSQH));
1436 stat = le32_to_cpu(tsqe->word_2);
1438 if (stat & SAR_TSQE_INVALID)
1442 TXPRINTK("tsqe: 0x%p [0x%08x 0x%08x]\n", tsqe,
1443 le32_to_cpu(tsqe->word_1),
1444 le32_to_cpu(tsqe->word_2));
1446 switch (stat & SAR_TSQE_TYPE) {
1447 case SAR_TSQE_TYPE_TIMER:
1448 TXPRINTK("%s: Timer RollOver detected.\n", card->name);
1451 case SAR_TSQE_TYPE_IDLE:
1453 conn = le32_to_cpu(tsqe->word_1);
1455 if (SAR_TSQE_TAG(stat) == 0x10) {
1457 printk("%s: Connection %d halted.\n",
1459 le32_to_cpu(tsqe->word_1) & 0x1fff);
1464 vc = card->vcs[conn & 0x1fff];
1466 printk("%s: could not find VC from conn %d\n",
1467 card->name, conn & 0x1fff);
1471 printk("%s: Connection %d IDLE.\n",
1472 card->name, vc->index);
1474 set_bit(VCF_IDLE, &vc->flags);
1477 case SAR_TSQE_TYPE_TSR:
1479 conn = le32_to_cpu(tsqe->word_1);
1481 vc = card->vcs[conn & 0x1fff];
1483 printk("%s: no VC at index %d\n",
1485 le32_to_cpu(tsqe->word_1) & 0x1fff);
1489 drain_scq(card, vc);
1492 case SAR_TSQE_TYPE_TBD_COMP:
1494 conn = le32_to_cpu(tsqe->word_1);
1496 vpi = (conn >> SAR_TBD_VPI_SHIFT) & 0x00ff;
1497 vci = (conn >> SAR_TBD_VCI_SHIFT) & 0xffff;
1499 if (vpi >= (1 << card->vpibits) ||
1500 vci >= (1 << card->vcibits)) {
1501 printk("%s: TBD complete: "
1502 "out of range VPI.VCI %u.%u\n",
1503 card->name, vpi, vci);
1507 vc = card->vcs[VPCI2VC(card, vpi, vci)];
1509 printk("%s: TBD complete: "
1510 "no VC at VPI.VCI %u.%u\n",
1511 card->name, vpi, vci);
1515 drain_scq(card, vc);
1519 tsqe->word_2 = cpu_to_le32(SAR_TSQE_INVALID);
1521 card->tsq.next = tsqe;
1522 if (card->tsq.next == card->tsq.last)
1523 tsqe = card->tsq.base;
1525 tsqe = card->tsq.next + 1;
1527 TXPRINTK("tsqe: %p: base %p, next %p, last %p\n", tsqe,
1528 card->tsq.base, card->tsq.next, card->tsq.last);
1530 stat = le32_to_cpu(tsqe->word_2);
1532 } while (!(stat & SAR_TSQE_INVALID));
1534 writel((unsigned long)card->tsq.next - (unsigned long)card->tsq.base,
1537 XPRINTK("idt77252_tx-after writel%d: TSQ head = 0x%x, tail = 0x%x, next = 0x%p.\n",
1538 card->index, readl(SAR_REG_TSQH),
1539 readl(SAR_REG_TSQT), card->tsq.next);
1544 tst_timer(unsigned long data)
1546 struct idt77252_dev *card = (struct idt77252_dev *)data;
1547 unsigned long base, idle, jump;
1548 unsigned long flags;
1552 spin_lock_irqsave(&card->tst_lock, flags);
1554 base = card->tst[card->tst_index];
1555 idle = card->tst[card->tst_index ^ 1];
1557 if (test_bit(TST_SWITCH_WAIT, &card->tst_state)) {
1558 jump = base + card->tst_size - 2;
1560 pc = readl(SAR_REG_NOW) >> 2;
1561 if ((pc ^ idle) & ~(card->tst_size - 1)) {
1562 mod_timer(&card->tst_timer, jiffies + 1);
1566 clear_bit(TST_SWITCH_WAIT, &card->tst_state);
1568 card->tst_index ^= 1;
1569 write_sram(card, jump, TSTE_OPC_JMP | (base << 2));
1571 base = card->tst[card->tst_index];
1572 idle = card->tst[card->tst_index ^ 1];
1574 for (e = 0; e < card->tst_size - 2; e++) {
1575 if (card->soft_tst[e].tste & TSTE_PUSH_IDLE) {
1576 write_sram(card, idle + e,
1577 card->soft_tst[e].tste & TSTE_MASK);
1578 card->soft_tst[e].tste &= ~(TSTE_PUSH_IDLE);
1583 if (test_and_clear_bit(TST_SWITCH_PENDING, &card->tst_state)) {
1585 for (e = 0; e < card->tst_size - 2; e++) {
1586 if (card->soft_tst[e].tste & TSTE_PUSH_ACTIVE) {
1587 write_sram(card, idle + e,
1588 card->soft_tst[e].tste & TSTE_MASK);
1589 card->soft_tst[e].tste &= ~(TSTE_PUSH_ACTIVE);
1590 card->soft_tst[e].tste |= TSTE_PUSH_IDLE;
1594 jump = base + card->tst_size - 2;
1596 write_sram(card, jump, TSTE_OPC_NULL);
1597 set_bit(TST_SWITCH_WAIT, &card->tst_state);
1599 mod_timer(&card->tst_timer, jiffies + 1);
1603 spin_unlock_irqrestore(&card->tst_lock, flags);
1607 __fill_tst(struct idt77252_dev *card, struct vc_map *vc,
1608 int n, unsigned int opc)
1610 unsigned long cl, avail;
1615 avail = card->tst_size - 2;
1616 for (e = 0; e < avail; e++) {
1617 if (card->soft_tst[e].vc == NULL)
1621 printk("%s: No free TST entries found\n", card->name);
1625 NPRINTK("%s: conn %d: first TST entry at %d.\n",
1626 card->name, vc ? vc->index : -1, e);
1630 data = opc & TSTE_OPC_MASK;
1631 if (vc && (opc != TSTE_OPC_NULL))
1632 data = opc | vc->index;
1634 idle = card->tst[card->tst_index ^ 1];
1640 if ((cl >= avail) && (card->soft_tst[e].vc == NULL)) {
1642 card->soft_tst[e].vc = vc;
1644 card->soft_tst[e].vc = (void *)-1;
1646 card->soft_tst[e].tste = data;
1647 if (timer_pending(&card->tst_timer))
1648 card->soft_tst[e].tste |= TSTE_PUSH_ACTIVE;
1650 write_sram(card, idle + e, data);
1651 card->soft_tst[e].tste |= TSTE_PUSH_IDLE;
1654 cl -= card->tst_size;
1667 fill_tst(struct idt77252_dev *card, struct vc_map *vc, int n, unsigned int opc)
1669 unsigned long flags;
1672 spin_lock_irqsave(&card->tst_lock, flags);
1674 res = __fill_tst(card, vc, n, opc);
1676 set_bit(TST_SWITCH_PENDING, &card->tst_state);
1677 if (!timer_pending(&card->tst_timer))
1678 mod_timer(&card->tst_timer, jiffies + 1);
1680 spin_unlock_irqrestore(&card->tst_lock, flags);
1685 __clear_tst(struct idt77252_dev *card, struct vc_map *vc)
1690 idle = card->tst[card->tst_index ^ 1];
1692 for (e = 0; e < card->tst_size - 2; e++) {
1693 if (card->soft_tst[e].vc == vc) {
1694 card->soft_tst[e].vc = NULL;
1696 card->soft_tst[e].tste = TSTE_OPC_VAR;
1697 if (timer_pending(&card->tst_timer))
1698 card->soft_tst[e].tste |= TSTE_PUSH_ACTIVE;
1700 write_sram(card, idle + e, TSTE_OPC_VAR);
1701 card->soft_tst[e].tste |= TSTE_PUSH_IDLE;
1710 clear_tst(struct idt77252_dev *card, struct vc_map *vc)
1712 unsigned long flags;
1715 spin_lock_irqsave(&card->tst_lock, flags);
1717 res = __clear_tst(card, vc);
1719 set_bit(TST_SWITCH_PENDING, &card->tst_state);
1720 if (!timer_pending(&card->tst_timer))
1721 mod_timer(&card->tst_timer, jiffies + 1);
1723 spin_unlock_irqrestore(&card->tst_lock, flags);
1728 change_tst(struct idt77252_dev *card, struct vc_map *vc,
1729 int n, unsigned int opc)
1731 unsigned long flags;
1734 spin_lock_irqsave(&card->tst_lock, flags);
1736 __clear_tst(card, vc);
1737 res = __fill_tst(card, vc, n, opc);
1739 set_bit(TST_SWITCH_PENDING, &card->tst_state);
1740 if (!timer_pending(&card->tst_timer))
1741 mod_timer(&card->tst_timer, jiffies + 1);
1743 spin_unlock_irqrestore(&card->tst_lock, flags);
1749 set_tct(struct idt77252_dev *card, struct vc_map *vc)
1753 tct = (unsigned long) (card->tct_base + vc->index * SAR_SRAM_TCT_SIZE);
1755 switch (vc->class) {
1757 OPRINTK("%s: writing TCT at 0x%lx, SCD 0x%lx.\n",
1758 card->name, tct, vc->scq->scd);
1760 write_sram(card, tct + 0, TCT_CBR | vc->scq->scd);
1761 write_sram(card, tct + 1, 0);
1762 write_sram(card, tct + 2, 0);
1763 write_sram(card, tct + 3, 0);
1764 write_sram(card, tct + 4, 0);
1765 write_sram(card, tct + 5, 0);
1766 write_sram(card, tct + 6, 0);
1767 write_sram(card, tct + 7, 0);
1771 OPRINTK("%s: writing TCT at 0x%lx, SCD 0x%lx.\n",
1772 card->name, tct, vc->scq->scd);
1774 write_sram(card, tct + 0, TCT_UBR | vc->scq->scd);
1775 write_sram(card, tct + 1, 0);
1776 write_sram(card, tct + 2, TCT_TSIF);
1777 write_sram(card, tct + 3, TCT_HALT | TCT_IDLE);
1778 write_sram(card, tct + 4, 0);
1779 write_sram(card, tct + 5, vc->init_er);
1780 write_sram(card, tct + 6, 0);
1781 write_sram(card, tct + 7, TCT_FLAG_UBR);
1793 /*****************************************************************************/
1797 /*****************************************************************************/
1799 static __inline__ int
1800 idt77252_fbq_level(struct idt77252_dev *card, int queue)
1802 return (readl(SAR_REG_STAT) >> (16 + (queue << 2))) & 0x0f;
1805 static __inline__ int
1806 idt77252_fbq_full(struct idt77252_dev *card, int queue)
1808 return (readl(SAR_REG_STAT) >> (16 + (queue << 2))) == 0x0f;
1812 push_rx_skb(struct idt77252_dev *card, struct sk_buff *skb, int queue)
1814 unsigned long flags;
1818 skb->data = skb->tail = skb->head;
1821 skb_reserve(skb, 16);
1825 skb_put(skb, SAR_FB_SIZE_0);
1828 skb_put(skb, SAR_FB_SIZE_1);
1831 skb_put(skb, SAR_FB_SIZE_2);
1834 skb_put(skb, SAR_FB_SIZE_3);
1841 if (idt77252_fbq_full(card, queue))
1844 memset(&skb->data[(skb->len & ~(0x3f)) - 64], 0, 2 * sizeof(u32));
1846 handle = IDT77252_PRV_POOL(skb);
1847 addr = IDT77252_PRV_PADDR(skb);
1849 spin_lock_irqsave(&card->cmd_lock, flags);
1850 writel(handle, card->fbq[queue]);
1851 writel(addr, card->fbq[queue]);
1852 spin_unlock_irqrestore(&card->cmd_lock, flags);
1858 add_rx_skb(struct idt77252_dev *card, int queue,
1859 unsigned int size, unsigned int count)
1861 struct sk_buff *skb;
1866 skb = dev_alloc_skb(size);
1870 if (sb_pool_add(card, skb, queue)) {
1871 printk("%s: SB POOL full\n", __FUNCTION__);
1875 paddr = pci_map_single(card->pcidev, skb->data,
1876 skb->end - skb->data,
1877 PCI_DMA_FROMDEVICE);
1878 IDT77252_PRV_PADDR(skb) = paddr;
1880 if (push_rx_skb(card, skb, queue)) {
1881 printk("%s: FB QUEUE full\n", __FUNCTION__);
1889 pci_unmap_single(card->pcidev, IDT77252_PRV_PADDR(skb),
1890 skb->end - skb->data, PCI_DMA_FROMDEVICE);
1892 handle = IDT77252_PRV_POOL(skb);
1893 card->sbpool[POOL_QUEUE(handle)].skb[POOL_INDEX(handle)] = NULL;
1901 recycle_rx_skb(struct idt77252_dev *card, struct sk_buff *skb)
1903 u32 handle = IDT77252_PRV_POOL(skb);
1906 pci_dma_sync_single_for_device(card->pcidev, IDT77252_PRV_PADDR(skb),
1907 skb->end - skb->data, PCI_DMA_FROMDEVICE);
1909 err = push_rx_skb(card, skb, POOL_QUEUE(handle));
1911 pci_unmap_single(card->pcidev, IDT77252_PRV_PADDR(skb),
1912 skb->end - skb->data, PCI_DMA_FROMDEVICE);
1913 sb_pool_remove(card, skb);
1919 flush_rx_pool(struct idt77252_dev *card, struct rx_pool *rpp)
1924 rpp->last = &rpp->first;
1928 recycle_rx_pool_skb(struct idt77252_dev *card, struct rx_pool *rpp)
1930 struct sk_buff *skb, *next;
1934 for (i = 0; i < rpp->count; i++) {
1937 recycle_rx_skb(card, skb);
1940 flush_rx_pool(card, rpp);
1943 /*****************************************************************************/
1947 /*****************************************************************************/
1950 idt77252_phy_put(struct atm_dev *dev, unsigned char value, unsigned long addr)
1952 write_utility(dev->dev_data, 0x100 + (addr & 0x1ff), value);
1955 static unsigned char
1956 idt77252_phy_get(struct atm_dev *dev, unsigned long addr)
1958 return read_utility(dev->dev_data, 0x100 + (addr & 0x1ff));
1962 idt77252_send_skb(struct atm_vcc *vcc, struct sk_buff *skb, int oam)
1964 struct atm_dev *dev = vcc->dev;
1965 struct idt77252_dev *card = dev->dev_data;
1966 struct vc_map *vc = vcc->dev_data;
1970 printk("%s: NULL connection in send().\n", card->name);
1971 atomic_inc(&vcc->stats->tx_err);
1975 if (!test_bit(VCF_TX, &vc->flags)) {
1976 printk("%s: Trying to transmit on a non-tx VC.\n", card->name);
1977 atomic_inc(&vcc->stats->tx_err);
1982 switch (vcc->qos.aal) {
1988 printk("%s: Unsupported AAL: %d\n", card->name, vcc->qos.aal);
1989 atomic_inc(&vcc->stats->tx_err);
1994 if (skb_shinfo(skb)->nr_frags != 0) {
1995 printk("%s: No scatter-gather yet.\n", card->name);
1996 atomic_inc(&vcc->stats->tx_err);
2000 ATM_SKB(skb)->vcc = vcc;
2002 err = queue_skb(card, vc, skb, oam);
2004 atomic_inc(&vcc->stats->tx_err);
2013 idt77252_send(struct atm_vcc *vcc, struct sk_buff *skb)
2015 return idt77252_send_skb(vcc, skb, 0);
2019 idt77252_send_oam(struct atm_vcc *vcc, void *cell, int flags)
2021 struct atm_dev *dev = vcc->dev;
2022 struct idt77252_dev *card = dev->dev_data;
2023 struct sk_buff *skb;
2025 skb = dev_alloc_skb(64);
2027 printk("%s: Out of memory in send_oam().\n", card->name);
2028 atomic_inc(&vcc->stats->tx_err);
2031 atomic_add(skb->truesize, &vcc->sk->sk_wmem_alloc);
2033 memcpy(skb_put(skb, 52), cell, 52);
2035 return idt77252_send_skb(vcc, skb, 1);
2038 static __inline__ unsigned int
2039 idt77252_fls(unsigned int x)
2045 if (x & 0xffff0000) {
2067 idt77252_int_to_atmfp(unsigned int rate)
2073 e = idt77252_fls(rate) - 1;
2075 m = (rate - (1 << e)) << (9 - e);
2077 m = (rate - (1 << e));
2079 m = (rate - (1 << e)) >> (e - 9);
2080 return 0x4000 | (e << 9) | m;
2084 idt77252_rate_logindex(struct idt77252_dev *card, int pcr)
2088 afp = idt77252_int_to_atmfp(pcr < 0 ? -pcr : pcr);
2090 return rate_to_log[(afp >> 5) & 0x1ff];
2091 return rate_to_log[((afp >> 5) + 1) & 0x1ff];
2095 idt77252_est_timer(unsigned long data)
2097 struct vc_map *vc = (struct vc_map *)data;
2098 struct idt77252_dev *card = vc->card;
2099 struct rate_estimator *est;
2100 unsigned long flags;
2105 spin_lock_irqsave(&vc->lock, flags);
2106 est = vc->estimator;
2110 ncells = est->cells;
2112 rate = ((u32)(ncells - est->last_cells)) << (7 - est->interval);
2113 est->last_cells = ncells;
2114 est->avcps += ((long)rate - (long)est->avcps) >> est->ewma_log;
2115 est->cps = (est->avcps + 0x1f) >> 5;
2118 if (cps < (est->maxcps >> 4))
2119 cps = est->maxcps >> 4;
2121 lacr = idt77252_rate_logindex(card, cps);
2122 if (lacr > vc->max_er)
2125 if (lacr != vc->lacr) {
2127 writel(TCMDQ_LACR|(vc->lacr << 16)|vc->index, SAR_REG_TCMDQ);
2130 est->timer.expires = jiffies + ((HZ / 4) << est->interval);
2131 add_timer(&est->timer);
2134 spin_unlock_irqrestore(&vc->lock, flags);
2137 static struct rate_estimator *
2138 idt77252_init_est(struct vc_map *vc, int pcr)
2140 struct rate_estimator *est;
2142 est = kmalloc(sizeof(struct rate_estimator), GFP_KERNEL);
2145 memset(est, 0, sizeof(*est));
2147 est->maxcps = pcr < 0 ? -pcr : pcr;
2148 est->cps = est->maxcps;
2149 est->avcps = est->cps << 5;
2151 est->interval = 2; /* XXX: make this configurable */
2152 est->ewma_log = 2; /* XXX: make this configurable */
2153 init_timer(&est->timer);
2154 est->timer.data = (unsigned long)vc;
2155 est->timer.function = idt77252_est_timer;
2157 est->timer.expires = jiffies + ((HZ / 4) << est->interval);
2158 add_timer(&est->timer);
2164 idt77252_init_cbr(struct idt77252_dev *card, struct vc_map *vc,
2165 struct atm_vcc *vcc, struct atm_qos *qos)
2167 int tst_free, tst_used, tst_entries;
2168 unsigned long tmpl, modl;
2171 if ((qos->txtp.max_pcr == 0) &&
2172 (qos->txtp.pcr == 0) && (qos->txtp.min_pcr == 0)) {
2173 printk("%s: trying to open a CBR VC with cell rate = 0\n",
2179 tst_free = card->tst_free;
2180 if (test_bit(VCF_TX, &vc->flags))
2181 tst_used = vc->ntste;
2182 tst_free += tst_used;
2184 tcr = atm_pcr_goal(&qos->txtp);
2185 tcra = tcr >= 0 ? tcr : -tcr;
2187 TXPRINTK("%s: CBR target cell rate = %d\n", card->name, tcra);
2189 tmpl = (unsigned long) tcra * ((unsigned long) card->tst_size - 2);
2190 modl = tmpl % (unsigned long)card->utopia_pcr;
2192 tst_entries = (int) (tmpl / card->utopia_pcr);
2196 } else if (tcr == 0) {
2197 tst_entries = tst_free - SAR_TST_RESERVED;
2198 if (tst_entries <= 0) {
2199 printk("%s: no CBR bandwidth free.\n", card->name);
2204 if (tst_entries == 0) {
2205 printk("%s: selected CBR bandwidth < granularity.\n",
2210 if (tst_entries > (tst_free - SAR_TST_RESERVED)) {
2211 printk("%s: not enough CBR bandwidth free.\n", card->name);
2215 vc->ntste = tst_entries;
2217 card->tst_free = tst_free - tst_entries;
2218 if (test_bit(VCF_TX, &vc->flags)) {
2219 if (tst_used == tst_entries)
2222 OPRINTK("%s: modify %d -> %d entries in TST.\n",
2223 card->name, tst_used, tst_entries);
2224 change_tst(card, vc, tst_entries, TSTE_OPC_CBR);
2228 OPRINTK("%s: setting %d entries in TST.\n", card->name, tst_entries);
2229 fill_tst(card, vc, tst_entries, TSTE_OPC_CBR);
2234 idt77252_init_ubr(struct idt77252_dev *card, struct vc_map *vc,
2235 struct atm_vcc *vcc, struct atm_qos *qos)
2237 unsigned long flags;
2240 spin_lock_irqsave(&vc->lock, flags);
2241 if (vc->estimator) {
2242 del_timer(&vc->estimator->timer);
2243 kfree(vc->estimator);
2244 vc->estimator = NULL;
2246 spin_unlock_irqrestore(&vc->lock, flags);
2248 tcr = atm_pcr_goal(&qos->txtp);
2250 tcr = card->link_pcr;
2252 vc->estimator = idt77252_init_est(vc, tcr);
2254 vc->class = SCHED_UBR;
2255 vc->init_er = idt77252_rate_logindex(card, tcr);
2256 vc->lacr = vc->init_er;
2258 vc->max_er = vc->init_er;
2266 idt77252_init_tx(struct idt77252_dev *card, struct vc_map *vc,
2267 struct atm_vcc *vcc, struct atm_qos *qos)
2271 if (test_bit(VCF_TX, &vc->flags))
2274 switch (qos->txtp.traffic_class) {
2276 vc->class = SCHED_CBR;
2280 vc->class = SCHED_UBR;
2286 return -EPROTONOSUPPORT;
2289 vc->scq = alloc_scq(card, vc->class);
2291 printk("%s: can't get SCQ.\n", card->name);
2295 vc->scq->scd = get_free_scd(card, vc);
2296 if (vc->scq->scd == 0) {
2297 printk("%s: no SCD available.\n", card->name);
2298 free_scq(card, vc->scq);
2302 fill_scd(card, vc->scq, vc->class);
2304 if (set_tct(card, vc)) {
2305 printk("%s: class %d not supported.\n",
2306 card->name, qos->txtp.traffic_class);
2308 card->scd2vc[vc->scd_index] = NULL;
2309 free_scq(card, vc->scq);
2310 return -EPROTONOSUPPORT;
2313 switch (vc->class) {
2315 error = idt77252_init_cbr(card, vc, vcc, qos);
2317 card->scd2vc[vc->scd_index] = NULL;
2318 free_scq(card, vc->scq);
2322 clear_bit(VCF_IDLE, &vc->flags);
2323 writel(TCMDQ_START | vc->index, SAR_REG_TCMDQ);
2327 error = idt77252_init_ubr(card, vc, vcc, qos);
2329 card->scd2vc[vc->scd_index] = NULL;
2330 free_scq(card, vc->scq);
2334 set_bit(VCF_IDLE, &vc->flags);
2339 set_bit(VCF_TX, &vc->flags);
2344 idt77252_init_rx(struct idt77252_dev *card, struct vc_map *vc,
2345 struct atm_vcc *vcc, struct atm_qos *qos)
2347 unsigned long flags;
2351 if (test_bit(VCF_RX, &vc->flags))
2355 set_bit(VCF_RX, &vc->flags);
2357 if ((vcc->vci == 3) || (vcc->vci == 4))
2360 flush_rx_pool(card, &vc->rcv.rx_pool);
2362 rcte |= SAR_RCTE_CONNECTOPEN;
2363 rcte |= SAR_RCTE_RAWCELLINTEN;
2367 rcte |= SAR_RCTE_RCQ;
2370 rcte |= SAR_RCTE_OAM; /* Let SAR drop Video */
2373 rcte |= SAR_RCTE_AAL34;
2376 rcte |= SAR_RCTE_AAL5;
2379 rcte |= SAR_RCTE_RCQ;
2383 if (qos->aal != ATM_AAL5)
2384 rcte |= SAR_RCTE_FBP_1;
2385 else if (qos->rxtp.max_sdu > SAR_FB_SIZE_2)
2386 rcte |= SAR_RCTE_FBP_3;
2387 else if (qos->rxtp.max_sdu > SAR_FB_SIZE_1)
2388 rcte |= SAR_RCTE_FBP_2;
2389 else if (qos->rxtp.max_sdu > SAR_FB_SIZE_0)
2390 rcte |= SAR_RCTE_FBP_1;
2392 rcte |= SAR_RCTE_FBP_01;
2394 addr = card->rct_base + (vc->index << 2);
2396 OPRINTK("%s: writing RCT at 0x%lx\n", card->name, addr);
2397 write_sram(card, addr, rcte);
2399 spin_lock_irqsave(&card->cmd_lock, flags);
2400 writel(SAR_CMD_OPEN_CONNECTION | (addr << 2), SAR_REG_CMD);
2402 spin_unlock_irqrestore(&card->cmd_lock, flags);
2408 idt77252_open(struct atm_vcc *vcc)
2410 struct atm_dev *dev = vcc->dev;
2411 struct idt77252_dev *card = dev->dev_data;
2417 short vpi = vcc->vpi;
2419 if (vpi == ATM_VPI_UNSPEC || vci == ATM_VCI_UNSPEC)
2422 if (vpi >= (1 << card->vpibits)) {
2423 printk("%s: unsupported VPI: %d\n", card->name, vpi);
2427 if (vci >= (1 << card->vcibits)) {
2428 printk("%s: unsupported VCI: %d\n", card->name, vci);
2432 set_bit(ATM_VF_ADDR, &vcc->flags);
2436 OPRINTK("%s: opening vpi.vci: %d.%d\n", card->name, vpi, vci);
2438 switch (vcc->qos.aal) {
2444 printk("%s: Unsupported AAL: %d\n", card->name, vcc->qos.aal);
2446 return -EPROTONOSUPPORT;
2449 index = VPCI2VC(card, vpi, vci);
2450 if (!card->vcs[index]) {
2451 card->vcs[index] = kmalloc(sizeof(struct vc_map), GFP_KERNEL);
2452 if (!card->vcs[index]) {
2453 printk("%s: can't alloc vc in open()\n", card->name);
2457 memset(card->vcs[index], 0, sizeof(struct vc_map));
2459 card->vcs[index]->card = card;
2460 card->vcs[index]->index = index;
2462 spin_lock_init(&card->vcs[index]->lock);
2464 vc = card->vcs[index];
2468 IPRINTK("%s: idt77252_open: vc = %d (%d.%d) %s/%s (max RX SDU: %u)\n",
2469 card->name, vc->index, vcc->vpi, vcc->vci,
2470 vcc->qos.rxtp.traffic_class != ATM_NONE ? "rx" : "--",
2471 vcc->qos.txtp.traffic_class != ATM_NONE ? "tx" : "--",
2472 vcc->qos.rxtp.max_sdu);
2475 if (vcc->qos.txtp.traffic_class != ATM_NONE &&
2476 test_bit(VCF_TX, &vc->flags))
2478 if (vcc->qos.rxtp.traffic_class != ATM_NONE &&
2479 test_bit(VCF_RX, &vc->flags))
2483 printk("%s: %s vci already in use.\n", card->name,
2484 inuse == 1 ? "tx" : inuse == 2 ? "rx" : "tx and rx");
2489 if (vcc->qos.txtp.traffic_class != ATM_NONE) {
2490 error = idt77252_init_tx(card, vc, vcc, &vcc->qos);
2497 if (vcc->qos.rxtp.traffic_class != ATM_NONE) {
2498 error = idt77252_init_rx(card, vc, vcc, &vcc->qos);
2505 set_bit(ATM_VF_READY, &vcc->flags);
2512 idt77252_close(struct atm_vcc *vcc)
2514 struct atm_dev *dev = vcc->dev;
2515 struct idt77252_dev *card = dev->dev_data;
2516 struct vc_map *vc = vcc->dev_data;
2517 unsigned long flags;
2523 IPRINTK("%s: idt77252_close: vc = %d (%d.%d)\n",
2524 card->name, vc->index, vcc->vpi, vcc->vci);
2526 clear_bit(ATM_VF_READY, &vcc->flags);
2528 if (vcc->qos.rxtp.traffic_class != ATM_NONE) {
2530 spin_lock_irqsave(&vc->lock, flags);
2531 clear_bit(VCF_RX, &vc->flags);
2533 spin_unlock_irqrestore(&vc->lock, flags);
2535 if ((vcc->vci == 3) || (vcc->vci == 4))
2538 addr = card->rct_base + vc->index * SAR_SRAM_RCT_SIZE;
2540 spin_lock_irqsave(&card->cmd_lock, flags);
2541 writel(SAR_CMD_CLOSE_CONNECTION | (addr << 2), SAR_REG_CMD);
2543 spin_unlock_irqrestore(&card->cmd_lock, flags);
2545 if (vc->rcv.rx_pool.count) {
2546 DPRINTK("%s: closing a VC with pending rx buffers.\n",
2549 recycle_rx_pool_skb(card, &vc->rcv.rx_pool);
2554 if (vcc->qos.txtp.traffic_class != ATM_NONE) {
2556 spin_lock_irqsave(&vc->lock, flags);
2557 clear_bit(VCF_TX, &vc->flags);
2558 clear_bit(VCF_IDLE, &vc->flags);
2559 clear_bit(VCF_RSV, &vc->flags);
2562 if (vc->estimator) {
2563 del_timer(&vc->estimator->timer);
2564 kfree(vc->estimator);
2565 vc->estimator = NULL;
2567 spin_unlock_irqrestore(&vc->lock, flags);
2570 while (atomic_read(&vc->scq->used) > 0) {
2571 timeout = schedule_timeout(timeout);
2576 printk("%s: SCQ drain timeout: %u used\n",
2577 card->name, atomic_read(&vc->scq->used));
2579 writel(TCMDQ_HALT | vc->index, SAR_REG_TCMDQ);
2580 clear_scd(card, vc->scq, vc->class);
2582 if (vc->class == SCHED_CBR) {
2583 clear_tst(card, vc);
2584 card->tst_free += vc->ntste;
2588 card->scd2vc[vc->scd_index] = NULL;
2589 free_scq(card, vc->scq);
2596 idt77252_change_qos(struct atm_vcc *vcc, struct atm_qos *qos, int flags)
2598 struct atm_dev *dev = vcc->dev;
2599 struct idt77252_dev *card = dev->dev_data;
2600 struct vc_map *vc = vcc->dev_data;
2605 if (qos->txtp.traffic_class != ATM_NONE) {
2606 if (!test_bit(VCF_TX, &vc->flags)) {
2607 error = idt77252_init_tx(card, vc, vcc, qos);
2611 switch (qos->txtp.traffic_class) {
2613 error = idt77252_init_cbr(card, vc, vcc, qos);
2619 error = idt77252_init_ubr(card, vc, vcc, qos);
2623 if (!test_bit(VCF_IDLE, &vc->flags)) {
2624 writel(TCMDQ_LACR | (vc->lacr << 16) |
2625 vc->index, SAR_REG_TCMDQ);
2631 error = -EOPNOTSUPP;
2637 if ((qos->rxtp.traffic_class != ATM_NONE) &&
2638 !test_bit(VCF_RX, &vc->flags)) {
2639 error = idt77252_init_rx(card, vc, vcc, qos);
2644 memcpy(&vcc->qos, qos, sizeof(struct atm_qos));
2646 set_bit(ATM_VF_HASQOS, &vcc->flags);
2654 idt77252_proc_read(struct atm_dev *dev, loff_t * pos, char *page)
2656 struct idt77252_dev *card = dev->dev_data;
2661 return sprintf(page, "IDT77252 Interrupts:\n");
2663 return sprintf(page, "TSIF: %lu\n", card->irqstat[15]);
2665 return sprintf(page, "TXICP: %lu\n", card->irqstat[14]);
2667 return sprintf(page, "TSQF: %lu\n", card->irqstat[12]);
2669 return sprintf(page, "TMROF: %lu\n", card->irqstat[11]);
2671 return sprintf(page, "PHYI: %lu\n", card->irqstat[10]);
2673 return sprintf(page, "FBQ3A: %lu\n", card->irqstat[8]);
2675 return sprintf(page, "FBQ2A: %lu\n", card->irqstat[7]);
2677 return sprintf(page, "RSQF: %lu\n", card->irqstat[6]);
2679 return sprintf(page, "EPDU: %lu\n", card->irqstat[5]);
2681 return sprintf(page, "RAWCF: %lu\n", card->irqstat[4]);
2683 return sprintf(page, "FBQ1A: %lu\n", card->irqstat[3]);
2685 return sprintf(page, "FBQ0A: %lu\n", card->irqstat[2]);
2687 return sprintf(page, "RSQAF: %lu\n", card->irqstat[1]);
2689 return sprintf(page, "IDT77252 Transmit Connection Table:\n");
2691 for (i = 0; i < card->tct_size; i++) {
2693 struct atm_vcc *vcc;
2710 p += sprintf(p, " %4u: %u.%u: ", i, vcc->vpi, vcc->vci);
2711 tct = (unsigned long) (card->tct_base + i * SAR_SRAM_TCT_SIZE);
2713 for (i = 0; i < 8; i++)
2714 p += sprintf(p, " %08x", read_sram(card, tct + i));
2715 p += sprintf(p, "\n");
2721 /*****************************************************************************/
2723 /* Interrupt handler */
2725 /*****************************************************************************/
2728 idt77252_collect_stat(struct idt77252_dev *card)
2732 cdc = readl(SAR_REG_CDC);
2733 vpec = readl(SAR_REG_VPEC);
2734 icc = readl(SAR_REG_ICC);
2737 printk("%s:", card->name);
2739 if (cdc & 0x7f0000) {
2743 if (cdc & (1 << 22)) {
2744 printk("%sRM ID", s);
2747 if (cdc & (1 << 21)) {
2748 printk("%sCON TAB", s);
2751 if (cdc & (1 << 20)) {
2752 printk("%sNO FB", s);
2755 if (cdc & (1 << 19)) {
2756 printk("%sOAM CRC", s);
2759 if (cdc & (1 << 18)) {
2760 printk("%sRM CRC", s);
2763 if (cdc & (1 << 17)) {
2764 printk("%sRM FIFO", s);
2767 if (cdc & (1 << 16)) {
2768 printk("%sRX FIFO", s);
2774 printk(" CDC %04x, VPEC %04x, ICC: %04x\n",
2775 cdc & 0xffff, vpec & 0xffff, icc & 0xffff);
2780 idt77252_interrupt(int irq, void *dev_id, struct pt_regs *ptregs)
2782 struct idt77252_dev *card = dev_id;
2785 stat = readl(SAR_REG_STAT) & 0xffff;
2786 if (!stat) /* no interrupt for us */
2789 if (test_and_set_bit(IDT77252_BIT_INTERRUPT, &card->flags)) {
2790 printk("%s: Re-entering irq_handler()\n", card->name);
2794 writel(stat, SAR_REG_STAT); /* reset interrupt */
2796 if (stat & SAR_STAT_TSIF) { /* entry written to TSQ */
2797 INTPRINTK("%s: TSIF\n", card->name);
2798 card->irqstat[15]++;
2801 if (stat & SAR_STAT_TXICP) { /* Incomplete CS-PDU has */
2802 INTPRINTK("%s: TXICP\n", card->name);
2803 card->irqstat[14]++;
2804 #ifdef CONFIG_ATM_IDT77252_DEBUG
2805 idt77252_tx_dump(card);
2808 if (stat & SAR_STAT_TSQF) { /* TSQ 7/8 full */
2809 INTPRINTK("%s: TSQF\n", card->name);
2810 card->irqstat[12]++;
2813 if (stat & SAR_STAT_TMROF) { /* Timer overflow */
2814 INTPRINTK("%s: TMROF\n", card->name);
2815 card->irqstat[11]++;
2816 idt77252_collect_stat(card);
2819 if (stat & SAR_STAT_EPDU) { /* Got complete CS-PDU */
2820 INTPRINTK("%s: EPDU\n", card->name);
2824 if (stat & SAR_STAT_RSQAF) { /* RSQ is 7/8 full */
2825 INTPRINTK("%s: RSQAF\n", card->name);
2829 if (stat & SAR_STAT_RSQF) { /* RSQ is full */
2830 INTPRINTK("%s: RSQF\n", card->name);
2834 if (stat & SAR_STAT_RAWCF) { /* Raw cell received */
2835 INTPRINTK("%s: RAWCF\n", card->name);
2837 idt77252_rx_raw(card);
2840 if (stat & SAR_STAT_PHYI) { /* PHY device interrupt */
2841 INTPRINTK("%s: PHYI", card->name);
2842 card->irqstat[10]++;
2843 if (card->atmdev->phy && card->atmdev->phy->interrupt)
2844 card->atmdev->phy->interrupt(card->atmdev);
2847 if (stat & (SAR_STAT_FBQ0A | SAR_STAT_FBQ1A |
2848 SAR_STAT_FBQ2A | SAR_STAT_FBQ3A)) {
2850 writel(readl(SAR_REG_CFG) & ~(SAR_CFG_FBIE), SAR_REG_CFG);
2852 INTPRINTK("%s: FBQA: %04x\n", card->name, stat);
2854 if (stat & SAR_STAT_FBQ0A)
2856 if (stat & SAR_STAT_FBQ1A)
2858 if (stat & SAR_STAT_FBQ2A)
2860 if (stat & SAR_STAT_FBQ3A)
2863 schedule_work(&card->tqueue);
2867 clear_bit(IDT77252_BIT_INTERRUPT, &card->flags);
2872 idt77252_softint(void *dev_id)
2874 struct idt77252_dev *card = dev_id;
2878 for (done = 1; ; done = 1) {
2879 stat = readl(SAR_REG_STAT) >> 16;
2881 if ((stat & 0x0f) < SAR_FBQ0_HIGH) {
2882 add_rx_skb(card, 0, SAR_FB_SIZE_0, 32);
2887 if ((stat & 0x0f) < SAR_FBQ1_HIGH) {
2888 add_rx_skb(card, 1, SAR_FB_SIZE_1, 32);
2893 if ((stat & 0x0f) < SAR_FBQ2_HIGH) {
2894 add_rx_skb(card, 2, SAR_FB_SIZE_2, 32);
2899 if ((stat & 0x0f) < SAR_FBQ3_HIGH) {
2900 add_rx_skb(card, 3, SAR_FB_SIZE_3, 32);
2908 writel(readl(SAR_REG_CFG) | SAR_CFG_FBIE, SAR_REG_CFG);
2913 open_card_oam(struct idt77252_dev *card)
2915 unsigned long flags;
2922 for (vpi = 0; vpi < (1 << card->vpibits); vpi++) {
2923 for (vci = 3; vci < 5; vci++) {
2924 index = VPCI2VC(card, vpi, vci);
2926 vc = kmalloc(sizeof(struct vc_map), GFP_KERNEL);
2928 printk("%s: can't alloc vc\n", card->name);
2931 memset(vc, 0, sizeof(struct vc_map));
2934 card->vcs[index] = vc;
2936 flush_rx_pool(card, &vc->rcv.rx_pool);
2938 rcte = SAR_RCTE_CONNECTOPEN |
2939 SAR_RCTE_RAWCELLINTEN |
2943 addr = card->rct_base + (vc->index << 2);
2944 write_sram(card, addr, rcte);
2946 spin_lock_irqsave(&card->cmd_lock, flags);
2947 writel(SAR_CMD_OPEN_CONNECTION | (addr << 2),
2950 spin_unlock_irqrestore(&card->cmd_lock, flags);
2958 close_card_oam(struct idt77252_dev *card)
2960 unsigned long flags;
2966 for (vpi = 0; vpi < (1 << card->vpibits); vpi++) {
2967 for (vci = 3; vci < 5; vci++) {
2968 index = VPCI2VC(card, vpi, vci);
2969 vc = card->vcs[index];
2971 addr = card->rct_base + vc->index * SAR_SRAM_RCT_SIZE;
2973 spin_lock_irqsave(&card->cmd_lock, flags);
2974 writel(SAR_CMD_CLOSE_CONNECTION | (addr << 2),
2977 spin_unlock_irqrestore(&card->cmd_lock, flags);
2979 if (vc->rcv.rx_pool.count) {
2980 DPRINTK("%s: closing a VC "
2981 "with pending rx buffers.\n",
2984 recycle_rx_pool_skb(card, &vc->rcv.rx_pool);
2991 open_card_ubr0(struct idt77252_dev *card)
2995 vc = kmalloc(sizeof(struct vc_map), GFP_KERNEL);
2997 printk("%s: can't alloc vc\n", card->name);
3000 memset(vc, 0, sizeof(struct vc_map));
3002 vc->class = SCHED_UBR0;
3004 vc->scq = alloc_scq(card, vc->class);
3006 printk("%s: can't get SCQ.\n", card->name);
3010 card->scd2vc[0] = vc;
3012 vc->scq->scd = card->scd_base;
3014 fill_scd(card, vc->scq, vc->class);
3016 write_sram(card, card->tct_base + 0, TCT_UBR | card->scd_base);
3017 write_sram(card, card->tct_base + 1, 0);
3018 write_sram(card, card->tct_base + 2, 0);
3019 write_sram(card, card->tct_base + 3, 0);
3020 write_sram(card, card->tct_base + 4, 0);
3021 write_sram(card, card->tct_base + 5, 0);
3022 write_sram(card, card->tct_base + 6, 0);
3023 write_sram(card, card->tct_base + 7, TCT_FLAG_UBR);
3025 clear_bit(VCF_IDLE, &vc->flags);
3026 writel(TCMDQ_START | 0, SAR_REG_TCMDQ);
3031 idt77252_dev_open(struct idt77252_dev *card)
3035 if (!test_bit(IDT77252_BIT_INIT, &card->flags)) {
3036 printk("%s: SAR not yet initialized.\n", card->name);
3040 conf = SAR_CFG_RXPTH| /* enable receive path */
3041 SAR_RX_DELAY | /* interrupt on complete PDU */
3042 SAR_CFG_RAWIE | /* interrupt enable on raw cells */
3043 SAR_CFG_RQFIE | /* interrupt on RSQ almost full */
3044 SAR_CFG_TMOIE | /* interrupt on timer overflow */
3045 SAR_CFG_FBIE | /* interrupt on low free buffers */
3046 SAR_CFG_TXEN | /* transmit operation enable */
3047 SAR_CFG_TXINT | /* interrupt on transmit status */
3048 SAR_CFG_TXUIE | /* interrupt on transmit underrun */
3049 SAR_CFG_TXSFI | /* interrupt on TSQ almost full */
3050 SAR_CFG_PHYIE /* enable PHY interrupts */
3053 #ifdef CONFIG_ATM_IDT77252_RCV_ALL
3054 /* Test RAW cell receive. */
3055 conf |= SAR_CFG_VPECA;
3058 writel(readl(SAR_REG_CFG) | conf, SAR_REG_CFG);
3060 if (open_card_oam(card)) {
3061 printk("%s: Error initializing OAM.\n", card->name);
3065 if (open_card_ubr0(card)) {
3066 printk("%s: Error initializing UBR0.\n", card->name);
3070 IPRINTK("%s: opened IDT77252 ABR SAR.\n", card->name);
3075 idt77252_dev_close(struct atm_dev *dev)
3077 struct idt77252_dev *card = dev->dev_data;
3080 close_card_oam(card);
3082 conf = SAR_CFG_RXPTH | /* enable receive path */
3083 SAR_RX_DELAY | /* interrupt on complete PDU */
3084 SAR_CFG_RAWIE | /* interrupt enable on raw cells */
3085 SAR_CFG_RQFIE | /* interrupt on RSQ almost full */
3086 SAR_CFG_TMOIE | /* interrupt on timer overflow */
3087 SAR_CFG_FBIE | /* interrupt on low free buffers */
3088 SAR_CFG_TXEN | /* transmit operation enable */
3089 SAR_CFG_TXINT | /* interrupt on transmit status */
3090 SAR_CFG_TXUIE | /* interrupt on xmit underrun */
3091 SAR_CFG_TXSFI /* interrupt on TSQ almost full */
3094 writel(readl(SAR_REG_CFG) & ~(conf), SAR_REG_CFG);
3096 DIPRINTK("%s: closed IDT77252 ABR SAR.\n", card->name);
3100 /*****************************************************************************/
3102 /* Initialisation and Deinitialization of IDT77252 */
3104 /*****************************************************************************/
3108 deinit_card(struct idt77252_dev *card)
3110 struct sk_buff *skb;
3113 if (!test_bit(IDT77252_BIT_INIT, &card->flags)) {
3114 printk("%s: SAR not yet initialized.\n", card->name);
3117 DIPRINTK("idt77252: deinitialize card %u\n", card->index);
3119 writel(0, SAR_REG_CFG);
3122 atm_dev_deregister(card->atmdev);
3124 for (i = 0; i < 4; i++) {
3125 for (j = 0; j < FBQ_SIZE; j++) {
3126 skb = card->sbpool[i].skb[j];
3128 pci_unmap_single(card->pcidev,
3129 IDT77252_PRV_PADDR(skb),
3130 skb->end - skb->data,
3131 PCI_DMA_FROMDEVICE);
3132 card->sbpool[i].skb[j] = NULL;
3139 vfree(card->soft_tst);
3142 vfree(card->scd2vc);
3147 if (card->raw_cell_hnd) {
3148 pci_free_consistent(card->pcidev, 2 * sizeof(u32),
3149 card->raw_cell_hnd, card->raw_cell_paddr);
3152 if (card->rsq.base) {
3153 DIPRINTK("%s: Release RSQ ...\n", card->name);
3157 if (card->tsq.base) {
3158 DIPRINTK("%s: Release TSQ ...\n", card->name);
3162 DIPRINTK("idt77252: Release IRQ.\n");
3163 free_irq(card->pcidev->irq, card);
3165 for (i = 0; i < 4; i++) {
3167 iounmap((void *) card->fbq[i]);
3171 iounmap((void *) card->membase);
3173 clear_bit(IDT77252_BIT_INIT, &card->flags);
3174 DIPRINTK("%s: Card deinitialized.\n", card->name);
3178 static int __devinit
3179 init_sram(struct idt77252_dev *card)
3183 for (i = 0; i < card->sramsize; i += 4)
3184 write_sram(card, (i >> 2), 0);
3186 /* set SRAM layout for THIS card */
3187 if (card->sramsize == (512 * 1024)) {
3188 card->tct_base = SAR_SRAM_TCT_128_BASE;
3189 card->tct_size = (SAR_SRAM_TCT_128_TOP - card->tct_base + 1)
3190 / SAR_SRAM_TCT_SIZE;
3191 card->rct_base = SAR_SRAM_RCT_128_BASE;
3192 card->rct_size = (SAR_SRAM_RCT_128_TOP - card->rct_base + 1)
3193 / SAR_SRAM_RCT_SIZE;
3194 card->rt_base = SAR_SRAM_RT_128_BASE;
3195 card->scd_base = SAR_SRAM_SCD_128_BASE;
3196 card->scd_size = (SAR_SRAM_SCD_128_TOP - card->scd_base + 1)
3197 / SAR_SRAM_SCD_SIZE;
3198 card->tst[0] = SAR_SRAM_TST1_128_BASE;
3199 card->tst[1] = SAR_SRAM_TST2_128_BASE;
3200 card->tst_size = SAR_SRAM_TST1_128_TOP - card->tst[0] + 1;
3201 card->abrst_base = SAR_SRAM_ABRSTD_128_BASE;
3202 card->abrst_size = SAR_ABRSTD_SIZE_8K;
3203 card->fifo_base = SAR_SRAM_FIFO_128_BASE;
3204 card->fifo_size = SAR_RXFD_SIZE_32K;
3206 card->tct_base = SAR_SRAM_TCT_32_BASE;
3207 card->tct_size = (SAR_SRAM_TCT_32_TOP - card->tct_base + 1)
3208 / SAR_SRAM_TCT_SIZE;
3209 card->rct_base = SAR_SRAM_RCT_32_BASE;
3210 card->rct_size = (SAR_SRAM_RCT_32_TOP - card->rct_base + 1)
3211 / SAR_SRAM_RCT_SIZE;
3212 card->rt_base = SAR_SRAM_RT_32_BASE;
3213 card->scd_base = SAR_SRAM_SCD_32_BASE;
3214 card->scd_size = (SAR_SRAM_SCD_32_TOP - card->scd_base + 1)
3215 / SAR_SRAM_SCD_SIZE;
3216 card->tst[0] = SAR_SRAM_TST1_32_BASE;
3217 card->tst[1] = SAR_SRAM_TST2_32_BASE;
3218 card->tst_size = (SAR_SRAM_TST1_32_TOP - card->tst[0] + 1);
3219 card->abrst_base = SAR_SRAM_ABRSTD_32_BASE;
3220 card->abrst_size = SAR_ABRSTD_SIZE_1K;
3221 card->fifo_base = SAR_SRAM_FIFO_32_BASE;
3222 card->fifo_size = SAR_RXFD_SIZE_4K;
3225 /* Initialize TCT */
3226 for (i = 0; i < card->tct_size; i++) {
3227 write_sram(card, i * SAR_SRAM_TCT_SIZE + 0, 0);
3228 write_sram(card, i * SAR_SRAM_TCT_SIZE + 1, 0);
3229 write_sram(card, i * SAR_SRAM_TCT_SIZE + 2, 0);
3230 write_sram(card, i * SAR_SRAM_TCT_SIZE + 3, 0);
3231 write_sram(card, i * SAR_SRAM_TCT_SIZE + 4, 0);
3232 write_sram(card, i * SAR_SRAM_TCT_SIZE + 5, 0);
3233 write_sram(card, i * SAR_SRAM_TCT_SIZE + 6, 0);
3234 write_sram(card, i * SAR_SRAM_TCT_SIZE + 7, 0);
3237 /* Initialize RCT */
3238 for (i = 0; i < card->rct_size; i++) {
3239 write_sram(card, card->rct_base + i * SAR_SRAM_RCT_SIZE,
3240 (u32) SAR_RCTE_RAWCELLINTEN);
3241 write_sram(card, card->rct_base + i * SAR_SRAM_RCT_SIZE + 1,
3243 write_sram(card, card->rct_base + i * SAR_SRAM_RCT_SIZE + 2,
3245 write_sram(card, card->rct_base + i * SAR_SRAM_RCT_SIZE + 3,
3249 writel((SAR_FBQ0_LOW << 28) | 0x00000000 | 0x00000000 |
3250 (SAR_FB_SIZE_0 / 48), SAR_REG_FBQS0);
3251 writel((SAR_FBQ1_LOW << 28) | 0x00000000 | 0x00000000 |
3252 (SAR_FB_SIZE_1 / 48), SAR_REG_FBQS1);
3253 writel((SAR_FBQ2_LOW << 28) | 0x00000000 | 0x00000000 |
3254 (SAR_FB_SIZE_2 / 48), SAR_REG_FBQS2);
3255 writel((SAR_FBQ3_LOW << 28) | 0x00000000 | 0x00000000 |
3256 (SAR_FB_SIZE_3 / 48), SAR_REG_FBQS3);
3258 /* Initialize rate table */
3259 for (i = 0; i < 256; i++) {
3260 write_sram(card, card->rt_base + i, log_to_rate[i]);
3263 for (i = 0; i < 128; i++) {
3266 tmp = rate_to_log[(i << 2) + 0] << 0;
3267 tmp |= rate_to_log[(i << 2) + 1] << 8;
3268 tmp |= rate_to_log[(i << 2) + 2] << 16;
3269 tmp |= rate_to_log[(i << 2) + 3] << 24;
3270 write_sram(card, card->rt_base + 256 + i, tmp);
3273 #if 0 /* Fill RDF and AIR tables. */
3274 for (i = 0; i < 128; i++) {
3277 tmp = RDF[0][(i << 1) + 0] << 16;
3278 tmp |= RDF[0][(i << 1) + 1] << 0;
3279 write_sram(card, card->rt_base + 512 + i, tmp);
3282 for (i = 0; i < 128; i++) {
3285 tmp = AIR[0][(i << 1) + 0] << 16;
3286 tmp |= AIR[0][(i << 1) + 1] << 0;
3287 write_sram(card, card->rt_base + 640 + i, tmp);
3291 IPRINTK("%s: initialize rate table ...\n", card->name);
3292 writel(card->rt_base << 2, SAR_REG_RTBL);
3294 /* Initialize TSTs */
3295 IPRINTK("%s: initialize TST ...\n", card->name);
3296 card->tst_free = card->tst_size - 2; /* last two are jumps */
3298 for (i = card->tst[0]; i < card->tst[0] + card->tst_size - 2; i++)
3299 write_sram(card, i, TSTE_OPC_VAR);
3300 write_sram(card, i++, TSTE_OPC_JMP | (card->tst[0] << 2));
3301 idt77252_sram_write_errors = 1;
3302 write_sram(card, i++, TSTE_OPC_JMP | (card->tst[1] << 2));
3303 idt77252_sram_write_errors = 0;
3304 for (i = card->tst[1]; i < card->tst[1] + card->tst_size - 2; i++)
3305 write_sram(card, i, TSTE_OPC_VAR);
3306 write_sram(card, i++, TSTE_OPC_JMP | (card->tst[1] << 2));
3307 idt77252_sram_write_errors = 1;
3308 write_sram(card, i++, TSTE_OPC_JMP | (card->tst[0] << 2));
3309 idt77252_sram_write_errors = 0;
3311 card->tst_index = 0;
3312 writel(card->tst[0] << 2, SAR_REG_TSTB);
3314 /* Initialize ABRSTD and Receive FIFO */
3315 IPRINTK("%s: initialize ABRSTD ...\n", card->name);
3316 writel(card->abrst_size | (card->abrst_base << 2),
3319 IPRINTK("%s: initialize receive fifo ...\n", card->name);
3320 writel(card->fifo_size | (card->fifo_base << 2),
3323 IPRINTK("%s: SRAM initialization complete.\n", card->name);
3327 static int __devinit
3328 init_card(struct atm_dev *dev)
3330 struct idt77252_dev *card = dev->dev_data;
3331 struct pci_dev *pcidev = card->pcidev;
3332 unsigned long tmpl, modl;
3333 unsigned int linkrate, rsvdcr;
3334 unsigned int tst_entries;
3335 struct net_device *tmp;
3343 if (test_bit(IDT77252_BIT_INIT, &card->flags)) {
3344 printk("Error: SAR already initialized.\n");
3348 /*****************************************************************/
3349 /* P C I C O N F I G U R A T I O N */
3350 /*****************************************************************/
3352 /* Set PCI Retry-Timeout and TRDY timeout */
3353 IPRINTK("%s: Checking PCI retries.\n", card->name);
3354 if (pci_read_config_byte(pcidev, 0x40, &pci_byte) != 0) {
3355 printk("%s: can't read PCI retry timeout.\n", card->name);
3359 if (pci_byte != 0) {
3360 IPRINTK("%s: PCI retry timeout: %d, set to 0.\n",
3361 card->name, pci_byte);
3362 if (pci_write_config_byte(pcidev, 0x40, 0) != 0) {
3363 printk("%s: can't set PCI retry timeout.\n",
3369 IPRINTK("%s: Checking PCI TRDY.\n", card->name);
3370 if (pci_read_config_byte(pcidev, 0x41, &pci_byte) != 0) {
3371 printk("%s: can't read PCI TRDY timeout.\n", card->name);
3375 if (pci_byte != 0) {
3376 IPRINTK("%s: PCI TRDY timeout: %d, set to 0.\n",
3377 card->name, pci_byte);
3378 if (pci_write_config_byte(pcidev, 0x41, 0) != 0) {
3379 printk("%s: can't set PCI TRDY timeout.\n", card->name);
3384 /* Reset Timer register */
3385 if (readl(SAR_REG_STAT) & SAR_STAT_TMROF) {
3386 printk("%s: resetting timer overflow.\n", card->name);
3387 writel(SAR_STAT_TMROF, SAR_REG_STAT);
3389 IPRINTK("%s: Request IRQ ... ", card->name);
3390 if (request_irq(pcidev->irq, idt77252_interrupt, SA_INTERRUPT|SA_SHIRQ,
3391 card->name, card) != 0) {
3392 printk("%s: can't allocate IRQ.\n", card->name);
3396 IPRINTK("got %d.\n", pcidev->irq);
3398 /*****************************************************************/
3399 /* C H E C K A N D I N I T S R A M */
3400 /*****************************************************************/
3402 IPRINTK("%s: Initializing SRAM\n", card->name);
3404 /* preset size of connecton table, so that init_sram() knows about it */
3405 conf = SAR_CFG_TX_FIFO_SIZE_9 | /* Use maximum fifo size */
3406 SAR_CFG_RXSTQ_SIZE_8k | /* Receive Status Queue is 8k */
3407 SAR_CFG_IDLE_CLP | /* Set CLP on idle cells */
3408 #ifndef CONFIG_ATM_IDT77252_SEND_IDLE
3409 SAR_CFG_NO_IDLE | /* Do not send idle cells */
3413 if (card->sramsize == (512 * 1024))
3414 conf |= SAR_CFG_CNTBL_1k;
3416 conf |= SAR_CFG_CNTBL_512;
3420 conf |= SAR_CFG_VPVCS_0;
3424 conf |= SAR_CFG_VPVCS_1;
3427 conf |= SAR_CFG_VPVCS_2;
3430 conf |= SAR_CFG_VPVCS_8;
3434 writel(readl(SAR_REG_CFG) | conf, SAR_REG_CFG);
3436 if (init_sram(card) < 0)
3439 /********************************************************************/
3440 /* A L L O C R A M A N D S E T V A R I O U S T H I N G S */
3441 /********************************************************************/
3442 /* Initialize TSQ */
3443 if (0 != init_tsq(card)) {
3447 /* Initialize RSQ */
3448 if (0 != init_rsq(card)) {
3453 card->vpibits = vpibits;
3454 if (card->sramsize == (512 * 1024)) {
3455 card->vcibits = 10 - card->vpibits;
3457 card->vcibits = 9 - card->vpibits;
3461 for (k = 0, i = 1; k < card->vcibits; k++) {
3466 IPRINTK("%s: Setting VPI/VCI mask to zero.\n", card->name);
3467 writel(0, SAR_REG_VPM);
3469 /* Little Endian Order */
3470 writel(0, SAR_REG_GP);
3472 /* Initialize RAW Cell Handle Register */
3473 card->raw_cell_hnd = pci_alloc_consistent(card->pcidev, 2 * sizeof(u32),
3474 &card->raw_cell_paddr);
3475 if (!card->raw_cell_hnd) {
3476 printk("%s: memory allocation failure.\n", card->name);
3480 memset(card->raw_cell_hnd, 0, 2 * sizeof(u32));
3481 writel(card->raw_cell_paddr, SAR_REG_RAWHND);
3482 IPRINTK("%s: raw cell handle is at 0x%p.\n", card->name,
3483 card->raw_cell_hnd);
3485 size = sizeof(struct vc_map *) * card->tct_size;
3486 IPRINTK("%s: allocate %d byte for VC map.\n", card->name, size);
3487 if (NULL == (card->vcs = vmalloc(size))) {
3488 printk("%s: memory allocation failure.\n", card->name);
3492 memset(card->vcs, 0, size);
3494 size = sizeof(struct vc_map *) * card->scd_size;
3495 IPRINTK("%s: allocate %d byte for SCD to VC mapping.\n",
3497 if (NULL == (card->scd2vc = vmalloc(size))) {
3498 printk("%s: memory allocation failure.\n", card->name);
3502 memset(card->scd2vc, 0, size);
3504 size = sizeof(struct tst_info) * (card->tst_size - 2);
3505 IPRINTK("%s: allocate %d byte for TST to VC mapping.\n",
3507 if (NULL == (card->soft_tst = vmalloc(size))) {
3508 printk("%s: memory allocation failure.\n", card->name);
3512 for (i = 0; i < card->tst_size - 2; i++) {
3513 card->soft_tst[i].tste = TSTE_OPC_VAR;
3514 card->soft_tst[i].vc = NULL;
3517 if (dev->phy == NULL) {
3518 printk("%s: No LT device defined.\n", card->name);
3522 if (dev->phy->ioctl == NULL) {
3523 printk("%s: LT had no IOCTL funtion defined.\n", card->name);
3528 #ifdef CONFIG_ATM_IDT77252_USE_SUNI
3530 * this is a jhs hack to get around special functionality in the
3531 * phy driver for the atecom hardware; the functionality doesn't
3532 * exist in the linux atm suni driver
3534 * it isn't the right way to do things, but as the guy from NIST
3535 * said, talking about their measurement of the fine structure
3536 * constant, "it's good enough for government work."
3538 linkrate = 149760000;
3541 card->link_pcr = (linkrate / 8 / 53);
3542 printk("%s: Linkrate on ATM line : %u bit/s, %u cell/s.\n",
3543 card->name, linkrate, card->link_pcr);
3545 #ifdef CONFIG_ATM_IDT77252_SEND_IDLE
3546 card->utopia_pcr = card->link_pcr;
3548 card->utopia_pcr = (160000000 / 8 / 54);
3552 if (card->utopia_pcr > card->link_pcr)
3553 rsvdcr = card->utopia_pcr - card->link_pcr;
3555 tmpl = (unsigned long) rsvdcr * ((unsigned long) card->tst_size - 2);
3556 modl = tmpl % (unsigned long)card->utopia_pcr;
3557 tst_entries = (int) (tmpl / (unsigned long)card->utopia_pcr);
3560 card->tst_free -= tst_entries;
3561 fill_tst(card, NULL, tst_entries, TSTE_OPC_NULL);
3564 idt77252_eeprom_init(card);
3565 printk("%s: EEPROM: %02x:", card->name,
3566 idt77252_eeprom_read_status(card));
3568 for (i = 0; i < 0x80; i++) {
3570 idt77252_eeprom_read_byte(card, i)
3574 #endif /* HAVE_EEPROM */
3579 sprintf(tname, "eth%d", card->index);
3580 tmp = dev_get_by_name(tname); /* jhs: was "tmp = dev_get(tname);" */
3582 memcpy(card->atmdev->esi, tmp->dev_addr, 6);
3584 printk("%s: ESI %02x:%02x:%02x:%02x:%02x:%02x\n",
3585 card->name, card->atmdev->esi[0], card->atmdev->esi[1],
3586 card->atmdev->esi[2], card->atmdev->esi[3],
3587 card->atmdev->esi[4], card->atmdev->esi[5]);
3593 /* Set Maximum Deficit Count for now. */
3594 writel(0xffff, SAR_REG_MDFCT);
3596 set_bit(IDT77252_BIT_INIT, &card->flags);
3598 XPRINTK("%s: IDT77252 ABR SAR initialization complete.\n", card->name);
3603 /*****************************************************************************/
3605 /* Probing of IDT77252 ABR SAR */
3607 /*****************************************************************************/
3610 static int __devinit
3611 idt77252_preset(struct idt77252_dev *card)
3615 /*****************************************************************/
3616 /* P C I C O N F I G U R A T I O N */
3617 /*****************************************************************/
3619 XPRINTK("%s: Enable PCI master and memory access for SAR.\n",
3621 if (pci_read_config_word(card->pcidev, PCI_COMMAND, &pci_command)) {
3622 printk("%s: can't read PCI_COMMAND.\n", card->name);
3626 if (!(pci_command & PCI_COMMAND_IO)) {
3627 printk("%s: PCI_COMMAND: %04x (???)\n",
3628 card->name, pci_command);
3632 pci_command |= (PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
3633 if (pci_write_config_word(card->pcidev, PCI_COMMAND, pci_command)) {
3634 printk("%s: can't write PCI_COMMAND.\n", card->name);
3638 /*****************************************************************/
3639 /* G E N E R I C R E S E T */
3640 /*****************************************************************/
3642 /* Software reset */
3643 writel(SAR_CFG_SWRST, SAR_REG_CFG);
3645 writel(0, SAR_REG_CFG);
3647 IPRINTK("%s: Software resetted.\n", card->name);
3652 static unsigned long __devinit
3653 probe_sram(struct idt77252_dev *card)
3657 writel(0, SAR_REG_DR0);
3658 writel(SAR_CMD_WRITE_SRAM | (0 << 2), SAR_REG_CMD);
3660 for (addr = 0x4000; addr < 0x80000; addr += 0x4000) {
3661 writel(0xdeadbeef, SAR_REG_DR0);
3662 writel(SAR_CMD_WRITE_SRAM | (addr << 2), SAR_REG_CMD);
3664 writel(SAR_CMD_READ_SRAM | (0 << 2), SAR_REG_CMD);
3665 data = readl(SAR_REG_DR0);
3671 return addr * sizeof(u32);
3674 static int __devinit
3675 idt77252_init_one(struct pci_dev *pcidev, const struct pci_device_id *id)
3677 static struct idt77252_dev **last = &idt77252_chain;
3678 static int index = 0;
3680 unsigned long membase, srambase;
3681 struct idt77252_dev *card;
3682 struct atm_dev *dev;
3683 ushort revision = 0;
3687 if (pci_read_config_word(pcidev, PCI_REVISION_ID, &revision)) {
3688 printk("idt77252-%d: can't read PCI_REVISION_ID\n", index);
3692 card = kmalloc(sizeof(struct idt77252_dev), GFP_KERNEL);
3694 printk("idt77252-%d: can't allocate private data\n", index);
3697 memset(card, 0, sizeof(struct idt77252_dev));
3699 card->revision = revision;
3700 card->index = index;
3701 card->pcidev = pcidev;
3702 sprintf(card->name, "idt77252-%d", card->index);
3704 INIT_WORK(&card->tqueue, idt77252_softint, (void *)card);
3706 membase = pci_resource_start(pcidev, 1);
3707 srambase = pci_resource_start(pcidev, 2);
3709 init_MUTEX(&card->mutex);
3710 spin_lock_init(&card->cmd_lock);
3711 spin_lock_init(&card->tst_lock);
3713 init_timer(&card->tst_timer);
3714 card->tst_timer.data = (unsigned long)card;
3715 card->tst_timer.function = tst_timer;
3717 /* Do the I/O remapping... */
3718 card->membase = (unsigned long) ioremap(membase, 1024);
3719 if (!card->membase) {
3720 printk("%s: can't ioremap() membase\n", card->name);
3725 if (idt77252_preset(card)) {
3726 printk("%s: preset failed\n", card->name);
3727 iounmap((void *) card->membase);
3732 dev = atm_dev_register("idt77252", &idt77252_ops, -1, 0);
3734 printk("%s: can't register atm device\n", card->name);
3735 iounmap((void *) card->membase);
3739 dev->dev_data = card;
3742 #ifdef CONFIG_ATM_IDT77252_USE_SUNI
3745 printk("%s: can't init SUNI\n", card->name);
3750 #endif /* CONFIG_ATM_IDT77252_USE_SUNI */
3752 card->sramsize = probe_sram(card);
3754 for (i = 0; i < 4; i++) {
3755 card->fbq[i] = (unsigned long)
3756 ioremap(srambase | 0x200000 | (i << 18), 4);
3757 if (!card->fbq[i]) {
3758 printk("%s: can't ioremap() FBQ%d\n", card->name, i);
3765 printk("%s: ABR SAR (Rev %c): MEM %08lx SRAM %08lx [%u KB]\n",
3766 card->name, ((revision > 1) && (revision < 25)) ?
3767 'A' + revision - 1 : '?', membase, srambase,
3768 card->sramsize / 1024);
3770 if (init_card(dev)) {
3771 printk("%s: init_card failed\n", card->name);
3777 dev->ci_range.vpi_bits = card->vpibits;
3778 dev->ci_range.vci_bits = card->vcibits;
3779 dev->link_rate = card->link_pcr;
3781 if (dev->phy->start)
3782 dev->phy->start(dev);
3784 if (idt77252_dev_open(card)) {
3785 printk("%s: dev_open failed\n", card->name);
3788 dev->phy->stop(dev);
3801 static struct pci_device_id idt77252_pci_tbl[] =
3803 { PCI_VENDOR_ID_IDT, PCI_DEVICE_ID_IDT_IDT77252,
3804 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
3808 static struct pci_driver idt77252_driver = {
3810 .id_table = idt77252_pci_tbl,
3811 .probe = idt77252_init_one,
3814 static int __init idt77252_init(void)
3816 struct sk_buff *skb;
3818 printk("%s: at %p\n", __FUNCTION__, idt77252_init);
3820 if (sizeof(skb->cb) < sizeof(struct atm_skb_data) +
3821 sizeof(struct idt77252_skb_prv)) {
3822 printk(KERN_ERR "%s: skb->cb is too small (%lu < %lu)\n",
3823 __FUNCTION__, (unsigned long) sizeof(skb->cb),
3824 (unsigned long) sizeof(struct atm_skb_data) +
3825 sizeof(struct idt77252_skb_prv));
3829 if (pci_register_driver(&idt77252_driver) > 0)
3832 pci_unregister_driver(&idt77252_driver);
3836 static void __exit idt77252_exit(void)
3838 struct idt77252_dev *card;
3839 struct atm_dev *dev;
3841 pci_unregister_driver(&idt77252_driver);
3843 while (idt77252_chain) {
3844 card = idt77252_chain;
3846 idt77252_chain = card->next;
3849 dev->phy->stop(dev);
3854 DIPRINTK("idt77252: finished cleanup-module().\n");
3857 module_init(idt77252_init);
3858 module_exit(idt77252_exit);
3860 MODULE_LICENSE("GPL");
3862 MODULE_PARM(vpibits, "i");
3863 MODULE_PARM_DESC(vpibits, "number of VPI bits supported (0, 1, or 2)");
3864 #ifdef CONFIG_ATM_IDT77252_DEBUG
3865 MODULE_PARM(debug, "i");
3866 MODULE_PARM_DESC(debug, "debug bitmap, see drivers/atm/idt77252.h");
3869 MODULE_AUTHOR("Eddie C. Dost <ecd@atecom.com>");
3870 MODULE_DESCRIPTION("IDT77252 ABR SAR Driver");