1 /******************************************************************************
2 iphase.c: Device driver for Interphase ATM PCI adapter cards
3 Author: Peter Wang <pwang@iphase.com>
4 Some fixes: Arnaldo Carvalho de Melo <acme@conectiva.com.br>
5 Interphase Corporation <www.iphase.com>
7 *******************************************************************************
9 This software may be used and distributed according to the terms
10 of the GNU General Public License (GPL), incorporated herein by reference.
11 Drivers based on this skeleton fall under the GPL and must retain
12 the authorship (implicit copyright) notice.
14 This program is distributed in the hope that it will be useful, but
15 WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
17 General Public License for more details.
19 Modified from an incomplete driver for Interphase 5575 1KVC 1M card which
20 was originally written by Monalisa Agrawal at UNH. Now this driver
21 supports a variety of varients of Interphase ATM PCI (i)Chip adapter
22 card family (See www.iphase.com/products/ClassSheet.cfm?ClassID=ATM)
23 in terms of PHY type, the size of control memory and the size of
24 packet memory. The followings are the change log and history:
26 Bugfix the Mona's UBR driver.
27 Modify the basic memory allocation and dma logic.
28 Port the driver to the latest kernel from 2.0.46.
29 Complete the ABR logic of the driver, and added the ABR work-
30 around for the hardware anormalies.
32 Add the flow control logic to the driver to allow rate-limit VC.
33 Add 4K VC support to the board with 512K control memory.
34 Add the support of all the variants of the Interphase ATM PCI
35 (i)Chip adapter cards including x575 (155M OC3 and UTP155), x525
36 (25M UTP25) and x531 (DS3 and E3).
39 Support and updates available at: ftp://ftp.iphase.com/pub/atm
41 *******************************************************************************/
43 #include <linux/module.h>
44 #include <linux/kernel.h>
46 #include <linux/pci.h>
47 #include <linux/errno.h>
48 #include <linux/atm.h>
49 #include <linux/atmdev.h>
50 #include <linux/sonet.h>
51 #include <linux/skbuff.h>
52 #include <linux/time.h>
53 #include <linux/delay.h>
54 #include <linux/uio.h>
55 #include <linux/init.h>
56 #include <asm/system.h>
58 #include <asm/atomic.h>
59 #include <asm/uaccess.h>
60 #include <asm/string.h>
61 #include <asm/byteorder.h>
62 #include <linux/vmalloc.h>
65 #define swap(x) (((x & 0xff) << 8) | ((x & 0xff00) >> 8))
67 struct k_sonet_stats sonet_stats; /* link diagnostics */
68 unsigned char loop_mode; /* loopback mode */
69 struct atm_dev *dev; /* device back-pointer */
70 struct suni_priv *next; /* next SUNI */
72 #define PRIV(dev) ((struct suni_priv *) dev->phy_data)
74 static unsigned char ia_phy_get(struct atm_dev *dev, unsigned long addr);
76 static IADEV *ia_dev[8];
77 static struct atm_dev *_ia_dev[8];
78 static int iadev_count;
79 static void ia_led_timer(unsigned long arg);
80 static struct timer_list ia_timer = TIMER_INITIALIZER(ia_led_timer, 0, 0);
81 struct atm_vcc *vcc_close_que[100];
82 static int IA_TX_BUF = DFL_TX_BUFFERS, IA_TX_BUF_SZ = DFL_TX_BUF_SZ;
83 static int IA_RX_BUF = DFL_RX_BUFFERS, IA_RX_BUF_SZ = DFL_RX_BUF_SZ;
84 static uint IADebugFlag = /* IF_IADBG_ERR | IF_IADBG_CBR| IF_IADBG_INIT_ADAPTER
85 |IF_IADBG_ABR | IF_IADBG_EVENT*/ 0;
87 module_param(IA_TX_BUF, int, 0);
88 module_param(IA_TX_BUF_SZ, int, 0);
89 module_param(IA_RX_BUF, int, 0);
90 module_param(IA_RX_BUF_SZ, int, 0);
91 module_param(IADebugFlag, uint, 0644);
93 MODULE_LICENSE("GPL");
95 #if BITS_PER_LONG != 32
96 # error FIXME: this driver only works on 32-bit platforms
99 /**************************** IA_LIB **********************************/
101 static void ia_init_rtn_q (IARTN_Q *que)
107 static void ia_enque_head_rtn_q (IARTN_Q *que, IARTN_Q * data)
110 if (que->next == NULL)
111 que->next = que->tail = data;
113 data->next = que->next;
119 static int ia_enque_rtn_q (IARTN_Q *que, struct desc_tbl_t data) {
120 IARTN_Q *entry = kmalloc(sizeof(*entry), GFP_ATOMIC);
121 if (!entry) return -1;
124 if (que->next == NULL)
125 que->next = que->tail = entry;
127 que->tail->next = entry;
128 que->tail = que->tail->next;
133 static IARTN_Q * ia_deque_rtn_q (IARTN_Q *que) {
135 if (que->next == NULL)
138 if ( que->next == que->tail)
139 que->next = que->tail = NULL;
141 que->next = que->next->next;
145 static void ia_hack_tcq(IADEV *dev) {
149 struct ia_vcc *iavcc_r = NULL;
150 extern void desc_dbg(IADEV *iadev);
152 tcq_wr = readl(dev->seg_reg+TCQ_WR_PTR) & 0xffff;
153 while (dev->host_tcq_wr != tcq_wr) {
154 desc1 = *(u_short *)(dev->seg_ram + dev->host_tcq_wr);
156 else if (!dev->desc_tbl[desc1 -1].timestamp) {
157 IF_ABR(printk(" Desc %d is reset at %ld\n", desc1 -1, jiffies);)
158 *(u_short *) (dev->seg_ram + dev->host_tcq_wr) = 0;
160 else if (dev->desc_tbl[desc1 -1].timestamp) {
161 if (!(iavcc_r = dev->desc_tbl[desc1 -1].iavcc)) {
162 printk("IA: Fatal err in get_desc\n");
165 iavcc_r->vc_desc_cnt--;
166 dev->desc_tbl[desc1 -1].timestamp = 0;
167 IF_EVENT(printk("ia_hack: return_q skb = 0x%x desc = %d\n",
168 (u32)dev->desc_tbl[desc1 -1].txskb, desc1);)
169 if (iavcc_r->pcr < dev->rate_limit) {
170 IA_SKB_STATE (dev->desc_tbl[desc1-1].txskb) |= IA_TX_DONE;
171 if (ia_enque_rtn_q(&dev->tx_return_q, dev->desc_tbl[desc1 -1]) < 0)
172 printk("ia_hack_tcq: No memory available\n");
174 dev->desc_tbl[desc1 -1].iavcc = NULL;
175 dev->desc_tbl[desc1 -1].txskb = NULL;
177 dev->host_tcq_wr += 2;
178 if (dev->host_tcq_wr > dev->ffL.tcq_ed)
179 dev->host_tcq_wr = dev->ffL.tcq_st;
183 static u16 get_desc (IADEV *dev, struct ia_vcc *iavcc) {
186 struct ia_vcc *iavcc_r = NULL;
188 static unsigned long timer = 0;
190 extern void desc_dbg(IADEV *iadev);
193 if(((jiffies - timer)>50)||((dev->ffL.tcq_rd==dev->host_tcq_wr))){
196 while (i < dev->num_tx_desc) {
197 if (!dev->desc_tbl[i].timestamp) {
201 ltimeout = dev->desc_tbl[i].iavcc->ltimeout;
202 delta = jiffies - dev->desc_tbl[i].timestamp;
203 if (delta >= ltimeout) {
204 IF_ABR(printk("RECOVER run!! desc_tbl %d = %d delta = %ld, time = %ld\n", i,dev->desc_tbl[i].timestamp, delta, jiffies);)
205 if (dev->ffL.tcq_rd == dev->ffL.tcq_st)
206 dev->ffL.tcq_rd = dev->ffL.tcq_ed;
208 dev->ffL.tcq_rd -= 2;
209 *(u_short *)(dev->seg_ram + dev->ffL.tcq_rd) = i+1;
210 if (!(skb = dev->desc_tbl[i].txskb) ||
211 !(iavcc_r = dev->desc_tbl[i].iavcc))
212 printk("Fatal err, desc table vcc or skb is NULL\n");
214 iavcc_r->vc_desc_cnt--;
215 dev->desc_tbl[i].timestamp = 0;
216 dev->desc_tbl[i].iavcc = NULL;
217 dev->desc_tbl[i].txskb = NULL;
222 if (dev->ffL.tcq_rd == dev->host_tcq_wr)
225 /* Get the next available descriptor number from TCQ */
226 desc_num = *(u_short *)(dev->seg_ram + dev->ffL.tcq_rd);
228 while (!desc_num || (dev->desc_tbl[desc_num -1]).timestamp) {
229 dev->ffL.tcq_rd += 2;
230 if (dev->ffL.tcq_rd > dev->ffL.tcq_ed)
231 dev->ffL.tcq_rd = dev->ffL.tcq_st;
232 if (dev->ffL.tcq_rd == dev->host_tcq_wr)
234 desc_num = *(u_short *)(dev->seg_ram + dev->ffL.tcq_rd);
237 /* get system time */
238 dev->desc_tbl[desc_num -1].timestamp = jiffies;
242 static void clear_lockup (struct atm_vcc *vcc, IADEV *dev) {
244 vcstatus_t *vcstatus;
246 u_short tempCellSlot, tempFract;
247 struct main_vc *abr_vc = (struct main_vc *)dev->MAIN_VC_TABLE_ADDR;
248 struct ext_vc *eabr_vc = (struct ext_vc *)dev->EXT_VC_TABLE_ADDR;
251 if (vcc->qos.txtp.traffic_class == ATM_ABR) {
252 vcstatus = (vcstatus_t *) &(dev->testTable[vcc->vci]->vc_status);
255 if( vcstatus->cnt == 0x05 ) {
258 if( eabr_vc->last_desc ) {
259 if( (abr_vc->status & 0x07) == ABR_STATE /* 0x2 */ ) {
260 /* Wait for 10 Micro sec */
262 if ((eabr_vc->last_desc)&&((abr_vc->status & 0x07)==ABR_STATE))
266 tempCellSlot = abr_vc->last_cell_slot;
267 tempFract = abr_vc->fraction;
268 if((tempCellSlot == dev->testTable[vcc->vci]->lastTime)
269 && (tempFract == dev->testTable[vcc->vci]->fract))
271 dev->testTable[vcc->vci]->lastTime = tempCellSlot;
272 dev->testTable[vcc->vci]->fract = tempFract;
274 } /* last descriptor */
276 } /* vcstatus->cnt */
279 IF_ABR(printk("LOCK UP found\n");)
280 writew(0xFFFD, dev->seg_reg+MODE_REG_0);
281 /* Wait for 10 Micro sec */
283 abr_vc->status &= 0xFFF8;
284 abr_vc->status |= 0x0001; /* state is idle */
285 shd_tbl = (u_short *)dev->ABR_SCHED_TABLE_ADDR;
286 for( i = 0; ((i < dev->num_vc) && (shd_tbl[i])); i++ );
288 shd_tbl[i] = vcc->vci;
290 IF_ERR(printk("ABR Seg. may not continue on VC %x\n",vcc->vci);)
291 writew(T_ONLINE, dev->seg_reg+MODE_REG_0);
292 writew(~(TRANSMIT_DONE|TCQ_NOT_EMPTY), dev->seg_reg+SEG_MASK_REG);
293 writew(TRANSMIT_DONE, dev->seg_reg+SEG_INTR_STATUS_REG);
303 ** Conversion of 24-bit cellrate (cells/sec) to 16-bit floating point format.
305 ** +----+----+------------------+-------------------------------+
306 ** | R | NZ | 5-bit exponent | 9-bit mantissa |
307 ** +----+----+------------------+-------------------------------+
309 ** R = reserverd (written as 0)
310 ** NZ = 0 if 0 cells/sec; 1 otherwise
312 ** if NZ = 1, rate = 1.mmmmmmmmm x 2^(eeeee) cells/sec
315 cellrate_to_float(u32 cr)
319 #define M_BITS 9 /* Number of bits in mantissa */
320 #define E_BITS 5 /* Number of bits in exponent */
324 u32 tmp = cr & 0x00ffffff;
333 flot = NZ | (i << M_BITS) | (cr & M_MASK);
335 flot = NZ | (i << M_BITS) | ((cr << (M_BITS - i)) & M_MASK);
337 flot = NZ | (i << M_BITS) | ((cr >> (i - M_BITS)) & M_MASK);
343 ** Conversion of 16-bit floating point format to 24-bit cellrate (cells/sec).
346 float_to_cellrate(u16 rate)
348 u32 exp, mantissa, cps;
349 if ((rate & NZ) == 0)
351 exp = (rate >> M_BITS) & E_MASK;
352 mantissa = rate & M_MASK;
355 cps = (1 << M_BITS) | mantissa;
358 else if (exp > M_BITS)
359 cps <<= (exp - M_BITS);
361 cps >>= (M_BITS - exp);
366 static void init_abr_vc (IADEV *dev, srv_cls_param_t *srv_p) {
367 srv_p->class_type = ATM_ABR;
368 srv_p->pcr = dev->LineRate;
370 srv_p->icr = 0x055cb7;
371 srv_p->tbe = 0xffffff;
382 ia_open_abr_vc(IADEV *dev, srv_cls_param_t *srv_p,
383 struct atm_vcc *vcc, u8 flag)
385 f_vc_abr_entry *f_abr_vc;
386 r_vc_abr_entry *r_abr_vc;
389 u16 adtf, air, *ptr16;
390 f_abr_vc =(f_vc_abr_entry *)dev->MAIN_VC_TABLE_ADDR;
391 f_abr_vc += vcc->vci;
393 case 1: /* FFRED initialization */
394 #if 0 /* sanity check */
397 if (srv_p->pcr > dev->LineRate)
398 srv_p->pcr = dev->LineRate;
399 if ((srv_p->mcr + dev->sum_mcr) > dev->LineRate)
400 return MCR_UNAVAILABLE;
401 if (srv_p->mcr > srv_p->pcr)
404 srv_p->icr = srv_p->pcr;
405 if ((srv_p->icr < srv_p->mcr) || (srv_p->icr > srv_p->pcr))
407 if ((srv_p->tbe < MIN_TBE) || (srv_p->tbe > MAX_TBE))
409 if ((srv_p->frtt < MIN_FRTT) || (srv_p->frtt > MAX_FRTT))
411 if (srv_p->nrm > MAX_NRM)
413 if (srv_p->trm > MAX_TRM)
415 if (srv_p->adtf > MAX_ADTF)
417 else if (srv_p->adtf == 0)
419 if (srv_p->cdf > MAX_CDF)
421 if (srv_p->rif > MAX_RIF)
423 if (srv_p->rdf > MAX_RDF)
426 memset ((caddr_t)f_abr_vc, 0, sizeof(*f_abr_vc));
427 f_abr_vc->f_vc_type = ABR;
428 nrm = 2 << srv_p->nrm; /* (2 ** (srv_p->nrm +1)) */
429 /* i.e 2**n = 2 << (n-1) */
430 f_abr_vc->f_nrm = nrm << 8 | nrm;
431 trm = 100000/(2 << (16 - srv_p->trm));
432 if ( trm == 0) trm = 1;
433 f_abr_vc->f_nrmexp =(((srv_p->nrm +1) & 0x0f) << 12)|(MRM << 8) | trm;
434 crm = srv_p->tbe / nrm;
435 if (crm == 0) crm = 1;
436 f_abr_vc->f_crm = crm & 0xff;
437 f_abr_vc->f_pcr = cellrate_to_float(srv_p->pcr);
438 icr = min( srv_p->icr, (srv_p->tbe > srv_p->frtt) ?
439 ((srv_p->tbe/srv_p->frtt)*1000000) :
440 (1000000/(srv_p->frtt/srv_p->tbe)));
441 f_abr_vc->f_icr = cellrate_to_float(icr);
442 adtf = (10000 * srv_p->adtf)/8192;
443 if (adtf == 0) adtf = 1;
444 f_abr_vc->f_cdf = ((7 - srv_p->cdf) << 12 | adtf) & 0xfff;
445 f_abr_vc->f_mcr = cellrate_to_float(srv_p->mcr);
446 f_abr_vc->f_acr = f_abr_vc->f_icr;
447 f_abr_vc->f_status = 0x0042;
449 case 0: /* RFRED initialization */
450 ptr16 = (u_short *)(dev->reass_ram + REASS_TABLE*dev->memSize);
451 *(ptr16 + vcc->vci) = NO_AAL5_PKT | REASS_ABR;
452 r_abr_vc = (r_vc_abr_entry*)(dev->reass_ram+ABR_VC_TABLE*dev->memSize);
453 r_abr_vc += vcc->vci;
454 r_abr_vc->r_status_rdf = (15 - srv_p->rdf) & 0x000f;
455 air = srv_p->pcr << (15 - srv_p->rif);
456 if (air == 0) air = 1;
457 r_abr_vc->r_air = cellrate_to_float(air);
458 dev->testTable[vcc->vci]->vc_status = VC_ACTIVE | VC_ABR;
459 dev->sum_mcr += srv_p->mcr;
467 static int ia_cbr_setup (IADEV *dev, struct atm_vcc *vcc) {
468 u32 rateLow=0, rateHigh, rate;
470 struct ia_vcc *ia_vcc;
472 int idealSlot =0, testSlot, toBeAssigned, inc;
474 u16 *SchedTbl, *TstSchedTbl;
480 /* IpAdjustTrafficParams */
481 if (vcc->qos.txtp.max_pcr <= 0) {
482 IF_ERR(printk("PCR for CBR not defined\n");)
485 rate = vcc->qos.txtp.max_pcr;
486 entries = rate / dev->Granularity;
487 IF_CBR(printk("CBR: CBR entries=0x%x for rate=0x%x & Gran=0x%x\n",
488 entries, rate, dev->Granularity);)
490 IF_CBR(printk("CBR: Bandwidth smaller than granularity of CBR table\n");)
491 rateLow = entries * dev->Granularity;
492 rateHigh = (entries + 1) * dev->Granularity;
493 if (3*(rate - rateLow) > (rateHigh - rate))
495 if (entries > dev->CbrRemEntries) {
496 IF_CBR(printk("CBR: Not enough bandwidth to support this PCR.\n");)
497 IF_CBR(printk("Entries = 0x%x, CbrRemEntries = 0x%x.\n",
498 entries, dev->CbrRemEntries);)
502 ia_vcc = INPH_IA_VCC(vcc);
503 ia_vcc->NumCbrEntry = entries;
504 dev->sum_mcr += entries * dev->Granularity;
505 /* IaFFrednInsertCbrSched */
506 // Starting at an arbitrary location, place the entries into the table
507 // as smoothly as possible
509 spacing = dev->CbrTotEntries / entries;
510 sp_mod = dev->CbrTotEntries % entries; // get modulo
511 toBeAssigned = entries;
514 IF_CBR(printk("Vci=0x%x,Spacing=0x%x,Sp_mod=0x%x\n",vcIndex,spacing,sp_mod);)
517 // If this is the first time, start the table loading for this connection
518 // as close to entryPoint as possible.
519 if (toBeAssigned == entries)
521 idealSlot = dev->CbrEntryPt;
522 dev->CbrEntryPt += 2; // Adding 2 helps to prevent clumping
523 if (dev->CbrEntryPt >= dev->CbrTotEntries)
524 dev->CbrEntryPt -= dev->CbrTotEntries;// Wrap if necessary
526 idealSlot += (u32)(spacing + fracSlot); // Point to the next location
527 // in the table that would be smoothest
528 fracSlot = ((sp_mod + sp_mod2) / entries); // get new integer part
529 sp_mod2 = ((sp_mod + sp_mod2) % entries); // calc new fractional part
531 if (idealSlot >= (int)dev->CbrTotEntries)
532 idealSlot -= dev->CbrTotEntries;
533 // Continuously check around this ideal value until a null
534 // location is encountered.
535 SchedTbl = (u16*)(dev->seg_ram+CBR_SCHED_TABLE*dev->memSize);
537 testSlot = idealSlot;
538 TstSchedTbl = (u16*)(SchedTbl+testSlot); //set index and read in value
539 IF_CBR(printk("CBR Testslot 0x%x AT Location 0x%x, NumToAssign=%d\n",
540 testSlot, (u32)TstSchedTbl,toBeAssigned);)
541 memcpy((caddr_t)&cbrVC,(caddr_t)TstSchedTbl,sizeof(cbrVC));
542 while (cbrVC) // If another VC at this location, we have to keep looking
545 testSlot = idealSlot - inc;
546 if (testSlot < 0) { // Wrap if necessary
547 testSlot += dev->CbrTotEntries;
548 IF_CBR(printk("Testslot Wrap. STable Start=0x%x,Testslot=%d\n",
549 (u32)SchedTbl,testSlot);)
551 TstSchedTbl = (u16 *)(SchedTbl + testSlot); // set table index
552 memcpy((caddr_t)&cbrVC,(caddr_t)TstSchedTbl,sizeof(cbrVC));
555 testSlot = idealSlot + inc;
556 if (testSlot >= (int)dev->CbrTotEntries) { // Wrap if necessary
557 testSlot -= dev->CbrTotEntries;
558 IF_CBR(printk("TotCbrEntries=%d",dev->CbrTotEntries);)
559 IF_CBR(printk(" Testslot=0x%x ToBeAssgned=%d\n",
560 testSlot, toBeAssigned);)
562 // set table index and read in value
563 TstSchedTbl = (u16*)(SchedTbl + testSlot);
564 IF_CBR(printk("Reading CBR Tbl from 0x%x, CbrVal=0x%x Iteration %d\n",
565 (u32)TstSchedTbl,cbrVC,inc);)
566 memcpy((caddr_t)&cbrVC,(caddr_t)TstSchedTbl,sizeof(cbrVC));
568 // Move this VCI number into this location of the CBR Sched table.
569 memcpy((caddr_t)TstSchedTbl, (caddr_t)&vcIndex,sizeof(TstSchedTbl));
570 dev->CbrRemEntries--;
574 /* IaFFrednCbrEnable */
575 dev->NumEnabledCBR++;
576 if (dev->NumEnabledCBR == 1) {
577 writew((CBR_EN | UBR_EN | ABR_EN | (0x23 << 2)), dev->seg_reg+STPARMS);
578 IF_CBR(printk("CBR is enabled\n");)
582 static void ia_cbrVc_close (struct atm_vcc *vcc) {
584 u16 *SchedTbl, NullVci = 0;
587 iadev = INPH_IA_DEV(vcc->dev);
588 iadev->NumEnabledCBR--;
589 SchedTbl = (u16*)(iadev->seg_ram+CBR_SCHED_TABLE*iadev->memSize);
590 if (iadev->NumEnabledCBR == 0) {
591 writew((UBR_EN | ABR_EN | (0x23 << 2)), iadev->seg_reg+STPARMS);
592 IF_CBR (printk("CBR support disabled\n");)
595 for (i=0; i < iadev->CbrTotEntries; i++)
597 if (*SchedTbl == vcc->vci) {
598 iadev->CbrRemEntries++;
604 IF_CBR(printk("Exit ia_cbrVc_close, NumRemoved=%d\n",NumFound);)
607 static int ia_avail_descs(IADEV *iadev) {
610 if (iadev->host_tcq_wr >= iadev->ffL.tcq_rd)
611 tmp = (iadev->host_tcq_wr - iadev->ffL.tcq_rd) / 2;
613 tmp = (iadev->ffL.tcq_ed - iadev->ffL.tcq_rd + 2 + iadev->host_tcq_wr -
614 iadev->ffL.tcq_st) / 2;
618 static int ia_pkt_tx (struct atm_vcc *vcc, struct sk_buff *skb);
620 static int ia_que_tx (IADEV *iadev) {
624 struct ia_vcc *iavcc;
625 num_desc = ia_avail_descs(iadev);
627 while (num_desc && (skb = skb_dequeue(&iadev->tx_backlog))) {
628 if (!(vcc = ATM_SKB(skb)->vcc)) {
629 dev_kfree_skb_any(skb);
630 printk("ia_que_tx: Null vcc\n");
633 if (!test_bit(ATM_VF_READY,&vcc->flags)) {
634 dev_kfree_skb_any(skb);
635 printk("Free the SKB on closed vci %d \n", vcc->vci);
638 iavcc = INPH_IA_VCC(vcc);
639 if (ia_pkt_tx (vcc, skb)) {
640 skb_queue_head(&iadev->tx_backlog, skb);
647 void ia_tx_poll (IADEV *iadev) {
648 struct atm_vcc *vcc = NULL;
649 struct sk_buff *skb = NULL, *skb1 = NULL;
650 struct ia_vcc *iavcc;
654 while ( (rtne = ia_deque_rtn_q(&iadev->tx_return_q))) {
655 skb = rtne->data.txskb;
657 printk("ia_tx_poll: skb is null\n");
660 vcc = ATM_SKB(skb)->vcc;
662 printk("ia_tx_poll: vcc is null\n");
663 dev_kfree_skb_any(skb);
667 iavcc = INPH_IA_VCC(vcc);
669 printk("ia_tx_poll: iavcc is null\n");
670 dev_kfree_skb_any(skb);
674 skb1 = skb_dequeue(&iavcc->txing_skb);
675 while (skb1 && (skb1 != skb)) {
676 if (!(IA_SKB_STATE(skb1) & IA_TX_DONE)) {
677 printk("IA_tx_intr: Vci %d lost pkt!!!\n", vcc->vci);
679 IF_ERR(printk("Release the SKB not match\n");)
680 if ((vcc->pop) && (skb1->len != 0))
683 IF_EVENT(printk("Tansmit Done - skb 0x%lx return\n",
687 dev_kfree_skb_any(skb1);
688 skb1 = skb_dequeue(&iavcc->txing_skb);
691 IF_EVENT(printk("IA: Vci %d - skb not found requed\n",vcc->vci);)
692 ia_enque_head_rtn_q (&iadev->tx_return_q, rtne);
695 if ((vcc->pop) && (skb->len != 0))
698 IF_EVENT(printk("Tx Done - skb 0x%lx return\n",(long)skb);)
701 dev_kfree_skb_any(skb);
709 static void ia_eeprom_put (IADEV *iadev, u32 addr, u_short val)
714 * Issue a command to enable writes to the NOVRAM
716 NVRAM_CMD (EXTEND + EWEN);
719 * issue the write command
721 NVRAM_CMD(IAWRITE + addr);
723 * Send the data, starting with D15, then D14, and so on for 16 bits
725 for (i=15; i>=0; i--) {
726 NVRAM_CLKOUT (val & 0x8000);
731 t = readl(iadev->reg+IPHASE5575_EEPROM_ACCESS);
733 t = readl(iadev->reg+IPHASE5575_EEPROM_ACCESS);
737 * disable writes again
739 NVRAM_CMD(EXTEND + EWDS)
745 static u16 ia_eeprom_get (IADEV *iadev, u32 addr)
751 * Read the first bit that was clocked with the falling edge of the
752 * the last command data clock
754 NVRAM_CMD(IAREAD + addr);
756 * Now read the rest of the bits, the next bit read is D14, then D13,
760 for (i=15; i>=0; i--) {
769 static void ia_hw_type(IADEV *iadev) {
770 u_short memType = ia_eeprom_get(iadev, 25);
771 iadev->memType = memType;
772 if ((memType & MEM_SIZE_MASK) == MEM_SIZE_1M) {
773 iadev->num_tx_desc = IA_TX_BUF;
774 iadev->tx_buf_sz = IA_TX_BUF_SZ;
775 iadev->num_rx_desc = IA_RX_BUF;
776 iadev->rx_buf_sz = IA_RX_BUF_SZ;
777 } else if ((memType & MEM_SIZE_MASK) == MEM_SIZE_512K) {
778 if (IA_TX_BUF == DFL_TX_BUFFERS)
779 iadev->num_tx_desc = IA_TX_BUF / 2;
781 iadev->num_tx_desc = IA_TX_BUF;
782 iadev->tx_buf_sz = IA_TX_BUF_SZ;
783 if (IA_RX_BUF == DFL_RX_BUFFERS)
784 iadev->num_rx_desc = IA_RX_BUF / 2;
786 iadev->num_rx_desc = IA_RX_BUF;
787 iadev->rx_buf_sz = IA_RX_BUF_SZ;
790 if (IA_TX_BUF == DFL_TX_BUFFERS)
791 iadev->num_tx_desc = IA_TX_BUF / 8;
793 iadev->num_tx_desc = IA_TX_BUF;
794 iadev->tx_buf_sz = IA_TX_BUF_SZ;
795 if (IA_RX_BUF == DFL_RX_BUFFERS)
796 iadev->num_rx_desc = IA_RX_BUF / 8;
798 iadev->num_rx_desc = IA_RX_BUF;
799 iadev->rx_buf_sz = IA_RX_BUF_SZ;
801 iadev->rx_pkt_ram = TX_PACKET_RAM + (iadev->num_tx_desc * iadev->tx_buf_sz);
802 IF_INIT(printk("BUF: tx=%d,sz=%d rx=%d sz= %d rx_pkt_ram=%d\n",
803 iadev->num_tx_desc, iadev->tx_buf_sz, iadev->num_rx_desc,
804 iadev->rx_buf_sz, iadev->rx_pkt_ram);)
807 if ((memType & FE_MASK) == FE_SINGLE_MODE) {
808 iadev->phy_type = PHY_OC3C_S;
809 else if ((memType & FE_MASK) == FE_UTP_OPTION)
810 iadev->phy_type = PHY_UTP155;
812 iadev->phy_type = PHY_OC3C_M;
815 iadev->phy_type = memType & FE_MASK;
816 IF_INIT(printk("memType = 0x%x iadev->phy_type = 0x%x\n",
817 memType,iadev->phy_type);)
818 if (iadev->phy_type == FE_25MBIT_PHY)
819 iadev->LineRate = (u32)(((25600000/8)*26)/(27*53));
820 else if (iadev->phy_type == FE_DS3_PHY)
821 iadev->LineRate = (u32)(((44736000/8)*26)/(27*53));
822 else if (iadev->phy_type == FE_E3_PHY)
823 iadev->LineRate = (u32)(((34368000/8)*26)/(27*53));
825 iadev->LineRate = (u32)(ATM_OC3_PCR);
826 IF_INIT(printk("iadev->LineRate = %d \n", iadev->LineRate);)
830 static void IaFrontEndIntr(IADEV *iadev) {
831 volatile IA_SUNI *suni;
832 volatile ia_mb25_t *mb25;
833 volatile suni_pm7345_t *suni_pm7345;
837 if(iadev->phy_type & FE_25MBIT_PHY) {
838 mb25 = (ia_mb25_t*)iadev->phy;
839 iadev->carrier_detect = Boolean(mb25->mb25_intr_status & MB25_IS_GSB);
840 } else if (iadev->phy_type & FE_DS3_PHY) {
841 suni_pm7345 = (suni_pm7345_t *)iadev->phy;
842 /* clear FRMR interrupts */
843 frmr_intr = suni_pm7345->suni_ds3_frm_intr_stat;
844 iadev->carrier_detect =
845 Boolean(!(suni_pm7345->suni_ds3_frm_stat & SUNI_DS3_LOSV));
846 } else if (iadev->phy_type & FE_E3_PHY ) {
847 suni_pm7345 = (suni_pm7345_t *)iadev->phy;
848 frmr_intr = suni_pm7345->suni_e3_frm_maint_intr_ind;
849 iadev->carrier_detect =
850 Boolean(!(suni_pm7345->suni_e3_frm_fram_intr_ind_stat&SUNI_E3_LOS));
853 suni = (IA_SUNI *)iadev->phy;
854 intr_status = suni->suni_rsop_status & 0xff;
855 iadev->carrier_detect = Boolean(!(suni->suni_rsop_status & SUNI_LOSV));
857 if (iadev->carrier_detect)
858 printk("IA: SUNI carrier detected\n");
860 printk("IA: SUNI carrier lost signal\n");
864 void ia_mb25_init (IADEV *iadev)
866 volatile ia_mb25_t *mb25 = (ia_mb25_t*)iadev->phy;
868 mb25->mb25_master_ctrl = MB25_MC_DRIC | MB25_MC_DREC | MB25_MC_ENABLED;
870 mb25->mb25_master_ctrl = MB25_MC_DRIC | MB25_MC_DREC;
871 mb25->mb25_diag_control = 0;
873 * Initialize carrier detect state
875 iadev->carrier_detect = Boolean(mb25->mb25_intr_status & MB25_IS_GSB);
879 void ia_suni_pm7345_init (IADEV *iadev)
881 volatile suni_pm7345_t *suni_pm7345 = (suni_pm7345_t *)iadev->phy;
882 if (iadev->phy_type & FE_DS3_PHY)
884 iadev->carrier_detect =
885 Boolean(!(suni_pm7345->suni_ds3_frm_stat & SUNI_DS3_LOSV));
886 suni_pm7345->suni_ds3_frm_intr_enbl = 0x17;
887 suni_pm7345->suni_ds3_frm_cfg = 1;
888 suni_pm7345->suni_ds3_tran_cfg = 1;
889 suni_pm7345->suni_config = 0;
890 suni_pm7345->suni_splr_cfg = 0;
891 suni_pm7345->suni_splt_cfg = 0;
895 iadev->carrier_detect =
896 Boolean(!(suni_pm7345->suni_e3_frm_fram_intr_ind_stat & SUNI_E3_LOS));
897 suni_pm7345->suni_e3_frm_fram_options = 0x4;
898 suni_pm7345->suni_e3_frm_maint_options = 0x20;
899 suni_pm7345->suni_e3_frm_fram_intr_enbl = 0x1d;
900 suni_pm7345->suni_e3_frm_maint_intr_enbl = 0x30;
901 suni_pm7345->suni_e3_tran_stat_diag_options = 0x0;
902 suni_pm7345->suni_e3_tran_fram_options = 0x1;
903 suni_pm7345->suni_config = SUNI_PM7345_E3ENBL;
904 suni_pm7345->suni_splr_cfg = 0x41;
905 suni_pm7345->suni_splt_cfg = 0x41;
908 * Enable RSOP loss of signal interrupt.
910 suni_pm7345->suni_intr_enbl = 0x28;
913 * Clear error counters
915 suni_pm7345->suni_id_reset = 0;
918 * Clear "PMCTST" in master test register.
920 suni_pm7345->suni_master_test = 0;
922 suni_pm7345->suni_rxcp_ctrl = 0x2c;
923 suni_pm7345->suni_rxcp_fctrl = 0x81;
925 suni_pm7345->suni_rxcp_idle_pat_h1 =
926 suni_pm7345->suni_rxcp_idle_pat_h2 =
927 suni_pm7345->suni_rxcp_idle_pat_h3 = 0;
928 suni_pm7345->suni_rxcp_idle_pat_h4 = 1;
930 suni_pm7345->suni_rxcp_idle_mask_h1 = 0xff;
931 suni_pm7345->suni_rxcp_idle_mask_h2 = 0xff;
932 suni_pm7345->suni_rxcp_idle_mask_h3 = 0xff;
933 suni_pm7345->suni_rxcp_idle_mask_h4 = 0xfe;
935 suni_pm7345->suni_rxcp_cell_pat_h1 =
936 suni_pm7345->suni_rxcp_cell_pat_h2 =
937 suni_pm7345->suni_rxcp_cell_pat_h3 = 0;
938 suni_pm7345->suni_rxcp_cell_pat_h4 = 1;
940 suni_pm7345->suni_rxcp_cell_mask_h1 =
941 suni_pm7345->suni_rxcp_cell_mask_h2 =
942 suni_pm7345->suni_rxcp_cell_mask_h3 =
943 suni_pm7345->suni_rxcp_cell_mask_h4 = 0xff;
945 suni_pm7345->suni_txcp_ctrl = 0xa4;
946 suni_pm7345->suni_txcp_intr_en_sts = 0x10;
947 suni_pm7345->suni_txcp_idle_pat_h5 = 0x55;
949 suni_pm7345->suni_config &= ~(SUNI_PM7345_LLB |
954 suni_pm7345->suni_rxcp_intr_en_sts |= SUNI_OOCDE;
955 #endif /* __SNMP__ */
960 /***************************** IA_LIB END *****************************/
962 /* pwang_test debug utility */
963 int tcnter = 0, rcnter = 0;
964 void xdump( u_char* cp, int length, char* prefix )
968 u_char* pBuf = prntBuf;
970 while(count < length){
971 pBuf += sprintf( pBuf, "%s", prefix );
972 for(col = 0;count + col < length && col < 16; col++){
973 if (col != 0 && (col % 4) == 0)
974 pBuf += sprintf( pBuf, " " );
975 pBuf += sprintf( pBuf, "%02X ", cp[count + col] );
977 while(col++ < 16){ /* pad end of buffer with blanks */
979 sprintf( pBuf, " " );
980 pBuf += sprintf( pBuf, " " );
982 pBuf += sprintf( pBuf, " " );
983 for(col = 0;count + col < length && col < 16; col++){
984 if (isprint((int)cp[count + col]))
985 pBuf += sprintf( pBuf, "%c", cp[count + col] );
987 pBuf += sprintf( pBuf, "." );
989 sprintf( pBuf, "\n" );
996 } /* close xdump(... */
999 static struct atm_dev *ia_boards = NULL;
1001 #define ACTUAL_RAM_BASE \
1002 RAM_BASE*((iadev->mem)/(128 * 1024))
1003 #define ACTUAL_SEG_RAM_BASE \
1004 IPHASE5575_FRAG_CONTROL_RAM_BASE*((iadev->mem)/(128 * 1024))
1005 #define ACTUAL_REASS_RAM_BASE \
1006 IPHASE5575_REASS_CONTROL_RAM_BASE*((iadev->mem)/(128 * 1024))
1009 /*-- some utilities and memory allocation stuff will come here -------------*/
1011 void desc_dbg(IADEV *iadev) {
1013 u_short tcq_wr_ptr, tcq_st_ptr, tcq_ed_ptr;
1016 // regval = readl((u32)ia_cmds->maddr);
1017 tcq_wr_ptr = readw(iadev->seg_reg+TCQ_WR_PTR);
1018 printk("B_tcq_wr = 0x%x desc = %d last desc = %d\n",
1019 tcq_wr_ptr, readw(iadev->seg_ram+tcq_wr_ptr),
1020 readw(iadev->seg_ram+tcq_wr_ptr-2));
1021 printk(" host_tcq_wr = 0x%x host_tcq_rd = 0x%x \n", iadev->host_tcq_wr,
1023 tcq_st_ptr = readw(iadev->seg_reg+TCQ_ST_ADR);
1024 tcq_ed_ptr = readw(iadev->seg_reg+TCQ_ED_ADR);
1025 printk("tcq_st_ptr = 0x%x tcq_ed_ptr = 0x%x \n", tcq_st_ptr, tcq_ed_ptr);
1027 while (tcq_st_ptr != tcq_ed_ptr) {
1028 tmp = iadev->seg_ram+tcq_st_ptr;
1029 printk("TCQ slot %d desc = %d Addr = %p\n", i++, readw(tmp), tmp);
1032 for(i=0; i <iadev->num_tx_desc; i++)
1033 printk("Desc_tbl[%d] = %d \n", i, iadev->desc_tbl[i].timestamp);
1037 /*----------------------------- Recieving side stuff --------------------------*/
1039 static void rx_excp_rcvd(struct atm_dev *dev)
1041 #if 0 /* closing the receiving size will cause too many excp int */
1044 u_short excpq_rd_ptr;
1047 iadev = INPH_IA_DEV(dev);
1048 state = readl(iadev->reass_reg + STATE_REG) & 0xffff;
1049 while((state & EXCPQ_EMPTY) != EXCPQ_EMPTY)
1050 { printk("state = %x \n", state);
1051 excpq_rd_ptr = readw(iadev->reass_reg + EXCP_Q_RD_PTR) & 0xffff;
1052 printk("state = %x excpq_rd_ptr = %x \n", state, excpq_rd_ptr);
1053 if (excpq_rd_ptr == *(u16*)(iadev->reass_reg + EXCP_Q_WR_PTR))
1054 IF_ERR(printk("excpq_rd_ptr is wrong!!!\n");)
1055 // TODO: update exception stat
1056 vci = readw(iadev->reass_ram+excpq_rd_ptr);
1057 error = readw(iadev->reass_ram+excpq_rd_ptr+2) & 0x0007;
1060 if (excpq_rd_ptr > (readw(iadev->reass_reg + EXCP_Q_ED_ADR)& 0xffff))
1061 excpq_rd_ptr = readw(iadev->reass_reg + EXCP_Q_ST_ADR)& 0xffff;
1062 writew( excpq_rd_ptr, iadev->reass_reg + EXCP_Q_RD_PTR);
1063 state = readl(iadev->reass_reg + STATE_REG) & 0xffff;
1068 static void free_desc(struct atm_dev *dev, int desc)
1071 iadev = INPH_IA_DEV(dev);
1072 writew(desc, iadev->reass_ram+iadev->rfL.fdq_wr);
1073 iadev->rfL.fdq_wr +=2;
1074 if (iadev->rfL.fdq_wr > iadev->rfL.fdq_ed)
1075 iadev->rfL.fdq_wr = iadev->rfL.fdq_st;
1076 writew(iadev->rfL.fdq_wr, iadev->reass_reg+FREEQ_WR_PTR);
1080 static int rx_pkt(struct atm_dev *dev)
1083 struct atm_vcc *vcc;
1084 unsigned short status;
1085 struct rx_buf_desc __iomem *buf_desc_ptr;
1089 struct sk_buff *skb;
1090 u_int buf_addr, dma_addr;
1092 iadev = INPH_IA_DEV(dev);
1093 if (iadev->rfL.pcq_rd == (readw(iadev->reass_reg+PCQ_WR_PTR)&0xffff))
1095 printk(KERN_ERR DEV_LABEL "(itf %d) Receive queue empty\n", dev->number);
1098 /* mask 1st 3 bits to get the actual descno. */
1099 desc = readw(iadev->reass_ram+iadev->rfL.pcq_rd) & 0x1fff;
1100 IF_RX(printk("reass_ram = %p iadev->rfL.pcq_rd = 0x%x desc = %d\n",
1101 iadev->reass_ram, iadev->rfL.pcq_rd, desc);
1102 printk(" pcq_wr_ptr = 0x%x\n",
1103 readw(iadev->reass_reg+PCQ_WR_PTR)&0xffff);)
1104 /* update the read pointer - maybe we shud do this in the end*/
1105 if ( iadev->rfL.pcq_rd== iadev->rfL.pcq_ed)
1106 iadev->rfL.pcq_rd = iadev->rfL.pcq_st;
1108 iadev->rfL.pcq_rd += 2;
1109 writew(iadev->rfL.pcq_rd, iadev->reass_reg+PCQ_RD_PTR);
1111 /* get the buffer desc entry.
1112 update stuff. - doesn't seem to be any update necessary
1114 buf_desc_ptr = iadev->RX_DESC_BASE_ADDR;
1115 /* make the ptr point to the corresponding buffer desc entry */
1116 buf_desc_ptr += desc;
1117 if (!desc || (desc > iadev->num_rx_desc) ||
1118 ((buf_desc_ptr->vc_index & 0xffff) > iadev->num_vc)) {
1119 free_desc(dev, desc);
1120 IF_ERR(printk("IA: bad descriptor desc = %d \n", desc);)
1123 vcc = iadev->rx_open[buf_desc_ptr->vc_index & 0xffff];
1126 free_desc(dev, desc);
1127 printk("IA: null vcc, drop PDU\n");
1132 /* might want to check the status bits for errors */
1133 status = (u_short) (buf_desc_ptr->desc_mode);
1134 if (status & (RX_CER | RX_PTE | RX_OFL))
1136 atomic_inc(&vcc->stats->rx_err);
1137 IF_ERR(printk("IA: bad packet, dropping it");)
1138 if (status & RX_CER) {
1139 IF_ERR(printk(" cause: packet CRC error\n");)
1141 else if (status & RX_PTE) {
1142 IF_ERR(printk(" cause: packet time out\n");)
1145 IF_ERR(printk(" cause: buffer over flow\n");)
1154 buf_addr = (buf_desc_ptr->buf_start_hi << 16) | buf_desc_ptr->buf_start_lo;
1155 dma_addr = (buf_desc_ptr->dma_start_hi << 16) | buf_desc_ptr->dma_start_lo;
1156 len = dma_addr - buf_addr;
1157 if (len > iadev->rx_buf_sz) {
1158 printk("Over %d bytes sdu received, dropped!!!\n", iadev->rx_buf_sz);
1159 atomic_inc(&vcc->stats->rx_err);
1163 if (!(skb = atm_alloc_charge(vcc, len, GFP_ATOMIC))) {
1165 printk("Drop control packets\n");
1170 ATM_SKB(skb)->vcc = vcc;
1171 ATM_DESC(skb) = desc;
1172 skb_queue_tail(&iadev->rx_dma_q, skb);
1174 /* Build the DLE structure */
1175 wr_ptr = iadev->rx_dle_q.write;
1176 wr_ptr->sys_pkt_addr = pci_map_single(iadev->pci, skb->data,
1177 len, PCI_DMA_FROMDEVICE);
1178 wr_ptr->local_pkt_addr = buf_addr;
1179 wr_ptr->bytes = len; /* We don't know this do we ?? */
1180 wr_ptr->mode = DMA_INT_ENABLE;
1182 /* shud take care of wrap around here too. */
1183 if(++wr_ptr == iadev->rx_dle_q.end)
1184 wr_ptr = iadev->rx_dle_q.start;
1185 iadev->rx_dle_q.write = wr_ptr;
1187 /* Increment transaction counter */
1188 writel(1, iadev->dma+IPHASE5575_RX_COUNTER);
1191 free_desc(dev, desc);
1195 static void rx_intr(struct atm_dev *dev)
1201 iadev = INPH_IA_DEV(dev);
1202 status = readl(iadev->reass_reg+REASS_INTR_STATUS_REG) & 0xffff;
1203 IF_EVENT(printk("rx_intr: status = 0x%x\n", status);)
1204 if (status & RX_PKT_RCVD)
1207 /* Basically recvd an interrupt for receving a packet.
1208 A descriptor would have been written to the packet complete
1209 queue. Get all the descriptors and set up dma to move the
1210 packets till the packet complete queue is empty..
1212 state = readl(iadev->reass_reg + STATE_REG) & 0xffff;
1213 IF_EVENT(printk("Rx intr status: RX_PKT_RCVD %08x\n", status);)
1214 while(!(state & PCQ_EMPTY))
1217 state = readl(iadev->reass_reg + STATE_REG) & 0xffff;
1221 if (status & RX_FREEQ_EMPT)
1224 iadev->rx_tmp_cnt = iadev->rx_pkt_cnt;
1225 iadev->rx_tmp_jif = jiffies;
1228 else if (((jiffies - iadev->rx_tmp_jif) > 50) &&
1229 ((iadev->rx_pkt_cnt - iadev->rx_tmp_cnt) == 0)) {
1230 for (i = 1; i <= iadev->num_rx_desc; i++)
1232 printk("Test logic RUN!!!!\n");
1233 writew( ~(RX_FREEQ_EMPT|RX_EXCP_RCVD),iadev->reass_reg+REASS_MASK_REG);
1236 IF_EVENT(printk("Rx intr status: RX_FREEQ_EMPT %08x\n", status);)
1239 if (status & RX_EXCP_RCVD)
1241 /* probably need to handle the exception queue also. */
1242 IF_EVENT(printk("Rx intr status: RX_EXCP_RCVD %08x\n", status);)
1247 if (status & RX_RAW_RCVD)
1249 /* need to handle the raw incoming cells. This deepnds on
1250 whether we have programmed to receive the raw cells or not.
1252 IF_EVENT(printk("Rx intr status: RX_RAW_RCVD %08x\n", status);)
1257 static void rx_dle_intr(struct atm_dev *dev)
1260 struct atm_vcc *vcc;
1261 struct sk_buff *skb;
1264 struct dle *dle, *cur_dle;
1267 iadev = INPH_IA_DEV(dev);
1269 /* free all the dles done, that is just update our own dle read pointer
1270 - do we really need to do this. Think not. */
1271 /* DMA is done, just get all the recevie buffers from the rx dma queue
1272 and push them up to the higher layer protocol. Also free the desc
1273 associated with the buffer. */
1274 dle = iadev->rx_dle_q.read;
1275 dle_lp = readl(iadev->dma+IPHASE5575_RX_LIST_ADDR) & (sizeof(struct dle)*DLE_ENTRIES - 1);
1276 cur_dle = (struct dle*)(iadev->rx_dle_q.start + (dle_lp >> 4));
1277 while(dle != cur_dle)
1279 /* free the DMAed skb */
1280 skb = skb_dequeue(&iadev->rx_dma_q);
1283 desc = ATM_DESC(skb);
1284 free_desc(dev, desc);
1286 if (!(len = skb->len))
1288 printk("rx_dle_intr: skb len 0\n");
1289 dev_kfree_skb_any(skb);
1293 struct cpcs_trailer *trailer;
1295 struct ia_vcc *ia_vcc;
1297 pci_unmap_single(iadev->pci, iadev->rx_dle_q.write->sys_pkt_addr,
1298 len, PCI_DMA_FROMDEVICE);
1299 /* no VCC related housekeeping done as yet. lets see */
1300 vcc = ATM_SKB(skb)->vcc;
1302 printk("IA: null vcc\n");
1303 dev_kfree_skb_any(skb);
1306 ia_vcc = INPH_IA_VCC(vcc);
1309 atomic_inc(&vcc->stats->rx_err);
1310 dev_kfree_skb_any(skb);
1311 atm_return(vcc, atm_guess_pdu2truesize(len));
1314 // get real pkt length pwang_test
1315 trailer = (struct cpcs_trailer*)((u_char *)skb->data +
1316 skb->len - sizeof(*trailer));
1317 length = swap(trailer->length);
1318 if ((length > iadev->rx_buf_sz) || (length >
1319 (skb->len - sizeof(struct cpcs_trailer))))
1321 atomic_inc(&vcc->stats->rx_err);
1322 IF_ERR(printk("rx_dle_intr: Bad AAL5 trailer %d (skb len %d)",
1324 dev_kfree_skb_any(skb);
1325 atm_return(vcc, atm_guess_pdu2truesize(len));
1328 skb_trim(skb, length);
1330 /* Display the packet */
1331 IF_RXPKT(printk("\nDmad Recvd data: len = %d \n", skb->len);
1332 xdump(skb->data, skb->len, "RX: ");
1335 IF_RX(printk("rx_dle_intr: skb push");)
1337 atomic_inc(&vcc->stats->rx);
1338 iadev->rx_pkt_cnt++;
1341 if (++dle == iadev->rx_dle_q.end)
1342 dle = iadev->rx_dle_q.start;
1344 iadev->rx_dle_q.read = dle;
1346 /* if the interrupts are masked because there were no free desc available,
1348 if (!iadev->rxing) {
1349 state = readl(iadev->reass_reg + STATE_REG) & 0xffff;
1350 if (!(state & FREEQ_EMPTY)) {
1351 state = readl(iadev->reass_reg + REASS_MASK_REG) & 0xffff;
1352 writel(state & ~(RX_FREEQ_EMPT |/* RX_EXCP_RCVD |*/ RX_PKT_RCVD),
1353 iadev->reass_reg+REASS_MASK_REG);
1360 static int open_rx(struct atm_vcc *vcc)
1363 u_short __iomem *vc_table;
1364 u_short __iomem *reass_ptr;
1365 IF_EVENT(printk("iadev: open_rx %d.%d\n", vcc->vpi, vcc->vci);)
1367 if (vcc->qos.rxtp.traffic_class == ATM_NONE) return 0;
1368 iadev = INPH_IA_DEV(vcc->dev);
1369 if (vcc->qos.rxtp.traffic_class == ATM_ABR) {
1370 if (iadev->phy_type & FE_25MBIT_PHY) {
1371 printk("IA: ABR not support\n");
1375 /* Make only this VCI in the vc table valid and let all
1376 others be invalid entries */
1377 vc_table = iadev->reass_ram+RX_VC_TABLE*iadev->memSize;
1378 vc_table += vcc->vci;
1379 /* mask the last 6 bits and OR it with 3 for 1K VCs */
1381 *vc_table = vcc->vci << 6;
1382 /* Also keep a list of open rx vcs so that we can attach them with
1383 incoming PDUs later. */
1384 if ((vcc->qos.rxtp.traffic_class == ATM_ABR) ||
1385 (vcc->qos.txtp.traffic_class == ATM_ABR))
1387 srv_cls_param_t srv_p;
1388 init_abr_vc(iadev, &srv_p);
1389 ia_open_abr_vc(iadev, &srv_p, vcc, 0);
1391 else { /* for UBR later may need to add CBR logic */
1392 reass_ptr = iadev->reass_ram+REASS_TABLE*iadev->memSize;
1393 reass_ptr += vcc->vci;
1394 *reass_ptr = NO_AAL5_PKT;
1397 if (iadev->rx_open[vcc->vci])
1398 printk(KERN_CRIT DEV_LABEL "(itf %d): VCI %d already open\n",
1399 vcc->dev->number, vcc->vci);
1400 iadev->rx_open[vcc->vci] = vcc;
1404 static int rx_init(struct atm_dev *dev)
1407 struct rx_buf_desc __iomem *buf_desc_ptr;
1408 unsigned long rx_pkt_start = 0;
1410 struct abr_vc_table *abr_vc_table;
1414 int i,j, vcsize_sel;
1415 u_short freeq_st_adr;
1416 u_short *freeq_start;
1418 iadev = INPH_IA_DEV(dev);
1419 // spin_lock_init(&iadev->rx_lock);
1421 /* Allocate 4k bytes - more aligned than needed (4k boundary) */
1422 dle_addr = pci_alloc_consistent(iadev->pci, DLE_TOTAL_SIZE,
1423 &iadev->rx_dle_dma);
1425 printk(KERN_ERR DEV_LABEL "can't allocate DLEs\n");
1428 iadev->rx_dle_q.start = (struct dle*)dle_addr;
1429 iadev->rx_dle_q.read = iadev->rx_dle_q.start;
1430 iadev->rx_dle_q.write = iadev->rx_dle_q.start;
1431 iadev->rx_dle_q.end = (struct dle*)((u32)dle_addr+sizeof(struct dle)*DLE_ENTRIES);
1432 /* the end of the dle q points to the entry after the last
1433 DLE that can be used. */
1435 /* write the upper 20 bits of the start address to rx list address register */
1436 writel(iadev->rx_dle_dma & 0xfffff000,
1437 iadev->dma + IPHASE5575_RX_LIST_ADDR);
1438 IF_INIT(printk("Tx Dle list addr: 0x%08x value: 0x%0x\n",
1439 (u32)(iadev->dma+IPHASE5575_TX_LIST_ADDR),
1440 *(u32*)(iadev->dma+IPHASE5575_TX_LIST_ADDR));
1441 printk("Rx Dle list addr: 0x%08x value: 0x%0x\n",
1442 (u32)(iadev->dma+IPHASE5575_RX_LIST_ADDR),
1443 *(u32*)(iadev->dma+IPHASE5575_RX_LIST_ADDR));)
1445 writew(0xffff, iadev->reass_reg+REASS_MASK_REG);
1446 writew(0, iadev->reass_reg+MODE_REG);
1447 writew(RESET_REASS, iadev->reass_reg+REASS_COMMAND_REG);
1449 /* Receive side control memory map
1450 -------------------------------
1452 Buffer descr 0x0000 (736 - 23K)
1453 VP Table 0x5c00 (256 - 512)
1454 Except q 0x5e00 (128 - 512)
1455 Free buffer q 0x6000 (1K - 2K)
1456 Packet comp q 0x6800 (1K - 2K)
1457 Reass Table 0x7000 (1K - 2K)
1458 VC Table 0x7800 (1K - 2K)
1459 ABR VC Table 0x8000 (1K - 32K)
1462 /* Base address for Buffer Descriptor Table */
1463 writew(RX_DESC_BASE >> 16, iadev->reass_reg+REASS_DESC_BASE);
1464 /* Set the buffer size register */
1465 writew(iadev->rx_buf_sz, iadev->reass_reg+BUF_SIZE);
1467 /* Initialize each entry in the Buffer Descriptor Table */
1468 iadev->RX_DESC_BASE_ADDR = iadev->reass_ram+RX_DESC_BASE*iadev->memSize;
1469 buf_desc_ptr = iadev->RX_DESC_BASE_ADDR;
1470 memset_io(buf_desc_ptr, 0, sizeof(*buf_desc_ptr));
1472 rx_pkt_start = iadev->rx_pkt_ram;
1473 for(i=1; i<=iadev->num_rx_desc; i++)
1475 memset_io(buf_desc_ptr, 0, sizeof(*buf_desc_ptr));
1476 buf_desc_ptr->buf_start_hi = rx_pkt_start >> 16;
1477 buf_desc_ptr->buf_start_lo = rx_pkt_start & 0x0000ffff;
1479 rx_pkt_start += iadev->rx_buf_sz;
1481 IF_INIT(printk("Rx Buffer desc ptr: 0x%0x\n", (u32)(buf_desc_ptr));)
1482 i = FREE_BUF_DESC_Q*iadev->memSize;
1483 writew(i >> 16, iadev->reass_reg+REASS_QUEUE_BASE);
1484 writew(i, iadev->reass_reg+FREEQ_ST_ADR);
1485 writew(i+iadev->num_rx_desc*sizeof(u_short),
1486 iadev->reass_reg+FREEQ_ED_ADR);
1487 writew(i, iadev->reass_reg+FREEQ_RD_PTR);
1488 writew(i+iadev->num_rx_desc*sizeof(u_short),
1489 iadev->reass_reg+FREEQ_WR_PTR);
1490 /* Fill the FREEQ with all the free descriptors. */
1491 freeq_st_adr = readw(iadev->reass_reg+FREEQ_ST_ADR);
1492 freeq_start = (u_short *)(iadev->reass_ram+freeq_st_adr);
1493 for(i=1; i<=iadev->num_rx_desc; i++)
1495 *freeq_start = (u_short)i;
1498 IF_INIT(printk("freeq_start: 0x%0x\n", (u32)freeq_start);)
1499 /* Packet Complete Queue */
1500 i = (PKT_COMP_Q * iadev->memSize) & 0xffff;
1501 writew(i, iadev->reass_reg+PCQ_ST_ADR);
1502 writew(i+iadev->num_vc*sizeof(u_short), iadev->reass_reg+PCQ_ED_ADR);
1503 writew(i, iadev->reass_reg+PCQ_RD_PTR);
1504 writew(i, iadev->reass_reg+PCQ_WR_PTR);
1506 /* Exception Queue */
1507 i = (EXCEPTION_Q * iadev->memSize) & 0xffff;
1508 writew(i, iadev->reass_reg+EXCP_Q_ST_ADR);
1509 writew(i + NUM_RX_EXCP * sizeof(RX_ERROR_Q),
1510 iadev->reass_reg+EXCP_Q_ED_ADR);
1511 writew(i, iadev->reass_reg+EXCP_Q_RD_PTR);
1512 writew(i, iadev->reass_reg+EXCP_Q_WR_PTR);
1514 /* Load local copy of FREEQ and PCQ ptrs */
1515 iadev->rfL.fdq_st = readw(iadev->reass_reg+FREEQ_ST_ADR) & 0xffff;
1516 iadev->rfL.fdq_ed = readw(iadev->reass_reg+FREEQ_ED_ADR) & 0xffff ;
1517 iadev->rfL.fdq_rd = readw(iadev->reass_reg+FREEQ_RD_PTR) & 0xffff;
1518 iadev->rfL.fdq_wr = readw(iadev->reass_reg+FREEQ_WR_PTR) & 0xffff;
1519 iadev->rfL.pcq_st = readw(iadev->reass_reg+PCQ_ST_ADR) & 0xffff;
1520 iadev->rfL.pcq_ed = readw(iadev->reass_reg+PCQ_ED_ADR) & 0xffff;
1521 iadev->rfL.pcq_rd = readw(iadev->reass_reg+PCQ_RD_PTR) & 0xffff;
1522 iadev->rfL.pcq_wr = readw(iadev->reass_reg+PCQ_WR_PTR) & 0xffff;
1524 IF_INIT(printk("INIT:pcq_st:0x%x pcq_ed:0x%x pcq_rd:0x%x pcq_wr:0x%x",
1525 iadev->rfL.pcq_st, iadev->rfL.pcq_ed, iadev->rfL.pcq_rd,
1526 iadev->rfL.pcq_wr);)
1527 /* just for check - no VP TBL */
1529 /* writew(0x0b80, iadev->reass_reg+VP_LKUP_BASE); */
1530 /* initialize VP Table for invalid VPIs
1531 - I guess we can write all 1s or 0x000f in the entire memory
1532 space or something similar.
1535 /* This seems to work and looks right to me too !!! */
1536 i = REASS_TABLE * iadev->memSize;
1537 writew((i >> 3), iadev->reass_reg+REASS_TABLE_BASE);
1538 /* initialize Reassembly table to I don't know what ???? */
1539 reass_table = (u16 *)(iadev->reass_ram+i);
1540 j = REASS_TABLE_SZ * iadev->memSize;
1541 for(i=0; i < j; i++)
1542 *reass_table++ = NO_AAL5_PKT;
1545 while (i != iadev->num_vc) {
1549 i = RX_VC_TABLE * iadev->memSize;
1550 writew(((i>>3) & 0xfff8) | vcsize_sel, iadev->reass_reg+VC_LKUP_BASE);
1551 vc_table = (u16 *)(iadev->reass_ram+RX_VC_TABLE*iadev->memSize);
1552 j = RX_VC_TABLE_SZ * iadev->memSize;
1553 for(i = 0; i < j; i++)
1555 /* shift the reassembly pointer by 3 + lower 3 bits of
1556 vc_lkup_base register (=3 for 1K VCs) and the last byte
1557 is those low 3 bits.
1558 Shall program this later.
1560 *vc_table = (i << 6) | 15; /* for invalid VCI */
1564 i = ABR_VC_TABLE * iadev->memSize;
1565 writew(i >> 3, iadev->reass_reg+ABR_LKUP_BASE);
1567 i = ABR_VC_TABLE * iadev->memSize;
1568 abr_vc_table = (struct abr_vc_table *)(iadev->reass_ram+i);
1569 j = REASS_TABLE_SZ * iadev->memSize;
1570 memset ((char*)abr_vc_table, 0, j * sizeof(*abr_vc_table));
1571 for(i = 0; i < j; i++) {
1572 abr_vc_table->rdf = 0x0003;
1573 abr_vc_table->air = 0x5eb1;
1577 /* Initialize other registers */
1579 /* VP Filter Register set for VC Reassembly only */
1580 writew(0xff00, iadev->reass_reg+VP_FILTER);
1581 writew(0, iadev->reass_reg+XTRA_RM_OFFSET);
1582 writew(0x1, iadev->reass_reg+PROTOCOL_ID);
1584 /* Packet Timeout Count related Registers :
1585 Set packet timeout to occur in about 3 seconds
1586 Set Packet Aging Interval count register to overflow in about 4 us
1588 writew(0xF6F8, iadev->reass_reg+PKT_TM_CNT );
1590 i = ((u32)ptr16 >> 6) & 0xff;
1592 i |=(((u32)ptr16 << 2) & 0xff00);
1593 writew(i, iadev->reass_reg+TMOUT_RANGE);
1594 /* initiate the desc_tble */
1595 for(i=0; i<iadev->num_tx_desc;i++)
1596 iadev->desc_tbl[i].timestamp = 0;
1598 /* to clear the interrupt status register - read it */
1599 readw(iadev->reass_reg+REASS_INTR_STATUS_REG);
1601 /* Mask Register - clear it */
1602 writew(~(RX_FREEQ_EMPT|RX_PKT_RCVD), iadev->reass_reg+REASS_MASK_REG);
1604 skb_queue_head_init(&iadev->rx_dma_q);
1605 iadev->rx_free_desc_qhead = NULL;
1606 iadev->rx_open = kmalloc(4*iadev->num_vc,GFP_KERNEL);
1607 if (!iadev->rx_open)
1609 printk(KERN_ERR DEV_LABEL "itf %d couldn't get free page\n",
1613 memset(iadev->rx_open, 0, 4*iadev->num_vc);
1615 iadev->rx_pkt_cnt = 0;
1617 writew(R_ONLINE, iadev->reass_reg+MODE_REG);
1621 pci_free_consistent(iadev->pci, DLE_TOTAL_SIZE, iadev->rx_dle_q.start,
1629 The memory map suggested in appendix A and the coding for it.
1630 Keeping it around just in case we change our mind later.
1632 Buffer descr 0x0000 (128 - 4K)
1633 UBR sched 0x1000 (1K - 4K)
1634 UBR Wait q 0x2000 (1K - 4K)
1635 Commn queues 0x3000 Packet Ready, Trasmit comp(0x3100)
1637 extended VC 0x4000 (1K - 8K)
1638 ABR sched 0x6000 and ABR wait queue (1K - 2K) each
1639 CBR sched 0x7000 (as needed)
1640 VC table 0x8000 (1K - 32K)
1643 static void tx_intr(struct atm_dev *dev)
1646 unsigned short status;
1647 unsigned long flags;
1649 iadev = INPH_IA_DEV(dev);
1651 status = readl(iadev->seg_reg+SEG_INTR_STATUS_REG);
1652 if (status & TRANSMIT_DONE){
1654 IF_EVENT(printk("Tansmit Done Intr logic run\n");)
1655 spin_lock_irqsave(&iadev->tx_lock, flags);
1657 spin_unlock_irqrestore(&iadev->tx_lock, flags);
1658 writew(TRANSMIT_DONE, iadev->seg_reg+SEG_INTR_STATUS_REG);
1659 if (iadev->close_pending)
1660 wake_up(&iadev->close_wait);
1662 if (status & TCQ_NOT_EMPTY)
1664 IF_EVENT(printk("TCQ_NOT_EMPTY int received\n");)
1668 static void tx_dle_intr(struct atm_dev *dev)
1671 struct dle *dle, *cur_dle;
1672 struct sk_buff *skb;
1673 struct atm_vcc *vcc;
1674 struct ia_vcc *iavcc;
1676 unsigned long flags;
1678 iadev = INPH_IA_DEV(dev);
1679 spin_lock_irqsave(&iadev->tx_lock, flags);
1680 dle = iadev->tx_dle_q.read;
1681 dle_lp = readl(iadev->dma+IPHASE5575_TX_LIST_ADDR) &
1682 (sizeof(struct dle)*DLE_ENTRIES - 1);
1683 cur_dle = (struct dle*)(iadev->tx_dle_q.start + (dle_lp >> 4));
1684 while (dle != cur_dle)
1686 /* free the DMAed skb */
1687 skb = skb_dequeue(&iadev->tx_dma_q);
1690 /* Revenge of the 2 dle (skb + trailer) used in ia_pkt_tx() */
1691 if (!((dle - iadev->tx_dle_q.start)%(2*sizeof(struct dle)))) {
1692 pci_unmap_single(iadev->pci, dle->sys_pkt_addr, skb->len,
1695 vcc = ATM_SKB(skb)->vcc;
1697 printk("tx_dle_intr: vcc is null\n");
1698 spin_unlock_irqrestore(&iadev->tx_lock, flags);
1699 dev_kfree_skb_any(skb);
1703 iavcc = INPH_IA_VCC(vcc);
1705 printk("tx_dle_intr: iavcc is null\n");
1706 spin_unlock_irqrestore(&iadev->tx_lock, flags);
1707 dev_kfree_skb_any(skb);
1710 if (vcc->qos.txtp.pcr >= iadev->rate_limit) {
1711 if ((vcc->pop) && (skb->len != 0))
1716 dev_kfree_skb_any(skb);
1719 else { /* Hold the rate-limited skb for flow control */
1720 IA_SKB_STATE(skb) |= IA_DLED;
1721 skb_queue_tail(&iavcc->txing_skb, skb);
1723 IF_EVENT(printk("tx_dle_intr: enque skb = 0x%x \n", (u32)skb);)
1724 if (++dle == iadev->tx_dle_q.end)
1725 dle = iadev->tx_dle_q.start;
1727 iadev->tx_dle_q.read = dle;
1728 spin_unlock_irqrestore(&iadev->tx_lock, flags);
1731 static int open_tx(struct atm_vcc *vcc)
1733 struct ia_vcc *ia_vcc;
1738 IF_EVENT(printk("iadev: open_tx entered vcc->vci = %d\n", vcc->vci);)
1739 if (vcc->qos.txtp.traffic_class == ATM_NONE) return 0;
1740 iadev = INPH_IA_DEV(vcc->dev);
1742 if (iadev->phy_type & FE_25MBIT_PHY) {
1743 if (vcc->qos.txtp.traffic_class == ATM_ABR) {
1744 printk("IA: ABR not support\n");
1747 if (vcc->qos.txtp.traffic_class == ATM_CBR) {
1748 printk("IA: CBR not support\n");
1752 ia_vcc = INPH_IA_VCC(vcc);
1753 memset((caddr_t)ia_vcc, 0, sizeof(*ia_vcc));
1754 if (vcc->qos.txtp.max_sdu >
1755 (iadev->tx_buf_sz - sizeof(struct cpcs_trailer))){
1756 printk("IA: SDU size over (%d) the configured SDU size %d\n",
1757 vcc->qos.txtp.max_sdu,iadev->tx_buf_sz);
1758 vcc->dev_data = NULL;
1762 ia_vcc->vc_desc_cnt = 0;
1766 if (vcc->qos.txtp.max_pcr == ATM_MAX_PCR)
1767 vcc->qos.txtp.pcr = iadev->LineRate;
1768 else if ((vcc->qos.txtp.max_pcr == 0)&&( vcc->qos.txtp.pcr <= 0))
1769 vcc->qos.txtp.pcr = iadev->LineRate;
1770 else if ((vcc->qos.txtp.max_pcr > vcc->qos.txtp.pcr) && (vcc->qos.txtp.max_pcr> 0))
1771 vcc->qos.txtp.pcr = vcc->qos.txtp.max_pcr;
1772 if (vcc->qos.txtp.pcr > iadev->LineRate)
1773 vcc->qos.txtp.pcr = iadev->LineRate;
1774 ia_vcc->pcr = vcc->qos.txtp.pcr;
1776 if (ia_vcc->pcr > (iadev->LineRate / 6) ) ia_vcc->ltimeout = HZ / 10;
1777 else if (ia_vcc->pcr > (iadev->LineRate / 130)) ia_vcc->ltimeout = HZ;
1778 else if (ia_vcc->pcr <= 170) ia_vcc->ltimeout = 16 * HZ;
1779 else ia_vcc->ltimeout = 2700 * HZ / ia_vcc->pcr;
1780 if (ia_vcc->pcr < iadev->rate_limit)
1781 skb_queue_head_init (&ia_vcc->txing_skb);
1782 if (ia_vcc->pcr < iadev->rate_limit) {
1783 if (vcc->qos.txtp.max_sdu != 0) {
1784 if (ia_vcc->pcr > 60000)
1785 vcc->sk->sk_sndbuf = vcc->qos.txtp.max_sdu * 5;
1786 else if (ia_vcc->pcr > 2000)
1787 vcc->sk->sk_sndbuf = vcc->qos.txtp.max_sdu * 4;
1789 vcc->sk->sk_sndbuf = vcc->qos.txtp.max_sdu * 3;
1792 vcc->sk->sk_sndbuf = 24576;
1795 vc = (struct main_vc *)iadev->MAIN_VC_TABLE_ADDR;
1796 evc = (struct ext_vc *)iadev->EXT_VC_TABLE_ADDR;
1799 memset((caddr_t)vc, 0, sizeof(*vc));
1800 memset((caddr_t)evc, 0, sizeof(*evc));
1802 /* store the most significant 4 bits of vci as the last 4 bits
1803 of first part of atm header.
1804 store the last 12 bits of vci as first 12 bits of the second
1805 part of the atm header.
1807 evc->atm_hdr1 = (vcc->vci >> 12) & 0x000f;
1808 evc->atm_hdr2 = (vcc->vci & 0x0fff) << 4;
1810 /* check the following for different traffic classes */
1811 if (vcc->qos.txtp.traffic_class == ATM_UBR)
1814 vc->status = CRC_APPEND;
1815 vc->acr = cellrate_to_float(iadev->LineRate);
1816 if (vcc->qos.txtp.pcr > 0)
1817 vc->acr = cellrate_to_float(vcc->qos.txtp.pcr);
1818 IF_UBR(printk("UBR: txtp.pcr = 0x%x f_rate = 0x%x\n",
1819 vcc->qos.txtp.max_pcr,vc->acr);)
1821 else if (vcc->qos.txtp.traffic_class == ATM_ABR)
1822 { srv_cls_param_t srv_p;
1823 IF_ABR(printk("Tx ABR VCC\n");)
1824 init_abr_vc(iadev, &srv_p);
1825 if (vcc->qos.txtp.pcr > 0)
1826 srv_p.pcr = vcc->qos.txtp.pcr;
1827 if (vcc->qos.txtp.min_pcr > 0) {
1828 int tmpsum = iadev->sum_mcr+iadev->sum_cbr+vcc->qos.txtp.min_pcr;
1829 if (tmpsum > iadev->LineRate)
1831 srv_p.mcr = vcc->qos.txtp.min_pcr;
1832 iadev->sum_mcr += vcc->qos.txtp.min_pcr;
1835 if (vcc->qos.txtp.icr)
1836 srv_p.icr = vcc->qos.txtp.icr;
1837 if (vcc->qos.txtp.tbe)
1838 srv_p.tbe = vcc->qos.txtp.tbe;
1839 if (vcc->qos.txtp.frtt)
1840 srv_p.frtt = vcc->qos.txtp.frtt;
1841 if (vcc->qos.txtp.rif)
1842 srv_p.rif = vcc->qos.txtp.rif;
1843 if (vcc->qos.txtp.rdf)
1844 srv_p.rdf = vcc->qos.txtp.rdf;
1845 if (vcc->qos.txtp.nrm_pres)
1846 srv_p.nrm = vcc->qos.txtp.nrm;
1847 if (vcc->qos.txtp.trm_pres)
1848 srv_p.trm = vcc->qos.txtp.trm;
1849 if (vcc->qos.txtp.adtf_pres)
1850 srv_p.adtf = vcc->qos.txtp.adtf;
1851 if (vcc->qos.txtp.cdf_pres)
1852 srv_p.cdf = vcc->qos.txtp.cdf;
1853 if (srv_p.icr > srv_p.pcr)
1854 srv_p.icr = srv_p.pcr;
1855 IF_ABR(printk("ABR:vcc->qos.txtp.max_pcr = %d mcr = %d\n",
1856 srv_p.pcr, srv_p.mcr);)
1857 ia_open_abr_vc(iadev, &srv_p, vcc, 1);
1858 } else if (vcc->qos.txtp.traffic_class == ATM_CBR) {
1859 if (iadev->phy_type & FE_25MBIT_PHY) {
1860 printk("IA: CBR not support\n");
1863 if (vcc->qos.txtp.max_pcr > iadev->LineRate) {
1864 IF_CBR(printk("PCR is not availble\n");)
1868 vc->status = CRC_APPEND;
1869 if ((ret = ia_cbr_setup (iadev, vcc)) < 0) {
1874 printk("iadev: Non UBR, ABR and CBR traffic not supportedn");
1876 iadev->testTable[vcc->vci]->vc_status |= VC_ACTIVE;
1877 IF_EVENT(printk("ia open_tx returning \n");)
1882 static int tx_init(struct atm_dev *dev)
1885 struct tx_buf_desc *buf_desc_ptr;
1886 unsigned int tx_pkt_start;
1898 iadev = INPH_IA_DEV(dev);
1899 spin_lock_init(&iadev->tx_lock);
1901 IF_INIT(printk("Tx MASK REG: 0x%0x\n",
1902 readw(iadev->seg_reg+SEG_MASK_REG));)
1904 /* Allocate 4k (boundary aligned) bytes */
1905 dle_addr = pci_alloc_consistent(iadev->pci, DLE_TOTAL_SIZE,
1906 &iadev->tx_dle_dma);
1908 printk(KERN_ERR DEV_LABEL "can't allocate DLEs\n");
1911 iadev->tx_dle_q.start = (struct dle*)dle_addr;
1912 iadev->tx_dle_q.read = iadev->tx_dle_q.start;
1913 iadev->tx_dle_q.write = iadev->tx_dle_q.start;
1914 iadev->tx_dle_q.end = (struct dle*)((u32)dle_addr+sizeof(struct dle)*DLE_ENTRIES);
1916 /* write the upper 20 bits of the start address to tx list address register */
1917 writel(iadev->tx_dle_dma & 0xfffff000,
1918 iadev->dma + IPHASE5575_TX_LIST_ADDR);
1919 writew(0xffff, iadev->seg_reg+SEG_MASK_REG);
1920 writew(0, iadev->seg_reg+MODE_REG_0);
1921 writew(RESET_SEG, iadev->seg_reg+SEG_COMMAND_REG);
1922 iadev->MAIN_VC_TABLE_ADDR = iadev->seg_ram+MAIN_VC_TABLE*iadev->memSize;
1923 iadev->EXT_VC_TABLE_ADDR = iadev->seg_ram+EXT_VC_TABLE*iadev->memSize;
1924 iadev->ABR_SCHED_TABLE_ADDR=iadev->seg_ram+ABR_SCHED_TABLE*iadev->memSize;
1927 Transmit side control memory map
1928 --------------------------------
1929 Buffer descr 0x0000 (128 - 4K)
1930 Commn queues 0x1000 Transmit comp, Packet ready(0x1400)
1933 CBR Table 0x1800 (as needed) - 6K
1934 UBR Table 0x3000 (1K - 4K) - 12K
1935 UBR Wait queue 0x4000 (1K - 4K) - 16K
1936 ABR sched 0x5000 and ABR wait queue (1K - 2K) each
1937 ABR Tbl - 20K, ABR Wq - 22K
1938 extended VC 0x6000 (1K - 8K) - 24K
1939 VC Table 0x8000 (1K - 32K) - 32K
1941 Between 0x2000 (8K) and 0x3000 (12K) there is 4K space left for VBR Tbl
1942 and Wait q, which can be allotted later.
1945 /* Buffer Descriptor Table Base address */
1946 writew(TX_DESC_BASE, iadev->seg_reg+SEG_DESC_BASE);
1948 /* initialize each entry in the buffer descriptor table */
1949 buf_desc_ptr =(struct tx_buf_desc *)(iadev->seg_ram+TX_DESC_BASE);
1950 memset((caddr_t)buf_desc_ptr, 0, sizeof(*buf_desc_ptr));
1952 tx_pkt_start = TX_PACKET_RAM;
1953 for(i=1; i<=iadev->num_tx_desc; i++)
1955 memset((caddr_t)buf_desc_ptr, 0, sizeof(*buf_desc_ptr));
1956 buf_desc_ptr->desc_mode = AAL5;
1957 buf_desc_ptr->buf_start_hi = tx_pkt_start >> 16;
1958 buf_desc_ptr->buf_start_lo = tx_pkt_start & 0x0000ffff;
1960 tx_pkt_start += iadev->tx_buf_sz;
1962 iadev->tx_buf = kmalloc(iadev->num_tx_desc*sizeof(struct cpcs_trailer_desc), GFP_KERNEL);
1963 if (!iadev->tx_buf) {
1964 printk(KERN_ERR DEV_LABEL " couldn't get mem\n");
1967 for (i= 0; i< iadev->num_tx_desc; i++)
1969 struct cpcs_trailer *cpcs;
1971 cpcs = kmalloc(sizeof(*cpcs), GFP_KERNEL|GFP_DMA);
1973 printk(KERN_ERR DEV_LABEL " couldn't get freepage\n");
1974 goto err_free_tx_bufs;
1976 iadev->tx_buf[i].cpcs = cpcs;
1977 iadev->tx_buf[i].dma_addr = pci_map_single(iadev->pci,
1978 cpcs, sizeof(*cpcs), PCI_DMA_TODEVICE);
1980 iadev->desc_tbl = kmalloc(iadev->num_tx_desc *
1981 sizeof(struct desc_tbl_t), GFP_KERNEL);
1982 if (!iadev->desc_tbl) {
1983 printk(KERN_ERR DEV_LABEL " couldn't get mem\n");
1984 goto err_free_all_tx_bufs;
1987 /* Communication Queues base address */
1988 i = TX_COMP_Q * iadev->memSize;
1989 writew(i >> 16, iadev->seg_reg+SEG_QUEUE_BASE);
1991 /* Transmit Complete Queue */
1992 writew(i, iadev->seg_reg+TCQ_ST_ADR);
1993 writew(i, iadev->seg_reg+TCQ_RD_PTR);
1994 writew(i+iadev->num_tx_desc*sizeof(u_short),iadev->seg_reg+TCQ_WR_PTR);
1995 iadev->host_tcq_wr = i + iadev->num_tx_desc*sizeof(u_short);
1996 writew(i+2 * iadev->num_tx_desc * sizeof(u_short),
1997 iadev->seg_reg+TCQ_ED_ADR);
1998 /* Fill the TCQ with all the free descriptors. */
1999 tcq_st_adr = readw(iadev->seg_reg+TCQ_ST_ADR);
2000 tcq_start = (u_short *)(iadev->seg_ram+tcq_st_adr);
2001 for(i=1; i<=iadev->num_tx_desc; i++)
2003 *tcq_start = (u_short)i;
2007 /* Packet Ready Queue */
2008 i = PKT_RDY_Q * iadev->memSize;
2009 writew(i, iadev->seg_reg+PRQ_ST_ADR);
2010 writew(i+2 * iadev->num_tx_desc * sizeof(u_short),
2011 iadev->seg_reg+PRQ_ED_ADR);
2012 writew(i, iadev->seg_reg+PRQ_RD_PTR);
2013 writew(i, iadev->seg_reg+PRQ_WR_PTR);
2015 /* Load local copy of PRQ and TCQ ptrs */
2016 iadev->ffL.prq_st = readw(iadev->seg_reg+PRQ_ST_ADR) & 0xffff;
2017 iadev->ffL.prq_ed = readw(iadev->seg_reg+PRQ_ED_ADR) & 0xffff;
2018 iadev->ffL.prq_wr = readw(iadev->seg_reg+PRQ_WR_PTR) & 0xffff;
2020 iadev->ffL.tcq_st = readw(iadev->seg_reg+TCQ_ST_ADR) & 0xffff;
2021 iadev->ffL.tcq_ed = readw(iadev->seg_reg+TCQ_ED_ADR) & 0xffff;
2022 iadev->ffL.tcq_rd = readw(iadev->seg_reg+TCQ_RD_PTR) & 0xffff;
2024 /* Just for safety initializing the queue to have desc 1 always */
2025 /* Fill the PRQ with all the free descriptors. */
2026 prq_st_adr = readw(iadev->seg_reg+PRQ_ST_ADR);
2027 prq_start = (u_short *)(iadev->seg_ram+prq_st_adr);
2028 for(i=1; i<=iadev->num_tx_desc; i++)
2030 *prq_start = (u_short)0; /* desc 1 in all entries */
2034 IF_INIT(printk("Start CBR Init\n");)
2035 #if 1 /* for 1K VC board, CBR_PTR_BASE is 0 */
2036 writew(0,iadev->seg_reg+CBR_PTR_BASE);
2037 #else /* Charlie's logic is wrong ? */
2038 tmp16 = (iadev->seg_ram+CBR_SCHED_TABLE*iadev->memSize)>>17;
2039 IF_INIT(printk("cbr_ptr_base = 0x%x ", tmp16);)
2040 writew(tmp16,iadev->seg_reg+CBR_PTR_BASE);
2043 IF_INIT(printk("value in register = 0x%x\n",
2044 readw(iadev->seg_reg+CBR_PTR_BASE));)
2045 tmp16 = (CBR_SCHED_TABLE*iadev->memSize) >> 1;
2046 writew(tmp16, iadev->seg_reg+CBR_TAB_BEG);
2047 IF_INIT(printk("cbr_tab_beg = 0x%x in reg = 0x%x \n", tmp16,
2048 readw(iadev->seg_reg+CBR_TAB_BEG));)
2049 writew(tmp16, iadev->seg_reg+CBR_TAB_END+1); // CBR_PTR;
2050 tmp16 = (CBR_SCHED_TABLE*iadev->memSize + iadev->num_vc*6 - 2) >> 1;
2051 writew(tmp16, iadev->seg_reg+CBR_TAB_END);
2052 IF_INIT(printk("iadev->seg_reg = 0x%x CBR_PTR_BASE = 0x%x\n",
2053 (u32)iadev->seg_reg, readw(iadev->seg_reg+CBR_PTR_BASE));)
2054 IF_INIT(printk("CBR_TAB_BEG = 0x%x, CBR_TAB_END = 0x%x, CBR_PTR = 0x%x\n",
2055 readw(iadev->seg_reg+CBR_TAB_BEG), readw(iadev->seg_reg+CBR_TAB_END),
2056 readw(iadev->seg_reg+CBR_TAB_END+1));)
2058 /* Initialize the CBR Schedualing Table */
2059 memset_io(iadev->seg_ram+CBR_SCHED_TABLE*iadev->memSize,
2060 0, iadev->num_vc*6);
2061 iadev->CbrRemEntries = iadev->CbrTotEntries = iadev->num_vc*3;
2062 iadev->CbrEntryPt = 0;
2063 iadev->Granularity = MAX_ATM_155 / iadev->CbrTotEntries;
2064 iadev->NumEnabledCBR = 0;
2066 /* UBR scheduling Table and wait queue */
2067 /* initialize all bytes of UBR scheduler table and wait queue to 0
2068 - SCHEDSZ is 1K (# of entries).
2069 - UBR Table size is 4K
2070 - UBR wait queue is 4K
2071 since the table and wait queues are contiguous, all the bytes
2072 can be initialized by one memeset.
2077 while (i != iadev->num_vc) {
2082 i = MAIN_VC_TABLE * iadev->memSize;
2083 writew(vcsize_sel | ((i >> 8) & 0xfff8),iadev->seg_reg+VCT_BASE);
2084 i = EXT_VC_TABLE * iadev->memSize;
2085 writew((i >> 8) & 0xfffe, iadev->seg_reg+VCTE_BASE);
2086 i = UBR_SCHED_TABLE * iadev->memSize;
2087 writew((i & 0xffff) >> 11, iadev->seg_reg+UBR_SBPTR_BASE);
2088 i = UBR_WAIT_Q * iadev->memSize;
2089 writew((i >> 7) & 0xffff, iadev->seg_reg+UBRWQ_BASE);
2090 memset((caddr_t)(iadev->seg_ram+UBR_SCHED_TABLE*iadev->memSize),
2091 0, iadev->num_vc*8);
2092 /* ABR scheduling Table(0x5000-0x57ff) and wait queue(0x5800-0x5fff)*/
2093 /* initialize all bytes of ABR scheduler table and wait queue to 0
2094 - SCHEDSZ is 1K (# of entries).
2095 - ABR Table size is 2K
2096 - ABR wait queue is 2K
2097 since the table and wait queues are contiguous, all the bytes
2098 can be intialized by one memeset.
2100 i = ABR_SCHED_TABLE * iadev->memSize;
2101 writew((i >> 11) & 0xffff, iadev->seg_reg+ABR_SBPTR_BASE);
2102 i = ABR_WAIT_Q * iadev->memSize;
2103 writew((i >> 7) & 0xffff, iadev->seg_reg+ABRWQ_BASE);
2105 i = ABR_SCHED_TABLE*iadev->memSize;
2106 memset((caddr_t)(iadev->seg_ram+i), 0, iadev->num_vc*4);
2107 vc = (struct main_vc *)iadev->MAIN_VC_TABLE_ADDR;
2108 evc = (struct ext_vc *)iadev->EXT_VC_TABLE_ADDR;
2109 iadev->testTable = kmalloc(sizeof(long)*iadev->num_vc, GFP_KERNEL);
2110 if (!iadev->testTable) {
2111 printk("Get freepage failed\n");
2112 goto err_free_desc_tbl;
2114 for(i=0; i<iadev->num_vc; i++)
2116 memset((caddr_t)vc, 0, sizeof(*vc));
2117 memset((caddr_t)evc, 0, sizeof(*evc));
2118 iadev->testTable[i] = kmalloc(sizeof(struct testTable_t),
2120 if (!iadev->testTable[i])
2121 goto err_free_test_tables;
2122 iadev->testTable[i]->lastTime = 0;
2123 iadev->testTable[i]->fract = 0;
2124 iadev->testTable[i]->vc_status = VC_UBR;
2129 /* Other Initialization */
2131 /* Max Rate Register */
2132 if (iadev->phy_type & FE_25MBIT_PHY) {
2133 writew(RATE25, iadev->seg_reg+MAXRATE);
2134 writew((UBR_EN | (0x23 << 2)), iadev->seg_reg+STPARMS);
2137 writew(cellrate_to_float(iadev->LineRate),iadev->seg_reg+MAXRATE);
2138 writew((UBR_EN | ABR_EN | (0x23 << 2)), iadev->seg_reg+STPARMS);
2140 /* Set Idle Header Reigisters to be sure */
2141 writew(0, iadev->seg_reg+IDLEHEADHI);
2142 writew(0, iadev->seg_reg+IDLEHEADLO);
2144 /* Program ABR UBR Priority Register as PRI_ABR_UBR_EQUAL */
2145 writew(0xaa00, iadev->seg_reg+ABRUBR_ARB);
2147 iadev->close_pending = 0;
2148 init_waitqueue_head(&iadev->close_wait);
2149 init_waitqueue_head(&iadev->timeout_wait);
2150 skb_queue_head_init(&iadev->tx_dma_q);
2151 ia_init_rtn_q(&iadev->tx_return_q);
2153 /* RM Cell Protocol ID and Message Type */
2154 writew(RM_TYPE_4_0, iadev->seg_reg+RM_TYPE);
2155 skb_queue_head_init (&iadev->tx_backlog);
2157 /* Mode Register 1 */
2158 writew(MODE_REG_1_VAL, iadev->seg_reg+MODE_REG_1);
2160 /* Mode Register 0 */
2161 writew(T_ONLINE, iadev->seg_reg+MODE_REG_0);
2163 /* Interrupt Status Register - read to clear */
2164 readw(iadev->seg_reg+SEG_INTR_STATUS_REG);
2166 /* Interrupt Mask Reg- don't mask TCQ_NOT_EMPTY interrupt generation */
2167 writew(~(TRANSMIT_DONE | TCQ_NOT_EMPTY), iadev->seg_reg+SEG_MASK_REG);
2168 writew(TRANSMIT_DONE, iadev->seg_reg+SEG_INTR_STATUS_REG);
2169 iadev->tx_pkt_cnt = 0;
2170 iadev->rate_limit = iadev->LineRate / 3;
2174 err_free_test_tables:
2176 kfree(iadev->testTable[i]);
2177 kfree(iadev->testTable);
2179 kfree(iadev->desc_tbl);
2180 err_free_all_tx_bufs:
2181 i = iadev->num_tx_desc;
2184 struct cpcs_trailer_desc *desc = iadev->tx_buf + i;
2186 pci_unmap_single(iadev->pci, desc->dma_addr,
2187 sizeof(*desc->cpcs), PCI_DMA_TODEVICE);
2190 kfree(iadev->tx_buf);
2192 pci_free_consistent(iadev->pci, DLE_TOTAL_SIZE, iadev->tx_dle_q.start,
2198 static irqreturn_t ia_int(int irq, void *dev_id, struct pt_regs *regs)
2200 struct atm_dev *dev;
2202 unsigned int status;
2206 iadev = INPH_IA_DEV(dev);
2207 while( (status = readl(iadev->reg+IPHASE5575_BUS_STATUS_REG) & 0x7f))
2210 IF_EVENT(printk("ia_int: status = 0x%x\n", status);)
2211 if (status & STAT_REASSINT)
2214 IF_EVENT(printk("REASSINT Bus status reg: %08x\n", status);)
2217 if (status & STAT_DLERINT)
2219 /* Clear this bit by writing a 1 to it. */
2220 *(u_int *)(iadev->reg+IPHASE5575_BUS_STATUS_REG) = STAT_DLERINT;
2223 if (status & STAT_SEGINT)
2226 IF_EVENT(printk("IA: tx_intr \n");)
2229 if (status & STAT_DLETINT)
2231 *(u_int *)(iadev->reg+IPHASE5575_BUS_STATUS_REG) = STAT_DLETINT;
2234 if (status & (STAT_FEINT | STAT_ERRINT | STAT_MARKINT))
2236 if (status & STAT_FEINT)
2237 IaFrontEndIntr(iadev);
2240 return IRQ_RETVAL(handled);
2245 /*----------------------------- entries --------------------------------*/
2246 static int get_esi(struct atm_dev *dev)
2253 iadev = INPH_IA_DEV(dev);
2254 mac1 = cpu_to_be32(le32_to_cpu(readl(
2255 iadev->reg+IPHASE5575_MAC1)));
2256 mac2 = cpu_to_be16(le16_to_cpu(readl(iadev->reg+IPHASE5575_MAC2)));
2257 IF_INIT(printk("ESI: 0x%08x%04x\n", mac1, mac2);)
2258 for (i=0; i<MAC1_LEN; i++)
2259 dev->esi[i] = mac1 >>(8*(MAC1_LEN-1-i));
2261 for (i=0; i<MAC2_LEN; i++)
2262 dev->esi[i+MAC1_LEN] = mac2 >>(8*(MAC2_LEN - 1 -i));
2266 static int reset_sar(struct atm_dev *dev)
2270 unsigned int pci[64];
2272 iadev = INPH_IA_DEV(dev);
2274 if ((error = pci_read_config_dword(iadev->pci,
2275 i*4, &pci[i])) != PCIBIOS_SUCCESSFUL)
2277 writel(0, iadev->reg+IPHASE5575_EXT_RESET);
2279 if ((error = pci_write_config_dword(iadev->pci,
2280 i*4, pci[i])) != PCIBIOS_SUCCESSFUL)
2287 static int __init ia_init(struct atm_dev *dev)
2290 unsigned long real_base;
2292 unsigned short command;
2293 unsigned char revision;
2296 /* The device has been identified and registered. Now we read
2297 necessary configuration info like memory base address,
2298 interrupt number etc */
2300 IF_INIT(printk(">ia_init\n");)
2301 dev->ci_range.vpi_bits = 0;
2302 dev->ci_range.vci_bits = NR_VCI_LD;
2304 iadev = INPH_IA_DEV(dev);
2305 real_base = pci_resource_start (iadev->pci, 0);
2306 iadev->irq = iadev->pci->irq;
2308 if ((error = pci_read_config_word(iadev->pci, PCI_COMMAND,&command))
2309 || (error = pci_read_config_byte(iadev->pci,
2310 PCI_REVISION_ID,&revision)))
2312 printk(KERN_ERR DEV_LABEL "(itf %d): init error 0x%x\n",
2316 IF_INIT(printk(DEV_LABEL "(itf %d): rev.%d,realbase=0x%lx,irq=%d\n",
2317 dev->number, revision, real_base, iadev->irq);)
2319 /* find mapping size of board */
2321 iadev->pci_map_size = pci_resource_len(iadev->pci, 0);
2323 if (iadev->pci_map_size == 0x100000){
2324 iadev->num_vc = 4096;
2325 dev->ci_range.vci_bits = NR_VCI_4K_LD;
2328 else if (iadev->pci_map_size == 0x40000) {
2329 iadev->num_vc = 1024;
2333 printk("Unknown pci_map_size = 0x%x\n", iadev->pci_map_size);
2336 IF_INIT(printk (DEV_LABEL "map size: %i\n", iadev->pci_map_size);)
2338 /* enable bus mastering */
2339 pci_set_master(iadev->pci);
2342 * Delay at least 1us before doing any mem accesses (how 'bout 10?)
2346 /* mapping the physical address to a virtual address in address space */
2347 base = ioremap(real_base,iadev->pci_map_size); /* ioremap is not resolved ??? */
2351 printk(DEV_LABEL " (itf %d): can't set up page mapping\n",
2355 IF_INIT(printk(DEV_LABEL " (itf %d): rev.%d,base=%p,irq=%d\n",
2356 dev->number, revision, base, iadev->irq);)
2358 /* filling the iphase dev structure */
2359 iadev->mem = iadev->pci_map_size /2;
2360 iadev->real_base = real_base;
2363 /* Bus Interface Control Registers */
2364 iadev->reg = base + REG_BASE;
2365 /* Segmentation Control Registers */
2366 iadev->seg_reg = base + SEG_BASE;
2367 /* Reassembly Control Registers */
2368 iadev->reass_reg = base + REASS_BASE;
2369 /* Front end/ DMA control registers */
2370 iadev->phy = base + PHY_BASE;
2371 iadev->dma = base + PHY_BASE;
2372 /* RAM - Segmentation RAm and Reassembly RAM */
2373 iadev->ram = base + ACTUAL_RAM_BASE;
2374 iadev->seg_ram = base + ACTUAL_SEG_RAM_BASE;
2375 iadev->reass_ram = base + ACTUAL_REASS_RAM_BASE;
2377 /* lets print out the above */
2378 IF_INIT(printk("Base addrs: %p %p %p \n %p %p %p %p\n",
2379 iadev->reg,iadev->seg_reg,iadev->reass_reg,
2380 iadev->phy, iadev->ram, iadev->seg_ram,
2383 /* lets try reading the MAC address */
2384 error = get_esi(dev);
2386 iounmap(iadev->base);
2390 for (i=0; i < ESI_LEN; i++)
2391 printk("%s%02X",i ? "-" : "",dev->esi[i]);
2395 if (reset_sar(dev)) {
2396 iounmap(iadev->base);
2397 printk("IA: reset SAR fail, please try again\n");
2403 static void ia_update_stats(IADEV *iadev) {
2404 if (!iadev->carrier_detect)
2406 iadev->rx_cell_cnt += readw(iadev->reass_reg+CELL_CTR0)&0xffff;
2407 iadev->rx_cell_cnt += (readw(iadev->reass_reg+CELL_CTR1) & 0xffff) << 16;
2408 iadev->drop_rxpkt += readw(iadev->reass_reg + DRP_PKT_CNTR ) & 0xffff;
2409 iadev->drop_rxcell += readw(iadev->reass_reg + ERR_CNTR) & 0xffff;
2410 iadev->tx_cell_cnt += readw(iadev->seg_reg + CELL_CTR_LO_AUTO)&0xffff;
2411 iadev->tx_cell_cnt += (readw(iadev->seg_reg+CELL_CTR_HIGH_AUTO)&0xffff)<<16;
2415 static void ia_led_timer(unsigned long arg) {
2416 unsigned long flags;
2417 static u_char blinking[8] = {0, 0, 0, 0, 0, 0, 0, 0};
2419 static u32 ctrl_reg;
2420 for (i = 0; i < iadev_count; i++) {
2422 ctrl_reg = readl(ia_dev[i]->reg+IPHASE5575_BUS_CONTROL_REG);
2423 if (blinking[i] == 0) {
2425 ctrl_reg &= (~CTRL_LED);
2426 writel(ctrl_reg, ia_dev[i]->reg+IPHASE5575_BUS_CONTROL_REG);
2427 ia_update_stats(ia_dev[i]);
2431 ctrl_reg |= CTRL_LED;
2432 writel(ctrl_reg, ia_dev[i]->reg+IPHASE5575_BUS_CONTROL_REG);
2433 spin_lock_irqsave(&ia_dev[i]->tx_lock, flags);
2434 if (ia_dev[i]->close_pending)
2435 wake_up(&ia_dev[i]->close_wait);
2436 ia_tx_poll(ia_dev[i]);
2437 spin_unlock_irqrestore(&ia_dev[i]->tx_lock, flags);
2441 mod_timer(&ia_timer, jiffies + HZ / 4);
2445 static void ia_phy_put(struct atm_dev *dev, unsigned char value,
2448 writel(value, INPH_IA_DEV(dev)->phy+addr);
2451 static unsigned char ia_phy_get(struct atm_dev *dev, unsigned long addr)
2453 return readl(INPH_IA_DEV(dev)->phy+addr);
2456 static void ia_free_tx(IADEV *iadev)
2460 kfree(iadev->desc_tbl);
2461 for (i = 0; i < iadev->num_vc; i++)
2462 kfree(iadev->testTable[i]);
2463 kfree(iadev->testTable);
2464 for (i = 0; i < iadev->num_tx_desc; i++) {
2465 struct cpcs_trailer_desc *desc = iadev->tx_buf + i;
2467 pci_unmap_single(iadev->pci, desc->dma_addr,
2468 sizeof(*desc->cpcs), PCI_DMA_TODEVICE);
2471 kfree(iadev->tx_buf);
2472 pci_free_consistent(iadev->pci, DLE_TOTAL_SIZE, iadev->tx_dle_q.start,
2476 static void ia_free_rx(IADEV *iadev)
2478 kfree(iadev->rx_open);
2479 pci_free_consistent(iadev->pci, DLE_TOTAL_SIZE, iadev->rx_dle_q.start,
2483 static int __init ia_start(struct atm_dev *dev)
2489 IF_EVENT(printk(">ia_start\n");)
2490 iadev = INPH_IA_DEV(dev);
2491 if (request_irq(iadev->irq, &ia_int, SA_SHIRQ, DEV_LABEL, dev)) {
2492 printk(KERN_ERR DEV_LABEL "(itf %d): IRQ%d is already in use\n",
2493 dev->number, iadev->irq);
2497 /* @@@ should release IRQ on error */
2498 /* enabling memory + master */
2499 if ((error = pci_write_config_word(iadev->pci,
2501 PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER )))
2503 printk(KERN_ERR DEV_LABEL "(itf %d): can't enable memory+"
2504 "master (0x%x)\n",dev->number, error);
2510 /* Maybe we should reset the front end, initialize Bus Interface Control
2511 Registers and see. */
2513 IF_INIT(printk("Bus ctrl reg: %08x\n",
2514 readl(iadev->reg+IPHASE5575_BUS_CONTROL_REG));)
2515 ctrl_reg = readl(iadev->reg+IPHASE5575_BUS_CONTROL_REG);
2516 ctrl_reg = (ctrl_reg & (CTRL_LED | CTRL_FE_RST))
2524 | CTRL_DLETMASK /* shud be removed l8r */
2531 writel(ctrl_reg, iadev->reg+IPHASE5575_BUS_CONTROL_REG);
2533 IF_INIT(printk("Bus ctrl reg after initializing: %08x\n",
2534 readl(iadev->reg+IPHASE5575_BUS_CONTROL_REG));
2535 printk("Bus status reg after init: %08x\n",
2536 readl(iadev->reg+IPHASE5575_BUS_STATUS_REG));)
2539 error = tx_init(dev);
2542 error = rx_init(dev);
2546 ctrl_reg = readl(iadev->reg+IPHASE5575_BUS_CONTROL_REG);
2547 writel(ctrl_reg | CTRL_FE_RST, iadev->reg+IPHASE5575_BUS_CONTROL_REG);
2548 IF_INIT(printk("Bus ctrl reg after initializing: %08x\n",
2549 readl(iadev->reg+IPHASE5575_BUS_CONTROL_REG));)
2550 phy = 0; /* resolve compiler complaint */
2552 if ((phy=ia_phy_get(dev,0)) == 0x30)
2553 printk("IA: pm5346,rev.%d\n",phy&0x0f);
2555 printk("IA: utopia,rev.%0x\n",phy);)
2557 if (iadev->phy_type & FE_25MBIT_PHY)
2558 ia_mb25_init(iadev);
2559 else if (iadev->phy_type & (FE_DS3_PHY | FE_E3_PHY))
2560 ia_suni_pm7345_init(iadev);
2562 error = suni_init(dev);
2566 * Enable interrupt on loss of signal
2567 * SUNI_RSOP_CIE - 0x10
2568 * SUNI_RSOP_CIE_LOSE - 0x04
2570 ia_phy_put(dev, ia_phy_get(dev, 0x10) | 0x04, 0x10);
2572 error = dev->phy->start(dev);
2576 /* Get iadev->carrier_detect status */
2577 IaFrontEndIntr(iadev);
2586 free_irq(iadev->irq, dev);
2591 static void ia_close(struct atm_vcc *vcc)
2595 struct ia_vcc *ia_vcc;
2596 struct sk_buff *skb = NULL;
2597 struct sk_buff_head tmp_tx_backlog, tmp_vcc_backlog;
2598 unsigned long closetime, flags;
2601 iadev = INPH_IA_DEV(vcc->dev);
2602 ia_vcc = INPH_IA_VCC(vcc);
2603 if (!ia_vcc) return;
2605 IF_EVENT(printk("ia_close: ia_vcc->vc_desc_cnt = %d vci = %d\n",
2606 ia_vcc->vc_desc_cnt,vcc->vci);)
2607 clear_bit(ATM_VF_READY,&vcc->flags);
2608 skb_queue_head_init (&tmp_tx_backlog);
2609 skb_queue_head_init (&tmp_vcc_backlog);
2610 if (vcc->qos.txtp.traffic_class != ATM_NONE) {
2611 iadev->close_pending++;
2612 sleep_on_timeout(&iadev->timeout_wait, 50);
2613 spin_lock_irqsave(&iadev->tx_lock, flags);
2614 while((skb = skb_dequeue(&iadev->tx_backlog))) {
2615 if (ATM_SKB(skb)->vcc == vcc){
2616 if (vcc->pop) vcc->pop(vcc, skb);
2617 else dev_kfree_skb_any(skb);
2620 skb_queue_tail(&tmp_tx_backlog, skb);
2622 while((skb = skb_dequeue(&tmp_tx_backlog)))
2623 skb_queue_tail(&iadev->tx_backlog, skb);
2624 IF_EVENT(printk("IA TX Done decs_cnt = %d\n", ia_vcc->vc_desc_cnt);)
2625 closetime = jiffies;
2626 ctimeout = 300000 / ia_vcc->pcr;
2629 while (ia_vcc->vc_desc_cnt > 0){
2630 if ((jiffies - closetime) >= ctimeout)
2632 spin_unlock_irqrestore(&iadev->tx_lock, flags);
2633 sleep_on(&iadev->close_wait);
2634 spin_lock_irqsave(&iadev->tx_lock, flags);
2636 iadev->close_pending--;
2637 iadev->testTable[vcc->vci]->lastTime = 0;
2638 iadev->testTable[vcc->vci]->fract = 0;
2639 iadev->testTable[vcc->vci]->vc_status = VC_UBR;
2640 if (vcc->qos.txtp.traffic_class == ATM_ABR) {
2641 if (vcc->qos.txtp.min_pcr > 0)
2642 iadev->sum_mcr -= vcc->qos.txtp.min_pcr;
2644 if (vcc->qos.txtp.traffic_class == ATM_CBR) {
2645 ia_vcc = INPH_IA_VCC(vcc);
2646 iadev->sum_mcr -= ia_vcc->NumCbrEntry*iadev->Granularity;
2647 ia_cbrVc_close (vcc);
2649 spin_unlock_irqrestore(&iadev->tx_lock, flags);
2652 if (vcc->qos.rxtp.traffic_class != ATM_NONE) {
2653 // reset reass table
2654 vc_table = (u16 *)(iadev->reass_ram+REASS_TABLE*iadev->memSize);
2655 vc_table += vcc->vci;
2656 *vc_table = NO_AAL5_PKT;
2658 vc_table = (u16 *)(iadev->reass_ram+RX_VC_TABLE*iadev->memSize);
2659 vc_table += vcc->vci;
2660 *vc_table = (vcc->vci << 6) | 15;
2661 if (vcc->qos.rxtp.traffic_class == ATM_ABR) {
2662 struct abr_vc_table __iomem *abr_vc_table =
2663 (iadev->reass_ram+ABR_VC_TABLE*iadev->memSize);
2664 abr_vc_table += vcc->vci;
2665 abr_vc_table->rdf = 0x0003;
2666 abr_vc_table->air = 0x5eb1;
2668 // Drain the packets
2669 rx_dle_intr(vcc->dev);
2670 iadev->rx_open[vcc->vci] = NULL;
2672 kfree(INPH_IA_VCC(vcc));
2674 vcc->dev_data = NULL;
2675 clear_bit(ATM_VF_ADDR,&vcc->flags);
2679 static int ia_open(struct atm_vcc *vcc)
2682 struct ia_vcc *ia_vcc;
2684 if (!test_bit(ATM_VF_PARTIAL,&vcc->flags))
2686 IF_EVENT(printk("ia: not partially allocated resources\n");)
2687 vcc->dev_data = NULL;
2689 iadev = INPH_IA_DEV(vcc->dev);
2690 if (vcc->vci != ATM_VPI_UNSPEC && vcc->vpi != ATM_VCI_UNSPEC)
2692 IF_EVENT(printk("iphase open: unspec part\n");)
2693 set_bit(ATM_VF_ADDR,&vcc->flags);
2695 if (vcc->qos.aal != ATM_AAL5)
2697 IF_EVENT(printk(DEV_LABEL "(itf %d): open %d.%d\n",
2698 vcc->dev->number, vcc->vpi, vcc->vci);)
2700 /* Device dependent initialization */
2701 ia_vcc = kmalloc(sizeof(*ia_vcc), GFP_KERNEL);
2702 if (!ia_vcc) return -ENOMEM;
2703 vcc->dev_data = ia_vcc;
2705 if ((error = open_rx(vcc)))
2707 IF_EVENT(printk("iadev: error in open_rx, closing\n");)
2712 if ((error = open_tx(vcc)))
2714 IF_EVENT(printk("iadev: error in open_tx, closing\n");)
2719 set_bit(ATM_VF_READY,&vcc->flags);
2723 static u8 first = 1;
2725 ia_timer.expires = jiffies + 3*HZ;
2726 add_timer(&ia_timer);
2731 IF_EVENT(printk("ia open returning\n");)
2735 static int ia_change_qos(struct atm_vcc *vcc, struct atm_qos *qos, int flags)
2737 IF_EVENT(printk(">ia_change_qos\n");)
2741 static int ia_ioctl(struct atm_dev *dev, unsigned int cmd, void __user *arg)
2747 IF_EVENT(printk(">ia_ioctl\n");)
2748 if (cmd != IA_CMD) {
2749 if (!dev->phy->ioctl) return -EINVAL;
2750 return dev->phy->ioctl(dev,cmd,arg);
2752 if (copy_from_user(&ia_cmds, arg, sizeof ia_cmds)) return -EFAULT;
2753 board = ia_cmds.status;
2754 if ((board < 0) || (board > iadev_count))
2756 iadev = ia_dev[board];
2757 switch (ia_cmds.cmd) {
2760 switch (ia_cmds.sub_cmd) {
2762 if (!capable(CAP_NET_ADMIN)) return -EPERM;
2763 if (copy_to_user(ia_cmds.buf, iadev, sizeof(IADEV)))
2767 case MEMDUMP_SEGREG:
2768 if (!capable(CAP_NET_ADMIN)) return -EPERM;
2769 tmps = (u16 __user *)ia_cmds.buf;
2770 for(i=0; i<0x80; i+=2, tmps++)
2771 if(put_user((u16)(readl(iadev->seg_reg+i) & 0xffff), tmps)) return -EFAULT;
2775 case MEMDUMP_REASSREG:
2776 if (!capable(CAP_NET_ADMIN)) return -EPERM;
2777 tmps = (u16 __user *)ia_cmds.buf;
2778 for(i=0; i<0x80; i+=2, tmps++)
2779 if(put_user((u16)(readl(iadev->reass_reg+i) & 0xffff), tmps)) return -EFAULT;
2785 ia_regs_t *regs_local;
2789 if (!capable(CAP_NET_ADMIN)) return -EPERM;
2790 regs_local = kmalloc(sizeof(*regs_local), GFP_KERNEL);
2791 if (!regs_local) return -ENOMEM;
2792 ffL = ®s_local->ffredn;
2793 rfL = ®s_local->rfredn;
2794 /* Copy real rfred registers into the local copy */
2795 for (i=0; i<(sizeof (rfredn_t))/4; i++)
2796 ((u_int *)rfL)[i] = readl(iadev->reass_reg + i) & 0xffff;
2797 /* Copy real ffred registers into the local copy */
2798 for (i=0; i<(sizeof (ffredn_t))/4; i++)
2799 ((u_int *)ffL)[i] = readl(iadev->seg_reg + i) & 0xffff;
2801 if (copy_to_user(ia_cmds.buf, regs_local,sizeof(ia_regs_t))) {
2806 printk("Board %d registers dumped\n", board);
2812 if (!capable(CAP_NET_ADMIN)) return -EPERM;
2820 printk("skb = 0x%lx\n", (long)skb_peek(&iadev->tx_backlog));
2821 printk("rtn_q: 0x%lx\n",(long)ia_deque_rtn_q(&iadev->tx_return_q));
2826 struct k_sonet_stats *stats;
2827 stats = &PRIV(_ia_dev[board])->sonet_stats;
2828 printk("section_bip: %d\n", atomic_read(&stats->section_bip));
2829 printk("line_bip : %d\n", atomic_read(&stats->line_bip));
2830 printk("path_bip : %d\n", atomic_read(&stats->path_bip));
2831 printk("line_febe : %d\n", atomic_read(&stats->line_febe));
2832 printk("path_febe : %d\n", atomic_read(&stats->path_febe));
2833 printk("corr_hcs : %d\n", atomic_read(&stats->corr_hcs));
2834 printk("uncorr_hcs : %d\n", atomic_read(&stats->uncorr_hcs));
2835 printk("tx_cells : %d\n", atomic_read(&stats->tx_cells));
2836 printk("rx_cells : %d\n", atomic_read(&stats->rx_cells));
2841 if (!capable(CAP_NET_ADMIN)) return -EPERM;
2842 for (i = 1; i <= iadev->num_rx_desc; i++)
2843 free_desc(_ia_dev[board], i);
2844 writew( ~(RX_FREEQ_EMPT | RX_EXCP_RCVD),
2845 iadev->reass_reg+REASS_MASK_REG);
2852 if (!capable(CAP_NET_ADMIN)) return -EPERM;
2853 IaFrontEndIntr(iadev);
2856 if (!capable(CAP_NET_ADMIN)) return -EPERM;
2859 IADebugFlag = ia_cmds.maddr;
2860 printk("New debug option loaded\n");
2876 static int ia_getsockopt(struct atm_vcc *vcc, int level, int optname,
2877 void __user *optval, int optlen)
2879 IF_EVENT(printk(">ia_getsockopt\n");)
2883 static int ia_setsockopt(struct atm_vcc *vcc, int level, int optname,
2884 void __user *optval, int optlen)
2886 IF_EVENT(printk(">ia_setsockopt\n");)
2890 static int ia_pkt_tx (struct atm_vcc *vcc, struct sk_buff *skb) {
2893 struct tx_buf_desc __iomem *buf_desc_ptr;
2897 struct cpcs_trailer *trailer;
2898 struct ia_vcc *iavcc;
2900 iadev = INPH_IA_DEV(vcc->dev);
2901 iavcc = INPH_IA_VCC(vcc);
2902 if (!iavcc->txing) {
2903 printk("discard packet on closed VC\n");
2907 dev_kfree_skb_any(skb);
2911 if (skb->len > iadev->tx_buf_sz - 8) {
2912 printk("Transmit size over tx buffer size\n");
2916 dev_kfree_skb_any(skb);
2919 if ((u32)skb->data & 3) {
2920 printk("Misaligned SKB\n");
2924 dev_kfree_skb_any(skb);
2927 /* Get a descriptor number from our free descriptor queue
2928 We get the descr number from the TCQ now, since I am using
2929 the TCQ as a free buffer queue. Initially TCQ will be
2930 initialized with all the descriptors and is hence, full.
2932 desc = get_desc (iadev, iavcc);
2935 comp_code = desc >> 13;
2938 if ((desc == 0) || (desc > iadev->num_tx_desc))
2940 IF_ERR(printk(DEV_LABEL "invalid desc for send: %d\n", desc);)
2941 atomic_inc(&vcc->stats->tx);
2945 dev_kfree_skb_any(skb);
2946 return 0; /* return SUCCESS */
2951 IF_ERR(printk(DEV_LABEL "send desc:%d completion code %d error\n",
2955 /* remember the desc and vcc mapping */
2956 iavcc->vc_desc_cnt++;
2957 iadev->desc_tbl[desc-1].iavcc = iavcc;
2958 iadev->desc_tbl[desc-1].txskb = skb;
2959 IA_SKB_STATE(skb) = 0;
2961 iadev->ffL.tcq_rd += 2;
2962 if (iadev->ffL.tcq_rd > iadev->ffL.tcq_ed)
2963 iadev->ffL.tcq_rd = iadev->ffL.tcq_st;
2964 writew(iadev->ffL.tcq_rd, iadev->seg_reg+TCQ_RD_PTR);
2966 /* Put the descriptor number in the packet ready queue
2967 and put the updated write pointer in the DLE field
2969 *(u16*)(iadev->seg_ram+iadev->ffL.prq_wr) = desc;
2971 iadev->ffL.prq_wr += 2;
2972 if (iadev->ffL.prq_wr > iadev->ffL.prq_ed)
2973 iadev->ffL.prq_wr = iadev->ffL.prq_st;
2975 /* Figure out the exact length of the packet and padding required to
2976 make it aligned on a 48 byte boundary. */
2977 total_len = skb->len + sizeof(struct cpcs_trailer);
2978 total_len = ((total_len + 47) / 48) * 48;
2979 IF_TX(printk("ia packet len:%d padding:%d\n", total_len, total_len - skb->len);)
2981 /* Put the packet in a tx buffer */
2982 trailer = iadev->tx_buf[desc-1].cpcs;
2983 IF_TX(printk("Sent: skb = 0x%x skb->data: 0x%x len: %d, desc: %d\n",
2984 (u32)skb, (u32)skb->data, skb->len, desc);)
2985 trailer->control = 0;
2987 trailer->length = ((skb->len & 0xff) << 8) | ((skb->len & 0xff00) >> 8);
2988 trailer->crc32 = 0; /* not needed - dummy bytes */
2990 /* Display the packet */
2991 IF_TXPKT(printk("Sent data: len = %d MsgNum = %d\n",
2992 skb->len, tcnter++);
2993 xdump(skb->data, skb->len, "TX: ");
2996 /* Build the buffer descriptor */
2997 buf_desc_ptr = iadev->seg_ram+TX_DESC_BASE;
2998 buf_desc_ptr += desc; /* points to the corresponding entry */
2999 buf_desc_ptr->desc_mode = AAL5 | EOM_EN | APP_CRC32 | CMPL_INT;
3000 /* Huh ? p.115 of users guide describes this as a read-only register */
3001 writew(TRANSMIT_DONE, iadev->seg_reg+SEG_INTR_STATUS_REG);
3002 buf_desc_ptr->vc_index = vcc->vci;
3003 buf_desc_ptr->bytes = total_len;
3005 if (vcc->qos.txtp.traffic_class == ATM_ABR)
3006 clear_lockup (vcc, iadev);
3008 /* Build the DLE structure */
3009 wr_ptr = iadev->tx_dle_q.write;
3010 memset((caddr_t)wr_ptr, 0, sizeof(*wr_ptr));
3011 wr_ptr->sys_pkt_addr = pci_map_single(iadev->pci, skb->data,
3012 skb->len, PCI_DMA_TODEVICE);
3013 wr_ptr->local_pkt_addr = (buf_desc_ptr->buf_start_hi << 16) |
3014 buf_desc_ptr->buf_start_lo;
3015 /* wr_ptr->bytes = swap(total_len); didn't seem to affect ?? */
3016 wr_ptr->bytes = skb->len;
3018 /* hw bug - DLEs of 0x2d, 0x2e, 0x2f cause DMA lockup */
3019 if ((wr_ptr->bytes >> 2) == 0xb)
3020 wr_ptr->bytes = 0x30;
3022 wr_ptr->mode = TX_DLE_PSI;
3023 wr_ptr->prq_wr_ptr_data = 0;
3025 /* end is not to be used for the DLE q */
3026 if (++wr_ptr == iadev->tx_dle_q.end)
3027 wr_ptr = iadev->tx_dle_q.start;
3029 /* Build trailer dle */
3030 wr_ptr->sys_pkt_addr = iadev->tx_buf[desc-1].dma_addr;
3031 wr_ptr->local_pkt_addr = ((buf_desc_ptr->buf_start_hi << 16) |
3032 buf_desc_ptr->buf_start_lo) + total_len - sizeof(struct cpcs_trailer);
3034 wr_ptr->bytes = sizeof(struct cpcs_trailer);
3035 wr_ptr->mode = DMA_INT_ENABLE;
3036 wr_ptr->prq_wr_ptr_data = iadev->ffL.prq_wr;
3038 /* end is not to be used for the DLE q */
3039 if (++wr_ptr == iadev->tx_dle_q.end)
3040 wr_ptr = iadev->tx_dle_q.start;
3042 iadev->tx_dle_q.write = wr_ptr;
3043 ATM_DESC(skb) = vcc->vci;
3044 skb_queue_tail(&iadev->tx_dma_q, skb);
3046 atomic_inc(&vcc->stats->tx);
3047 iadev->tx_pkt_cnt++;
3048 /* Increment transaction counter */
3049 writel(2, iadev->dma+IPHASE5575_TX_COUNTER);
3052 /* add flow control logic */
3053 if (atomic_read(&vcc->stats->tx) % 20 == 0) {
3054 if (iavcc->vc_desc_cnt > 10) {
3055 vcc->tx_quota = vcc->tx_quota * 3 / 4;
3056 printk("Tx1: vcc->tx_quota = %d \n", (u32)vcc->tx_quota );
3057 iavcc->flow_inc = -1;
3058 iavcc->saved_tx_quota = vcc->tx_quota;
3059 } else if ((iavcc->flow_inc < 0) && (iavcc->vc_desc_cnt < 3)) {
3060 // vcc->tx_quota = 3 * iavcc->saved_tx_quota / 4;
3061 printk("Tx2: vcc->tx_quota = %d \n", (u32)vcc->tx_quota );
3062 iavcc->flow_inc = 0;
3066 IF_TX(printk("ia send done\n");)
3070 static int ia_send(struct atm_vcc *vcc, struct sk_buff *skb)
3073 struct ia_vcc *iavcc;
3074 unsigned long flags;
3076 iadev = INPH_IA_DEV(vcc->dev);
3077 iavcc = INPH_IA_VCC(vcc);
3078 if ((!skb)||(skb->len>(iadev->tx_buf_sz-sizeof(struct cpcs_trailer))))
3081 printk(KERN_CRIT "null skb in ia_send\n");
3082 else dev_kfree_skb_any(skb);
3085 spin_lock_irqsave(&iadev->tx_lock, flags);
3086 if (!test_bit(ATM_VF_READY,&vcc->flags)){
3087 dev_kfree_skb_any(skb);
3088 spin_unlock_irqrestore(&iadev->tx_lock, flags);
3091 ATM_SKB(skb)->vcc = vcc;
3093 if (skb_peek(&iadev->tx_backlog)) {
3094 skb_queue_tail(&iadev->tx_backlog, skb);
3097 if (ia_pkt_tx (vcc, skb)) {
3098 skb_queue_tail(&iadev->tx_backlog, skb);
3101 spin_unlock_irqrestore(&iadev->tx_lock, flags);
3106 static int ia_proc_read(struct atm_dev *dev,loff_t *pos,char *page)
3110 IADEV *iadev = INPH_IA_DEV(dev);
3112 if (iadev->phy_type == FE_25MBIT_PHY) {
3113 n = sprintf(page, " Board Type : Iphase5525-1KVC-128K\n");
3116 if (iadev->phy_type == FE_DS3_PHY)
3117 n = sprintf(page, " Board Type : Iphase-ATM-DS3");
3118 else if (iadev->phy_type == FE_E3_PHY)
3119 n = sprintf(page, " Board Type : Iphase-ATM-E3");
3120 else if (iadev->phy_type == FE_UTP_OPTION)
3121 n = sprintf(page, " Board Type : Iphase-ATM-UTP155");
3123 n = sprintf(page, " Board Type : Iphase-ATM-OC3");
3125 if (iadev->pci_map_size == 0x40000)
3126 n += sprintf(tmpPtr, "-1KVC-");
3128 n += sprintf(tmpPtr, "-4KVC-");
3130 if ((iadev->memType & MEM_SIZE_MASK) == MEM_SIZE_1M)
3131 n += sprintf(tmpPtr, "1M \n");
3132 else if ((iadev->memType & MEM_SIZE_MASK) == MEM_SIZE_512K)
3133 n += sprintf(tmpPtr, "512K\n");
3135 n += sprintf(tmpPtr, "128K\n");
3139 return sprintf(page, " Number of Tx Buffer: %u\n"
3140 " Size of Tx Buffer : %u\n"
3141 " Number of Rx Buffer: %u\n"
3142 " Size of Rx Buffer : %u\n"
3143 " Packets Receiverd : %u\n"
3144 " Packets Transmitted: %u\n"
3145 " Cells Received : %u\n"
3146 " Cells Transmitted : %u\n"
3147 " Board Dropped Cells: %u\n"
3148 " Board Dropped Pkts : %u\n",
3149 iadev->num_tx_desc, iadev->tx_buf_sz,
3150 iadev->num_rx_desc, iadev->rx_buf_sz,
3151 iadev->rx_pkt_cnt, iadev->tx_pkt_cnt,
3152 iadev->rx_cell_cnt, iadev->tx_cell_cnt,
3153 iadev->drop_rxcell, iadev->drop_rxpkt);
3158 static const struct atmdev_ops ops = {
3162 .getsockopt = ia_getsockopt,
3163 .setsockopt = ia_setsockopt,
3165 .phy_put = ia_phy_put,
3166 .phy_get = ia_phy_get,
3167 .change_qos = ia_change_qos,
3168 .proc_read = ia_proc_read,
3169 .owner = THIS_MODULE,
3172 static int __devinit ia_init_one(struct pci_dev *pdev,
3173 const struct pci_device_id *ent)
3175 struct atm_dev *dev;
3177 unsigned long flags;
3180 iadev = kmalloc(sizeof(*iadev), GFP_KERNEL);
3185 memset(iadev, 0, sizeof(*iadev));
3188 IF_INIT(printk("ia detected at bus:%d dev: %d function:%d\n",
3189 pdev->bus->number, PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn));)
3190 if (pci_enable_device(pdev)) {
3192 goto err_out_free_iadev;
3194 dev = atm_dev_register(DEV_LABEL, &ops, -1, NULL);
3197 goto err_out_disable_dev;
3199 dev->dev_data = iadev;
3200 IF_INIT(printk(DEV_LABEL "registered at (itf :%d)\n", dev->number);)
3201 IF_INIT(printk("dev_id = 0x%x iadev->LineRate = %d \n", (u32)dev,
3204 ia_dev[iadev_count] = iadev;
3205 _ia_dev[iadev_count] = dev;
3207 spin_lock_init(&iadev->misc_lock);
3208 /* First fixes first. I don't want to think about this now. */
3209 spin_lock_irqsave(&iadev->misc_lock, flags);
3210 if (ia_init(dev) || ia_start(dev)) {
3211 IF_INIT(printk("IA register failed!\n");)
3213 ia_dev[iadev_count] = NULL;
3214 _ia_dev[iadev_count] = NULL;
3215 spin_unlock_irqrestore(&iadev->misc_lock, flags);
3217 goto err_out_deregister_dev;
3219 spin_unlock_irqrestore(&iadev->misc_lock, flags);
3220 IF_EVENT(printk("iadev_count = %d\n", iadev_count);)
3222 iadev->next_board = ia_boards;
3225 pci_set_drvdata(pdev, dev);
3229 err_out_deregister_dev:
3230 atm_dev_deregister(dev);
3231 err_out_disable_dev:
3232 pci_disable_device(pdev);
3239 static void __devexit ia_remove_one(struct pci_dev *pdev)
3241 struct atm_dev *dev = pci_get_drvdata(pdev);
3242 IADEV *iadev = INPH_IA_DEV(dev);
3244 ia_phy_put(dev, ia_phy_get(dev,0x10) & ~(0x4), 0x10);
3247 /* De-register device */
3248 free_irq(iadev->irq, dev);
3250 ia_dev[iadev_count] = NULL;
3251 _ia_dev[iadev_count] = NULL;
3252 atm_dev_deregister(dev);
3253 IF_EVENT(printk("iav deregistered at (itf:%d)\n", dev->number);)
3255 iounmap(iadev->base);
3256 pci_disable_device(pdev);
3264 static struct pci_device_id ia_pci_tbl[] = {
3265 { PCI_VENDOR_ID_IPHASE, 0x0008, PCI_ANY_ID, PCI_ANY_ID, },
3266 { PCI_VENDOR_ID_IPHASE, 0x0009, PCI_ANY_ID, PCI_ANY_ID, },
3269 MODULE_DEVICE_TABLE(pci, ia_pci_tbl);
3271 static struct pci_driver ia_driver = {
3273 .id_table = ia_pci_tbl,
3274 .probe = ia_init_one,
3275 .remove = __devexit_p(ia_remove_one),
3278 static int __init ia_module_init(void)
3282 ret = pci_module_init(&ia_driver);
3284 ia_timer.expires = jiffies + 3*HZ;
3285 add_timer(&ia_timer);
3287 printk(KERN_ERR DEV_LABEL ": no adapter found\n");
3291 static void __exit ia_module_exit(void)
3293 pci_unregister_driver(&ia_driver);
3295 del_timer(&ia_timer);
3298 module_init(ia_module_init);
3299 module_exit(ia_module_exit);