3 * Copyright (C) 2002-2004 Dave Jones
4 * Copyright (C) 1999 Jeff Hartmann
5 * Copyright (C) 1999 Precision Insight, Inc.
6 * Copyright (C) 1999 Xi Graphics, Inc.
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
15 * The above copyright notice and this permission notice shall be included
16 * in all copies or substantial portions of the Software.
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
19 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
21 * JEFF HARTMANN, OR ANY OTHER CONTRIBUTORS BE LIABLE FOR ANY CLAIM,
22 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
23 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE
24 * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
28 #ifndef _AGP_BACKEND_PRIV_H
29 #define _AGP_BACKEND_PRIV_H 1
31 #include <asm/agp.h> /* for flush_agp_cache() */
33 #define PFX "agpgart: "
37 #define DBG(x,y...) printk (KERN_DEBUG PFX "%s: " x "\n", __FUNCTION__ , ## y)
39 #define DBG(x,y...) do { } while (0)
42 extern struct agp_bridge_data *agp_bridge;
55 /* totally device specific, for integrated chipsets that
56 * might have different types of memory masks. For other
57 * devices this will probably be ignored */
60 struct aper_size_info_8 {
67 struct aper_size_info_16 {
74 struct aper_size_info_32 {
81 struct aper_size_info_lvl2 {
87 struct aper_size_info_fixed {
93 struct agp_bridge_driver {
96 int num_aperture_sizes;
97 enum aper_size_type size_type;
98 int cant_use_aperture;
99 int needs_scratch_page;
100 struct gatt_mask *masks;
101 int (*fetch_size)(void);
102 int (*configure)(void);
103 void (*agp_enable)(u32);
104 void (*cleanup)(void);
105 void (*tlb_flush)(struct agp_memory *);
106 unsigned long (*mask_memory)(unsigned long, int);
107 void (*cache_flush)(void);
108 int (*create_gatt_table)(void);
109 int (*free_gatt_table)(void);
110 int (*insert_memory)(struct agp_memory *, off_t, int);
111 int (*remove_memory)(struct agp_memory *, off_t, int);
112 struct agp_memory *(*alloc_by_type) (size_t, int);
113 void (*free_by_type)(struct agp_memory *);
114 void *(*agp_alloc_page)(void);
115 void (*agp_destroy_page)(void *);
118 struct agp_bridge_data {
119 struct agp_version *version;
120 struct agp_bridge_driver *driver;
121 struct vm_operations_struct *vm_ops;
124 void *dev_private_data;
126 u32 __iomem *gatt_table;
127 u32 *gatt_table_real;
128 unsigned long scratch_page;
129 unsigned long scratch_page_real;
130 unsigned long gart_bus_addr;
131 unsigned long gatt_bus_addr;
133 enum chipset_type type;
134 unsigned long *key_list;
135 atomic_t current_memory_agp;
137 int max_memory_agp; /* in number of pages */
138 int aperture_size_idx;
144 #define KB(x) ((x) * 1024)
145 #define MB(x) (KB (KB (x)))
146 #define GB(x) (MB (KB (x)))
148 #define A_SIZE_8(x) ((struct aper_size_info_8 *) x)
149 #define A_SIZE_16(x) ((struct aper_size_info_16 *) x)
150 #define A_SIZE_32(x) ((struct aper_size_info_32 *) x)
151 #define A_SIZE_LVL2(x) ((struct aper_size_info_lvl2 *) x)
152 #define A_SIZE_FIX(x) ((struct aper_size_info_fixed *) x)
153 #define A_IDX8(bridge) (A_SIZE_8((bridge)->driver->aperture_sizes) + i)
154 #define A_IDX16(bridge) (A_SIZE_16((bridge)->driver->aperture_sizes) + i)
155 #define A_IDX32(bridge) (A_SIZE_32((bridge)->driver->aperture_sizes) + i)
156 #define MAXKEY (4096 * 32)
158 #define PGE_EMPTY(b, p) (!(p) || (p) == (unsigned long) (b)->scratch_page)
161 /* Intel registers */
162 #define INTEL_APSIZE 0xb4
163 #define INTEL_ATTBASE 0xb8
164 #define INTEL_AGPCTRL 0xb0
165 #define INTEL_NBXCFG 0x50
166 #define INTEL_ERRSTS 0x91
168 /* Intel i830 registers */
169 #define I830_GMCH_CTRL 0x52
170 #define I830_GMCH_ENABLED 0x4
171 #define I830_GMCH_MEM_MASK 0x1
172 #define I830_GMCH_MEM_64M 0x1
173 #define I830_GMCH_MEM_128M 0
174 #define I830_GMCH_GMS_MASK 0x70
175 #define I830_GMCH_GMS_DISABLED 0x00
176 #define I830_GMCH_GMS_LOCAL 0x10
177 #define I830_GMCH_GMS_STOLEN_512 0x20
178 #define I830_GMCH_GMS_STOLEN_1024 0x30
179 #define I830_GMCH_GMS_STOLEN_8192 0x40
180 #define I830_RDRAM_CHANNEL_TYPE 0x03010
181 #define I830_RDRAM_ND(x) (((x) & 0x20) >> 5)
182 #define I830_RDRAM_DDT(x) (((x) & 0x18) >> 3)
184 /* This one is for I830MP w. an external graphic card */
185 #define INTEL_I830_ERRSTS 0x92
187 /* Intel 855GM/852GM registers */
188 #define I855_GMCH_GMS_STOLEN_0M 0x0
189 #define I855_GMCH_GMS_STOLEN_1M (0x1 << 4)
190 #define I855_GMCH_GMS_STOLEN_4M (0x2 << 4)
191 #define I855_GMCH_GMS_STOLEN_8M (0x3 << 4)
192 #define I855_GMCH_GMS_STOLEN_16M (0x4 << 4)
193 #define I855_GMCH_GMS_STOLEN_32M (0x5 << 4)
194 #define I85X_CAPID 0x44
195 #define I85X_VARIANT_MASK 0x7
196 #define I85X_VARIANT_SHIFT 5
202 /* Intel i845 registers */
203 #define INTEL_I845_AGPM 0x51
204 #define INTEL_I845_ERRSTS 0xc8
206 /* Intel i860 registers */
207 #define INTEL_I860_MCHCFG 0x50
208 #define INTEL_I860_ERRSTS 0xc8
210 /* Intel i810 registers */
211 #define I810_GMADDR 0x10
212 #define I810_MMADDR 0x14
213 #define I810_PTE_BASE 0x10000
214 #define I810_PTE_MAIN_UNCACHED 0x00000000
215 #define I810_PTE_LOCAL 0x00000002
216 #define I810_PTE_VALID 0x00000001
217 #define I810_SMRAM_MISCC 0x70
218 #define I810_GFX_MEM_WIN_SIZE 0x00010000
219 #define I810_GFX_MEM_WIN_32M 0x00010000
220 #define I810_GMS 0x000000c0
221 #define I810_GMS_DISABLE 0x00000000
222 #define I810_PGETBL_CTL 0x2020
223 #define I810_PGETBL_ENABLED 0x00000001
224 #define I810_DRAM_CTL 0x3000
225 #define I810_DRAM_ROW_0 0x00000001
226 #define I810_DRAM_ROW_0_SDRAM 0x00000001
228 struct agp_device_ids {
229 unsigned short device_id; /* first, to make table easier to read */
230 enum chipset_type chipset;
231 const char *chipset_name;
232 int (*chipset_setup) (struct pci_dev *pdev); /* used to override generic */
235 /* Driver registration */
236 struct agp_bridge_data *agp_alloc_bridge(void);
237 void agp_put_bridge(struct agp_bridge_data *bridge);
238 int agp_add_bridge(struct agp_bridge_data *bridge);
239 void agp_remove_bridge(struct agp_bridge_data *bridge);
241 /* Frontend routines. */
242 int agp_frontend_initialize(void);
243 void agp_frontend_cleanup(void);
245 /* Generic routines. */
246 void agp_generic_enable(u32 mode);
247 int agp_generic_create_gatt_table(void);
248 int agp_generic_free_gatt_table(void);
249 struct agp_memory *agp_create_memory(int scratch_pages);
250 int agp_generic_insert_memory(struct agp_memory *mem, off_t pg_start, int type);
251 int agp_generic_remove_memory(struct agp_memory *mem, off_t pg_start, int type);
252 struct agp_memory *agp_generic_alloc_by_type(size_t page_count, int type);
253 void agp_generic_free_by_type(struct agp_memory *curr);
254 void *agp_generic_alloc_page(void);
255 void agp_generic_destroy_page(void *addr);
256 void agp_free_key(int key);
257 int agp_num_entries(void);
258 u32 agp_collect_device_status(u32 mode, u32 command);
259 void agp_device_command(u32 command, int agp_v3);
260 int agp_3_5_enable(struct agp_bridge_data *bridge);
261 void global_cache_flush(void);
262 void get_agp_version(struct agp_bridge_data *bridge);
263 unsigned long agp_generic_mask_memory(unsigned long addr, int type);
265 /* generic routines for agp>=3 */
266 int agp3_generic_fetch_size(void);
267 void agp3_generic_tlbflush(struct agp_memory *mem);
268 int agp3_generic_configure(void);
269 void agp3_generic_cleanup(void);
271 /* aperture sizes have been standardised since v3 */
272 #define AGP_GENERIC_SIZES_ENTRIES 11
273 extern struct aper_size_info_16 agp3_generic_sizes[];
277 extern int agp_try_unsupported_boot;
279 /* Chipset independant registers (from AGP Spec) */
280 #define AGP_APBASE 0x10
284 #define AGPNISTAT 0xc
286 #define AGPAPSIZE 0x14
288 #define AGPGARTLO 0x18
289 #define AGPGARTHI 0x1c
290 #define AGPNICMD 0x20
292 #define AGP_MAJOR_VERSION_SHIFT (20)
293 #define AGP_MINOR_VERSION_SHIFT (16)
295 #define AGPSTAT_RQ_DEPTH (0xff000000)
296 #define AGPSTAT_RQ_DEPTH_SHIFT 24
298 #define AGPSTAT_CAL_MASK (1<<12|1<<11|1<<10)
299 #define AGPSTAT_ARQSZ (1<<15|1<<14|1<<13)
300 #define AGPSTAT_ARQSZ_SHIFT 13
302 #define AGPSTAT_SBA (1<<9)
303 #define AGPSTAT_AGP_ENABLE (1<<8)
304 #define AGPSTAT_FW (1<<4)
305 #define AGPSTAT_MODE_3_0 (1<<3)
307 #define AGPSTAT2_1X (1<<0)
308 #define AGPSTAT2_2X (1<<1)
309 #define AGPSTAT2_4X (1<<2)
311 #define AGPSTAT3_RSVD (1<<2)
312 #define AGPSTAT3_8X (1<<1)
313 #define AGPSTAT3_4X (1)
315 #define AGPCTRL_APERENB (1<<8)
316 #define AGPCTRL_GTLBEN (1<<7)
318 #endif /* _AGP_BACKEND_PRIV_H */