3 * Copyright (C) 2002-2003 Hewlett-Packard Co
4 * Bjorn Helgaas <bjorn_helgaas@hp.com>
7 #include <linux/acpi.h>
8 #include <linux/module.h>
10 #include <linux/init.h>
11 #include <linux/agp_backend.h>
13 #include <asm/acpi-ext.h>
18 #define log2(x) ffz(~(x))
21 #define HP_ZX1_IOC_OFFSET 0x1000 /* ACPI reports SBA, we want IOC */
23 /* HP ZX1 IOC registers */
24 #define HP_ZX1_IBASE 0x300
25 #define HP_ZX1_IMASK 0x308
26 #define HP_ZX1_PCOM 0x310
27 #define HP_ZX1_TCNFG 0x318
28 #define HP_ZX1_PDIR_BASE 0x320
30 #define HP_ZX1_IOVA_BASE GB(1UL)
31 #define HP_ZX1_IOVA_SIZE GB(1UL)
32 #define HP_ZX1_GART_SIZE (HP_ZX1_IOVA_SIZE / 2)
33 #define HP_ZX1_SBA_IOMMU_COOKIE 0x0000badbadc0ffeeUL
35 #define HP_ZX1_PDIR_VALID_BIT 0x8000000000000000UL
36 #define HP_ZX1_IOVA_TO_PDIR(va) ((va - hp_private.iova_base) >> hp_private.io_tlb_shift)
38 #define AGP8X_MODE_BIT 3
39 #define AGP8X_MODE (1 << AGP8X_MODE_BIT)
41 /* AGP bridge need not be PCI device, but DRM thinks it is. */
42 static struct pci_dev fake_bridge_dev;
44 static int hp_zx1_gart_found;
46 static struct aper_size_info_fixed hp_zx1_sizes[] =
48 {0, 0, 0}, /* filled in by hp_zx1_fetch_size() */
51 static struct gatt_mask hp_zx1_masks[] =
53 {.mask = HP_ZX1_PDIR_VALID_BIT, .type = 0}
56 static struct _hp_private {
57 volatile u8 *ioc_regs;
58 volatile u8 *lba_regs;
60 u64 *io_pdir; // PDIR for entire IOVA
61 u64 *gatt; // PDIR just for GART (subset of above)
67 int io_pdir_owner; // do we own it, or share it with sba_iommu?
70 int io_tlb_ps; // IOC ps config
71 int io_pages_per_kpage;
74 static int __init hp_zx1_ioc_shared(void)
76 struct _hp_private *hp = &hp_private;
78 printk(KERN_INFO PFX "HP ZX1 IOC: IOPDIR shared with sba_iommu\n");
81 * IOC already configured by sba_iommu module; just use
82 * its setup. We assume:
83 * - IOVA space is 1Gb in size
84 * - first 512Mb is IOMMU, second 512Mb is GART
86 hp->io_tlb_ps = INREG64(hp->ioc_regs, HP_ZX1_TCNFG);
87 switch (hp->io_tlb_ps) {
88 case 0: hp->io_tlb_shift = 12; break;
89 case 1: hp->io_tlb_shift = 13; break;
90 case 2: hp->io_tlb_shift = 14; break;
91 case 3: hp->io_tlb_shift = 16; break;
93 printk(KERN_ERR PFX "Invalid IOTLB page size "
94 "configuration 0x%x\n", hp->io_tlb_ps);
99 hp->io_page_size = 1 << hp->io_tlb_shift;
100 hp->io_pages_per_kpage = PAGE_SIZE / hp->io_page_size;
102 hp->iova_base = INREG64(hp->ioc_regs, HP_ZX1_IBASE) & ~0x1;
103 hp->gart_base = hp->iova_base + HP_ZX1_IOVA_SIZE - HP_ZX1_GART_SIZE;
105 hp->gart_size = HP_ZX1_GART_SIZE;
106 hp->gatt_entries = hp->gart_size / hp->io_page_size;
108 hp->io_pdir = phys_to_virt(INREG64(hp->ioc_regs, HP_ZX1_PDIR_BASE));
109 hp->gatt = &hp->io_pdir[HP_ZX1_IOVA_TO_PDIR(hp->gart_base)];
111 if (hp->gatt[0] != HP_ZX1_SBA_IOMMU_COOKIE) {
112 /* Normal case when no AGP device in system */
114 hp->gatt_entries = 0;
115 printk(KERN_ERR PFX "No reserved IO PDIR entry found; "
124 hp_zx1_ioc_owner (void)
126 struct _hp_private *hp = &hp_private;
128 printk(KERN_INFO PFX "HP ZX1 IOC: IOPDIR dedicated to GART\n");
131 * Select an IOV page size no larger than system page size.
133 if (PAGE_SIZE >= KB(64)) {
134 hp->io_tlb_shift = 16;
136 } else if (PAGE_SIZE >= KB(16)) {
137 hp->io_tlb_shift = 14;
139 } else if (PAGE_SIZE >= KB(8)) {
140 hp->io_tlb_shift = 13;
143 hp->io_tlb_shift = 12;
146 hp->io_page_size = 1 << hp->io_tlb_shift;
147 hp->io_pages_per_kpage = PAGE_SIZE / hp->io_page_size;
149 hp->iova_base = HP_ZX1_IOVA_BASE;
150 hp->gart_size = HP_ZX1_GART_SIZE;
151 hp->gart_base = hp->iova_base + HP_ZX1_IOVA_SIZE - hp->gart_size;
153 hp->gatt_entries = hp->gart_size / hp->io_page_size;
154 hp->io_pdir_size = (HP_ZX1_IOVA_SIZE / hp->io_page_size) * sizeof(u64);
160 hp_zx1_ioc_init (u64 hpa)
162 struct _hp_private *hp = &hp_private;
164 hp->ioc_regs = ioremap(hpa, 1024);
169 * If the IOTLB is currently disabled, we can take it over.
170 * Otherwise, we have to share with sba_iommu.
172 hp->io_pdir_owner = (INREG64(hp->ioc_regs, HP_ZX1_IBASE) & 0x1) == 0;
174 if (hp->io_pdir_owner)
175 return hp_zx1_ioc_owner();
177 return hp_zx1_ioc_shared();
181 hp_zx1_lba_find_capability (volatile u8 *hpa, int cap)
187 status = INREG16(hpa, PCI_STATUS);
188 if (!(status & PCI_STATUS_CAP_LIST))
190 pos = INREG8(hpa, PCI_CAPABILITY_LIST);
191 while (ttl-- && pos >= 0x40) {
193 id = INREG8(hpa, pos + PCI_CAP_LIST_ID);
198 pos = INREG8(hpa, pos + PCI_CAP_LIST_NEXT);
204 hp_zx1_lba_init (u64 hpa)
206 struct _hp_private *hp = &hp_private;
209 hp->lba_regs = ioremap(hpa, 256);
213 hp->lba_cap_offset = hp_zx1_lba_find_capability(hp->lba_regs, PCI_CAP_ID_AGP);
215 cap = INREG32(hp->lba_regs, hp->lba_cap_offset) & 0xff;
216 if (cap != PCI_CAP_ID_AGP) {
217 printk(KERN_ERR PFX "Invalid capability ID 0x%02x at 0x%x\n",
218 cap, hp->lba_cap_offset);
226 hp_zx1_fetch_size(void)
230 size = hp_private.gart_size / MB(1);
231 hp_zx1_sizes[0].size = size;
232 agp_bridge->current_size = (void *) &hp_zx1_sizes[0];
237 hp_zx1_configure (void)
239 struct _hp_private *hp = &hp_private;
241 agp_bridge->gart_bus_addr = hp->gart_base;
242 agp_bridge->capndx = hp->lba_cap_offset;
243 agp_bridge->mode = INREG32(hp->lba_regs, hp->lba_cap_offset + PCI_AGP_STATUS);
245 if (hp->io_pdir_owner) {
246 OUTREG64(hp->ioc_regs, HP_ZX1_PDIR_BASE, virt_to_phys(hp->io_pdir));
247 OUTREG64(hp->ioc_regs, HP_ZX1_TCNFG, hp->io_tlb_ps);
248 OUTREG64(hp->ioc_regs, HP_ZX1_IMASK, ~(HP_ZX1_IOVA_SIZE - 1));
249 OUTREG64(hp->ioc_regs, HP_ZX1_IBASE, hp->iova_base | 0x1);
250 OUTREG64(hp->ioc_regs, HP_ZX1_PCOM, hp->iova_base | log2(HP_ZX1_IOVA_SIZE));
251 INREG64(hp->ioc_regs, HP_ZX1_PCOM);
258 hp_zx1_cleanup (void)
260 struct _hp_private *hp = &hp_private;
263 if (hp->io_pdir_owner)
264 OUTREG64(hp->ioc_regs, HP_ZX1_IBASE, 0);
265 iounmap((void *) hp->ioc_regs);
268 iounmap((void *) hp->lba_regs);
272 hp_zx1_tlbflush (struct agp_memory *mem)
274 struct _hp_private *hp = &hp_private;
276 OUTREG64(hp->ioc_regs, HP_ZX1_PCOM, hp->gart_base | log2(hp->gart_size));
277 INREG64(hp->ioc_regs, HP_ZX1_PCOM);
281 hp_zx1_create_gatt_table (void)
283 struct _hp_private *hp = &hp_private;
286 if (hp->io_pdir_owner) {
287 hp->io_pdir = (u64 *) __get_free_pages(GFP_KERNEL,
288 get_order(hp->io_pdir_size));
290 printk(KERN_ERR PFX "Couldn't allocate contiguous "
291 "memory for I/O PDIR\n");
293 hp->gatt_entries = 0;
296 memset(hp->io_pdir, 0, hp->io_pdir_size);
298 hp->gatt = &hp->io_pdir[HP_ZX1_IOVA_TO_PDIR(hp->gart_base)];
301 for (i = 0; i < hp->gatt_entries; i++) {
302 hp->gatt[i] = (unsigned long) agp_bridge->scratch_page;
309 hp_zx1_free_gatt_table (void)
311 struct _hp_private *hp = &hp_private;
313 if (hp->io_pdir_owner)
314 free_pages((unsigned long) hp->io_pdir,
315 get_order(hp->io_pdir_size));
317 hp->gatt[0] = HP_ZX1_SBA_IOMMU_COOKIE;
322 hp_zx1_insert_memory (struct agp_memory *mem, off_t pg_start, int type)
324 struct _hp_private *hp = &hp_private;
326 off_t j, io_pg_start;
329 if (type != 0 || mem->type != 0) {
333 io_pg_start = hp->io_pages_per_kpage * pg_start;
334 io_pg_count = hp->io_pages_per_kpage * mem->page_count;
335 if ((io_pg_start + io_pg_count) > hp->gatt_entries) {
340 while (j < (io_pg_start + io_pg_count)) {
347 if (mem->is_flushed == FALSE) {
348 global_cache_flush();
349 mem->is_flushed = TRUE;
352 for (i = 0, j = io_pg_start; i < mem->page_count; i++) {
355 paddr = mem->memory[i];
357 k < hp->io_pages_per_kpage;
358 k++, j++, paddr += hp->io_page_size) {
359 hp->gatt[j] = agp_bridge->driver->mask_memory(paddr, type);
363 agp_bridge->driver->tlb_flush(mem);
368 hp_zx1_remove_memory (struct agp_memory *mem, off_t pg_start, int type)
370 struct _hp_private *hp = &hp_private;
371 int i, io_pg_start, io_pg_count;
373 if (type != 0 || mem->type != 0) {
377 io_pg_start = hp->io_pages_per_kpage * pg_start;
378 io_pg_count = hp->io_pages_per_kpage * mem->page_count;
379 for (i = io_pg_start; i < io_pg_count + io_pg_start; i++) {
380 hp->gatt[i] = agp_bridge->scratch_page;
383 agp_bridge->driver->tlb_flush(mem);
388 hp_zx1_mask_memory (unsigned long addr, int type)
390 return HP_ZX1_PDIR_VALID_BIT | addr;
394 hp_zx1_enable (u32 mode)
396 struct _hp_private *hp = &hp_private;
399 command = INREG32(hp->lba_regs, hp->lba_cap_offset + PCI_AGP_STATUS);
401 command = agp_collect_device_status(mode, command);
402 command |= 0x00000100;
404 OUTREG32(hp->lba_regs, hp->lba_cap_offset + PCI_AGP_COMMAND, command);
406 agp_device_command(command, (mode & AGP8X_MODE) != 0);
409 struct agp_bridge_driver hp_zx1_driver = {
410 .owner = THIS_MODULE,
411 .size_type = FIXED_APER_SIZE,
412 .configure = hp_zx1_configure,
413 .fetch_size = hp_zx1_fetch_size,
414 .cleanup = hp_zx1_cleanup,
415 .tlb_flush = hp_zx1_tlbflush,
416 .mask_memory = hp_zx1_mask_memory,
417 .masks = hp_zx1_masks,
418 .agp_enable = hp_zx1_enable,
419 .cache_flush = global_cache_flush,
420 .create_gatt_table = hp_zx1_create_gatt_table,
421 .free_gatt_table = hp_zx1_free_gatt_table,
422 .insert_memory = hp_zx1_insert_memory,
423 .remove_memory = hp_zx1_remove_memory,
424 .alloc_by_type = agp_generic_alloc_by_type,
425 .free_by_type = agp_generic_free_by_type,
426 .agp_alloc_page = agp_generic_alloc_page,
427 .agp_destroy_page = agp_generic_destroy_page,
428 .cant_use_aperture = 1,
432 hp_zx1_setup (u64 ioc_hpa, u64 lba_hpa)
434 struct agp_bridge_data *bridge;
437 error = hp_zx1_ioc_init(ioc_hpa);
441 error = hp_zx1_lba_init(lba_hpa);
445 bridge = agp_alloc_bridge();
450 bridge->driver = &hp_zx1_driver;
452 fake_bridge_dev.vendor = PCI_VENDOR_ID_HP;
453 fake_bridge_dev.device = PCI_DEVICE_ID_HP_PCIX_LBA;
454 bridge->dev = &fake_bridge_dev;
456 error = agp_add_bridge(bridge);
463 static acpi_status __init
464 zx1_gart_probe (acpi_handle obj, u32 depth, void *context, void **ret)
466 acpi_handle handle, parent;
468 struct acpi_buffer buffer;
469 struct acpi_device_info *info;
470 u64 lba_hpa, sba_hpa, length;
473 status = hp_acpi_csr_space(obj, &lba_hpa, &length);
474 if (ACPI_FAILURE(status))
475 return AE_OK; /* keep looking for another bridge */
477 /* Look for an enclosing IOC scope and find its CSR space */
480 buffer.length = ACPI_ALLOCATE_LOCAL_BUFFER;
481 status = acpi_get_object_info(handle, &buffer);
482 if (ACPI_SUCCESS(status)) {
483 /* TBD check _CID also */
484 info = buffer.pointer;
485 info->hardware_id.value[sizeof(info->hardware_id)-1] = '\0';
486 match = (strcmp(info->hardware_id.value, "HWP0001") == 0);
489 status = hp_acpi_csr_space(handle, &sba_hpa, &length);
490 if (ACPI_SUCCESS(status))
493 printk(KERN_ERR PFX "Detected HP ZX1 "
494 "AGP LBA but no IOC.\n");
500 status = acpi_get_parent(handle, &parent);
502 } while (ACPI_SUCCESS(status));
504 if (hp_zx1_setup(sba_hpa + HP_ZX1_IOC_OFFSET, lba_hpa))
507 printk(KERN_INFO PFX "Detected HP ZX1 %s AGP chipset (ioc=%lx, lba=%lx)\n",
508 (char *) context, sba_hpa + HP_ZX1_IOC_OFFSET, lba_hpa);
510 hp_zx1_gart_found = 1;
511 return AE_CTRL_TERMINATE; /* we only support one bridge; quit looking */
518 acpi_get_devices("HWP0003", zx1_gart_probe, "HWP0003", NULL);
519 if (hp_zx1_gart_found)
522 acpi_get_devices("HWP0007", zx1_gart_probe, "HWP0007", NULL);
523 if (hp_zx1_gart_found)
530 agp_hp_cleanup (void)
534 module_init(agp_hp_init);
535 module_exit(agp_hp_cleanup);
537 MODULE_LICENSE("GPL and additional rights");