2 * Serverworks AGPGART routines.
5 #include <linux/module.h>
7 #include <linux/init.h>
8 #include <linux/agp_backend.h>
11 #define SVWRKS_COMMAND 0x04
12 #define SVWRKS_APSIZE 0x10
13 #define SVWRKS_MMBASE 0x14
14 #define SVWRKS_CACHING 0x4b
15 #define SVWRKS_AGP_ENABLE 0x60
16 #define SVWRKS_FEATURE 0x68
18 #define SVWRKS_SIZE_MASK 0xfe000000
20 /* Memory mapped registers */
21 #define SVWRKS_GART_CACHE 0x02
22 #define SVWRKS_GATTBASE 0x04
23 #define SVWRKS_TLBFLUSH 0x10
24 #define SVWRKS_POSTFLUSH 0x14
25 #define SVWRKS_DIRFLUSH 0x0c
28 struct serverworks_page_map {
30 unsigned long *remapped;
33 static struct _serverworks_private {
34 struct pci_dev *svrwrks_dev; /* device one */
35 volatile u8 *registers;
36 struct serverworks_page_map **gatt_pages;
38 struct serverworks_page_map scratch_dir;
42 } serverworks_private;
44 static int serverworks_create_page_map(struct serverworks_page_map *page_map)
48 page_map->real = (unsigned long *) __get_free_page(GFP_KERNEL);
49 if (page_map->real == NULL) {
52 SetPageReserved(virt_to_page(page_map->real));
54 page_map->remapped = ioremap_nocache(virt_to_phys(page_map->real),
56 if (page_map->remapped == NULL) {
57 ClearPageReserved(virt_to_page(page_map->real));
58 free_page((unsigned long) page_map->real);
59 page_map->real = NULL;
64 for(i = 0; i < PAGE_SIZE / sizeof(unsigned long); i++) {
65 page_map->remapped[i] = agp_bridge->scratch_page;
71 static void serverworks_free_page_map(struct serverworks_page_map *page_map)
73 iounmap(page_map->remapped);
74 ClearPageReserved(virt_to_page(page_map->real));
75 free_page((unsigned long) page_map->real);
78 static void serverworks_free_gatt_pages(void)
81 struct serverworks_page_map **tables;
82 struct serverworks_page_map *entry;
84 tables = serverworks_private.gatt_pages;
85 for(i = 0; i < serverworks_private.num_tables; i++) {
88 if (entry->real != NULL) {
89 serverworks_free_page_map(entry);
97 static int serverworks_create_gatt_pages(int nr_tables)
99 struct serverworks_page_map **tables;
100 struct serverworks_page_map *entry;
104 tables = kmalloc((nr_tables + 1) * sizeof(struct serverworks_page_map *),
106 if (tables == NULL) {
109 memset(tables, 0, sizeof(struct serverworks_page_map *) * (nr_tables + 1));
110 for (i = 0; i < nr_tables; i++) {
111 entry = kmalloc(sizeof(struct serverworks_page_map), GFP_KERNEL);
116 memset(entry, 0, sizeof(struct serverworks_page_map));
118 retval = serverworks_create_page_map(entry);
119 if (retval != 0) break;
121 serverworks_private.num_tables = nr_tables;
122 serverworks_private.gatt_pages = tables;
124 if (retval != 0) serverworks_free_gatt_pages();
129 #define SVRWRKS_GET_GATT(addr) (serverworks_private.gatt_pages[\
130 GET_PAGE_DIR_IDX(addr)]->remapped)
132 #ifndef GET_PAGE_DIR_OFF
133 #define GET_PAGE_DIR_OFF(addr) (addr >> 22)
136 #ifndef GET_PAGE_DIR_IDX
137 #define GET_PAGE_DIR_IDX(addr) (GET_PAGE_DIR_OFF(addr) - \
138 GET_PAGE_DIR_OFF(agp_bridge->gart_bus_addr))
142 #define GET_GATT_OFF(addr) ((addr & 0x003ff000) >> 12)
145 static int serverworks_create_gatt_table(void)
147 struct aper_size_info_lvl2 *value;
148 struct serverworks_page_map page_dir;
153 value = A_SIZE_LVL2(agp_bridge->current_size);
154 retval = serverworks_create_page_map(&page_dir);
158 retval = serverworks_create_page_map(&serverworks_private.scratch_dir);
160 serverworks_free_page_map(&page_dir);
163 /* Create a fake scratch directory */
164 for(i = 0; i < 1024; i++) {
165 serverworks_private.scratch_dir.remapped[i] = (unsigned long) agp_bridge->scratch_page;
166 page_dir.remapped[i] =
167 virt_to_phys(serverworks_private.scratch_dir.real);
168 page_dir.remapped[i] |= 0x00000001;
171 retval = serverworks_create_gatt_pages(value->num_entries / 1024);
173 serverworks_free_page_map(&page_dir);
174 serverworks_free_page_map(&serverworks_private.scratch_dir);
178 agp_bridge->gatt_table_real = (u32 *)page_dir.real;
179 agp_bridge->gatt_table = (u32 *)page_dir.remapped;
180 agp_bridge->gatt_bus_addr = virt_to_phys(page_dir.real);
182 /* Get the address for the gart region.
183 * This is a bus address even on the alpha, b/c its
184 * used to program the agp master not the cpu
187 pci_read_config_dword(agp_bridge->dev,serverworks_private.gart_addr_ofs,&temp);
188 agp_bridge->gart_bus_addr = (temp & PCI_BASE_ADDRESS_MEM_MASK);
190 /* Calculate the agp offset */
192 for(i = 0; i < value->num_entries / 1024; i++) {
193 page_dir.remapped[i] =
194 virt_to_phys(serverworks_private.gatt_pages[i]->real);
195 page_dir.remapped[i] |= 0x00000001;
201 static int serverworks_free_gatt_table(void)
203 struct serverworks_page_map page_dir;
205 page_dir.real = (unsigned long *)agp_bridge->gatt_table_real;
206 page_dir.remapped = (unsigned long *)agp_bridge->gatt_table;
208 serverworks_free_gatt_pages();
209 serverworks_free_page_map(&page_dir);
210 serverworks_free_page_map(&serverworks_private.scratch_dir);
214 static int serverworks_fetch_size(void)
219 struct aper_size_info_lvl2 *values;
221 values = A_SIZE_LVL2(agp_bridge->driver->aperture_sizes);
222 pci_read_config_dword(agp_bridge->dev,serverworks_private.gart_addr_ofs,&temp);
223 pci_write_config_dword(agp_bridge->dev,serverworks_private.gart_addr_ofs,
225 pci_read_config_dword(agp_bridge->dev,serverworks_private.gart_addr_ofs,&temp2);
226 pci_write_config_dword(agp_bridge->dev,serverworks_private.gart_addr_ofs,temp);
227 temp2 &= SVWRKS_SIZE_MASK;
229 for (i = 0; i < agp_bridge->driver->num_aperture_sizes; i++) {
230 if (temp2 == values[i].size_value) {
231 agp_bridge->previous_size =
232 agp_bridge->current_size = (void *) (values + i);
234 agp_bridge->aperture_size_idx = i;
235 return values[i].size;
243 * This routine could be implemented by taking the addresses
244 * written to the GATT, and flushing them individually. However
245 * currently it just flushes the whole table. Which is probably
246 * more efficent, since agp_memory blocks can be a large number of
249 static void serverworks_tlbflush(struct agp_memory *temp)
253 OUTREG8(serverworks_private.registers, SVWRKS_POSTFLUSH, 0x01);
254 end = jiffies + 3*HZ;
255 while(INREG8(serverworks_private.registers,
256 SVWRKS_POSTFLUSH) == 0x01) {
257 if((signed)(end - jiffies) <= 0) {
258 printk(KERN_ERR PFX "Posted write buffer flush took more"
262 OUTREG32(serverworks_private.registers, SVWRKS_DIRFLUSH, 0x00000001);
263 end = jiffies + 3*HZ;
264 while(INREG32(serverworks_private.registers,
265 SVWRKS_DIRFLUSH) == 0x00000001) {
266 if((signed)(end - jiffies) <= 0) {
267 printk(KERN_ERR PFX "TLB flush took more"
273 static int serverworks_configure(void)
275 struct aper_size_info_lvl2 *current_size;
280 current_size = A_SIZE_LVL2(agp_bridge->current_size);
282 /* Get the memory mapped registers */
283 pci_read_config_dword(agp_bridge->dev, serverworks_private.mm_addr_ofs, &temp);
284 temp = (temp & PCI_BASE_ADDRESS_MEM_MASK);
285 serverworks_private.registers = (volatile u8 *) ioremap(temp, 4096);
286 if (!serverworks_private.registers) {
287 printk (KERN_ERR PFX "Unable to ioremap() memory.\n");
291 OUTREG8(serverworks_private.registers, SVWRKS_GART_CACHE, 0x0a);
293 OUTREG32(serverworks_private.registers, SVWRKS_GATTBASE,
294 agp_bridge->gatt_bus_addr);
296 cap_reg = INREG16(serverworks_private.registers, SVWRKS_COMMAND);
299 OUTREG16(serverworks_private.registers, SVWRKS_COMMAND, cap_reg);
301 pci_read_config_byte(serverworks_private.svrwrks_dev,
302 SVWRKS_AGP_ENABLE, &enable_reg);
303 enable_reg |= 0x1; /* Agp Enable bit */
304 pci_write_config_byte(serverworks_private.svrwrks_dev,
305 SVWRKS_AGP_ENABLE, enable_reg);
306 serverworks_tlbflush(NULL);
308 agp_bridge->capndx = pci_find_capability(serverworks_private.svrwrks_dev, PCI_CAP_ID_AGP);
310 /* Fill in the mode register */
311 pci_read_config_dword(serverworks_private.svrwrks_dev,
312 agp_bridge->capndx+PCI_AGP_STATUS, &agp_bridge->mode);
314 pci_read_config_byte(agp_bridge->dev, SVWRKS_CACHING, &enable_reg);
316 pci_write_config_byte(agp_bridge->dev, SVWRKS_CACHING, enable_reg);
318 pci_read_config_byte(agp_bridge->dev, SVWRKS_FEATURE, &enable_reg);
319 enable_reg |= (1<<6);
320 pci_write_config_byte(agp_bridge->dev,SVWRKS_FEATURE, enable_reg);
325 static void serverworks_cleanup(void)
327 iounmap((void *) serverworks_private.registers);
330 static int serverworks_insert_memory(struct agp_memory *mem,
331 off_t pg_start, int type)
333 int i, j, num_entries;
334 unsigned long *cur_gatt;
337 num_entries = A_SIZE_LVL2(agp_bridge->current_size)->num_entries;
339 if (type != 0 || mem->type != 0) {
342 if ((pg_start + mem->page_count) > num_entries) {
347 while (j < (pg_start + mem->page_count)) {
348 addr = (j * PAGE_SIZE) + agp_bridge->gart_bus_addr;
349 cur_gatt = SVRWRKS_GET_GATT(addr);
350 if (!PGE_EMPTY(agp_bridge, cur_gatt[GET_GATT_OFF(addr)])) {
356 if (mem->is_flushed == FALSE) {
357 global_cache_flush();
358 mem->is_flushed = TRUE;
361 for (i = 0, j = pg_start; i < mem->page_count; i++, j++) {
362 addr = (j * PAGE_SIZE) + agp_bridge->gart_bus_addr;
363 cur_gatt = SVRWRKS_GET_GATT(addr);
364 cur_gatt[GET_GATT_OFF(addr)] =
365 agp_bridge->driver->mask_memory(mem->memory[i], mem->type);
367 serverworks_tlbflush(mem);
371 static int serverworks_remove_memory(struct agp_memory *mem, off_t pg_start,
375 unsigned long *cur_gatt;
378 if (type != 0 || mem->type != 0) {
382 global_cache_flush();
383 serverworks_tlbflush(mem);
385 for (i = pg_start; i < (mem->page_count + pg_start); i++) {
386 addr = (i * PAGE_SIZE) + agp_bridge->gart_bus_addr;
387 cur_gatt = SVRWRKS_GET_GATT(addr);
388 cur_gatt[GET_GATT_OFF(addr)] =
389 (unsigned long) agp_bridge->scratch_page;
392 serverworks_tlbflush(mem);
396 static struct gatt_mask serverworks_masks[] =
398 {.mask = 1, .type = 0}
401 static struct aper_size_info_lvl2 serverworks_sizes[7] =
403 {2048, 524288, 0x80000000},
404 {1024, 262144, 0xc0000000},
405 {512, 131072, 0xe0000000},
406 {256, 65536, 0xf0000000},
407 {128, 32768, 0xf8000000},
408 {64, 16384, 0xfc000000},
409 {32, 8192, 0xfe000000}
412 static void serverworks_agp_enable(u32 mode)
416 pci_read_config_dword(serverworks_private.svrwrks_dev,
417 agp_bridge->capndx + PCI_AGP_STATUS,
420 command = agp_collect_device_status(mode, command);
422 command &= ~0x10; /* disable FW */
427 pci_write_config_dword(serverworks_private.svrwrks_dev,
428 agp_bridge->capndx + PCI_AGP_COMMAND,
431 agp_device_command(command, 0);
434 struct agp_bridge_driver sworks_driver = {
435 .owner = THIS_MODULE,
436 .aperture_sizes = serverworks_sizes,
437 .size_type = LVL2_APER_SIZE,
438 .num_aperture_sizes = 7,
439 .configure = serverworks_configure,
440 .fetch_size = serverworks_fetch_size,
441 .cleanup = serverworks_cleanup,
442 .tlb_flush = serverworks_tlbflush,
443 .mask_memory = agp_generic_mask_memory,
444 .masks = serverworks_masks,
445 .agp_enable = serverworks_agp_enable,
446 .cache_flush = global_cache_flush,
447 .create_gatt_table = serverworks_create_gatt_table,
448 .free_gatt_table = serverworks_free_gatt_table,
449 .insert_memory = serverworks_insert_memory,
450 .remove_memory = serverworks_remove_memory,
451 .alloc_by_type = agp_generic_alloc_by_type,
452 .free_by_type = agp_generic_free_by_type,
453 .agp_alloc_page = agp_generic_alloc_page,
454 .agp_destroy_page = agp_generic_destroy_page,
457 static int __devinit agp_serverworks_probe(struct pci_dev *pdev,
458 const struct pci_device_id *ent)
460 struct agp_bridge_data *bridge;
461 struct pci_dev *bridge_dev;
464 /* Everything is on func 1 here so we are hardcoding function one */
465 bridge_dev = pci_find_slot((unsigned int)pdev->bus->number,
468 printk(KERN_INFO PFX "Detected a Serverworks chipset "
469 "but could not find the secondary device.\n");
473 switch (pdev->device) {
475 /* ServerWorks CNB20HE
477 printk (KERN_ERR PFX "Detected ServerWorks CNB20HE chipset: No AGP present.\n");
480 case PCI_DEVICE_ID_SERVERWORKS_HE:
481 case PCI_DEVICE_ID_SERVERWORKS_LE:
486 printk(KERN_ERR PFX "Unsupported Serverworks chipset "
487 "(device id: %04x)\n", pdev->device);
491 serverworks_private.svrwrks_dev = bridge_dev;
492 serverworks_private.gart_addr_ofs = 0x10;
494 pci_read_config_dword(pdev, SVWRKS_APSIZE, &temp);
495 if (temp & PCI_BASE_ADDRESS_MEM_TYPE_64) {
496 pci_read_config_dword(pdev, SVWRKS_APSIZE + 4, &temp2);
498 printk(KERN_INFO PFX "Detected 64 bit aperture address, "
499 "but top bits are not zero. Disabling agp\n");
502 serverworks_private.mm_addr_ofs = 0x18;
504 serverworks_private.mm_addr_ofs = 0x14;
506 pci_read_config_dword(pdev, serverworks_private.mm_addr_ofs, &temp);
507 if (temp & PCI_BASE_ADDRESS_MEM_TYPE_64) {
508 pci_read_config_dword(pdev,
509 serverworks_private.mm_addr_ofs + 4, &temp2);
511 printk(KERN_INFO PFX "Detected 64 bit MMIO address, "
512 "but top bits are not zero. Disabling agp\n");
517 bridge = agp_alloc_bridge();
521 bridge->driver = &sworks_driver;
522 bridge->dev_private_data = &serverworks_private,
525 pci_set_drvdata(pdev, bridge);
526 return agp_add_bridge(bridge);
529 static void __devexit agp_serverworks_remove(struct pci_dev *pdev)
531 struct agp_bridge_data *bridge = pci_get_drvdata(pdev);
533 agp_remove_bridge(bridge);
534 agp_put_bridge(bridge);
537 static struct pci_device_id agp_serverworks_pci_table[] = {
539 .class = (PCI_CLASS_BRIDGE_HOST << 8),
541 .vendor = PCI_VENDOR_ID_SERVERWORKS,
542 .device = PCI_ANY_ID,
543 .subvendor = PCI_ANY_ID,
544 .subdevice = PCI_ANY_ID,
549 MODULE_DEVICE_TABLE(pci, agp_serverworks_pci_table);
551 static struct pci_driver agp_serverworks_pci_driver = {
552 .name = "agpgart-serverworks",
553 .id_table = agp_serverworks_pci_table,
554 .probe = agp_serverworks_probe,
555 .remove = agp_serverworks_remove,
558 static int __init agp_serverworks_init(void)
560 return pci_module_init(&agp_serverworks_pci_driver);
563 static void __exit agp_serverworks_cleanup(void)
565 pci_unregister_driver(&agp_serverworks_pci_driver);
568 module_init(agp_serverworks_init);
569 module_exit(agp_serverworks_cleanup);
571 MODULE_LICENSE("GPL and additional rights");