1 /* i810_drv.h -- Private header for the Matrox g200/g400 driver -*- linux-c -*-
2 * Created: Mon Dec 13 01:50:01 1999 by jhartmann@precisioninsight.com
4 * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas.
5 * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California.
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
23 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
24 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
25 * DEALINGS IN THE SOFTWARE.
27 * Authors: Rickard E. (Rik) Faith <faith@valinux.com>
28 * Jeff Hartmann <jhartmann@valinux.com>
35 typedef struct drm_i810_buf_priv {
41 } drm_i810_buf_priv_t;
43 typedef struct _drm_i810_ring_buffer{
52 } drm_i810_ring_buffer_t;
54 typedef struct drm_i810_private {
56 drm_map_t *buffer_map;
59 drm_i810_sarea_t *sarea_priv;
60 drm_i810_ring_buffer_t ring;
63 unsigned long counter;
65 dma_addr_t dma_status_page;
67 drm_buf_t *mmap_buffer;
70 u32 front_di1, back_di1, zi1;
87 wait_queue_head_t irq_queue;
88 atomic_t irq_received;
95 extern int i810_dma_schedule(drm_device_t *dev, int locked);
96 extern int i810_getbuf(struct inode *inode, struct file *filp,
97 unsigned int cmd, unsigned long arg);
98 extern int i810_dma_init(struct inode *inode, struct file *filp,
99 unsigned int cmd, unsigned long arg);
100 extern int i810_dma_cleanup(drm_device_t *dev);
101 extern int i810_flush_ioctl(struct inode *inode, struct file *filp,
102 unsigned int cmd, unsigned long arg);
103 extern void i810_reclaim_buffers(struct file *filp);
104 extern int i810_getage(struct inode *inode, struct file *filp,
105 unsigned int cmd, unsigned long arg);
106 extern int i810_mmap_buffers(struct file *filp, struct vm_area_struct *vma);
110 extern int i810_copybuf(struct inode *inode, struct file *filp,
111 unsigned int cmd, unsigned long arg);
114 extern int i810_docopy(struct inode *inode, struct file *filp,
115 unsigned int cmd, unsigned long arg);
117 extern int i810_rstatus(struct inode *inode, struct file *filp,
118 unsigned int cmd, unsigned long arg);
119 extern int i810_ov0_info(struct inode *inode, struct file *filp,
120 unsigned int cmd, unsigned long arg);
121 extern int i810_fstatus(struct inode *inode, struct file *filp,
122 unsigned int cmd, unsigned long arg);
123 extern int i810_ov0_flip(struct inode *inode, struct file *filp,
124 unsigned int cmd, unsigned long arg);
125 extern int i810_dma_mc(struct inode *inode, struct file *filp,
126 unsigned int cmd, unsigned long arg);
129 extern void i810_dma_quiescent(drm_device_t *dev);
131 int i810_dma_vertex(struct inode *inode, struct file *filp,
132 unsigned int cmd, unsigned long arg);
134 int i810_swap_bufs(struct inode *inode, struct file *filp,
135 unsigned int cmd, unsigned long arg);
137 int i810_clear_bufs(struct inode *inode, struct file *filp,
138 unsigned int cmd, unsigned long arg);
140 int i810_flip_bufs(struct inode *inode, struct file *filp,
141 unsigned int cmd, unsigned long arg);
143 #define I810_BASE(reg) ((unsigned long) \
144 dev_priv->mmio_map->handle)
145 #define I810_ADDR(reg) (I810_BASE(reg) + reg)
146 #define I810_DEREF(reg) *(__volatile__ int *)I810_ADDR(reg)
147 #define I810_READ(reg) I810_DEREF(reg)
148 #define I810_WRITE(reg,val) do { I810_DEREF(reg) = val; } while (0)
149 #define I810_DEREF16(reg) *(__volatile__ u16 *)I810_ADDR(reg)
150 #define I810_READ16(reg) I810_DEREF16(reg)
151 #define I810_WRITE16(reg,val) do { I810_DEREF16(reg) = val; } while (0)
153 #define I810_VERBOSE 0
154 #define RING_LOCALS unsigned int outring, ringmask; \
157 #define BEGIN_LP_RING(n) do { \
159 DRM_DEBUG("BEGIN_LP_RING(%d) in %s\n", n, __FUNCTION__); \
160 if (dev_priv->ring.space < n*4) \
161 i810_wait_ring(dev, n*4); \
162 dev_priv->ring.space -= n*4; \
163 outring = dev_priv->ring.tail; \
164 ringmask = dev_priv->ring.tail_mask; \
165 virt = dev_priv->ring.virtual_start; \
168 #define ADVANCE_LP_RING() do { \
169 if (I810_VERBOSE) DRM_DEBUG("ADVANCE_LP_RING\n"); \
170 dev_priv->ring.tail = outring; \
171 I810_WRITE(LP_RING + RING_TAIL, outring); \
174 #define OUT_RING(n) do { \
175 if (I810_VERBOSE) DRM_DEBUG(" OUT_RING %x\n", (int)(n)); \
176 *(volatile unsigned int *)(virt + outring) = n; \
178 outring &= ringmask; \
181 #define GFX_OP_USER_INTERRUPT ((0<<29)|(2<<23))
182 #define GFX_OP_BREAKPOINT_INTERRUPT ((0<<29)|(1<<23))
183 #define CMD_REPORT_HEAD (7<<23)
184 #define CMD_STORE_DWORD_IDX ((0x21<<23) | 0x1)
185 #define CMD_OP_BATCH_BUFFER ((0x0<<29)|(0x30<<23)|0x1)
187 #define INST_PARSER_CLIENT 0x00000000
188 #define INST_OP_FLUSH 0x02000000
189 #define INST_FLUSH_MAP_CACHE 0x00000001
192 #define BB1_START_ADDR_MASK (~0x7)
193 #define BB1_PROTECTED (1<<0)
194 #define BB1_UNPROTECTED (0<<0)
195 #define BB2_END_ADDR_MASK (~0x7)
197 #define I810REG_HWSTAM 0x02098
198 #define I810REG_INT_IDENTITY_R 0x020a4
199 #define I810REG_INT_MASK_R 0x020a8
200 #define I810REG_INT_ENABLE_R 0x020a0
202 #define LP_RING 0x2030
203 #define HP_RING 0x2040
204 #define RING_TAIL 0x00
205 #define TAIL_ADDR 0x000FFFF8
206 #define RING_HEAD 0x04
207 #define HEAD_WRAP_COUNT 0xFFE00000
208 #define HEAD_WRAP_ONE 0x00200000
209 #define HEAD_ADDR 0x001FFFFC
210 #define RING_START 0x08
211 #define START_ADDR 0x00FFFFF8
212 #define RING_LEN 0x0C
213 #define RING_NR_PAGES 0x000FF000
214 #define RING_REPORT_MASK 0x00000006
215 #define RING_REPORT_64K 0x00000002
216 #define RING_REPORT_128K 0x00000004
217 #define RING_NO_REPORT 0x00000000
218 #define RING_VALID_MASK 0x00000001
219 #define RING_VALID 0x00000001
220 #define RING_INVALID 0x00000000
222 #define GFX_OP_SCISSOR ((0x3<<29)|(0x1c<<24)|(0x10<<19))
223 #define SC_UPDATE_SCISSOR (0x1<<1)
224 #define SC_ENABLE_MASK (0x1<<0)
225 #define SC_ENABLE (0x1<<0)
227 #define GFX_OP_SCISSOR_INFO ((0x3<<29)|(0x1d<<24)|(0x81<<16)|(0x1))
228 #define SCI_YMIN_MASK (0xffff<<16)
229 #define SCI_XMIN_MASK (0xffff<<0)
230 #define SCI_YMAX_MASK (0xffff<<16)
231 #define SCI_XMAX_MASK (0xffff<<0)
233 #define GFX_OP_COLOR_FACTOR ((0x3<<29)|(0x1d<<24)|(0x1<<16)|0x0)
234 #define GFX_OP_STIPPLE ((0x3<<29)|(0x1d<<24)|(0x83<<16))
235 #define GFX_OP_MAP_INFO ((0x3<<29)|(0x1d<<24)|0x2)
236 #define GFX_OP_DESTBUFFER_VARS ((0x3<<29)|(0x1d<<24)|(0x85<<16)|0x0)
237 #define GFX_OP_DRAWRECT_INFO ((0x3<<29)|(0x1d<<24)|(0x80<<16)|(0x3))
238 #define GFX_OP_PRIMITIVE ((0x3<<29)|(0x1f<<24))
240 #define CMD_OP_Z_BUFFER_INFO ((0x0<<29)|(0x16<<23))
241 #define CMD_OP_DESTBUFFER_INFO ((0x0<<29)|(0x15<<23))
242 #define CMD_OP_FRONTBUFFER_INFO ((0x0<<29)|(0x14<<23))
243 #define CMD_OP_WAIT_FOR_EVENT ((0x0<<29)|(0x03<<23))
245 #define BR00_BITBLT_CLIENT 0x40000000
246 #define BR00_OP_COLOR_BLT 0x10000000
247 #define BR00_OP_SRC_COPY_BLT 0x10C00000
248 #define BR13_SOLID_PATTERN 0x80000000
250 #define WAIT_FOR_PLANE_A_SCANLINES (1<<1)
251 #define WAIT_FOR_PLANE_A_FLIP (1<<2)
252 #define WAIT_FOR_VBLANK (1<<3)