1 /* i830_dma.c -- DMA support for the I830 -*- linux-c -*-
2 * Created: Mon Dec 13 01:50:01 1999 by jhartmann@precisioninsight.com
4 * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas.
5 * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California.
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
23 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
24 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
25 * DEALINGS IN THE SOFTWARE.
27 * Authors: Rickard E. (Rik) Faith <faith@valinux.com>
28 * Jeff Hartmann <jhartmann@valinux.com>
29 * Keith Whitwell <keith@tungstengraphics.com>
30 * Abraham vd Merwe <abraham@2d3d.co.za>
39 #include <linux/interrupt.h> /* For task queue support */
40 #include <linux/pagemap.h> /* For FASTCALL on unlock_page() */
41 #include <linux/delay.h>
42 #include <asm/uaccess.h>
44 #define I830_BUF_FREE 2
45 #define I830_BUF_CLIENT 1
46 #define I830_BUF_HARDWARE 0
48 #define I830_BUF_UNMAPPED 0
49 #define I830_BUF_MAPPED 1
51 #if LINUX_VERSION_CODE <= KERNEL_VERSION(2,4,2)
52 #define down_write down
56 static inline void i830_print_status_page(drm_device_t *dev)
58 drm_device_dma_t *dma = dev->dma;
59 drm_i830_private_t *dev_priv = dev->dev_private;
60 u32 *temp = dev_priv->hw_status_page;
63 DRM_DEBUG( "hw_status: Interrupt Status : %x\n", temp[0]);
64 DRM_DEBUG( "hw_status: LpRing Head ptr : %x\n", temp[1]);
65 DRM_DEBUG( "hw_status: IRing Head ptr : %x\n", temp[2]);
66 DRM_DEBUG( "hw_status: Reserved : %x\n", temp[3]);
67 DRM_DEBUG( "hw_status: Driver Counter : %d\n", temp[5]);
68 for(i = 9; i < dma->buf_count + 9; i++) {
69 DRM_DEBUG( "buffer status idx : %d used: %d\n", i - 9, temp[i]);
73 static drm_buf_t *i830_freelist_get(drm_device_t *dev)
75 drm_device_dma_t *dma = dev->dma;
79 /* Linear search might not be the best solution */
81 for (i = 0; i < dma->buf_count; i++) {
82 drm_buf_t *buf = dma->buflist[ i ];
83 drm_i830_buf_priv_t *buf_priv = buf->dev_private;
84 /* In use is already a pointer */
85 used = cmpxchg(buf_priv->in_use, I830_BUF_FREE,
87 if(used == I830_BUF_FREE) {
94 /* This should only be called if the buffer is not sent to the hardware
95 * yet, the hardware updates in use for us once its on the ring buffer.
98 static int i830_freelist_put(drm_device_t *dev, drm_buf_t *buf)
100 drm_i830_buf_priv_t *buf_priv = buf->dev_private;
103 /* In use is already a pointer */
104 used = cmpxchg(buf_priv->in_use, I830_BUF_CLIENT, I830_BUF_FREE);
105 if(used != I830_BUF_CLIENT) {
106 DRM_ERROR("Freeing buffer thats not in use : %d\n", buf->idx);
113 static struct file_operations i830_buffer_fops = {
116 .release = DRM(release),
118 .mmap = i830_mmap_buffers,
119 .fasync = DRM(fasync),
122 int i830_mmap_buffers(struct file *filp, struct vm_area_struct *vma)
124 drm_file_t *priv = filp->private_data;
126 drm_i830_private_t *dev_priv;
128 drm_i830_buf_priv_t *buf_priv;
132 dev_priv = dev->dev_private;
133 buf = dev_priv->mmap_buffer;
134 buf_priv = buf->dev_private;
136 vma->vm_flags |= (VM_IO | VM_DONTCOPY);
139 buf_priv->currently_mapped = I830_BUF_MAPPED;
142 if (remap_pfn_range(DRM_RPR_ARG(vma) vma->vm_start,
143 VM_OFFSET(vma) >> PAGE_SHIFT,
144 vma->vm_end - vma->vm_start,
145 vma->vm_page_prot)) return -EAGAIN;
149 static int i830_map_buffer(drm_buf_t *buf, struct file *filp)
151 drm_file_t *priv = filp->private_data;
152 drm_device_t *dev = priv->dev;
153 drm_i830_buf_priv_t *buf_priv = buf->dev_private;
154 drm_i830_private_t *dev_priv = dev->dev_private;
155 struct file_operations *old_fops;
156 unsigned long virtual;
159 if(buf_priv->currently_mapped == I830_BUF_MAPPED) return -EINVAL;
161 down_write( ¤t->mm->mmap_sem );
162 old_fops = filp->f_op;
163 filp->f_op = &i830_buffer_fops;
164 dev_priv->mmap_buffer = buf;
165 virtual = do_mmap(filp, 0, buf->total, PROT_READ|PROT_WRITE,
166 MAP_SHARED, buf->bus_address);
167 dev_priv->mmap_buffer = NULL;
168 filp->f_op = old_fops;
169 if (IS_ERR((void *)virtual)) { /* ugh */
171 DRM_ERROR("mmap error\n");
173 buf_priv->virtual = NULL;
175 buf_priv->virtual = (void __user *)virtual;
177 up_write( ¤t->mm->mmap_sem );
182 static int i830_unmap_buffer(drm_buf_t *buf)
184 drm_i830_buf_priv_t *buf_priv = buf->dev_private;
187 if(buf_priv->currently_mapped != I830_BUF_MAPPED)
190 down_write(¤t->mm->mmap_sem);
191 retcode = do_munmap(current->mm,
192 (unsigned long)buf_priv->virtual,
193 (size_t) buf->total);
194 up_write(¤t->mm->mmap_sem);
196 buf_priv->currently_mapped = I830_BUF_UNMAPPED;
197 buf_priv->virtual = NULL;
202 static int i830_dma_get_buffer(drm_device_t *dev, drm_i830_dma_t *d,
206 drm_i830_buf_priv_t *buf_priv;
209 buf = i830_freelist_get(dev);
212 DRM_DEBUG("retcode=%d\n", retcode);
216 retcode = i830_map_buffer(buf, filp);
218 i830_freelist_put(dev, buf);
219 DRM_ERROR("mapbuf failed, retcode %d\n", retcode);
223 buf_priv = buf->dev_private;
225 d->request_idx = buf->idx;
226 d->request_size = buf->total;
227 d->virtual = buf_priv->virtual;
232 int i830_dma_cleanup(drm_device_t *dev)
234 drm_device_dma_t *dma = dev->dma;
236 /* Make sure interrupts are disabled here because the uninstall ioctl
237 * may not have been called from userspace and after dev_private
238 * is freed, it's too late.
240 if ( dev->irq_enabled ) DRM(irq_uninstall)(dev);
242 if (dev->dev_private) {
244 drm_i830_private_t *dev_priv =
245 (drm_i830_private_t *) dev->dev_private;
247 if (dev_priv->ring.virtual_start) {
248 DRM(ioremapfree)((void *) dev_priv->ring.virtual_start,
249 dev_priv->ring.Size, dev);
251 if (dev_priv->hw_status_page) {
252 pci_free_consistent(dev->pdev, PAGE_SIZE,
253 dev_priv->hw_status_page,
254 dev_priv->dma_status_page);
255 /* Need to rewrite hardware status page */
256 I830_WRITE(0x02080, 0x1ffff000);
259 DRM(free)(dev->dev_private, sizeof(drm_i830_private_t),
261 dev->dev_private = NULL;
263 for (i = 0; i < dma->buf_count; i++) {
264 drm_buf_t *buf = dma->buflist[ i ];
265 drm_i830_buf_priv_t *buf_priv = buf->dev_private;
266 if ( buf_priv->kernel_virtual && buf->total )
267 DRM(ioremapfree)(buf_priv->kernel_virtual, buf->total, dev);
273 int i830_wait_ring(drm_device_t *dev, int n, const char *caller)
275 drm_i830_private_t *dev_priv = dev->dev_private;
276 drm_i830_ring_buffer_t *ring = &(dev_priv->ring);
279 unsigned int last_head = I830_READ(LP_RING + RING_HEAD) & HEAD_ADDR;
281 end = jiffies + (HZ*3);
282 while (ring->space < n) {
283 ring->head = I830_READ(LP_RING + RING_HEAD) & HEAD_ADDR;
284 ring->space = ring->head - (ring->tail+8);
285 if (ring->space < 0) ring->space += ring->Size;
287 if (ring->head != last_head) {
288 end = jiffies + (HZ*3);
289 last_head = ring->head;
293 if(time_before(end, jiffies)) {
294 DRM_ERROR("space: %d wanted %d\n", ring->space, n);
295 DRM_ERROR("lockup\n");
299 dev_priv->sarea_priv->perf_boxes |= I830_BOX_WAIT;
306 static void i830_kernel_lost_context(drm_device_t *dev)
308 drm_i830_private_t *dev_priv = dev->dev_private;
309 drm_i830_ring_buffer_t *ring = &(dev_priv->ring);
311 ring->head = I830_READ(LP_RING + RING_HEAD) & HEAD_ADDR;
312 ring->tail = I830_READ(LP_RING + RING_TAIL) & TAIL_ADDR;
313 ring->space = ring->head - (ring->tail+8);
314 if (ring->space < 0) ring->space += ring->Size;
316 if (ring->head == ring->tail)
317 dev_priv->sarea_priv->perf_boxes |= I830_BOX_RING_EMPTY;
320 static int i830_freelist_init(drm_device_t *dev, drm_i830_private_t *dev_priv)
322 drm_device_dma_t *dma = dev->dma;
324 u32 *hw_status = (u32 *)(dev_priv->hw_status_page + my_idx);
327 if(dma->buf_count > 1019) {
328 /* Not enough space in the status page for the freelist */
332 for (i = 0; i < dma->buf_count; i++) {
333 drm_buf_t *buf = dma->buflist[ i ];
334 drm_i830_buf_priv_t *buf_priv = buf->dev_private;
336 buf_priv->in_use = hw_status++;
337 buf_priv->my_use_idx = my_idx;
340 *buf_priv->in_use = I830_BUF_FREE;
342 buf_priv->kernel_virtual = DRM(ioremap)(buf->bus_address,
348 static int i830_dma_initialize(drm_device_t *dev,
349 drm_i830_private_t *dev_priv,
350 drm_i830_init_t *init)
352 struct list_head *list;
354 memset(dev_priv, 0, sizeof(drm_i830_private_t));
356 list_for_each(list, &dev->maplist->head) {
357 drm_map_list_t *r_list = list_entry(list, drm_map_list_t, head);
359 r_list->map->type == _DRM_SHM &&
360 r_list->map->flags & _DRM_CONTAINS_LOCK ) {
361 dev_priv->sarea_map = r_list->map;
366 if(!dev_priv->sarea_map) {
367 dev->dev_private = (void *)dev_priv;
368 i830_dma_cleanup(dev);
369 DRM_ERROR("can not find sarea!\n");
372 dev_priv->mmio_map = drm_core_findmap(dev, init->mmio_offset);
373 if(!dev_priv->mmio_map) {
374 dev->dev_private = (void *)dev_priv;
375 i830_dma_cleanup(dev);
376 DRM_ERROR("can not find mmio map!\n");
379 dev->agp_buffer_map = drm_core_findmap(dev, init->buffers_offset);
380 if(!dev->agp_buffer_map) {
381 dev->dev_private = (void *)dev_priv;
382 i830_dma_cleanup(dev);
383 DRM_ERROR("can not find dma buffer map!\n");
387 dev_priv->sarea_priv = (drm_i830_sarea_t *)
388 ((u8 *)dev_priv->sarea_map->handle +
389 init->sarea_priv_offset);
391 dev_priv->ring.Start = init->ring_start;
392 dev_priv->ring.End = init->ring_end;
393 dev_priv->ring.Size = init->ring_size;
395 dev_priv->ring.virtual_start = DRM(ioremap)(dev->agp->base +
397 init->ring_size, dev);
399 if (dev_priv->ring.virtual_start == NULL) {
400 dev->dev_private = (void *) dev_priv;
401 i830_dma_cleanup(dev);
402 DRM_ERROR("can not ioremap virtual address for"
407 dev_priv->ring.tail_mask = dev_priv->ring.Size - 1;
409 dev_priv->w = init->w;
410 dev_priv->h = init->h;
411 dev_priv->pitch = init->pitch;
412 dev_priv->back_offset = init->back_offset;
413 dev_priv->depth_offset = init->depth_offset;
414 dev_priv->front_offset = init->front_offset;
416 dev_priv->front_di1 = init->front_offset | init->pitch_bits;
417 dev_priv->back_di1 = init->back_offset | init->pitch_bits;
418 dev_priv->zi1 = init->depth_offset | init->pitch_bits;
420 DRM_DEBUG("front_di1 %x\n", dev_priv->front_di1);
421 DRM_DEBUG("back_offset %x\n", dev_priv->back_offset);
422 DRM_DEBUG("back_di1 %x\n", dev_priv->back_di1);
423 DRM_DEBUG("pitch_bits %x\n", init->pitch_bits);
425 dev_priv->cpp = init->cpp;
426 /* We are using separate values as placeholders for mechanisms for
427 * private backbuffer/depthbuffer usage.
430 dev_priv->back_pitch = init->back_pitch;
431 dev_priv->depth_pitch = init->depth_pitch;
432 dev_priv->do_boxes = 0;
433 dev_priv->use_mi_batchbuffer_start = 0;
435 /* Program Hardware Status Page */
436 dev_priv->hw_status_page =
437 pci_alloc_consistent(dev->pdev, PAGE_SIZE,
438 &dev_priv->dma_status_page);
439 if (!dev_priv->hw_status_page) {
440 dev->dev_private = (void *)dev_priv;
441 i830_dma_cleanup(dev);
442 DRM_ERROR("Can not allocate hardware status page\n");
445 memset(dev_priv->hw_status_page, 0, PAGE_SIZE);
446 DRM_DEBUG("hw status page @ %p\n", dev_priv->hw_status_page);
448 I830_WRITE(0x02080, dev_priv->dma_status_page);
449 DRM_DEBUG("Enabled hardware status page\n");
451 /* Now we need to init our freelist */
452 if(i830_freelist_init(dev, dev_priv) != 0) {
453 dev->dev_private = (void *)dev_priv;
454 i830_dma_cleanup(dev);
455 DRM_ERROR("Not enough space in the status page for"
459 dev->dev_private = (void *)dev_priv;
464 int i830_dma_init(struct inode *inode, struct file *filp,
465 unsigned int cmd, unsigned long arg)
467 drm_file_t *priv = filp->private_data;
468 drm_device_t *dev = priv->dev;
469 drm_i830_private_t *dev_priv;
470 drm_i830_init_t init;
473 if (copy_from_user(&init, (void * __user) arg, sizeof(init)))
478 dev_priv = DRM(alloc)(sizeof(drm_i830_private_t),
480 if(dev_priv == NULL) return -ENOMEM;
481 retcode = i830_dma_initialize(dev, dev_priv, &init);
483 case I830_CLEANUP_DMA:
484 retcode = i830_dma_cleanup(dev);
494 #define GFX_OP_STIPPLE ((0x3<<29)|(0x1d<<24)|(0x83<<16))
495 #define ST1_ENABLE (1<<16)
496 #define ST1_MASK (0xffff)
498 /* Most efficient way to verify state for the i830 is as it is
499 * emitted. Non-conformant state is silently dropped.
501 static void i830EmitContextVerified( drm_device_t *dev,
504 drm_i830_private_t *dev_priv = dev->dev_private;
509 BEGIN_LP_RING( I830_CTX_SETUP_SIZE + 4 );
511 for ( i = 0 ; i < I830_CTXREG_BLENDCOLR0 ; i++ ) {
513 if ((tmp & (7<<29)) == CMD_3D &&
514 (tmp & (0x1f<<24)) < (0x1d<<24)) {
518 DRM_ERROR("Skipping %d\n", i);
522 OUT_RING( STATE3D_CONST_BLEND_COLOR_CMD );
523 OUT_RING( code[I830_CTXREG_BLENDCOLR] );
526 for ( i = I830_CTXREG_VF ; i < I830_CTXREG_MCSB0 ; i++ ) {
528 if ((tmp & (7<<29)) == CMD_3D &&
529 (tmp & (0x1f<<24)) < (0x1d<<24)) {
533 DRM_ERROR("Skipping %d\n", i);
537 OUT_RING( STATE3D_MAP_COORD_SETBIND_CMD );
538 OUT_RING( code[I830_CTXREG_MCSB1] );
547 static void i830EmitTexVerified( drm_device_t *dev, unsigned int *code )
549 drm_i830_private_t *dev_priv = dev->dev_private;
554 if (code[I830_TEXREG_MI0] == GFX_OP_MAP_INFO ||
555 (code[I830_TEXREG_MI0] & ~(0xf*LOAD_TEXTURE_MAP0)) ==
556 (STATE3D_LOAD_STATE_IMMEDIATE_2|4)) {
558 BEGIN_LP_RING( I830_TEX_SETUP_SIZE );
560 OUT_RING( code[I830_TEXREG_MI0] ); /* TM0LI */
561 OUT_RING( code[I830_TEXREG_MI1] ); /* TM0S0 */
562 OUT_RING( code[I830_TEXREG_MI2] ); /* TM0S1 */
563 OUT_RING( code[I830_TEXREG_MI3] ); /* TM0S2 */
564 OUT_RING( code[I830_TEXREG_MI4] ); /* TM0S3 */
565 OUT_RING( code[I830_TEXREG_MI5] ); /* TM0S4 */
567 for ( i = 6 ; i < I830_TEX_SETUP_SIZE ; i++ ) {
579 printk("rejected packet %x\n", code[0]);
582 static void i830EmitTexBlendVerified( drm_device_t *dev,
586 drm_i830_private_t *dev_priv = dev->dev_private;
594 BEGIN_LP_RING( num + 1 );
596 for ( i = 0 ; i < num ; i++ ) {
608 static void i830EmitTexPalette( drm_device_t *dev,
609 unsigned int *palette,
613 drm_i830_private_t *dev_priv = dev->dev_private;
619 BEGIN_LP_RING( 258 );
622 OUT_RING(CMD_OP_MAP_PALETTE_LOAD |
626 OUT_RING(CMD_OP_MAP_PALETTE_LOAD | MAP_PALETTE_NUM(number));
628 for(i = 0; i < 256; i++) {
629 OUT_RING(palette[i]);
632 /* KW: WHERE IS THE ADVANCE_LP_RING? This is effectively a noop!
636 /* Need to do some additional checking when setting the dest buffer.
638 static void i830EmitDestVerified( drm_device_t *dev,
641 drm_i830_private_t *dev_priv = dev->dev_private;
645 BEGIN_LP_RING( I830_DEST_SETUP_SIZE + 10 );
648 tmp = code[I830_DESTREG_CBUFADDR];
649 if (tmp == dev_priv->front_di1 || tmp == dev_priv->back_di1) {
650 if (((int)outring) & 8) {
655 OUT_RING( CMD_OP_DESTBUFFER_INFO );
656 OUT_RING( BUF_3D_ID_COLOR_BACK |
657 BUF_3D_PITCH(dev_priv->back_pitch * dev_priv->cpp) |
662 OUT_RING( CMD_OP_DESTBUFFER_INFO );
663 OUT_RING( BUF_3D_ID_DEPTH | BUF_3D_USE_FENCE |
664 BUF_3D_PITCH(dev_priv->depth_pitch * dev_priv->cpp));
665 OUT_RING( dev_priv->zi1 );
668 DRM_ERROR("bad di1 %x (allow %x or %x)\n",
669 tmp, dev_priv->front_di1, dev_priv->back_di1);
676 OUT_RING( GFX_OP_DESTBUFFER_VARS );
677 OUT_RING( code[I830_DESTREG_DV1] );
679 OUT_RING( GFX_OP_DRAWRECT_INFO );
680 OUT_RING( code[I830_DESTREG_DR1] );
681 OUT_RING( code[I830_DESTREG_DR2] );
682 OUT_RING( code[I830_DESTREG_DR3] );
683 OUT_RING( code[I830_DESTREG_DR4] );
685 /* Need to verify this */
686 tmp = code[I830_DESTREG_SENABLE];
687 if((tmp & ~0x3) == GFX_OP_SCISSOR_ENABLE) {
690 DRM_ERROR("bad scissor enable\n");
694 OUT_RING( GFX_OP_SCISSOR_RECT );
695 OUT_RING( code[I830_DESTREG_SR1] );
696 OUT_RING( code[I830_DESTREG_SR2] );
702 static void i830EmitStippleVerified( drm_device_t *dev,
705 drm_i830_private_t *dev_priv = dev->dev_private;
709 OUT_RING( GFX_OP_STIPPLE );
715 static void i830EmitState( drm_device_t *dev )
717 drm_i830_private_t *dev_priv = dev->dev_private;
718 drm_i830_sarea_t *sarea_priv = dev_priv->sarea_priv;
719 unsigned int dirty = sarea_priv->dirty;
721 DRM_DEBUG("%s %x\n", __FUNCTION__, dirty);
723 if (dirty & I830_UPLOAD_BUFFERS) {
724 i830EmitDestVerified( dev, sarea_priv->BufferState );
725 sarea_priv->dirty &= ~I830_UPLOAD_BUFFERS;
728 if (dirty & I830_UPLOAD_CTX) {
729 i830EmitContextVerified( dev, sarea_priv->ContextState );
730 sarea_priv->dirty &= ~I830_UPLOAD_CTX;
733 if (dirty & I830_UPLOAD_TEX0) {
734 i830EmitTexVerified( dev, sarea_priv->TexState[0] );
735 sarea_priv->dirty &= ~I830_UPLOAD_TEX0;
738 if (dirty & I830_UPLOAD_TEX1) {
739 i830EmitTexVerified( dev, sarea_priv->TexState[1] );
740 sarea_priv->dirty &= ~I830_UPLOAD_TEX1;
743 if (dirty & I830_UPLOAD_TEXBLEND0) {
744 i830EmitTexBlendVerified( dev, sarea_priv->TexBlendState[0],
745 sarea_priv->TexBlendStateWordsUsed[0]);
746 sarea_priv->dirty &= ~I830_UPLOAD_TEXBLEND0;
749 if (dirty & I830_UPLOAD_TEXBLEND1) {
750 i830EmitTexBlendVerified( dev, sarea_priv->TexBlendState[1],
751 sarea_priv->TexBlendStateWordsUsed[1]);
752 sarea_priv->dirty &= ~I830_UPLOAD_TEXBLEND1;
755 if (dirty & I830_UPLOAD_TEX_PALETTE_SHARED) {
756 i830EmitTexPalette(dev, sarea_priv->Palette[0], 0, 1);
758 if (dirty & I830_UPLOAD_TEX_PALETTE_N(0)) {
759 i830EmitTexPalette(dev, sarea_priv->Palette[0], 0, 0);
760 sarea_priv->dirty &= ~I830_UPLOAD_TEX_PALETTE_N(0);
762 if (dirty & I830_UPLOAD_TEX_PALETTE_N(1)) {
763 i830EmitTexPalette(dev, sarea_priv->Palette[1], 1, 0);
764 sarea_priv->dirty &= ~I830_UPLOAD_TEX_PALETTE_N(1);
770 if (dirty & I830_UPLOAD_TEX_PALETTE_N(2)) {
771 i830EmitTexPalette(dev, sarea_priv->Palette2[0], 0, 0);
772 sarea_priv->dirty &= ~I830_UPLOAD_TEX_PALETTE_N(2);
774 if (dirty & I830_UPLOAD_TEX_PALETTE_N(3)) {
775 i830EmitTexPalette(dev, sarea_priv->Palette2[1], 1, 0);
776 sarea_priv->dirty &= ~I830_UPLOAD_TEX_PALETTE_N(2);
783 if (dirty & I830_UPLOAD_STIPPLE) {
784 i830EmitStippleVerified( dev,
785 sarea_priv->StippleState);
786 sarea_priv->dirty &= ~I830_UPLOAD_STIPPLE;
789 if (dirty & I830_UPLOAD_TEX2) {
790 i830EmitTexVerified( dev, sarea_priv->TexState2 );
791 sarea_priv->dirty &= ~I830_UPLOAD_TEX2;
794 if (dirty & I830_UPLOAD_TEX3) {
795 i830EmitTexVerified( dev, sarea_priv->TexState3 );
796 sarea_priv->dirty &= ~I830_UPLOAD_TEX3;
800 if (dirty & I830_UPLOAD_TEXBLEND2) {
801 i830EmitTexBlendVerified(
803 sarea_priv->TexBlendState2,
804 sarea_priv->TexBlendStateWordsUsed2);
806 sarea_priv->dirty &= ~I830_UPLOAD_TEXBLEND2;
809 if (dirty & I830_UPLOAD_TEXBLEND3) {
810 i830EmitTexBlendVerified(
812 sarea_priv->TexBlendState3,
813 sarea_priv->TexBlendStateWordsUsed3);
814 sarea_priv->dirty &= ~I830_UPLOAD_TEXBLEND3;
818 /* ================================================================
819 * Performance monitoring functions
822 static void i830_fill_box( drm_device_t *dev,
823 int x, int y, int w, int h,
824 int r, int g, int b )
826 drm_i830_private_t *dev_priv = dev->dev_private;
828 unsigned int BR13, CMD;
831 BR13 = (0xF0 << 16) | (dev_priv->pitch * dev_priv->cpp) | (1<<24);
832 CMD = XY_COLOR_BLT_CMD;
833 x += dev_priv->sarea_priv->boxes[0].x1;
834 y += dev_priv->sarea_priv->boxes[0].y1;
836 if (dev_priv->cpp == 4) {
838 CMD |= (XY_COLOR_BLT_WRITE_ALPHA | XY_COLOR_BLT_WRITE_RGB);
839 color = (((0xff) << 24) | (r << 16) | (g << 8) | b);
841 color = (((r & 0xf8) << 8) |
849 OUT_RING( (y << 16) | x );
850 OUT_RING( ((y+h) << 16) | (x+w) );
852 if ( dev_priv->current_page == 1 ) {
853 OUT_RING( dev_priv->front_offset );
855 OUT_RING( dev_priv->back_offset );
862 static void i830_cp_performance_boxes( drm_device_t *dev )
864 drm_i830_private_t *dev_priv = dev->dev_private;
866 /* Purple box for page flipping
868 if ( dev_priv->sarea_priv->perf_boxes & I830_BOX_FLIP )
869 i830_fill_box( dev, 4, 4, 8, 8, 255, 0, 255 );
871 /* Red box if we have to wait for idle at any point
873 if ( dev_priv->sarea_priv->perf_boxes & I830_BOX_WAIT )
874 i830_fill_box( dev, 16, 4, 8, 8, 255, 0, 0 );
876 /* Blue box: lost context?
878 if ( dev_priv->sarea_priv->perf_boxes & I830_BOX_LOST_CONTEXT )
879 i830_fill_box( dev, 28, 4, 8, 8, 0, 0, 255 );
881 /* Yellow box for texture swaps
883 if ( dev_priv->sarea_priv->perf_boxes & I830_BOX_TEXTURE_LOAD )
884 i830_fill_box( dev, 40, 4, 8, 8, 255, 255, 0 );
886 /* Green box if hardware never idles (as far as we can tell)
888 if ( !(dev_priv->sarea_priv->perf_boxes & I830_BOX_RING_EMPTY) )
889 i830_fill_box( dev, 64, 4, 8, 8, 0, 255, 0 );
892 /* Draw bars indicating number of buffers allocated
893 * (not a great measure, easily confused)
895 if (dev_priv->dma_used) {
896 int bar = dev_priv->dma_used / 10240;
897 if (bar > 100) bar = 100;
898 if (bar < 1) bar = 1;
899 i830_fill_box( dev, 4, 16, bar, 4, 196, 128, 128 );
900 dev_priv->dma_used = 0;
903 dev_priv->sarea_priv->perf_boxes = 0;
906 static void i830_dma_dispatch_clear( drm_device_t *dev, int flags,
907 unsigned int clear_color,
908 unsigned int clear_zval,
909 unsigned int clear_depthmask)
911 drm_i830_private_t *dev_priv = dev->dev_private;
912 drm_i830_sarea_t *sarea_priv = dev_priv->sarea_priv;
913 int nbox = sarea_priv->nbox;
914 drm_clip_rect_t *pbox = sarea_priv->boxes;
915 int pitch = dev_priv->pitch;
916 int cpp = dev_priv->cpp;
918 unsigned int BR13, CMD, D_CMD;
922 if ( dev_priv->current_page == 1 ) {
923 unsigned int tmp = flags;
925 flags &= ~(I830_FRONT | I830_BACK);
926 if ( tmp & I830_FRONT ) flags |= I830_BACK;
927 if ( tmp & I830_BACK ) flags |= I830_FRONT;
930 i830_kernel_lost_context(dev);
934 BR13 = (0xF0 << 16) | (pitch * cpp) | (1<<24);
935 D_CMD = CMD = XY_COLOR_BLT_CMD;
938 BR13 = (0xF0 << 16) | (pitch * cpp) | (1<<24) | (1<<25);
939 CMD = (XY_COLOR_BLT_CMD | XY_COLOR_BLT_WRITE_ALPHA |
940 XY_COLOR_BLT_WRITE_RGB);
941 D_CMD = XY_COLOR_BLT_CMD;
942 if(clear_depthmask & 0x00ffffff)
943 D_CMD |= XY_COLOR_BLT_WRITE_RGB;
944 if(clear_depthmask & 0xff000000)
945 D_CMD |= XY_COLOR_BLT_WRITE_ALPHA;
948 BR13 = (0xF0 << 16) | (pitch * cpp) | (1<<24);
949 D_CMD = CMD = XY_COLOR_BLT_CMD;
953 if (nbox > I830_NR_SAREA_CLIPRECTS)
954 nbox = I830_NR_SAREA_CLIPRECTS;
956 for (i = 0 ; i < nbox ; i++, pbox++) {
957 if (pbox->x1 > pbox->x2 ||
958 pbox->y1 > pbox->y2 ||
959 pbox->x2 > dev_priv->w ||
960 pbox->y2 > dev_priv->h)
963 if ( flags & I830_FRONT ) {
964 DRM_DEBUG("clear front\n");
968 OUT_RING( (pbox->y1 << 16) | pbox->x1 );
969 OUT_RING( (pbox->y2 << 16) | pbox->x2 );
970 OUT_RING( dev_priv->front_offset );
971 OUT_RING( clear_color );
975 if ( flags & I830_BACK ) {
976 DRM_DEBUG("clear back\n");
980 OUT_RING( (pbox->y1 << 16) | pbox->x1 );
981 OUT_RING( (pbox->y2 << 16) | pbox->x2 );
982 OUT_RING( dev_priv->back_offset );
983 OUT_RING( clear_color );
987 if ( flags & I830_DEPTH ) {
988 DRM_DEBUG("clear depth\n");
992 OUT_RING( (pbox->y1 << 16) | pbox->x1 );
993 OUT_RING( (pbox->y2 << 16) | pbox->x2 );
994 OUT_RING( dev_priv->depth_offset );
995 OUT_RING( clear_zval );
1001 static void i830_dma_dispatch_swap( drm_device_t *dev )
1003 drm_i830_private_t *dev_priv = dev->dev_private;
1004 drm_i830_sarea_t *sarea_priv = dev_priv->sarea_priv;
1005 int nbox = sarea_priv->nbox;
1006 drm_clip_rect_t *pbox = sarea_priv->boxes;
1007 int pitch = dev_priv->pitch;
1008 int cpp = dev_priv->cpp;
1010 unsigned int CMD, BR13;
1013 DRM_DEBUG("swapbuffers\n");
1015 i830_kernel_lost_context(dev);
1017 if (dev_priv->do_boxes)
1018 i830_cp_performance_boxes( dev );
1022 BR13 = (pitch * cpp) | (0xCC << 16) | (1<<24);
1023 CMD = XY_SRC_COPY_BLT_CMD;
1026 BR13 = (pitch * cpp) | (0xCC << 16) | (1<<24) | (1<<25);
1027 CMD = (XY_SRC_COPY_BLT_CMD | XY_SRC_COPY_BLT_WRITE_ALPHA |
1028 XY_SRC_COPY_BLT_WRITE_RGB);
1031 BR13 = (pitch * cpp) | (0xCC << 16) | (1<<24);
1032 CMD = XY_SRC_COPY_BLT_CMD;
1037 if (nbox > I830_NR_SAREA_CLIPRECTS)
1038 nbox = I830_NR_SAREA_CLIPRECTS;
1040 for (i = 0 ; i < nbox; i++, pbox++)
1042 if (pbox->x1 > pbox->x2 ||
1043 pbox->y1 > pbox->y2 ||
1044 pbox->x2 > dev_priv->w ||
1045 pbox->y2 > dev_priv->h)
1048 DRM_DEBUG("dispatch swap %d,%d-%d,%d!\n",
1050 pbox->x2, pbox->y2);
1055 OUT_RING( (pbox->y1 << 16) | pbox->x1 );
1056 OUT_RING( (pbox->y2 << 16) | pbox->x2 );
1058 if (dev_priv->current_page == 0)
1059 OUT_RING( dev_priv->front_offset );
1061 OUT_RING( dev_priv->back_offset );
1063 OUT_RING( (pbox->y1 << 16) | pbox->x1 );
1064 OUT_RING( BR13 & 0xffff );
1066 if (dev_priv->current_page == 0)
1067 OUT_RING( dev_priv->back_offset );
1069 OUT_RING( dev_priv->front_offset );
1075 static void i830_dma_dispatch_flip( drm_device_t *dev )
1077 drm_i830_private_t *dev_priv = dev->dev_private;
1080 DRM_DEBUG( "%s: page=%d pfCurrentPage=%d\n",
1082 dev_priv->current_page,
1083 dev_priv->sarea_priv->pf_current_page);
1085 i830_kernel_lost_context(dev);
1087 if (dev_priv->do_boxes) {
1088 dev_priv->sarea_priv->perf_boxes |= I830_BOX_FLIP;
1089 i830_cp_performance_boxes( dev );
1094 OUT_RING( INST_PARSER_CLIENT | INST_OP_FLUSH | INST_FLUSH_MAP_CACHE );
1099 OUT_RING( CMD_OP_DISPLAYBUFFER_INFO | ASYNC_FLIP );
1101 if ( dev_priv->current_page == 0 ) {
1102 OUT_RING( dev_priv->back_offset );
1103 dev_priv->current_page = 1;
1105 OUT_RING( dev_priv->front_offset );
1106 dev_priv->current_page = 0;
1113 OUT_RING( MI_WAIT_FOR_EVENT |
1114 MI_WAIT_FOR_PLANE_A_FLIP );
1119 dev_priv->sarea_priv->pf_current_page = dev_priv->current_page;
1122 static void i830_dma_dispatch_vertex(drm_device_t *dev,
1127 drm_i830_private_t *dev_priv = dev->dev_private;
1128 drm_i830_buf_priv_t *buf_priv = buf->dev_private;
1129 drm_i830_sarea_t *sarea_priv = dev_priv->sarea_priv;
1130 drm_clip_rect_t *box = sarea_priv->boxes;
1131 int nbox = sarea_priv->nbox;
1132 unsigned long address = (unsigned long)buf->bus_address;
1133 unsigned long start = address - dev->agp->base;
1137 i830_kernel_lost_context(dev);
1139 if (nbox > I830_NR_SAREA_CLIPRECTS)
1140 nbox = I830_NR_SAREA_CLIPRECTS;
1143 u = cmpxchg(buf_priv->in_use, I830_BUF_CLIENT,
1145 if(u != I830_BUF_CLIENT) {
1146 DRM_DEBUG("xxxx 2\n");
1153 if (sarea_priv->dirty)
1154 i830EmitState( dev );
1156 DRM_DEBUG("dispatch vertex addr 0x%lx, used 0x%x nbox %d\n",
1157 address, used, nbox);
1159 dev_priv->counter++;
1160 DRM_DEBUG( "dispatch counter : %ld\n", dev_priv->counter);
1161 DRM_DEBUG( "i830_dma_dispatch\n");
1162 DRM_DEBUG( "start : %lx\n", start);
1163 DRM_DEBUG( "used : %d\n", used);
1164 DRM_DEBUG( "start + used - 4 : %ld\n", start + used - 4);
1166 if (buf_priv->currently_mapped == I830_BUF_MAPPED) {
1167 u32 *vp = buf_priv->kernel_virtual;
1169 vp[0] = (GFX_OP_PRIMITIVE |
1170 sarea_priv->vertex_prim |
1173 if (dev_priv->use_mi_batchbuffer_start) {
1174 vp[used/4] = MI_BATCH_BUFFER_END;
1183 i830_unmap_buffer(buf);
1190 OUT_RING( GFX_OP_DRAWRECT_INFO );
1191 OUT_RING( sarea_priv->BufferState[I830_DESTREG_DR1] );
1192 OUT_RING( box[i].x1 | (box[i].y1<<16) );
1193 OUT_RING( box[i].x2 | (box[i].y2<<16) );
1194 OUT_RING( sarea_priv->BufferState[I830_DESTREG_DR4] );
1199 if (dev_priv->use_mi_batchbuffer_start) {
1201 OUT_RING( MI_BATCH_BUFFER_START | (2<<6) );
1202 OUT_RING( start | MI_BATCH_NON_SECURE );
1207 OUT_RING( MI_BATCH_BUFFER );
1208 OUT_RING( start | MI_BATCH_NON_SECURE );
1209 OUT_RING( start + used - 4 );
1214 } while (++i < nbox);
1218 dev_priv->counter++;
1220 (void) cmpxchg(buf_priv->in_use, I830_BUF_CLIENT,
1224 OUT_RING( CMD_STORE_DWORD_IDX );
1226 OUT_RING( dev_priv->counter );
1227 OUT_RING( CMD_STORE_DWORD_IDX );
1228 OUT_RING( buf_priv->my_use_idx );
1229 OUT_RING( I830_BUF_FREE );
1230 OUT_RING( CMD_REPORT_HEAD );
1237 void i830_dma_quiescent(drm_device_t *dev)
1239 drm_i830_private_t *dev_priv = dev->dev_private;
1242 i830_kernel_lost_context(dev);
1245 OUT_RING( INST_PARSER_CLIENT | INST_OP_FLUSH | INST_FLUSH_MAP_CACHE );
1246 OUT_RING( CMD_REPORT_HEAD );
1251 i830_wait_ring( dev, dev_priv->ring.Size - 8, __FUNCTION__ );
1254 static int i830_flush_queue(drm_device_t *dev)
1256 drm_i830_private_t *dev_priv = dev->dev_private;
1257 drm_device_dma_t *dma = dev->dma;
1261 i830_kernel_lost_context(dev);
1264 OUT_RING( CMD_REPORT_HEAD );
1268 i830_wait_ring( dev, dev_priv->ring.Size - 8, __FUNCTION__ );
1270 for (i = 0; i < dma->buf_count; i++) {
1271 drm_buf_t *buf = dma->buflist[ i ];
1272 drm_i830_buf_priv_t *buf_priv = buf->dev_private;
1274 int used = cmpxchg(buf_priv->in_use, I830_BUF_HARDWARE,
1277 if (used == I830_BUF_HARDWARE)
1278 DRM_DEBUG("reclaimed from HARDWARE\n");
1279 if (used == I830_BUF_CLIENT)
1280 DRM_DEBUG("still on client\n");
1286 /* Must be called with the lock held */
1287 void i830_reclaim_buffers( struct file *filp )
1289 drm_file_t *priv = filp->private_data;
1290 drm_device_t *dev = priv->dev;
1291 drm_device_dma_t *dma = dev->dma;
1295 if (!dev->dev_private) return;
1296 if (!dma->buflist) return;
1298 i830_flush_queue(dev);
1300 for (i = 0; i < dma->buf_count; i++) {
1301 drm_buf_t *buf = dma->buflist[ i ];
1302 drm_i830_buf_priv_t *buf_priv = buf->dev_private;
1304 if (buf->filp == filp && buf_priv) {
1305 int used = cmpxchg(buf_priv->in_use, I830_BUF_CLIENT,
1308 if (used == I830_BUF_CLIENT)
1309 DRM_DEBUG("reclaimed from client\n");
1310 if(buf_priv->currently_mapped == I830_BUF_MAPPED)
1311 buf_priv->currently_mapped = I830_BUF_UNMAPPED;
1316 int i830_flush_ioctl(struct inode *inode, struct file *filp,
1317 unsigned int cmd, unsigned long arg)
1319 drm_file_t *priv = filp->private_data;
1320 drm_device_t *dev = priv->dev;
1322 if(!_DRM_LOCK_IS_HELD(dev->lock.hw_lock->lock)) {
1323 DRM_ERROR("i830_flush_ioctl called without lock held\n");
1327 i830_flush_queue(dev);
1331 int i830_dma_vertex(struct inode *inode, struct file *filp,
1332 unsigned int cmd, unsigned long arg)
1334 drm_file_t *priv = filp->private_data;
1335 drm_device_t *dev = priv->dev;
1336 drm_device_dma_t *dma = dev->dma;
1337 drm_i830_private_t *dev_priv = (drm_i830_private_t *)dev->dev_private;
1338 u32 *hw_status = dev_priv->hw_status_page;
1339 drm_i830_sarea_t *sarea_priv = (drm_i830_sarea_t *)
1340 dev_priv->sarea_priv;
1341 drm_i830_vertex_t vertex;
1343 if (copy_from_user(&vertex, (drm_i830_vertex_t __user *)arg, sizeof(vertex)))
1346 if(!_DRM_LOCK_IS_HELD(dev->lock.hw_lock->lock)) {
1347 DRM_ERROR("i830_dma_vertex called without lock held\n");
1351 DRM_DEBUG("i830 dma vertex, idx %d used %d discard %d\n",
1352 vertex.idx, vertex.used, vertex.discard);
1354 if(vertex.idx < 0 || vertex.idx > dma->buf_count) return -EINVAL;
1356 i830_dma_dispatch_vertex( dev,
1357 dma->buflist[ vertex.idx ],
1358 vertex.discard, vertex.used );
1360 sarea_priv->last_enqueue = dev_priv->counter-1;
1361 sarea_priv->last_dispatch = (int) hw_status[5];
1366 int i830_clear_bufs(struct inode *inode, struct file *filp,
1367 unsigned int cmd, unsigned long arg)
1369 drm_file_t *priv = filp->private_data;
1370 drm_device_t *dev = priv->dev;
1371 drm_i830_clear_t clear;
1373 if (copy_from_user(&clear, (drm_i830_clear_t __user *)arg, sizeof(clear)))
1376 if(!_DRM_LOCK_IS_HELD(dev->lock.hw_lock->lock)) {
1377 DRM_ERROR("i830_clear_bufs called without lock held\n");
1381 /* GH: Someone's doing nasty things... */
1382 if (!dev->dev_private) {
1386 i830_dma_dispatch_clear( dev, clear.flags,
1389 clear.clear_depthmask);
1393 int i830_swap_bufs(struct inode *inode, struct file *filp,
1394 unsigned int cmd, unsigned long arg)
1396 drm_file_t *priv = filp->private_data;
1397 drm_device_t *dev = priv->dev;
1399 DRM_DEBUG("i830_swap_bufs\n");
1401 if(!_DRM_LOCK_IS_HELD(dev->lock.hw_lock->lock)) {
1402 DRM_ERROR("i830_swap_buf called without lock held\n");
1406 i830_dma_dispatch_swap( dev );
1412 /* Not sure why this isn't set all the time:
1414 static void i830_do_init_pageflip( drm_device_t *dev )
1416 drm_i830_private_t *dev_priv = dev->dev_private;
1418 DRM_DEBUG("%s\n", __FUNCTION__);
1419 dev_priv->page_flipping = 1;
1420 dev_priv->current_page = 0;
1421 dev_priv->sarea_priv->pf_current_page = dev_priv->current_page;
1424 int i830_do_cleanup_pageflip( drm_device_t *dev )
1426 drm_i830_private_t *dev_priv = dev->dev_private;
1428 DRM_DEBUG("%s\n", __FUNCTION__);
1429 if (dev_priv->current_page != 0)
1430 i830_dma_dispatch_flip( dev );
1432 dev_priv->page_flipping = 0;
1436 int i830_flip_bufs(struct inode *inode, struct file *filp,
1437 unsigned int cmd, unsigned long arg)
1439 drm_file_t *priv = filp->private_data;
1440 drm_device_t *dev = priv->dev;
1441 drm_i830_private_t *dev_priv = dev->dev_private;
1443 DRM_DEBUG("%s\n", __FUNCTION__);
1445 if(!_DRM_LOCK_IS_HELD(dev->lock.hw_lock->lock)) {
1446 DRM_ERROR("i830_flip_buf called without lock held\n");
1450 if (!dev_priv->page_flipping)
1451 i830_do_init_pageflip( dev );
1453 i830_dma_dispatch_flip( dev );
1457 int i830_getage(struct inode *inode, struct file *filp, unsigned int cmd,
1460 drm_file_t *priv = filp->private_data;
1461 drm_device_t *dev = priv->dev;
1462 drm_i830_private_t *dev_priv = (drm_i830_private_t *)dev->dev_private;
1463 u32 *hw_status = dev_priv->hw_status_page;
1464 drm_i830_sarea_t *sarea_priv = (drm_i830_sarea_t *)
1465 dev_priv->sarea_priv;
1467 sarea_priv->last_dispatch = (int) hw_status[5];
1471 int i830_getbuf(struct inode *inode, struct file *filp, unsigned int cmd,
1474 drm_file_t *priv = filp->private_data;
1475 drm_device_t *dev = priv->dev;
1478 drm_i830_private_t *dev_priv = (drm_i830_private_t *)dev->dev_private;
1479 u32 *hw_status = dev_priv->hw_status_page;
1480 drm_i830_sarea_t *sarea_priv = (drm_i830_sarea_t *)
1481 dev_priv->sarea_priv;
1483 DRM_DEBUG("getbuf\n");
1484 if (copy_from_user(&d, (drm_i830_dma_t __user *)arg, sizeof(d)))
1487 if(!_DRM_LOCK_IS_HELD(dev->lock.hw_lock->lock)) {
1488 DRM_ERROR("i830_dma called without lock held\n");
1494 retcode = i830_dma_get_buffer(dev, &d, filp);
1496 DRM_DEBUG("i830_dma: %d returning %d, granted = %d\n",
1497 current->pid, retcode, d.granted);
1499 if (copy_to_user((drm_dma_t __user *)arg, &d, sizeof(d)))
1501 sarea_priv->last_dispatch = (int) hw_status[5];
1506 int i830_copybuf(struct inode *inode,
1511 /* Never copy - 2.4.x doesn't need it */
1515 int i830_docopy(struct inode *inode, struct file *filp, unsigned int cmd,
1523 int i830_getparam( struct inode *inode, struct file *filp, unsigned int cmd,
1526 drm_file_t *priv = filp->private_data;
1527 drm_device_t *dev = priv->dev;
1528 drm_i830_private_t *dev_priv = dev->dev_private;
1529 drm_i830_getparam_t param;
1533 DRM_ERROR( "%s called with no initialization\n", __FUNCTION__ );
1537 if (copy_from_user(¶m, (drm_i830_getparam_t __user *)arg, sizeof(param) ))
1540 switch( param.param ) {
1541 case I830_PARAM_IRQ_ACTIVE:
1542 value = dev->irq_enabled;
1548 if ( copy_to_user( param.value, &value, sizeof(int) ) ) {
1549 DRM_ERROR( "copy_to_user\n" );
1557 int i830_setparam( struct inode *inode, struct file *filp, unsigned int cmd,
1560 drm_file_t *priv = filp->private_data;
1561 drm_device_t *dev = priv->dev;
1562 drm_i830_private_t *dev_priv = dev->dev_private;
1563 drm_i830_setparam_t param;
1566 DRM_ERROR( "%s called with no initialization\n", __FUNCTION__ );
1570 if (copy_from_user(¶m, (drm_i830_setparam_t __user *)arg, sizeof(param) ))
1573 switch( param.param ) {
1574 case I830_SETPARAM_USE_MI_BATCHBUFFER_START:
1575 dev_priv->use_mi_batchbuffer_start = param.value;
1585 static void i830_driver_pretakedown(drm_device_t *dev)
1587 i830_dma_cleanup( dev );
1590 static void i830_driver_release(drm_device_t *dev, struct file *filp)
1592 i830_reclaim_buffers(filp);
1595 static int i830_driver_dma_quiescent(drm_device_t *dev)
1597 i830_dma_quiescent( dev );
1601 void i830_driver_register_fns(drm_device_t *dev)
1603 dev->driver_features = DRIVER_USE_AGP | DRIVER_REQUIRE_AGP | DRIVER_USE_MTRR | DRIVER_HAVE_DMA | DRIVER_DMA_QUEUE;
1605 dev->driver_features |= DRIVER_HAVE_IRQ | DRIVER_SHARED_IRQ;
1607 dev->dev_priv_size = sizeof(drm_i830_buf_priv_t);
1608 dev->fn_tbl.pretakedown = i830_driver_pretakedown;
1609 dev->fn_tbl.release = i830_driver_release;
1610 dev->fn_tbl.dma_quiescent = i830_driver_dma_quiescent;
1611 dev->fn_tbl.reclaim_buffers = i830_reclaim_buffers;
1613 dev->fn_tbl.irq_preinstall = i830_driver_irq_preinstall;
1614 dev->fn_tbl.irq_postinstall = i830_driver_irq_postinstall;
1615 dev->fn_tbl.irq_uninstall = i830_driver_irq_uninstall;
1616 dev->fn_tbl.irq_handler = i830_driver_irq_handler;
1619 dev->types[6] = _DRM_STAT_IRQ;
1620 dev->types[7] = _DRM_STAT_PRIMARY;
1621 dev->types[8] = _DRM_STAT_SECONDARY;
1622 dev->types[9] = _DRM_STAT_DMA;