1 /* mga_drv.h -- Private header for the Matrox G200/G400 driver -*- linux-c -*-
2 * Created: Mon Dec 13 01:50:01 1999 by jhartmann@precisioninsight.com
4 * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas.
5 * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California.
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
23 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
24 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
25 * OTHER DEALINGS IN THE SOFTWARE.
28 * Gareth Hughes <gareth@valinux.com>
34 typedef struct drm_mga_primary_buffer {
41 volatile long wrapped;
49 } drm_mga_primary_buffer_t;
51 typedef struct drm_mga_freelist {
52 struct drm_mga_freelist *next;
53 struct drm_mga_freelist *prev;
59 drm_mga_freelist_t *list_entry;
64 typedef struct drm_mga_private {
65 drm_mga_primary_buffer_t prim;
66 drm_mga_sarea_t *sarea_priv;
68 drm_mga_freelist_t *head;
69 drm_mga_freelist_t *tail;
71 unsigned int warp_pipe;
72 unsigned long warp_pipe_phys[MGA_MAX_WARP_PIPES];
81 unsigned int front_offset;
82 unsigned int front_pitch;
83 unsigned int back_offset;
84 unsigned int back_pitch;
86 unsigned int depth_cpp;
87 unsigned int depth_offset;
88 unsigned int depth_pitch;
90 unsigned int texture_offset;
91 unsigned int texture_size;
93 drm_local_map_t *sarea;
94 drm_local_map_t *mmio;
95 drm_local_map_t *status;
96 drm_local_map_t *warp;
97 drm_local_map_t *primary;
98 drm_local_map_t *buffers;
99 drm_local_map_t *agp_textures;
103 extern int mga_dma_init( DRM_IOCTL_ARGS );
104 extern int mga_dma_flush( DRM_IOCTL_ARGS );
105 extern int mga_dma_reset( DRM_IOCTL_ARGS );
106 extern int mga_dma_buffers( DRM_IOCTL_ARGS );
108 extern int mga_do_wait_for_idle( drm_mga_private_t *dev_priv );
109 extern int mga_do_dma_idle( drm_mga_private_t *dev_priv );
110 extern int mga_do_dma_reset( drm_mga_private_t *dev_priv );
111 extern int mga_do_engine_reset( drm_mga_private_t *dev_priv );
112 extern int mga_do_cleanup_dma( drm_device_t *dev );
114 extern void mga_do_dma_flush( drm_mga_private_t *dev_priv );
115 extern void mga_do_dma_wrap_start( drm_mga_private_t *dev_priv );
116 extern void mga_do_dma_wrap_end( drm_mga_private_t *dev_priv );
118 extern int mga_freelist_put( drm_device_t *dev, drm_buf_t *buf );
121 extern int mga_dma_clear( DRM_IOCTL_ARGS );
122 extern int mga_dma_swap( DRM_IOCTL_ARGS );
123 extern int mga_dma_vertex( DRM_IOCTL_ARGS );
124 extern int mga_dma_indices( DRM_IOCTL_ARGS );
125 extern int mga_dma_iload( DRM_IOCTL_ARGS );
126 extern int mga_dma_blit( DRM_IOCTL_ARGS );
127 extern int mga_getparam( DRM_IOCTL_ARGS );
130 extern int mga_warp_install_microcode( drm_mga_private_t *dev_priv );
131 extern int mga_warp_init( drm_mga_private_t *dev_priv );
133 extern int mga_driver_vblank_wait(drm_device_t *dev, unsigned int *sequence);
134 extern irqreturn_t mga_driver_irq_handler( DRM_IRQ_ARGS );
135 extern void mga_driver_irq_preinstall( drm_device_t *dev );
136 extern void mga_driver_irq_postinstall( drm_device_t *dev );
137 extern void mga_driver_irq_uninstall( drm_device_t *dev );
139 #define mga_flush_write_combine() DRM_WRITEMEMORYBARRIER()
141 #if defined(__linux__) && defined(__alpha__)
142 #define MGA_BASE( reg ) ((unsigned long)(dev_priv->mmio->handle))
143 #define MGA_ADDR( reg ) (MGA_BASE(reg) + reg)
145 #define MGA_DEREF( reg ) *(volatile u32 *)MGA_ADDR( reg )
146 #define MGA_DEREF8( reg ) *(volatile u8 *)MGA_ADDR( reg )
148 #define MGA_READ( reg ) (_MGA_READ((u32 *)MGA_ADDR(reg)))
149 #define MGA_READ8( reg ) (_MGA_READ((u8 *)MGA_ADDR(reg)))
150 #define MGA_WRITE( reg, val ) do { DRM_WRITEMEMORYBARRIER(); MGA_DEREF( reg ) = val; } while (0)
151 #define MGA_WRITE8( reg, val ) do { DRM_WRITEMEMORYBARRIER(); MGA_DEREF8( reg ) = val; } while (0)
153 static inline u32 _MGA_READ(u32 *addr)
156 return *(volatile u32 *)addr;
159 #define MGA_READ8( reg ) DRM_READ8(dev_priv->mmio, (reg))
160 #define MGA_READ( reg ) DRM_READ32(dev_priv->mmio, (reg))
161 #define MGA_WRITE8( reg, val ) DRM_WRITE8(dev_priv->mmio, (reg), (val))
162 #define MGA_WRITE( reg, val ) DRM_WRITE32(dev_priv->mmio, (reg), (val))
165 #define DWGREG0 0x1c00
166 #define DWGREG0_END 0x1dff
167 #define DWGREG1 0x2c00
168 #define DWGREG1_END 0x2dff
170 #define ISREG0(r) (r >= DWGREG0 && r <= DWGREG0_END)
171 #define DMAREG0(r) (u8)((r - DWGREG0) >> 2)
172 #define DMAREG1(r) (u8)(((r - DWGREG1) >> 2) | 0x80)
173 #define DMAREG(r) (ISREG0(r) ? DMAREG0(r) : DMAREG1(r))
177 /* ================================================================
181 #define MGA_EMIT_STATE( dev_priv, dirty ) \
183 if ( (dirty) & ~MGA_UPLOAD_CLIPRECTS ) { \
184 if ( dev_priv->chipset == MGA_CARD_TYPE_G400 ) { \
185 mga_g400_emit_state( dev_priv ); \
187 mga_g200_emit_state( dev_priv ); \
192 #define WRAP_TEST_WITH_RETURN( dev_priv ) \
194 if ( test_bit( 0, &dev_priv->prim.wrapped ) ) { \
195 if ( mga_is_idle( dev_priv ) ) { \
196 mga_do_dma_wrap_end( dev_priv ); \
197 } else if ( dev_priv->prim.space < \
198 dev_priv->prim.high_mark ) { \
199 if ( MGA_DMA_DEBUG ) \
200 DRM_INFO( "%s: wrap...\n", __FUNCTION__ ); \
201 return DRM_ERR(EBUSY); \
206 #define WRAP_WAIT_WITH_RETURN( dev_priv ) \
208 if ( test_bit( 0, &dev_priv->prim.wrapped ) ) { \
209 if ( mga_do_wait_for_idle( dev_priv ) < 0 ) { \
210 if ( MGA_DMA_DEBUG ) \
211 DRM_INFO( "%s: wrap...\n", __FUNCTION__ ); \
212 return DRM_ERR(EBUSY); \
214 mga_do_dma_wrap_end( dev_priv ); \
219 /* ================================================================
220 * Primary DMA command stream
223 #define MGA_VERBOSE 0
225 #define DMA_LOCALS unsigned int write; volatile u8 *prim;
227 #define DMA_BLOCK_SIZE (5 * sizeof(u32))
229 #define BEGIN_DMA( n ) \
231 if ( MGA_VERBOSE ) { \
232 DRM_INFO( "BEGIN_DMA( %d ) in %s\n", \
233 (n), __FUNCTION__ ); \
234 DRM_INFO( " space=0x%x req=0x%Zx\n", \
235 dev_priv->prim.space, (n) * DMA_BLOCK_SIZE ); \
237 prim = dev_priv->prim.start; \
238 write = dev_priv->prim.tail; \
241 #define BEGIN_DMA_WRAP() \
243 if ( MGA_VERBOSE ) { \
244 DRM_INFO( "BEGIN_DMA() in %s\n", __FUNCTION__ ); \
245 DRM_INFO( " space=0x%x\n", dev_priv->prim.space ); \
247 prim = dev_priv->prim.start; \
248 write = dev_priv->prim.tail; \
251 #define ADVANCE_DMA() \
253 dev_priv->prim.tail = write; \
254 if ( MGA_VERBOSE ) { \
255 DRM_INFO( "ADVANCE_DMA() tail=0x%05x sp=0x%x\n", \
256 write, dev_priv->prim.space ); \
260 #define FLUSH_DMA() \
263 DRM_INFO( "%s:\n", __FUNCTION__ ); \
264 DRM_INFO( " tail=0x%06x head=0x%06lx\n", \
265 dev_priv->prim.tail, \
266 MGA_READ( MGA_PRIMADDRESS ) - \
267 dev_priv->primary->offset ); \
269 if ( !test_bit( 0, &dev_priv->prim.wrapped ) ) { \
270 if ( dev_priv->prim.space < \
271 dev_priv->prim.high_mark ) { \
272 mga_do_dma_wrap_start( dev_priv ); \
274 mga_do_dma_flush( dev_priv ); \
279 /* Never use this, always use DMA_BLOCK(...) for primary DMA output.
281 #define DMA_WRITE( offset, val ) \
283 if ( MGA_VERBOSE ) { \
284 DRM_INFO( " DMA_WRITE( 0x%08x ) at 0x%04Zx\n", \
285 (u32)(val), write + (offset) * sizeof(u32) ); \
287 *(volatile u32 *)(prim + write + (offset) * sizeof(u32)) = val; \
290 #define DMA_BLOCK( reg0, val0, reg1, val1, reg2, val2, reg3, val3 ) \
292 DMA_WRITE( 0, ((DMAREG( reg0 ) << 0) | \
293 (DMAREG( reg1 ) << 8) | \
294 (DMAREG( reg2 ) << 16) | \
295 (DMAREG( reg3 ) << 24)) ); \
296 DMA_WRITE( 1, val0 ); \
297 DMA_WRITE( 2, val1 ); \
298 DMA_WRITE( 3, val2 ); \
299 DMA_WRITE( 4, val3 ); \
300 write += DMA_BLOCK_SIZE; \
304 /* Buffer aging via primary DMA stream head pointer.
307 #define SET_AGE( age, h, w ) \
313 #define TEST_AGE( age, h, w ) ( (age)->wrap < w || \
314 ( (age)->wrap == w && \
317 #define AGE_BUFFER( buf_priv ) \
319 drm_mga_freelist_t *entry = (buf_priv)->list_entry; \
320 if ( (buf_priv)->dispatched ) { \
321 entry->age.head = (dev_priv->prim.tail + \
322 dev_priv->primary->offset); \
323 entry->age.wrap = dev_priv->sarea_priv->last_wrap; \
325 entry->age.head = 0; \
326 entry->age.wrap = 0; \
331 #define MGA_ENGINE_IDLE_MASK (MGA_SOFTRAPEN | \
334 #define MGA_DMA_IDLE_MASK (MGA_SOFTRAPEN | \
337 #define MGA_DMA_DEBUG 0
341 /* A reduced set of the mga registers.
343 #define MGA_CRTC_INDEX 0x1fd4
344 #define MGA_CRTC_DATA 0x1fd5
347 #define MGA_VINTCLR (1 << 4)
348 #define MGA_VINTEN (1 << 5)
350 #define MGA_ALPHACTRL 0x2c7c
351 #define MGA_AR0 0x1c60
352 #define MGA_AR1 0x1c64
353 #define MGA_AR2 0x1c68
354 #define MGA_AR3 0x1c6c
355 #define MGA_AR4 0x1c70
356 #define MGA_AR5 0x1c74
357 #define MGA_AR6 0x1c78
359 #define MGA_CXBNDRY 0x1c80
360 #define MGA_CXLEFT 0x1ca0
361 #define MGA_CXRIGHT 0x1ca4
363 #define MGA_DMAPAD 0x1c54
364 #define MGA_DSTORG 0x2cb8
365 #define MGA_DWGCTL 0x1c00
366 # define MGA_OPCOD_MASK (15 << 0)
367 # define MGA_OPCOD_TRAP (4 << 0)
368 # define MGA_OPCOD_TEXTURE_TRAP (6 << 0)
369 # define MGA_OPCOD_BITBLT (8 << 0)
370 # define MGA_OPCOD_ILOAD (9 << 0)
371 # define MGA_ATYPE_MASK (7 << 4)
372 # define MGA_ATYPE_RPL (0 << 4)
373 # define MGA_ATYPE_RSTR (1 << 4)
374 # define MGA_ATYPE_ZI (3 << 4)
375 # define MGA_ATYPE_BLK (4 << 4)
376 # define MGA_ATYPE_I (7 << 4)
377 # define MGA_LINEAR (1 << 7)
378 # define MGA_ZMODE_MASK (7 << 8)
379 # define MGA_ZMODE_NOZCMP (0 << 8)
380 # define MGA_ZMODE_ZE (2 << 8)
381 # define MGA_ZMODE_ZNE (3 << 8)
382 # define MGA_ZMODE_ZLT (4 << 8)
383 # define MGA_ZMODE_ZLTE (5 << 8)
384 # define MGA_ZMODE_ZGT (6 << 8)
385 # define MGA_ZMODE_ZGTE (7 << 8)
386 # define MGA_SOLID (1 << 11)
387 # define MGA_ARZERO (1 << 12)
388 # define MGA_SGNZERO (1 << 13)
389 # define MGA_SHIFTZERO (1 << 14)
390 # define MGA_BOP_MASK (15 << 16)
391 # define MGA_BOP_ZERO (0 << 16)
392 # define MGA_BOP_DST (10 << 16)
393 # define MGA_BOP_SRC (12 << 16)
394 # define MGA_BOP_ONE (15 << 16)
395 # define MGA_TRANS_SHIFT 20
396 # define MGA_TRANS_MASK (15 << 20)
397 # define MGA_BLTMOD_MASK (15 << 25)
398 # define MGA_BLTMOD_BMONOLEF (0 << 25)
399 # define MGA_BLTMOD_BMONOWF (4 << 25)
400 # define MGA_BLTMOD_PLAN (1 << 25)
401 # define MGA_BLTMOD_BFCOL (2 << 25)
402 # define MGA_BLTMOD_BU32BGR (3 << 25)
403 # define MGA_BLTMOD_BU32RGB (7 << 25)
404 # define MGA_BLTMOD_BU24BGR (11 << 25)
405 # define MGA_BLTMOD_BU24RGB (15 << 25)
406 # define MGA_PATTERN (1 << 29)
407 # define MGA_TRANSC (1 << 30)
408 # define MGA_CLIPDIS (1 << 31)
409 #define MGA_DWGSYNC 0x2c4c
411 #define MGA_FCOL 0x1c24
412 #define MGA_FIFOSTATUS 0x1e10
413 #define MGA_FOGCOL 0x1cf4
414 #define MGA_FXBNDRY 0x1c84
415 #define MGA_FXLEFT 0x1ca8
416 #define MGA_FXRIGHT 0x1cac
418 #define MGA_ICLEAR 0x1e18
419 # define MGA_SOFTRAPICLR (1 << 0)
420 # define MGA_VLINEICLR (1 << 5)
421 #define MGA_IEN 0x1e1c
422 # define MGA_SOFTRAPIEN (1 << 0)
423 # define MGA_VLINEIEN (1 << 5)
425 #define MGA_LEN 0x1c5c
427 #define MGA_MACCESS 0x1c04
429 #define MGA_PITCH 0x1c8c
430 #define MGA_PLNWT 0x1c1c
431 #define MGA_PRIMADDRESS 0x1e58
432 # define MGA_DMA_GENERAL (0 << 0)
433 # define MGA_DMA_BLIT (1 << 0)
434 # define MGA_DMA_VECTOR (2 << 0)
435 # define MGA_DMA_VERTEX (3 << 0)
436 #define MGA_PRIMEND 0x1e5c
437 # define MGA_PRIMNOSTART (1 << 0)
438 # define MGA_PAGPXFER (1 << 1)
439 #define MGA_PRIMPTR 0x1e50
440 # define MGA_PRIMPTREN0 (1 << 0)
441 # define MGA_PRIMPTREN1 (1 << 1)
443 #define MGA_RST 0x1e40
444 # define MGA_SOFTRESET (1 << 0)
445 # define MGA_SOFTEXTRST (1 << 1)
447 #define MGA_SECADDRESS 0x2c40
448 #define MGA_SECEND 0x2c44
449 #define MGA_SETUPADDRESS 0x2cd0
450 #define MGA_SETUPEND 0x2cd4
451 #define MGA_SGN 0x1c58
452 #define MGA_SOFTRAP 0x2c48
453 #define MGA_SRCORG 0x2cb4
454 # define MGA_SRMMAP_MASK (1 << 0)
455 # define MGA_SRCMAP_FB (0 << 0)
456 # define MGA_SRCMAP_SYSMEM (1 << 0)
457 # define MGA_SRCACC_MASK (1 << 1)
458 # define MGA_SRCACC_PCI (0 << 1)
459 # define MGA_SRCACC_AGP (1 << 1)
460 #define MGA_STATUS 0x1e14
461 # define MGA_SOFTRAPEN (1 << 0)
462 # define MGA_VSYNCPEN (1 << 4)
463 # define MGA_VLINEPEN (1 << 5)
464 # define MGA_DWGENGSTS (1 << 16)
465 # define MGA_ENDPRDMASTS (1 << 17)
466 #define MGA_STENCIL 0x2cc8
467 #define MGA_STENCILCTL 0x2ccc
469 #define MGA_TDUALSTAGE0 0x2cf8
470 #define MGA_TDUALSTAGE1 0x2cfc
471 #define MGA_TEXBORDERCOL 0x2c5c
472 #define MGA_TEXCTL 0x2c30
473 #define MGA_TEXCTL2 0x2c3c
474 # define MGA_DUALTEX (1 << 7)
475 # define MGA_G400_TC2_MAGIC (1 << 15)
476 # define MGA_MAP1_ENABLE (1 << 31)
477 #define MGA_TEXFILTER 0x2c58
478 #define MGA_TEXHEIGHT 0x2c2c
479 #define MGA_TEXORG 0x2c24
480 # define MGA_TEXORGMAP_MASK (1 << 0)
481 # define MGA_TEXORGMAP_FB (0 << 0)
482 # define MGA_TEXORGMAP_SYSMEM (1 << 0)
483 # define MGA_TEXORGACC_MASK (1 << 1)
484 # define MGA_TEXORGACC_PCI (0 << 1)
485 # define MGA_TEXORGACC_AGP (1 << 1)
486 #define MGA_TEXORG1 0x2ca4
487 #define MGA_TEXORG2 0x2ca8
488 #define MGA_TEXORG3 0x2cac
489 #define MGA_TEXORG4 0x2cb0
490 #define MGA_TEXTRANS 0x2c34
491 #define MGA_TEXTRANSHIGH 0x2c38
492 #define MGA_TEXWIDTH 0x2c28
494 #define MGA_WACCEPTSEQ 0x1dd4
495 #define MGA_WCODEADDR 0x1e6c
496 #define MGA_WFLAG 0x1dc4
497 #define MGA_WFLAG1 0x1de0
498 #define MGA_WFLAGNB 0x1e64
499 #define MGA_WFLAGNB1 0x1e08
500 #define MGA_WGETMSB 0x1dc8
501 #define MGA_WIADDR 0x1dc0
502 #define MGA_WIADDR2 0x1dd8
503 # define MGA_WMODE_SUSPEND (0 << 0)
504 # define MGA_WMODE_RESUME (1 << 0)
505 # define MGA_WMODE_JUMP (2 << 0)
506 # define MGA_WMODE_START (3 << 0)
507 # define MGA_WAGP_ENABLE (1 << 2)
508 #define MGA_WMISC 0x1e70
509 # define MGA_WUCODECACHE_ENABLE (1 << 0)
510 # define MGA_WMASTER_ENABLE (1 << 1)
511 # define MGA_WCACHEFLUSH_ENABLE (1 << 3)
512 #define MGA_WVRTXSZ 0x1dcc
514 #define MGA_YBOT 0x1c9c
515 #define MGA_YDST 0x1c90
516 #define MGA_YDSTLEN 0x1c88
517 #define MGA_YDSTORG 0x1c94
518 #define MGA_YTOP 0x1c98
520 #define MGA_ZORG 0x1c0c
522 /* This finishes the current batch of commands
524 #define MGA_EXEC 0x0100
528 #define MGA_WR0 0x2d00
529 #define MGA_WR1 0x2d04
530 #define MGA_WR2 0x2d08
531 #define MGA_WR3 0x2d0c
532 #define MGA_WR4 0x2d10
533 #define MGA_WR5 0x2d14
534 #define MGA_WR6 0x2d18
535 #define MGA_WR7 0x2d1c
536 #define MGA_WR8 0x2d20
537 #define MGA_WR9 0x2d24
538 #define MGA_WR10 0x2d28
539 #define MGA_WR11 0x2d2c
540 #define MGA_WR12 0x2d30
541 #define MGA_WR13 0x2d34
542 #define MGA_WR14 0x2d38
543 #define MGA_WR15 0x2d3c
544 #define MGA_WR16 0x2d40
545 #define MGA_WR17 0x2d44
546 #define MGA_WR18 0x2d48
547 #define MGA_WR19 0x2d4c
548 #define MGA_WR20 0x2d50
549 #define MGA_WR21 0x2d54
550 #define MGA_WR22 0x2d58
551 #define MGA_WR23 0x2d5c
552 #define MGA_WR24 0x2d60
553 #define MGA_WR25 0x2d64
554 #define MGA_WR26 0x2d68
555 #define MGA_WR27 0x2d6c
556 #define MGA_WR28 0x2d70
557 #define MGA_WR29 0x2d74
558 #define MGA_WR30 0x2d78
559 #define MGA_WR31 0x2d7c
560 #define MGA_WR32 0x2d80
561 #define MGA_WR33 0x2d84
562 #define MGA_WR34 0x2d88
563 #define MGA_WR35 0x2d8c
564 #define MGA_WR36 0x2d90
565 #define MGA_WR37 0x2d94
566 #define MGA_WR38 0x2d98
567 #define MGA_WR39 0x2d9c
568 #define MGA_WR40 0x2da0
569 #define MGA_WR41 0x2da4
570 #define MGA_WR42 0x2da8
571 #define MGA_WR43 0x2dac
572 #define MGA_WR44 0x2db0
573 #define MGA_WR45 0x2db4
574 #define MGA_WR46 0x2db8
575 #define MGA_WR47 0x2dbc
576 #define MGA_WR48 0x2dc0
577 #define MGA_WR49 0x2dc4
578 #define MGA_WR50 0x2dc8
579 #define MGA_WR51 0x2dcc
580 #define MGA_WR52 0x2dd0
581 #define MGA_WR53 0x2dd4
582 #define MGA_WR54 0x2dd8
583 #define MGA_WR55 0x2ddc
584 #define MGA_WR56 0x2de0
585 #define MGA_WR57 0x2de4
586 #define MGA_WR58 0x2de8
587 #define MGA_WR59 0x2dec
588 #define MGA_WR60 0x2df0
589 #define MGA_WR61 0x2df4
590 #define MGA_WR62 0x2df8
591 #define MGA_WR63 0x2dfc
592 # define MGA_G400_WR_MAGIC (1 << 6)
593 # define MGA_G400_WR56_MAGIC 0x46480000 /* 12800.0f */
596 #define MGA_ILOAD_ALIGN 64
597 #define MGA_ILOAD_MASK (MGA_ILOAD_ALIGN - 1)
599 #define MGA_DWGCTL_FLUSH (MGA_OPCOD_TEXTURE_TRAP | \
605 (15 << MGA_TRANS_SHIFT))
607 #define MGA_DWGCTL_CLEAR (MGA_OPCOD_TRAP | \
614 (0 << MGA_TRANS_SHIFT) | \
615 MGA_BLTMOD_BMONOLEF | \
619 #define MGA_DWGCTL_COPY (MGA_OPCOD_BITBLT | \
624 (0 << MGA_TRANS_SHIFT) | \
630 static __inline__ int mga_is_idle( drm_mga_private_t *dev_priv )
632 u32 status = MGA_READ( MGA_STATUS ) & MGA_ENGINE_IDLE_MASK;
633 return ( status == MGA_ENDPRDMASTS );