drivers/char/drm/radeon_state.c

   1 /* radeon_state.c -- State support for Radeon -*- linux-c -*-
   2  *
   3  * Copyright 2000 VA Linux Systems, Inc., Fremont, California.
   4  * All Rights Reserved.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice (including the next
  14  * paragraph) shall be included in all copies or substantial portions of the
  15  * Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  20  * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
  21  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  22  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  23  * DEALINGS IN THE SOFTWARE.
  24  *
  25  * Authors:
  26  *    Gareth Hughes <gareth@valinux.com>
  27  *    Kevin E. Martin <martin@valinux.com>
  28  */
  29
  30 #include "radeon.h"
  31 #include "drmP.h"
  32 #include "drm.h"
  33 #include "drm_sarea.h"
  34 #include "radeon_drm.h"
  35 #include "radeon_drv.h"
  36
  37
  38 /* ================================================================
  39  * Helper functions for client state checking and fixup
  40  */
  41
  42 static __inline__ int radeon_check_and_fixup_offset( drm_radeon_private_t *dev_priv,
  43                                                      drm_file_t *filp_priv,
  44                                                      u32 *offset ) {
  45         u32 off = *offset;
  46         struct drm_radeon_driver_file_fields *radeon_priv;
  47
  48         if ( off >= dev_priv->fb_location &&
  49              off < ( dev_priv->gart_vm_start + dev_priv->gart_size ) )
  50                 return 0;
  51
  52         radeon_priv = filp_priv->driver_priv;
  53         off += radeon_priv->radeon_fb_delta;
  54
  55         DRM_DEBUG( "offset fixed up to 0x%x\n", off );
  56
  57         if ( off < dev_priv->fb_location ||
  58              off >= ( dev_priv->gart_vm_start + dev_priv->gart_size ) )
  59                 return DRM_ERR( EINVAL );
  60
  61         *offset = off;
  62
  63         return 0;
  64 }
  65
  66 static __inline__ int radeon_check_and_fixup_packets( drm_radeon_private_t *dev_priv,
  67                                                       drm_file_t *filp_priv,
  68                                                       int id,
  69                                                       u32 __user *data ) {
  70         switch ( id ) {
  71
  72         case RADEON_EMIT_PP_MISC:
  73                 if ( radeon_check_and_fixup_offset( dev_priv, filp_priv,
  74                                                     &data[( RADEON_RB3D_DEPTHOFFSET
  75                                                             - RADEON_PP_MISC ) / 4] ) ) {
  76                         DRM_ERROR( "Invalid depth buffer offset\n" );
  77                         return DRM_ERR( EINVAL );
  78                 }
  79                 break;
  80
  81         case RADEON_EMIT_PP_CNTL:
  82                 if ( radeon_check_and_fixup_offset( dev_priv, filp_priv,
  83                                                     &data[( RADEON_RB3D_COLOROFFSET
  84                                                             - RADEON_PP_CNTL ) / 4] ) ) {
  85                         DRM_ERROR( "Invalid colour buffer offset\n" );
  86                         return DRM_ERR( EINVAL );
  87                 }
  88                 break;
  89
  90         case R200_EMIT_PP_TXOFFSET_0:
  91         case R200_EMIT_PP_TXOFFSET_1:
  92         case R200_EMIT_PP_TXOFFSET_2:
  93         case R200_EMIT_PP_TXOFFSET_3:
  94         case R200_EMIT_PP_TXOFFSET_4:
  95         case R200_EMIT_PP_TXOFFSET_5:
  96                 if ( radeon_check_and_fixup_offset( dev_priv, filp_priv,
  97                                                     &data[0] ) ) {
  98                         DRM_ERROR( "Invalid R200 texture offset\n" );
  99                         return DRM_ERR( EINVAL );
 100                 }
 101                 break;
 102
 103         case RADEON_EMIT_PP_TXFILTER_0:
 104         case RADEON_EMIT_PP_TXFILTER_1:
 105         case RADEON_EMIT_PP_TXFILTER_2:
 106                 if ( radeon_check_and_fixup_offset( dev_priv, filp_priv,
 107                                                     &data[( RADEON_PP_TXOFFSET_0
 108                                                             - RADEON_PP_TXFILTER_0 ) / 4] ) ) {
 109                         DRM_ERROR( "Invalid R100 texture offset\n" );
 110                         return DRM_ERR( EINVAL );
 111                 }
 112                 break;
 113
 114         case R200_EMIT_PP_CUBIC_OFFSETS_0:
 115         case R200_EMIT_PP_CUBIC_OFFSETS_1:
 116         case R200_EMIT_PP_CUBIC_OFFSETS_2:
 117         case R200_EMIT_PP_CUBIC_OFFSETS_3:
 118         case R200_EMIT_PP_CUBIC_OFFSETS_4:
 119         case R200_EMIT_PP_CUBIC_OFFSETS_5: {
 120                 int i;
 121                 for ( i = 0; i < 5; i++ ) {
 122                         if ( radeon_check_and_fixup_offset( dev_priv, filp_priv,
 123                                                             &data[i] ) ) {
 124                                 DRM_ERROR( "Invalid R200 cubic texture offset\n" );
 125                                 return DRM_ERR( EINVAL );
 126                         }
 127                 }
 128                 break;
 129         }
 130
 131         case RADEON_EMIT_RB3D_COLORPITCH:
 132         case RADEON_EMIT_RE_LINE_PATTERN:
 133         case RADEON_EMIT_SE_LINE_WIDTH:
 134         case RADEON_EMIT_PP_LUM_MATRIX:
 135         case RADEON_EMIT_PP_ROT_MATRIX_0:
 136         case RADEON_EMIT_RB3D_STENCILREFMASK:
 137         case RADEON_EMIT_SE_VPORT_XSCALE:
 138         case RADEON_EMIT_SE_CNTL:
 139         case RADEON_EMIT_SE_CNTL_STATUS:
 140         case RADEON_EMIT_RE_MISC:
 141         case RADEON_EMIT_PP_BORDER_COLOR_0:
 142         case RADEON_EMIT_PP_BORDER_COLOR_1:
 143         case RADEON_EMIT_PP_BORDER_COLOR_2:
 144         case RADEON_EMIT_SE_ZBIAS_FACTOR:
 145         case RADEON_EMIT_SE_TCL_OUTPUT_VTX_FMT:
 146         case RADEON_EMIT_SE_TCL_MATERIAL_EMMISSIVE_RED:
 147         case R200_EMIT_PP_TXCBLEND_0:
 148         case R200_EMIT_PP_TXCBLEND_1:
 149         case R200_EMIT_PP_TXCBLEND_2:
 150         case R200_EMIT_PP_TXCBLEND_3:
 151         case R200_EMIT_PP_TXCBLEND_4:
 152         case R200_EMIT_PP_TXCBLEND_5:
 153         case R200_EMIT_PP_TXCBLEND_6:
 154         case R200_EMIT_PP_TXCBLEND_7:
 155         case R200_EMIT_TCL_LIGHT_MODEL_CTL_0:
 156         case R200_EMIT_TFACTOR_0:
 157         case R200_EMIT_VTX_FMT_0:
 158         case R200_EMIT_VAP_CTL:
 159         case R200_EMIT_MATRIX_SELECT_0:
 160         case R200_EMIT_TEX_PROC_CTL_2:
 161         case R200_EMIT_TCL_UCP_VERT_BLEND_CTL:
 162         case R200_EMIT_PP_TXFILTER_0:
 163         case R200_EMIT_PP_TXFILTER_1:
 164         case R200_EMIT_PP_TXFILTER_2:
 165         case R200_EMIT_PP_TXFILTER_3:
 166         case R200_EMIT_PP_TXFILTER_4:
 167         case R200_EMIT_PP_TXFILTER_5:
 168         case R200_EMIT_VTE_CNTL:
 169         case R200_EMIT_OUTPUT_VTX_COMP_SEL:
 170         case R200_EMIT_PP_TAM_DEBUG3:
 171         case R200_EMIT_PP_CNTL_X:
 172         case R200_EMIT_RB3D_DEPTHXY_OFFSET:
 173         case R200_EMIT_RE_AUX_SCISSOR_CNTL:
 174         case R200_EMIT_RE_SCISSOR_TL_0:
 175         case R200_EMIT_RE_SCISSOR_TL_1:
 176         case R200_EMIT_RE_SCISSOR_TL_2:
 177         case R200_EMIT_SE_VAP_CNTL_STATUS:
 178         case R200_EMIT_SE_VTX_STATE_CNTL:
 179         case R200_EMIT_RE_POINTSIZE:
 180         case R200_EMIT_TCL_INPUT_VTX_VECTOR_ADDR_0:
 181         case R200_EMIT_PP_CUBIC_FACES_0:
 182         case R200_EMIT_PP_CUBIC_FACES_1:
 183         case R200_EMIT_PP_CUBIC_FACES_2:
 184         case R200_EMIT_PP_CUBIC_FACES_3:
 185         case R200_EMIT_PP_CUBIC_FACES_4:
 186         case R200_EMIT_PP_CUBIC_FACES_5:
 187         case RADEON_EMIT_PP_TEX_SIZE_0:
 188         case RADEON_EMIT_PP_TEX_SIZE_1:
 189         case RADEON_EMIT_PP_TEX_SIZE_2:
 190         case R200_EMIT_RB3D_BLENDCOLOR:
 191                 /* These packets don't contain memory offsets */
 192                 break;
 193
 194         default:
 195                 DRM_ERROR( "Unknown state packet ID %d\n", id );
 196                 return DRM_ERR( EINVAL );
 197         }
 198
 199         return 0;
 200 }
 201
 202 static __inline__ int radeon_check_and_fixup_packet3( drm_radeon_private_t *dev_priv,
 203                                                       drm_file_t *filp_priv,
 204                                                       drm_radeon_cmd_buffer_t *cmdbuf,
 205                                                       unsigned int *cmdsz ) {
 206         u32 *cmd = (u32 *) cmdbuf->buf;
 207
 208         *cmdsz = 2 + ( ( cmd[0] & RADEON_CP_PACKET_COUNT_MASK ) >> 16 );
 209
 210         if ( ( cmd[0] & 0xc0000000 ) != RADEON_CP_PACKET3 ) {
 211                 DRM_ERROR( "Not a type 3 packet\n" );
 212                 return DRM_ERR( EINVAL );
 213         }
 214
 215         if ( 4 * *cmdsz > cmdbuf->bufsz ) {
 216                 DRM_ERROR( "Packet size larger than size of data provided\n" );
 217                 return DRM_ERR( EINVAL );
 218         }
 219
 220         /* Check client state and fix it up if necessary */
 221         if ( cmd[0] & 0x8000 ) { /* MSB of opcode: next DWORD GUI_CNTL */
 222                 u32 offset;
 223
 224                 if ( cmd[1] & ( RADEON_GMC_SRC_PITCH_OFFSET_CNTL
 225                               | RADEON_GMC_DST_PITCH_OFFSET_CNTL ) ) {
 226                         offset = cmd[2] << 10;
 227                         if ( radeon_check_and_fixup_offset( dev_priv, filp_priv, &offset ) ) {
 228                                 DRM_ERROR( "Invalid first packet offset\n" );
 229                                 return DRM_ERR( EINVAL );
 230                         }
 231                         cmd[2] = ( cmd[2] & 0xffc00000 ) | offset >> 10;
 232                 }
 233
 234                 if ( ( cmd[1] & RADEON_GMC_SRC_PITCH_OFFSET_CNTL ) &&
 235                      ( cmd[1] & RADEON_GMC_DST_PITCH_OFFSET_CNTL ) ) {
 236                         offset = cmd[3] << 10;
 237                         if ( radeon_check_and_fixup_offset( dev_priv, filp_priv, &offset ) ) {
 238                                 DRM_ERROR( "Invalid second packet offset\n" );
 239                                 return DRM_ERR( EINVAL );
 240                         }
 241                         cmd[3] = ( cmd[3] & 0xffc00000 ) | offset >> 10;
 242                 }
 243         }
 244
 245         return 0;
 246 }
 247
 248
 249 /* ================================================================
 250  * CP hardware state programming functions
 251  */
 252
 253 static __inline__ void radeon_emit_clip_rect( drm_radeon_private_t *dev_priv,
 254                                           drm_clip_rect_t *box )
 255 {
 256         RING_LOCALS;
 257
 258         DRM_DEBUG( "   box:  x1=%d y1=%d  x2=%d y2=%d\n",
 259                    box->x1, box->y1, box->x2, box->y2 );
 260
 261         BEGIN_RING( 4 );
 262         OUT_RING( CP_PACKET0( RADEON_RE_TOP_LEFT, 0 ) );
 263         OUT_RING( (box->y1 << 16) | box->x1 );
 264         OUT_RING( CP_PACKET0( RADEON_RE_WIDTH_HEIGHT, 0 ) );
 265         OUT_RING( ((box->y2 - 1) << 16) | (box->x2 - 1) );
 266         ADVANCE_RING();
 267 }
 268
 269 /* Emit 1.1 state
 270  */
 271 static int radeon_emit_state( drm_radeon_private_t *dev_priv,
 272                               drm_file_t *filp_priv,
 273                               drm_radeon_context_regs_t *ctx,
 274                               drm_radeon_texture_regs_t *tex,
 275                               unsigned int dirty )
 276 {
 277         RING_LOCALS;
 278         DRM_DEBUG( "dirty=0x%08x\n", dirty );
 279
 280         if ( dirty & RADEON_UPLOAD_CONTEXT ) {
 281                 if ( radeon_check_and_fixup_offset( dev_priv, filp_priv,
 282                                                     &ctx->rb3d_depthoffset ) ) {
 283                         DRM_ERROR( "Invalid depth buffer offset\n" );
 284                         return DRM_ERR( EINVAL );
 285                 }
 286
 287                 if ( radeon_check_and_fixup_offset( dev_priv, filp_priv,
 288                                                     &ctx->rb3d_coloroffset ) ) {
 289                         DRM_ERROR( "Invalid depth buffer offset\n" );
 290                         return DRM_ERR( EINVAL );
 291                 }
 292
 293                 BEGIN_RING( 14 );
 294                 OUT_RING( CP_PACKET0( RADEON_PP_MISC, 6 ) );
 295                 OUT_RING( ctx->pp_misc );
 296                 OUT_RING( ctx->pp_fog_color );
 297                 OUT_RING( ctx->re_solid_color );
 298                 OUT_RING( ctx->rb3d_blendcntl );
 299                 OUT_RING( ctx->rb3d_depthoffset );
 300                 OUT_RING( ctx->rb3d_depthpitch );
 301                 OUT_RING( ctx->rb3d_zstencilcntl );
 302                 OUT_RING( CP_PACKET0( RADEON_PP_CNTL, 2 ) );
 303                 OUT_RING( ctx->pp_cntl );
 304                 OUT_RING( ctx->rb3d_cntl );
 305                 OUT_RING( ctx->rb3d_coloroffset );
 306                 OUT_RING( CP_PACKET0( RADEON_RB3D_COLORPITCH, 0 ) );
 307                 OUT_RING( ctx->rb3d_colorpitch );
 308                 ADVANCE_RING();
 309         }
 310
 311         if ( dirty & RADEON_UPLOAD_VERTFMT ) {
 312                 BEGIN_RING( 2 );
 313                 OUT_RING( CP_PACKET0( RADEON_SE_COORD_FMT, 0 ) );
 314                 OUT_RING( ctx->se_coord_fmt );
 315                 ADVANCE_RING();
 316         }
 317
 318         if ( dirty & RADEON_UPLOAD_LINE ) {
 319                 BEGIN_RING( 5 );
 320                 OUT_RING( CP_PACKET0( RADEON_RE_LINE_PATTERN, 1 ) );
 321                 OUT_RING( ctx->re_line_pattern );
 322                 OUT_RING( ctx->re_line_state );
 323                 OUT_RING( CP_PACKET0( RADEON_SE_LINE_WIDTH, 0 ) );
 324                 OUT_RING( ctx->se_line_width );
 325                 ADVANCE_RING();
 326         }
 327
 328         if ( dirty & RADEON_UPLOAD_BUMPMAP ) {
 329                 BEGIN_RING( 5 );
 330                 OUT_RING( CP_PACKET0( RADEON_PP_LUM_MATRIX, 0 ) );
 331                 OUT_RING( ctx->pp_lum_matrix );
 332                 OUT_RING( CP_PACKET0( RADEON_PP_ROT_MATRIX_0, 1 ) );
 333                 OUT_RING( ctx->pp_rot_matrix_0 );
 334                 OUT_RING( ctx->pp_rot_matrix_1 );
 335                 ADVANCE_RING();
 336         }
 337
 338         if ( dirty & RADEON_UPLOAD_MASKS ) {
 339                 BEGIN_RING( 4 );
 340                 OUT_RING( CP_PACKET0( RADEON_RB3D_STENCILREFMASK, 2 ) );
 341                 OUT_RING( ctx->rb3d_stencilrefmask );
 342                 OUT_RING( ctx->rb3d_ropcntl );
 343                 OUT_RING( ctx->rb3d_planemask );
 344                 ADVANCE_RING();
 345         }
 346
 347         if ( dirty & RADEON_UPLOAD_VIEWPORT ) {
 348                 BEGIN_RING( 7 );
 349                 OUT_RING( CP_PACKET0( RADEON_SE_VPORT_XSCALE, 5 ) );
 350                 OUT_RING( ctx->se_vport_xscale );
 351                 OUT_RING( ctx->se_vport_xoffset );
 352                 OUT_RING( ctx->se_vport_yscale );
 353                 OUT_RING( ctx->se_vport_yoffset );
 354                 OUT_RING( ctx->se_vport_zscale );
 355                 OUT_RING( ctx->se_vport_zoffset );
 356                 ADVANCE_RING();
 357         }
 358
 359         if ( dirty & RADEON_UPLOAD_SETUP ) {
 360                 BEGIN_RING( 4 );
 361                 OUT_RING( CP_PACKET0( RADEON_SE_CNTL, 0 ) );
 362                 OUT_RING( ctx->se_cntl );
 363                 OUT_RING( CP_PACKET0( RADEON_SE_CNTL_STATUS, 0 ) );
 364                 OUT_RING( ctx->se_cntl_status );
 365                 ADVANCE_RING();
 366         }
 367
 368         if ( dirty & RADEON_UPLOAD_MISC ) {
 369                 BEGIN_RING( 2 );
 370                 OUT_RING( CP_PACKET0( RADEON_RE_MISC, 0 ) );
 371                 OUT_RING( ctx->re_misc );
 372                 ADVANCE_RING();
 373         }
 374
 375         if ( dirty & RADEON_UPLOAD_TEX0 ) {
 376                 if ( radeon_check_and_fixup_offset( dev_priv, filp_priv,
 377                                                     &tex[0].pp_txoffset ) ) {
 378                         DRM_ERROR( "Invalid texture offset for unit 0\n" );
 379                         return DRM_ERR( EINVAL );
 380                 }
 381
 382                 BEGIN_RING( 9 );
 383                 OUT_RING( CP_PACKET0( RADEON_PP_TXFILTER_0, 5 ) );
 384                 OUT_RING( tex[0].pp_txfilter );
 385                 OUT_RING( tex[0].pp_txformat );
 386                 OUT_RING( tex[0].pp_txoffset );
 387                 OUT_RING( tex[0].pp_txcblend );
 388                 OUT_RING( tex[0].pp_txablend );
 389                 OUT_RING( tex[0].pp_tfactor );
 390                 OUT_RING( CP_PACKET0( RADEON_PP_BORDER_COLOR_0, 0 ) );
 391                 OUT_RING( tex[0].pp_border_color );
 392                 ADVANCE_RING();
 393         }
 394
 395         if ( dirty & RADEON_UPLOAD_TEX1 ) {
 396                 if ( radeon_check_and_fixup_offset( dev_priv, filp_priv,
 397                                                     &tex[1].pp_txoffset ) ) {
 398                         DRM_ERROR( "Invalid texture offset for unit 1\n" );
 399                         return DRM_ERR( EINVAL );
 400                 }
 401
 402                 BEGIN_RING( 9 );
 403                 OUT_RING( CP_PACKET0( RADEON_PP_TXFILTER_1, 5 ) );
 404                 OUT_RING( tex[1].pp_txfilter );
 405                 OUT_RING( tex[1].pp_txformat );
 406                 OUT_RING( tex[1].pp_txoffset );
 407                 OUT_RING( tex[1].pp_txcblend );
 408                 OUT_RING( tex[1].pp_txablend );
 409                 OUT_RING( tex[1].pp_tfactor );
 410                 OUT_RING( CP_PACKET0( RADEON_PP_BORDER_COLOR_1, 0 ) );
 411                 OUT_RING( tex[1].pp_border_color );
 412                 ADVANCE_RING();
 413         }
 414
 415         if ( dirty & RADEON_UPLOAD_TEX2 ) {
 416                 if ( radeon_check_and_fixup_offset( dev_priv, filp_priv,
 417                                                     &tex[2].pp_txoffset ) ) {
 418                         DRM_ERROR( "Invalid texture offset for unit 2\n" );
 419                         return DRM_ERR( EINVAL );
 420                 }
 421
 422                 BEGIN_RING( 9 );
 423                 OUT_RING( CP_PACKET0( RADEON_PP_TXFILTER_2, 5 ) );
 424                 OUT_RING( tex[2].pp_txfilter );
 425                 OUT_RING( tex[2].pp_txformat );
 426                 OUT_RING( tex[2].pp_txoffset );
 427                 OUT_RING( tex[2].pp_txcblend );
 428                 OUT_RING( tex[2].pp_txablend );
 429                 OUT_RING( tex[2].pp_tfactor );
 430                 OUT_RING( CP_PACKET0( RADEON_PP_BORDER_COLOR_2, 0 ) );
 431                 OUT_RING( tex[2].pp_border_color );
 432                 ADVANCE_RING();
 433         }
 434
 435         return 0;
 436 }
 437
 438 /* Emit 1.2 state
 439  */
 440 static int radeon_emit_state2( drm_radeon_private_t *dev_priv,
 441                                drm_file_t *filp_priv,
 442                                drm_radeon_state_t *state )
 443 {
 444         RING_LOCALS;
 445
 446         if (state->dirty & RADEON_UPLOAD_ZBIAS) {
 447                 BEGIN_RING( 3 );
 448                 OUT_RING( CP_PACKET0( RADEON_SE_ZBIAS_FACTOR, 1 ) );
 449                 OUT_RING( state->context2.se_zbias_factor );
 450                 OUT_RING( state->context2.se_zbias_constant );
 451                 ADVANCE_RING();
 452         }
 453
 454         return radeon_emit_state( dev_priv, filp_priv, &state->context,
 455                            state->tex, state->dirty );
 456 }
 457
 458 /* New (1.3) state mechanism.  3 commands (packet, scalar, vector) in
 459  * 1.3 cmdbuffers allow all previous state to be updated as well as
 460  * the tcl scalar and vector areas.
 461  */
 462 static struct {
 463         int start;
 464         int len;
 465         const char *name;
 466 } packet[RADEON_MAX_STATE_PACKETS] = {
 467         { RADEON_PP_MISC,7,"RADEON_PP_MISC" },
 468         { RADEON_PP_CNTL,3,"RADEON_PP_CNTL" },
 469         { RADEON_RB3D_COLORPITCH,1,"RADEON_RB3D_COLORPITCH" },
 470         { RADEON_RE_LINE_PATTERN,2,"RADEON_RE_LINE_PATTERN" },
 471         { RADEON_SE_LINE_WIDTH,1,"RADEON_SE_LINE_WIDTH" },
 472         { RADEON_PP_LUM_MATRIX,1,"RADEON_PP_LUM_MATRIX" },
 473         { RADEON_PP_ROT_MATRIX_0,2,"RADEON_PP_ROT_MATRIX_0" },
 474         { RADEON_RB3D_STENCILREFMASK,3,"RADEON_RB3D_STENCILREFMASK" },
 475         { RADEON_SE_VPORT_XSCALE,6,"RADEON_SE_VPORT_XSCALE" },
 476         { RADEON_SE_CNTL,2,"RADEON_SE_CNTL" },
 477         { RADEON_SE_CNTL_STATUS,1,"RADEON_SE_CNTL_STATUS" },
 478         { RADEON_RE_MISC,1,"RADEON_RE_MISC" },
 479         { RADEON_PP_TXFILTER_0,6,"RADEON_PP_TXFILTER_0" },
 480         { RADEON_PP_BORDER_COLOR_0,1,"RADEON_PP_BORDER_COLOR_0" },
 481         { RADEON_PP_TXFILTER_1,6,"RADEON_PP_TXFILTER_1" },
 482         { RADEON_PP_BORDER_COLOR_1,1,"RADEON_PP_BORDER_COLOR_1" },
 483         { RADEON_PP_TXFILTER_2,6,"RADEON_PP_TXFILTER_2" },
 484         { RADEON_PP_BORDER_COLOR_2,1,"RADEON_PP_BORDER_COLOR_2" },
 485         { RADEON_SE_ZBIAS_FACTOR,2,"RADEON_SE_ZBIAS_FACTOR" },
 486         { RADEON_SE_TCL_OUTPUT_VTX_FMT,11,"RADEON_SE_TCL_OUTPUT_VTX_FMT" },
 487         { RADEON_SE_TCL_MATERIAL_EMMISSIVE_RED,17,"RADEON_SE_TCL_MATERIAL_EMMISSIVE_RED" },
 488         { R200_PP_TXCBLEND_0, 4, "R200_PP_TXCBLEND_0" },
 489         { R200_PP_TXCBLEND_1, 4, "R200_PP_TXCBLEND_1" },
 490         { R200_PP_TXCBLEND_2, 4, "R200_PP_TXCBLEND_2" },
 491         { R200_PP_TXCBLEND_3, 4, "R200_PP_TXCBLEND_3" },
 492         { R200_PP_TXCBLEND_4, 4, "R200_PP_TXCBLEND_4" },
 493         { R200_PP_TXCBLEND_5, 4, "R200_PP_TXCBLEND_5" },
 494         { R200_PP_TXCBLEND_6, 4, "R200_PP_TXCBLEND_6" },
 495         { R200_PP_TXCBLEND_7, 4, "R200_PP_TXCBLEND_7" },
 496         { R200_SE_TCL_LIGHT_MODEL_CTL_0, 6, "R200_SE_TCL_LIGHT_MODEL_CTL_0" },
 497         { R200_PP_TFACTOR_0, 6, "R200_PP_TFACTOR_0" },
 498         { R200_SE_VTX_FMT_0, 4, "R200_SE_VTX_FMT_0" },
 499         { R200_SE_VAP_CNTL, 1, "R200_SE_VAP_CNTL" },
 500         { R200_SE_TCL_MATRIX_SEL_0, 5, "R200_SE_TCL_MATRIX_SEL_0" },
 501         { R200_SE_TCL_TEX_PROC_CTL_2, 5, "R200_SE_TCL_TEX_PROC_CTL_2" },
 502         { R200_SE_TCL_UCP_VERT_BLEND_CTL, 1, "R200_SE_TCL_UCP_VERT_BLEND_CTL" },
 503         { R200_PP_TXFILTER_0, 6, "R200_PP_TXFILTER_0" },
 504         { R200_PP_TXFILTER_1, 6, "R200_PP_TXFILTER_1" },
 505         { R200_PP_TXFILTER_2, 6, "R200_PP_TXFILTER_2" },
 506         { R200_PP_TXFILTER_3, 6, "R200_PP_TXFILTER_3" },
 507         { R200_PP_TXFILTER_4, 6, "R200_PP_TXFILTER_4" },
 508         { R200_PP_TXFILTER_5, 6, "R200_PP_TXFILTER_5" },
 509         { R200_PP_TXOFFSET_0, 1, "R200_PP_TXOFFSET_0" },
 510         { R200_PP_TXOFFSET_1, 1, "R200_PP_TXOFFSET_1" },
 511         { R200_PP_TXOFFSET_2, 1, "R200_PP_TXOFFSET_2" },
 512         { R200_PP_TXOFFSET_3, 1, "R200_PP_TXOFFSET_3" },
 513         { R200_PP_TXOFFSET_4, 1, "R200_PP_TXOFFSET_4" },
 514         { R200_PP_TXOFFSET_5, 1, "R200_PP_TXOFFSET_5" },
 515         { R200_SE_VTE_CNTL, 1, "R200_SE_VTE_CNTL" },
 516         { R200_SE_TCL_OUTPUT_VTX_COMP_SEL, 1, "R200_SE_TCL_OUTPUT_VTX_COMP_SEL" },
 517         { R200_PP_TAM_DEBUG3, 1, "R200_PP_TAM_DEBUG3" },
 518         { R200_PP_CNTL_X, 1, "R200_PP_CNTL_X" },
 519         { R200_RB3D_DEPTHXY_OFFSET, 1, "R200_RB3D_DEPTHXY_OFFSET" },
 520         { R200_RE_AUX_SCISSOR_CNTL, 1, "R200_RE_AUX_SCISSOR_CNTL" },
 521         { R200_RE_SCISSOR_TL_0, 2, "R200_RE_SCISSOR_TL_0" },
 522         { R200_RE_SCISSOR_TL_1, 2, "R200_RE_SCISSOR_TL_1" },
 523         { R200_RE_SCISSOR_TL_2, 2, "R200_RE_SCISSOR_TL_2" },
 524         { R200_SE_VAP_CNTL_STATUS, 1, "R200_SE_VAP_CNTL_STATUS" },
 525         { R200_SE_VTX_STATE_CNTL, 1, "R200_SE_VTX_STATE_CNTL" },
 526         { R200_RE_POINTSIZE, 1, "R200_RE_POINTSIZE" },
 527         { R200_SE_TCL_INPUT_VTX_VECTOR_ADDR_0, 4, "R200_SE_TCL_INPUT_VTX_VECTOR_ADDR_0" },
 528         { R200_PP_CUBIC_FACES_0, 1, "R200_PP_CUBIC_FACES_0" }, /* 61 */
 529         { R200_PP_CUBIC_OFFSET_F1_0, 5, "R200_PP_CUBIC_OFFSET_F1_0" }, /* 62 */
 530         { R200_PP_CUBIC_FACES_1, 1, "R200_PP_CUBIC_FACES_1" },
 531         { R200_PP_CUBIC_OFFSET_F1_1, 5, "R200_PP_CUBIC_OFFSET_F1_1" },
 532         { R200_PP_CUBIC_FACES_2, 1, "R200_PP_CUBIC_FACES_2" },
 533         { R200_PP_CUBIC_OFFSET_F1_2, 5, "R200_PP_CUBIC_OFFSET_F1_2" },
 534         { R200_PP_CUBIC_FACES_3, 1, "R200_PP_CUBIC_FACES_3" },
 535         { R200_PP_CUBIC_OFFSET_F1_3, 5, "R200_PP_CUBIC_OFFSET_F1_3" },
 536         { R200_PP_CUBIC_FACES_4, 1, "R200_PP_CUBIC_FACES_4" },
 537         { R200_PP_CUBIC_OFFSET_F1_4, 5, "R200_PP_CUBIC_OFFSET_F1_4" },
 538         { R200_PP_CUBIC_FACES_5, 1, "R200_PP_CUBIC_FACES_5" },
 539         { R200_PP_CUBIC_OFFSET_F1_5, 5, "R200_PP_CUBIC_OFFSET_F1_5" },
 540         { RADEON_PP_TEX_SIZE_0, 2, "RADEON_PP_TEX_SIZE_0" },
 541         { RADEON_PP_TEX_SIZE_1, 2, "RADEON_PP_TEX_SIZE_1" },
 542         { RADEON_PP_TEX_SIZE_2, 2, "RADEON_PP_TEX_SIZE_2" },
 543         { R200_RB3D_BLENDCOLOR, 3, "R200_RB3D_BLENDCOLOR" },
 544 };
 545
 546
 547
 548 /* ================================================================
 549  * Performance monitoring functions
 550  */
 551
 552 static void radeon_clear_box( drm_radeon_private_t *dev_priv,
 553                               int x, int y, int w, int h,
 554                               int r, int g, int b )
 555 {
 556         u32 color;
 557         RING_LOCALS;
 558
 559         x += dev_priv->sarea_priv->boxes[0].x1;
 560         y += dev_priv->sarea_priv->boxes[0].y1;
 561
 562         switch ( dev_priv->color_fmt ) {
 563         case RADEON_COLOR_FORMAT_RGB565:
 564                 color = (((r & 0xf8) << 8) |
 565                          ((g & 0xfc) << 3) |
 566                          ((b & 0xf8) >> 3));
 567                 break;
 568         case RADEON_COLOR_FORMAT_ARGB8888:
 569         default:
 570                 color = (((0xff) << 24) | (r << 16) | (g <<  8) | b);
 571                 break;
 572         }
 573
 574         BEGIN_RING( 4 );
 575         RADEON_WAIT_UNTIL_3D_IDLE();
 576         OUT_RING( CP_PACKET0( RADEON_DP_WRITE_MASK, 0 ) );
 577         OUT_RING( 0xffffffff );
 578         ADVANCE_RING();
 579
 580         BEGIN_RING( 6 );
 581
 582         OUT_RING( CP_PACKET3( RADEON_CNTL_PAINT_MULTI, 4 ) );
 583         OUT_RING( RADEON_GMC_DST_PITCH_OFFSET_CNTL |
 584                   RADEON_GMC_BRUSH_SOLID_COLOR |
 585                   (dev_priv->color_fmt << 8) |
 586                   RADEON_GMC_SRC_DATATYPE_COLOR |
 587                   RADEON_ROP3_P |
 588                   RADEON_GMC_CLR_CMP_CNTL_DIS );
 589
 590         if ( dev_priv->page_flipping && dev_priv->current_page == 1 ) {
 591                 OUT_RING( dev_priv->front_pitch_offset );
 592         } else {
 593                 OUT_RING( dev_priv->back_pitch_offset );
 594         }
 595
 596         OUT_RING( color );
 597
 598         OUT_RING( (x << 16) | y );
 599         OUT_RING( (w << 16) | h );
 600
 601         ADVANCE_RING();
 602 }
 603
 604 static void radeon_cp_performance_boxes( drm_radeon_private_t *dev_priv )
 605 {
 606         /* Collapse various things into a wait flag -- trying to
 607          * guess if userspase slept -- better just to have them tell us.
 608          */
 609         if (dev_priv->stats.last_frame_reads > 1 ||
 610             dev_priv->stats.last_clear_reads > dev_priv->stats.clears) {
 611                 dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
 612         }
 613
 614         if (dev_priv->stats.freelist_loops) {
 615                 dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
 616         }
 617
 618         /* Purple box for page flipping
 619          */
 620         if ( dev_priv->stats.boxes & RADEON_BOX_FLIP )
 621                 radeon_clear_box( dev_priv, 4, 4, 8, 8, 255, 0, 255 );
 622
 623         /* Red box if we have to wait for idle at any point
 624          */
 625         if ( dev_priv->stats.boxes & RADEON_BOX_WAIT_IDLE )
 626                 radeon_clear_box( dev_priv, 16, 4, 8, 8, 255, 0, 0 );
 627
 628         /* Blue box: lost context?
 629          */
 630
 631         /* Yellow box for texture swaps
 632          */
 633         if ( dev_priv->stats.boxes & RADEON_BOX_TEXTURE_LOAD )
 634                 radeon_clear_box( dev_priv, 40, 4, 8, 8, 255, 255, 0 );
 635
 636         /* Green box if hardware never idles (as far as we can tell)
 637          */
 638         if ( !(dev_priv->stats.boxes & RADEON_BOX_DMA_IDLE) )
 639                 radeon_clear_box( dev_priv, 64, 4, 8, 8, 0, 255, 0 );
 640
 641
 642         /* Draw bars indicating number of buffers allocated
 643          * (not a great measure, easily confused)
 644          */
 645         if (dev_priv->stats.requested_bufs) {
 646                 if (dev_priv->stats.requested_bufs > 100)
 647                         dev_priv->stats.requested_bufs = 100;
 648
 649                 radeon_clear_box( dev_priv, 4, 16,
 650                                   dev_priv->stats.requested_bufs, 4,
 651                                   196, 128, 128 );
 652         }
 653
 654         memset( &dev_priv->stats, 0, sizeof(dev_priv->stats) );
 655
 656 }
 657 /* ================================================================
 658  * CP command dispatch functions
 659  */
 660
 661 static void radeon_cp_dispatch_clear( drm_device_t *dev,
 662                                       drm_radeon_clear_t *clear,
 663                                       drm_radeon_clear_rect_t *depth_boxes )
 664 {
 665         drm_radeon_private_t *dev_priv = dev->dev_private;
 666         drm_radeon_sarea_t *sarea_priv = dev_priv->sarea_priv;
 667         drm_radeon_depth_clear_t *depth_clear = &dev_priv->depth_clear;
 668         int nbox = sarea_priv->nbox;
 669         drm_clip_rect_t *pbox = sarea_priv->boxes;
 670         unsigned int flags = clear->flags;
 671         u32 rb3d_cntl = 0, rb3d_stencilrefmask= 0;
 672         int i;
 673         RING_LOCALS;
 674         DRM_DEBUG( "flags = 0x%x\n", flags );
 675
 676         dev_priv->stats.clears++;
 677
 678         if ( dev_priv->page_flipping && dev_priv->current_page == 1 ) {
 679                 unsigned int tmp = flags;
 680
 681                 flags &= ~(RADEON_FRONT | RADEON_BACK);
 682                 if ( tmp & RADEON_FRONT ) flags |= RADEON_BACK;
 683                 if ( tmp & RADEON_BACK )  flags |= RADEON_FRONT;
 684         }
 685
 686         if ( flags & (RADEON_FRONT | RADEON_BACK) ) {
 687
 688                 BEGIN_RING( 4 );
 689
 690                 /* Ensure the 3D stream is idle before doing a
 691                  * 2D fill to clear the front or back buffer.
 692                  */
 693                 RADEON_WAIT_UNTIL_3D_IDLE();
 694
 695                 OUT_RING( CP_PACKET0( RADEON_DP_WRITE_MASK, 0 ) );
 696                 OUT_RING( clear->color_mask );
 697
 698                 ADVANCE_RING();
 699
 700                 /* Make sure we restore the 3D state next time.
 701                  */
 702                 dev_priv->sarea_priv->ctx_owner = 0;
 703
 704                 for ( i = 0 ; i < nbox ; i++ ) {
 705                         int x = pbox[i].x1;
 706                         int y = pbox[i].y1;
 707                         int w = pbox[i].x2 - x;
 708                         int h = pbox[i].y2 - y;
 709
 710                         DRM_DEBUG( "dispatch clear %d,%d-%d,%d flags 0x%x\n",
 711                                    x, y, w, h, flags );
 712
 713                         if ( flags & RADEON_FRONT ) {
 714                                 BEGIN_RING( 6 );
 715
 716                                 OUT_RING( CP_PACKET3( RADEON_CNTL_PAINT_MULTI, 4 ) );
 717                                 OUT_RING( RADEON_GMC_DST_PITCH_OFFSET_CNTL |
 718                                           RADEON_GMC_BRUSH_SOLID_COLOR |
 719                                           (dev_priv->color_fmt << 8) |
 720                                           RADEON_GMC_SRC_DATATYPE_COLOR |
 721                                           RADEON_ROP3_P |
 722                                           RADEON_GMC_CLR_CMP_CNTL_DIS );
 723
 724                                 OUT_RING( dev_priv->front_pitch_offset );
 725                                 OUT_RING( clear->clear_color );
 726
 727                                 OUT_RING( (x << 16) | y );
 728                                 OUT_RING( (w << 16) | h );
 729
 730                                 ADVANCE_RING();
 731                         }
 732
 733                         if ( flags & RADEON_BACK ) {
 734                                 BEGIN_RING( 6 );
 735
 736                                 OUT_RING( CP_PACKET3( RADEON_CNTL_PAINT_MULTI, 4 ) );
 737                                 OUT_RING( RADEON_GMC_DST_PITCH_OFFSET_CNTL |
 738                                           RADEON_GMC_BRUSH_SOLID_COLOR |
 739                                           (dev_priv->color_fmt << 8) |
 740                                           RADEON_GMC_SRC_DATATYPE_COLOR |
 741                                           RADEON_ROP3_P |
 742                                           RADEON_GMC_CLR_CMP_CNTL_DIS );
 743
 744                                 OUT_RING( dev_priv->back_pitch_offset );
 745                                 OUT_RING( clear->clear_color );
 746
 747                                 OUT_RING( (x << 16) | y );
 748                                 OUT_RING( (w << 16) | h );
 749
 750                                 ADVANCE_RING();
 751                         }
 752                 }
 753         }
 754
 755         /* We have to clear the depth and/or stencil buffers by
 756          * rendering a quad into just those buffers.  Thus, we have to
 757          * make sure the 3D engine is configured correctly.
 758          */
 759         if ( dev_priv->is_r200 &&
 760              (flags & (RADEON_DEPTH | RADEON_STENCIL)) ) {
 761
 762                 int tempPP_CNTL;
 763                 int tempRE_CNTL;
 764                 int tempRB3D_CNTL;
 765                 int tempRB3D_ZSTENCILCNTL;
 766                 int tempRB3D_STENCILREFMASK;
 767                 int tempRB3D_PLANEMASK;
 768                 int tempSE_CNTL;
 769                 int tempSE_VTE_CNTL;
 770                 int tempSE_VTX_FMT_0;
 771                 int tempSE_VTX_FMT_1;
 772                 int tempSE_VAP_CNTL;
 773                 int tempRE_AUX_SCISSOR_CNTL;
 774
 775                 tempPP_CNTL = 0;
 776                 tempRE_CNTL = 0;
 777
 778                 tempRB3D_CNTL = depth_clear->rb3d_cntl;
 779                 tempRB3D_CNTL &= ~(1<<15); /* unset radeon magic flag */
 780
 781                 tempRB3D_ZSTENCILCNTL = depth_clear->rb3d_zstencilcntl;
 782                 tempRB3D_STENCILREFMASK = 0x0;
 783
 784                 tempSE_CNTL = depth_clear->se_cntl;
 785
 786
 787
 788                 /* Disable TCL */
 789
 790                 tempSE_VAP_CNTL = (/* SE_VAP_CNTL__FORCE_W_TO_ONE_MASK |  */
 791                                    (0x9 << SE_VAP_CNTL__VF_MAX_VTX_NUM__SHIFT));
 792
 793                 tempRB3D_PLANEMASK = 0x0;
 794
 795                 tempRE_AUX_SCISSOR_CNTL = 0x0;
 796
 797                 tempSE_VTE_CNTL =
 798                         SE_VTE_CNTL__VTX_XY_FMT_MASK |
 799                         SE_VTE_CNTL__VTX_Z_FMT_MASK;
 800
 801                 /* Vertex format (X, Y, Z, W)*/
 802                 tempSE_VTX_FMT_0 =
 803                         SE_VTX_FMT_0__VTX_Z0_PRESENT_MASK |
 804                         SE_VTX_FMT_0__VTX_W0_PRESENT_MASK;
 805                 tempSE_VTX_FMT_1 = 0x0;
 806
 807
 808                 /*
 809                  * Depth buffer specific enables
 810                  */
 811                 if (flags & RADEON_DEPTH) {
 812                         /* Enable depth buffer */
 813                         tempRB3D_CNTL |= RADEON_Z_ENABLE;
 814                 } else {
 815                         /* Disable depth buffer */
 816                         tempRB3D_CNTL &= ~RADEON_Z_ENABLE;
 817                 }
 818
 819                 /*
 820                  * Stencil buffer specific enables
 821                  */
 822                 if ( flags & RADEON_STENCIL ) {
 823                         tempRB3D_CNTL |=  RADEON_STENCIL_ENABLE;
 824                         tempRB3D_STENCILREFMASK = clear->depth_mask;
 825                 } else {
 826                         tempRB3D_CNTL &= ~RADEON_STENCIL_ENABLE;
 827                         tempRB3D_STENCILREFMASK = 0x00000000;
 828                 }
 829
 830                 BEGIN_RING( 26 );
 831                 RADEON_WAIT_UNTIL_2D_IDLE();
 832
 833                 OUT_RING_REG( RADEON_PP_CNTL, tempPP_CNTL );
 834                 OUT_RING_REG( R200_RE_CNTL, tempRE_CNTL );
 835                 OUT_RING_REG( RADEON_RB3D_CNTL, tempRB3D_CNTL );
 836                 OUT_RING_REG( RADEON_RB3D_ZSTENCILCNTL,
 837                               tempRB3D_ZSTENCILCNTL );
 838                 OUT_RING_REG( RADEON_RB3D_STENCILREFMASK,
 839                               tempRB3D_STENCILREFMASK );
 840                 OUT_RING_REG( RADEON_RB3D_PLANEMASK, tempRB3D_PLANEMASK );
 841                 OUT_RING_REG( RADEON_SE_CNTL, tempSE_CNTL );
 842                 OUT_RING_REG( R200_SE_VTE_CNTL, tempSE_VTE_CNTL );
 843                 OUT_RING_REG( R200_SE_VTX_FMT_0, tempSE_VTX_FMT_0 );
 844                 OUT_RING_REG( R200_SE_VTX_FMT_1, tempSE_VTX_FMT_1 );
 845                 OUT_RING_REG( R200_SE_VAP_CNTL, tempSE_VAP_CNTL );
 846                 OUT_RING_REG( R200_RE_AUX_SCISSOR_CNTL,
 847                               tempRE_AUX_SCISSOR_CNTL );
 848                 ADVANCE_RING();
 849
 850                 /* Make sure we restore the 3D state next time.
 851                  */
 852                 dev_priv->sarea_priv->ctx_owner = 0;
 853
 854                 for ( i = 0 ; i < nbox ; i++ ) {
 855
 856                         /* Funny that this should be required --
 857                          *  sets top-left?
 858                          */
 859                         radeon_emit_clip_rect( dev_priv,
 860                                                &sarea_priv->boxes[i] );
 861
 862                         BEGIN_RING( 14 );
 863                         OUT_RING( CP_PACKET3( R200_3D_DRAW_IMMD_2, 12 ) );
 864                         OUT_RING( (RADEON_PRIM_TYPE_RECT_LIST |
 865                                    RADEON_PRIM_WALK_RING |
 866                                    (3 << RADEON_NUM_VERTICES_SHIFT)) );
 867                         OUT_RING( depth_boxes[i].ui[CLEAR_X1] );
 868                         OUT_RING( depth_boxes[i].ui[CLEAR_Y1] );
 869                         OUT_RING( depth_boxes[i].ui[CLEAR_DEPTH] );
 870                         OUT_RING( 0x3f800000 );
 871                         OUT_RING( depth_boxes[i].ui[CLEAR_X1] );
 872                         OUT_RING( depth_boxes[i].ui[CLEAR_Y2] );
 873                         OUT_RING( depth_boxes[i].ui[CLEAR_DEPTH] );
 874                         OUT_RING( 0x3f800000 );
 875                         OUT_RING( depth_boxes[i].ui[CLEAR_X2] );
 876                         OUT_RING( depth_boxes[i].ui[CLEAR_Y2] );
 877                         OUT_RING( depth_boxes[i].ui[CLEAR_DEPTH] );
 878                         OUT_RING( 0x3f800000 );
 879                         ADVANCE_RING();
 880                 }
 881         }
 882         else if ( (flags & (RADEON_DEPTH | RADEON_STENCIL)) ) {
 883
 884                 rb3d_cntl = depth_clear->rb3d_cntl;
 885
 886                 if ( flags & RADEON_DEPTH ) {
 887                         rb3d_cntl |=  RADEON_Z_ENABLE;
 888                 } else {
 889                         rb3d_cntl &= ~RADEON_Z_ENABLE;
 890                 }
 891
 892                 if ( flags & RADEON_STENCIL ) {
 893                         rb3d_cntl |=  RADEON_STENCIL_ENABLE;
 894                         rb3d_stencilrefmask = clear->depth_mask; /* misnamed field */
 895                 } else {
 896                         rb3d_cntl &= ~RADEON_STENCIL_ENABLE;
 897                         rb3d_stencilrefmask = 0x00000000;
 898                 }
 899
 900                 BEGIN_RING( 13 );
 901                 RADEON_WAIT_UNTIL_2D_IDLE();
 902
 903                 OUT_RING( CP_PACKET0( RADEON_PP_CNTL, 1 ) );
 904                 OUT_RING( 0x00000000 );
 905                 OUT_RING( rb3d_cntl );
 906
 907                 OUT_RING_REG( RADEON_RB3D_ZSTENCILCNTL,
 908                               depth_clear->rb3d_zstencilcntl );
 909                 OUT_RING_REG( RADEON_RB3D_STENCILREFMASK,
 910                               rb3d_stencilrefmask );
 911                 OUT_RING_REG( RADEON_RB3D_PLANEMASK,
 912                               0x00000000 );
 913                 OUT_RING_REG( RADEON_SE_CNTL,
 914                               depth_clear->se_cntl );
 915                 ADVANCE_RING();
 916
 917                 /* Make sure we restore the 3D state next time.
 918                  */
 919                 dev_priv->sarea_priv->ctx_owner = 0;
 920
 921                 for ( i = 0 ; i < nbox ; i++ ) {
 922
 923                         /* Funny that this should be required --
 924                          *  sets top-left?
 925                          */
 926                         radeon_emit_clip_rect( dev_priv,
 927                                                &sarea_priv->boxes[i] );
 928
 929                         BEGIN_RING( 15 );
 930
 931                         OUT_RING( CP_PACKET3( RADEON_3D_DRAW_IMMD, 13 ) );
 932                         OUT_RING( RADEON_VTX_Z_PRESENT |
 933                                   RADEON_VTX_PKCOLOR_PRESENT);
 934                         OUT_RING( (RADEON_PRIM_TYPE_RECT_LIST |
 935                                    RADEON_PRIM_WALK_RING |
 936                                    RADEON_MAOS_ENABLE |
 937                                    RADEON_VTX_FMT_RADEON_MODE |
 938                                    (3 << RADEON_NUM_VERTICES_SHIFT)) );
 939
 940
 941                         OUT_RING( depth_boxes[i].ui[CLEAR_X1] );
 942                         OUT_RING( depth_boxes[i].ui[CLEAR_Y1] );
 943                         OUT_RING( depth_boxes[i].ui[CLEAR_DEPTH] );
 944                         OUT_RING( 0x0 );
 945
 946                         OUT_RING( depth_boxes[i].ui[CLEAR_X1] );
 947                         OUT_RING( depth_boxes[i].ui[CLEAR_Y2] );
 948                         OUT_RING( depth_boxes[i].ui[CLEAR_DEPTH] );
 949                         OUT_RING( 0x0 );
 950
 951                         OUT_RING( depth_boxes[i].ui[CLEAR_X2] );
 952                         OUT_RING( depth_boxes[i].ui[CLEAR_Y2] );
 953                         OUT_RING( depth_boxes[i].ui[CLEAR_DEPTH] );
 954                         OUT_RING( 0x0 );
 955
 956                         ADVANCE_RING();
 957                 }
 958         }
 959
 960         /* Increment the clear counter.  The client-side 3D driver must
 961          * wait on this value before performing the clear ioctl.  We
 962          * need this because the card's so damned fast...
 963          */
 964         dev_priv->sarea_priv->last_clear++;
 965
 966         BEGIN_RING( 4 );
 967
 968         RADEON_CLEAR_AGE( dev_priv->sarea_priv->last_clear );
 969         RADEON_WAIT_UNTIL_IDLE();
 970
 971         ADVANCE_RING();
 972 }
 973
 974 static void radeon_cp_dispatch_swap( drm_device_t *dev )
 975 {
 976         drm_radeon_private_t *dev_priv = dev->dev_private;
 977         drm_radeon_sarea_t *sarea_priv = dev_priv->sarea_priv;
 978         int nbox = sarea_priv->nbox;
 979         drm_clip_rect_t *pbox = sarea_priv->boxes;
 980         int i;
 981         RING_LOCALS;
 982         DRM_DEBUG( "\n" );
 983
 984         /* Do some trivial performance monitoring...
 985          */
 986         if (dev_priv->do_boxes)
 987                 radeon_cp_performance_boxes( dev_priv );
 988
 989
 990         /* Wait for the 3D stream to idle before dispatching the bitblt.
 991          * This will prevent data corruption between the two streams.
 992          */
 993         BEGIN_RING( 2 );
 994
 995         RADEON_WAIT_UNTIL_3D_IDLE();
 996
 997         ADVANCE_RING();
 998
 999         for ( i = 0 ; i < nbox ; i++ ) {
1000                 int x = pbox[i].x1;
1001                 int y = pbox[i].y1;
1002                 int w = pbox[i].x2 - x;
1003                 int h = pbox[i].y2 - y;
1004
1005                 DRM_DEBUG( "dispatch swap %d,%d-%d,%d\n",
1006                            x, y, w, h );
1007
1008                 BEGIN_RING( 7 );
1009
1010                 OUT_RING( CP_PACKET3( RADEON_CNTL_BITBLT_MULTI, 5 ) );
1011                 OUT_RING( RADEON_GMC_SRC_PITCH_OFFSET_CNTL |
1012                           RADEON_GMC_DST_PITCH_OFFSET_CNTL |
1013                           RADEON_GMC_BRUSH_NONE |
1014                           (dev_priv->color_fmt << 8) |
1015                           RADEON_GMC_SRC_DATATYPE_COLOR |
1016                           RADEON_ROP3_S |
1017                           RADEON_DP_SRC_SOURCE_MEMORY |
1018                           RADEON_GMC_CLR_CMP_CNTL_DIS |
1019                           RADEON_GMC_WR_MSK_DIS );
1020
1021                 /* Make this work even if front & back are flipped:
1022                  */
1023                 if (dev_priv->current_page == 0) {
1024                         OUT_RING( dev_priv->back_pitch_offset );
1025                         OUT_RING( dev_priv->front_pitch_offset );
1026                 }
1027                 else {
1028                         OUT_RING( dev_priv->front_pitch_offset );
1029                         OUT_RING( dev_priv->back_pitch_offset );
1030                 }
1031
1032                 OUT_RING( (x << 16) | y );
1033                 OUT_RING( (x << 16) | y );
1034                 OUT_RING( (w << 16) | h );
1035
1036                 ADVANCE_RING();
1037         }
1038
1039         /* Increment the frame counter.  The client-side 3D driver must
1040          * throttle the framerate by waiting for this value before
1041          * performing the swapbuffer ioctl.
1042          */
1043         dev_priv->sarea_priv->last_frame++;
1044
1045         BEGIN_RING( 4 );
1046
1047         RADEON_FRAME_AGE( dev_priv->sarea_priv->last_frame );
1048         RADEON_WAIT_UNTIL_2D_IDLE();
1049
1050         ADVANCE_RING();
1051 }
1052
1053 static void radeon_cp_dispatch_flip( drm_device_t *dev )
1054 {
1055         drm_radeon_private_t *dev_priv = dev->dev_private;
1056         drm_sarea_t *sarea = (drm_sarea_t *)dev_priv->sarea->handle;
1057         int offset = (dev_priv->current_page == 1)
1058                    ? dev_priv->front_offset : dev_priv->back_offset;
1059         RING_LOCALS;
1060         DRM_DEBUG( "%s: page=%d pfCurrentPage=%d\n",
1061                 __FUNCTION__,
1062                 dev_priv->current_page,
1063                 dev_priv->sarea_priv->pfCurrentPage);
1064
1065         /* Do some trivial performance monitoring...
1066          */
1067         if (dev_priv->do_boxes) {
1068                 dev_priv->stats.boxes |= RADEON_BOX_FLIP;
1069                 radeon_cp_performance_boxes( dev_priv );
1070         }
1071
1072         /* Update the frame offsets for both CRTCs
1073          */
1074         BEGIN_RING( 6 );
1075
1076         RADEON_WAIT_UNTIL_3D_IDLE();
1077         OUT_RING_REG( RADEON_CRTC_OFFSET, ( ( sarea->frame.y * dev_priv->front_pitch
1078                                               + sarea->frame.x
1079                                               * ( dev_priv->color_fmt - 2 ) ) & ~7 )
1080                                           + offset );
1081         OUT_RING_REG( RADEON_CRTC2_OFFSET, dev_priv->sarea_priv->crtc2_base
1082                                            + offset );
1083
1084         ADVANCE_RING();
1085
1086         /* Increment the frame counter.  The client-side 3D driver must
1087          * throttle the framerate by waiting for this value before
1088          * performing the swapbuffer ioctl.
1089          */
1090         dev_priv->sarea_priv->last_frame++;
1091         dev_priv->sarea_priv->pfCurrentPage = dev_priv->current_page =
1092                                               1 - dev_priv->current_page;
1093
1094         BEGIN_RING( 2 );
1095
1096         RADEON_FRAME_AGE( dev_priv->sarea_priv->last_frame );
1097
1098         ADVANCE_RING();
1099 }
1100
1101 static int bad_prim_vertex_nr( int primitive, int nr )
1102 {
1103         switch (primitive & RADEON_PRIM_TYPE_MASK) {
1104         case RADEON_PRIM_TYPE_NONE:
1105         case RADEON_PRIM_TYPE_POINT:
1106                 return nr < 1;
1107         case RADEON_PRIM_TYPE_LINE:
1108                 return (nr & 1) || nr == 0;
1109         case RADEON_PRIM_TYPE_LINE_STRIP:
1110                 return nr < 2;
1111         case RADEON_PRIM_TYPE_TRI_LIST:
1112         case RADEON_PRIM_TYPE_3VRT_POINT_LIST:
1113         case RADEON_PRIM_TYPE_3VRT_LINE_LIST:
1114         case RADEON_PRIM_TYPE_RECT_LIST:
1115                 return nr % 3 || nr == 0;
1116         case RADEON_PRIM_TYPE_TRI_FAN:
1117         case RADEON_PRIM_TYPE_TRI_STRIP:
1118                 return nr < 3;
1119         default:
1120                 return 1;
1121         }
1122 }
1123
1124
1125
1126 typedef struct {
1127         unsigned int start;
1128         unsigned int finish;
1129         unsigned int prim;
1130         unsigned int numverts;
1131         unsigned int offset;
1132         unsigned int vc_format;
1133 } drm_radeon_tcl_prim_t;
1134
1135 static void radeon_cp_dispatch_vertex( drm_device_t *dev,
1136                                        drm_buf_t *buf,
1137                                        drm_radeon_tcl_prim_t *prim )
1138
1139 {
1140         drm_radeon_private_t *dev_priv = dev->dev_private;
1141         drm_radeon_sarea_t *sarea_priv = dev_priv->sarea_priv;
1142         int offset = dev_priv->gart_buffers_offset + buf->offset + prim->start;
1143         int numverts = (int)prim->numverts;
1144         int nbox = sarea_priv->nbox;
1145         int i = 0;
1146         RING_LOCALS;
1147
1148         DRM_DEBUG("hwprim 0x%x vfmt 0x%x %d..%d %d verts\n",
1149                   prim->prim,
1150                   prim->vc_format,
1151                   prim->start,
1152                   prim->finish,
1153                   prim->numverts);
1154
1155         if (bad_prim_vertex_nr( prim->prim, prim->numverts )) {
1156                 DRM_ERROR( "bad prim %x numverts %d\n",
1157                            prim->prim, prim->numverts );
1158                 return;
1159         }
1160
1161         do {
1162                 /* Emit the next cliprect */
1163                 if ( i < nbox ) {
1164                         radeon_emit_clip_rect( dev_priv,
1165                                                &sarea_priv->boxes[i] );
1166                 }
1167
1168                 /* Emit the vertex buffer rendering commands */
1169                 BEGIN_RING( 5 );
1170
1171                 OUT_RING( CP_PACKET3( RADEON_3D_RNDR_GEN_INDX_PRIM, 3 ) );
1172                 OUT_RING( offset );
1173                 OUT_RING( numverts );
1174                 OUT_RING( prim->vc_format );
1175                 OUT_RING( prim->prim | RADEON_PRIM_WALK_LIST |
1176                           RADEON_COLOR_ORDER_RGBA |
1177                           RADEON_VTX_FMT_RADEON_MODE |
1178                           (numverts << RADEON_NUM_VERTICES_SHIFT) );
1179
1180                 ADVANCE_RING();
1181
1182                 i++;
1183         } while ( i < nbox );
1184 }
1185
1186
1187
1188 static void radeon_cp_discard_buffer( drm_device_t *dev, drm_buf_t *buf )
1189 {
1190         drm_radeon_private_t *dev_priv = dev->dev_private;
1191         drm_radeon_buf_priv_t *buf_priv = buf->dev_private;
1192         RING_LOCALS;
1193
1194         buf_priv->age = ++dev_priv->sarea_priv->last_dispatch;
1195
1196         /* Emit the vertex buffer age */
1197         BEGIN_RING( 2 );
1198         RADEON_DISPATCH_AGE( buf_priv->age );
1199         ADVANCE_RING();
1200
1201         buf->pending = 1;
1202         buf->used = 0;
1203 }
1204
1205 static void radeon_cp_dispatch_indirect( drm_device_t *dev,
1206                                          drm_buf_t *buf,
1207                                          int start, int end )
1208 {
1209         drm_radeon_private_t *dev_priv = dev->dev_private;
1210         RING_LOCALS;
1211         DRM_DEBUG( "indirect: buf=%d s=0x%x e=0x%x\n",
1212                    buf->idx, start, end );
1213
1214         if ( start != end ) {
1215                 int offset = (dev_priv->gart_buffers_offset
1216                               + buf->offset + start);
1217                 int dwords = (end - start + 3) / sizeof(u32);
1218
1219                 /* Indirect buffer data must be an even number of
1220                  * dwords, so if we've been given an odd number we must
1221                  * pad the data with a Type-2 CP packet.
1222                  */
1223                 if ( dwords & 1 ) {
1224                         u32 *data = (u32 *)
1225                                 ((char *)dev->agp_buffer_map->handle
1226                                  + buf->offset + start);
1227                         data[dwords++] = RADEON_CP_PACKET2;
1228                 }
1229
1230                 /* Fire off the indirect buffer */
1231                 BEGIN_RING( 3 );
1232
1233                 OUT_RING( CP_PACKET0( RADEON_CP_IB_BASE, 1 ) );
1234                 OUT_RING( offset );
1235                 OUT_RING( dwords );
1236
1237                 ADVANCE_RING();
1238         }
1239 }
1240
1241
1242 static void radeon_cp_dispatch_indices( drm_device_t *dev,
1243                                         drm_buf_t *elt_buf,
1244                                         drm_radeon_tcl_prim_t *prim )
1245 {
1246         drm_radeon_private_t *dev_priv = dev->dev_private;
1247         drm_radeon_sarea_t *sarea_priv = dev_priv->sarea_priv;
1248         int offset = dev_priv->gart_buffers_offset + prim->offset;
1249         u32 *data;
1250         int dwords;
1251         int i = 0;
1252         int start = prim->start + RADEON_INDEX_PRIM_OFFSET;
1253         int count = (prim->finish - start) / sizeof(u16);
1254         int nbox = sarea_priv->nbox;
1255
1256         DRM_DEBUG("hwprim 0x%x vfmt 0x%x %d..%d offset: %x nr %d\n",
1257                   prim->prim,
1258                   prim->vc_format,
1259                   prim->start,
1260                   prim->finish,
1261                   prim->offset,
1262                   prim->numverts);
1263
1264         if (bad_prim_vertex_nr( prim->prim, count )) {
1265                 DRM_ERROR( "bad prim %x count %d\n",
1266                            prim->prim, count );
1267                 return;
1268         }
1269
1270
1271         if ( start >= prim->finish ||
1272              (prim->start & 0x7) ) {
1273                 DRM_ERROR( "buffer prim %d\n", prim->prim );
1274                 return;
1275         }
1276
1277         dwords = (prim->finish - prim->start + 3) / sizeof(u32);
1278
1279         data = (u32 *)((char *)dev->agp_buffer_map->handle +
1280                        elt_buf->offset + prim->start);
1281
1282         data[0] = CP_PACKET3( RADEON_3D_RNDR_GEN_INDX_PRIM, dwords-2 );
1283         data[1] = offset;
1284         data[2] = prim->numverts;
1285         data[3] = prim->vc_format;
1286         data[4] = (prim->prim |
1287                    RADEON_PRIM_WALK_IND |
1288                    RADEON_COLOR_ORDER_RGBA |
1289                    RADEON_VTX_FMT_RADEON_MODE |
1290                    (count << RADEON_NUM_VERTICES_SHIFT) );
1291
1292         do {
1293                 if ( i < nbox )
1294                         radeon_emit_clip_rect( dev_priv,
1295                                                &sarea_priv->boxes[i] );
1296
1297                 radeon_cp_dispatch_indirect( dev, elt_buf,
1298                                              prim->start,
1299                                              prim->finish );
1300
1301                 i++;
1302         } while ( i < nbox );
1303
1304 }
1305
1306 #define RADEON_MAX_TEXTURE_SIZE (RADEON_BUFFER_SIZE - 8 * sizeof(u32))
1307
1308 static int radeon_cp_dispatch_texture( DRMFILE filp,
1309                                        drm_device_t *dev,
1310                                        drm_radeon_texture_t *tex,
1311                                        drm_radeon_tex_image_t *image )
1312 {
1313         drm_radeon_private_t *dev_priv = dev->dev_private;
1314         drm_file_t *filp_priv;
1315         drm_buf_t *buf;
1316         u32 format;
1317         u32 *buffer;
1318         const u8 __user *data;
1319         int size, dwords, tex_width, blit_width;
1320         u32 height;
1321         int i;
1322         RING_LOCALS;
1323
1324         DRM_GET_PRIV_WITH_RETURN( filp_priv, filp );
1325
1326         if ( radeon_check_and_fixup_offset( dev_priv, filp_priv, &tex->offset ) ) {
1327                 DRM_ERROR( "Invalid destination offset\n" );
1328                 return DRM_ERR( EINVAL );
1329         }
1330
1331         dev_priv->stats.boxes |= RADEON_BOX_TEXTURE_LOAD;
1332
1333         /* Flush the pixel cache.  This ensures no pixel data gets mixed
1334          * up with the texture data from the host data blit, otherwise
1335          * part of the texture image may be corrupted.
1336          */
1337         BEGIN_RING( 4 );
1338         RADEON_FLUSH_CACHE();
1339         RADEON_WAIT_UNTIL_IDLE();
1340         ADVANCE_RING();
1341
1342 #ifdef __BIG_ENDIAN
1343         /* The Mesa texture functions provide the data in little endian as the
1344          * chip wants it, but we need to compensate for the fact that the CP
1345          * ring gets byte-swapped
1346          */
1347         BEGIN_RING( 2 );
1348         OUT_RING_REG( RADEON_RBBM_GUICNTL, RADEON_HOST_DATA_SWAP_32BIT );
1349         ADVANCE_RING();
1350 #endif
1351
1352
1353         /* The compiler won't optimize away a division by a variable,
1354          * even if the only legal values are powers of two.  Thus, we'll
1355          * use a shift instead.
1356          */
1357         switch ( tex->format ) {
1358         case RADEON_TXFORMAT_ARGB8888:
1359         case RADEON_TXFORMAT_RGBA8888:
1360                 format = RADEON_COLOR_FORMAT_ARGB8888;
1361                 tex_width = tex->width * 4;
1362                 blit_width = image->width * 4;
1363                 break;
1364         case RADEON_TXFORMAT_AI88:
1365         case RADEON_TXFORMAT_ARGB1555:
1366         case RADEON_TXFORMAT_RGB565:
1367         case RADEON_TXFORMAT_ARGB4444:
1368         case RADEON_TXFORMAT_VYUY422:
1369         case RADEON_TXFORMAT_YVYU422:
1370                 format = RADEON_COLOR_FORMAT_RGB565;
1371                 tex_width = tex->width * 2;
1372                 blit_width = image->width * 2;
1373                 break;
1374         case RADEON_TXFORMAT_I8:
1375         case RADEON_TXFORMAT_RGB332:
1376                 format = RADEON_COLOR_FORMAT_CI8;
1377                 tex_width = tex->width * 1;
1378                 blit_width = image->width * 1;
1379                 break;
1380         default:
1381                 DRM_ERROR( "invalid texture format %d\n", tex->format );
1382                 return DRM_ERR(EINVAL);
1383         }
1384
1385         DRM_DEBUG("tex=%dx%d blit=%d\n", tex_width, tex->height, blit_width );
1386
1387         do {
1388                 DRM_DEBUG( "tex: ofs=0x%x p=%d f=%d x=%hd y=%hd w=%hd h=%hd\n",
1389                            tex->offset >> 10, tex->pitch, tex->format,
1390                            image->x, image->y, image->width, image->height );
1391
1392                 /* Make a copy of some parameters in case we have to
1393                  * update them for a multi-pass texture blit.
1394                  */
1395                 height = image->height;
1396                 data = (const u8 __user *)image->data;
1397
1398                 size = height * blit_width;
1399
1400                 if ( size > RADEON_MAX_TEXTURE_SIZE ) {
1401                         height = RADEON_MAX_TEXTURE_SIZE / blit_width;
1402                         size = height * blit_width;
1403                 } else if ( size < 4 && size > 0 ) {
1404                         size = 4;
1405                 } else if ( size == 0 ) {
1406                         return 0;
1407                 }
1408
1409                 buf = radeon_freelist_get( dev );
1410                 if ( 0 && !buf ) {
1411                         radeon_do_cp_idle( dev_priv );
1412                         buf = radeon_freelist_get( dev );
1413                 }
1414                 if ( !buf ) {
1415                         DRM_DEBUG("radeon_cp_dispatch_texture: EAGAIN\n");
1416                         DRM_COPY_TO_USER( tex->image, image, sizeof(*image) );
1417                         return DRM_ERR(EAGAIN);
1418                 }
1419
1420
1421                 /* Dispatch the indirect buffer.
1422                  */
1423                 buffer = (u32*)((char*)dev->agp_buffer_map->handle + buf->offset);
1424                 dwords = size / 4;
1425                 buffer[0] = CP_PACKET3( RADEON_CNTL_HOSTDATA_BLT, dwords + 6 );
1426                 buffer[1] = (RADEON_GMC_DST_PITCH_OFFSET_CNTL |
1427                              RADEON_GMC_BRUSH_NONE |
1428                              (format << 8) |
1429                              RADEON_GMC_SRC_DATATYPE_COLOR |
1430                              RADEON_ROP3_S |
1431                              RADEON_DP_SRC_SOURCE_HOST_DATA |
1432                              RADEON_GMC_CLR_CMP_CNTL_DIS |
1433                              RADEON_GMC_WR_MSK_DIS);
1434
1435                 buffer[2] = (tex->pitch << 22) | (tex->offset >> 10);
1436                 buffer[3] = 0xffffffff;
1437                 buffer[4] = 0xffffffff;
1438                 buffer[5] = (image->y << 16) | image->x;
1439                 buffer[6] = (height << 16) | image->width;
1440                 buffer[7] = dwords;
1441                 buffer += 8;
1442
1443                 if ( tex_width >= 32 ) {
1444                         /* Texture image width is larger than the minimum, so we
1445                          * can upload it directly.
1446                          */
1447                         if ( DRM_COPY_FROM_USER( buffer, data,
1448                                                  dwords * sizeof(u32) ) ) {
1449                                 DRM_ERROR( "EFAULT on data, %d dwords\n",
1450                                            dwords );
1451                                 return DRM_ERR(EFAULT);
1452                         }
1453                 } else {
1454                         /* Texture image width is less than the minimum, so we
1455                          * need to pad out each image scanline to the minimum
1456                          * width.
1457                          */
1458                         for ( i = 0 ; i < tex->height ; i++ ) {
1459                                 if ( DRM_COPY_FROM_USER( buffer, data,
1460                                                          tex_width ) ) {
1461                                         DRM_ERROR( "EFAULT on pad, %d bytes\n",
1462                                                    tex_width );
1463                                         return DRM_ERR(EFAULT);
1464                                 }
1465                                 buffer += 8;
1466                                 data += tex_width;
1467                         }
1468                 }
1469
1470                 buf->filp = filp;
1471                 buf->used = (dwords + 8) * sizeof(u32);
1472                 radeon_cp_dispatch_indirect( dev, buf, 0, buf->used );
1473                 radeon_cp_discard_buffer( dev, buf );
1474
1475                 /* Update the input parameters for next time */
1476                 image->y += height;
1477                 image->height -= height;
1478                 image->data = (const u8 __user *)image->data + size;
1479         } while (image->height > 0);
1480
1481         /* Flush the pixel cache after the blit completes.  This ensures
1482          * the texture data is written out to memory before rendering
1483          * continues.
1484          */
1485         BEGIN_RING( 4 );
1486         RADEON_FLUSH_CACHE();
1487         RADEON_WAIT_UNTIL_2D_IDLE();
1488         ADVANCE_RING();
1489         return 0;
1490 }
1491
1492
1493 static void radeon_cp_dispatch_stipple( drm_device_t *dev, u32 *stipple )
1494 {
1495         drm_radeon_private_t *dev_priv = dev->dev_private;
1496         int i;
1497         RING_LOCALS;
1498         DRM_DEBUG( "\n" );
1499
1500         BEGIN_RING( 35 );
1501
1502         OUT_RING( CP_PACKET0( RADEON_RE_STIPPLE_ADDR, 0 ) );
1503         OUT_RING( 0x00000000 );
1504
1505         OUT_RING( CP_PACKET0_TABLE( RADEON_RE_STIPPLE_DATA, 31 ) );
1506         for ( i = 0 ; i < 32 ; i++ ) {
1507                 OUT_RING( stipple[i] );
1508         }
1509
1510         ADVANCE_RING();
1511 }
1512
1513
1514 /* ================================================================
1515  * IOCTL functions
1516  */
1517
1518 int radeon_cp_clear( DRM_IOCTL_ARGS )
1519 {
1520         DRM_DEVICE;
1521         drm_radeon_private_t *dev_priv = dev->dev_private;
1522         drm_radeon_sarea_t *sarea_priv = dev_priv->sarea_priv;
1523         drm_radeon_clear_t clear;
1524         drm_radeon_clear_rect_t depth_boxes[RADEON_NR_SAREA_CLIPRECTS];
1525         DRM_DEBUG( "\n" );
1526
1527         LOCK_TEST_WITH_RETURN( dev, filp );
1528
1529         DRM_COPY_FROM_USER_IOCTL( clear, (drm_radeon_clear_t __user *)data,
1530                              sizeof(clear) );
1531
1532         RING_SPACE_TEST_WITH_RETURN( dev_priv );
1533
1534         if ( sarea_priv->nbox > RADEON_NR_SAREA_CLIPRECTS )
1535                 sarea_priv->nbox = RADEON_NR_SAREA_CLIPRECTS;
1536
1537         if ( DRM_COPY_FROM_USER( &depth_boxes, clear.depth_boxes,
1538                              sarea_priv->nbox * sizeof(depth_boxes[0]) ) )
1539                 return DRM_ERR(EFAULT);
1540
1541         radeon_cp_dispatch_clear( dev, &clear, depth_boxes );
1542
1543         COMMIT_RING();
1544         return 0;
1545 }
1546
1547
1548 /* Not sure why this isn't set all the time:
1549  */
1550 static int radeon_do_init_pageflip( drm_device_t *dev )
1551 {
1552         drm_radeon_private_t *dev_priv = dev->dev_private;
1553         RING_LOCALS;
1554
1555         DRM_DEBUG( "\n" );
1556
1557         BEGIN_RING( 6 );
1558         RADEON_WAIT_UNTIL_3D_IDLE();
1559         OUT_RING( CP_PACKET0( RADEON_CRTC_OFFSET_CNTL, 0 ) );
1560         OUT_RING( RADEON_READ( RADEON_CRTC_OFFSET_CNTL ) | RADEON_CRTC_OFFSET_FLIP_CNTL );
1561         OUT_RING( CP_PACKET0( RADEON_CRTC2_OFFSET_CNTL, 0 ) );
1562         OUT_RING( RADEON_READ( RADEON_CRTC2_OFFSET_CNTL ) | RADEON_CRTC_OFFSET_FLIP_CNTL );
1563         ADVANCE_RING();
1564
1565         dev_priv->page_flipping = 1;
1566         dev_priv->current_page = 0;
1567         dev_priv->sarea_priv->pfCurrentPage = dev_priv->current_page;
1568
1569         return 0;
1570 }
1571
1572 /* Called whenever a client dies, from DRM(release).
1573  * NOTE:  Lock isn't necessarily held when this is called!
1574  */
1575 int radeon_do_cleanup_pageflip( drm_device_t *dev )
1576 {
1577         drm_radeon_private_t *dev_priv = dev->dev_private;
1578         DRM_DEBUG( "\n" );
1579
1580         if (dev_priv->current_page != 0)
1581                 radeon_cp_dispatch_flip( dev );
1582
1583         dev_priv->page_flipping = 0;
1584         return 0;
1585 }
1586
1587 /* Swapping and flipping are different operations, need different ioctls.
1588  * They can & should be intermixed to support multiple 3d windows.
1589  */
1590 int radeon_cp_flip( DRM_IOCTL_ARGS )
1591 {
1592         DRM_DEVICE;
1593         drm_radeon_private_t *dev_priv = dev->dev_private;
1594         DRM_DEBUG( "\n" );
1595
1596         LOCK_TEST_WITH_RETURN( dev, filp );
1597
1598         RING_SPACE_TEST_WITH_RETURN( dev_priv );
1599
1600         if (!dev_priv->page_flipping)
1601                 radeon_do_init_pageflip( dev );
1602
1603         radeon_cp_dispatch_flip( dev );
1604
1605         COMMIT_RING();
1606         return 0;
1607 }
1608
1609 int radeon_cp_swap( DRM_IOCTL_ARGS )
1610 {
1611         DRM_DEVICE;
1612         drm_radeon_private_t *dev_priv = dev->dev_private;
1613         drm_radeon_sarea_t *sarea_priv = dev_priv->sarea_priv;
1614         DRM_DEBUG( "\n" );
1615
1616         LOCK_TEST_WITH_RETURN( dev, filp );
1617
1618         RING_SPACE_TEST_WITH_RETURN( dev_priv );
1619
1620         if ( sarea_priv->nbox > RADEON_NR_SAREA_CLIPRECTS )
1621                 sarea_priv->nbox = RADEON_NR_SAREA_CLIPRECTS;
1622
1623         radeon_cp_dispatch_swap( dev );
1624         dev_priv->sarea_priv->ctx_owner = 0;
1625
1626         COMMIT_RING();
1627         return 0;
1628 }
1629
1630 int radeon_cp_vertex( DRM_IOCTL_ARGS )
1631 {
1632         DRM_DEVICE;
1633         drm_radeon_private_t *dev_priv = dev->dev_private;
1634         drm_file_t *filp_priv;
1635         drm_radeon_sarea_t *sarea_priv = dev_priv->sarea_priv;
1636         drm_device_dma_t *dma = dev->dma;
1637         drm_buf_t *buf;
1638         drm_radeon_vertex_t vertex;
1639         drm_radeon_tcl_prim_t prim;
1640
1641         LOCK_TEST_WITH_RETURN( dev, filp );
1642
1643         DRM_GET_PRIV_WITH_RETURN( filp_priv, filp );
1644
1645         DRM_COPY_FROM_USER_IOCTL( vertex, (drm_radeon_vertex_t __user *)data,
1646                              sizeof(vertex) );
1647
1648         DRM_DEBUG( "pid=%d index=%d count=%d discard=%d\n",
1649                    DRM_CURRENTPID,
1650                    vertex.idx, vertex.count, vertex.discard );
1651
1652         if ( vertex.idx < 0 || vertex.idx >= dma->buf_count ) {
1653                 DRM_ERROR( "buffer index %d (of %d max)\n",
1654                            vertex.idx, dma->buf_count - 1 );
1655                 return DRM_ERR(EINVAL);
1656         }
1657         if ( vertex.prim < 0 ||
1658              vertex.prim > RADEON_PRIM_TYPE_3VRT_LINE_LIST ) {
1659                 DRM_ERROR( "buffer prim %d\n", vertex.prim );
1660                 return DRM_ERR(EINVAL);
1661         }
1662
1663         RING_SPACE_TEST_WITH_RETURN( dev_priv );
1664         VB_AGE_TEST_WITH_RETURN( dev_priv );
1665
1666         buf = dma->buflist[vertex.idx];
1667
1668         if ( buf->filp != filp ) {
1669                 DRM_ERROR( "process %d using buffer owned by %p\n",
1670                            DRM_CURRENTPID, buf->filp );
1671                 return DRM_ERR(EINVAL);
1672         }
1673         if ( buf->pending ) {
1674                 DRM_ERROR( "sending pending buffer %d\n", vertex.idx );
1675                 return DRM_ERR(EINVAL);
1676         }
1677
1678         /* Build up a prim_t record:
1679          */
1680         if (vertex.count) {
1681                 buf->used = vertex.count; /* not used? */
1682
1683                 if ( sarea_priv->dirty & ~RADEON_UPLOAD_CLIPRECTS ) {
1684                         if ( radeon_emit_state( dev_priv, filp_priv,
1685                                                 &sarea_priv->context_state,
1686                                                 sarea_priv->tex_state,
1687                                                 sarea_priv->dirty ) ) {
1688                                 DRM_ERROR( "radeon_emit_state failed\n" );
1689                                 return DRM_ERR( EINVAL );
1690                         }
1691
1692                         sarea_priv->dirty &= ~(RADEON_UPLOAD_TEX0IMAGES |
1693                                                RADEON_UPLOAD_TEX1IMAGES |
1694                                                RADEON_UPLOAD_TEX2IMAGES |
1695                                                RADEON_REQUIRE_QUIESCENCE);
1696                 }
1697
1698                 prim.start = 0;
1699                 prim.finish = vertex.count; /* unused */
1700                 prim.prim = vertex.prim;
1701                 prim.numverts = vertex.count;
1702                 prim.vc_format = dev_priv->sarea_priv->vc_format;
1703
1704                 radeon_cp_dispatch_vertex( dev, buf, &prim );
1705         }
1706
1707         if (vertex.discard) {
1708                 radeon_cp_discard_buffer( dev, buf );
1709         }
1710
1711         COMMIT_RING();
1712         return 0;
1713 }
1714
1715 int radeon_cp_indices( DRM_IOCTL_ARGS )
1716 {
1717         DRM_DEVICE;
1718         drm_radeon_private_t *dev_priv = dev->dev_private;
1719         drm_file_t *filp_priv;
1720         drm_radeon_sarea_t *sarea_priv = dev_priv->sarea_priv;
1721         drm_device_dma_t *dma = dev->dma;
1722         drm_buf_t *buf;
1723         drm_radeon_indices_t elts;
1724         drm_radeon_tcl_prim_t prim;
1725         int count;
1726
1727         LOCK_TEST_WITH_RETURN( dev, filp );
1728
1729         if ( !dev_priv ) {
1730                 DRM_ERROR( "%s called with no initialization\n", __FUNCTION__ );
1731                 return DRM_ERR(EINVAL);
1732         }
1733
1734         DRM_GET_PRIV_WITH_RETURN( filp_priv, filp );
1735
1736         DRM_COPY_FROM_USER_IOCTL( elts, (drm_radeon_indices_t __user *)data,
1737                              sizeof(elts) );
1738
1739         DRM_DEBUG( "pid=%d index=%d start=%d end=%d discard=%d\n",
1740                    DRM_CURRENTPID,
1741                    elts.idx, elts.start, elts.end, elts.discard );
1742
1743         if ( elts.idx < 0 || elts.idx >= dma->buf_count ) {
1744                 DRM_ERROR( "buffer index %d (of %d max)\n",
1745                            elts.idx, dma->buf_count - 1 );
1746                 return DRM_ERR(EINVAL);
1747         }
1748         if ( elts.prim < 0 ||
1749              elts.prim > RADEON_PRIM_TYPE_3VRT_LINE_LIST ) {
1750                 DRM_ERROR( "buffer prim %d\n", elts.prim );
1751                 return DRM_ERR(EINVAL);
1752         }
1753
1754         RING_SPACE_TEST_WITH_RETURN( dev_priv );
1755         VB_AGE_TEST_WITH_RETURN( dev_priv );
1756
1757         buf = dma->buflist[elts.idx];
1758
1759         if ( buf->filp != filp ) {
1760                 DRM_ERROR( "process %d using buffer owned by %p\n",
1761                            DRM_CURRENTPID, buf->filp );
1762                 return DRM_ERR(EINVAL);
1763         }
1764         if ( buf->pending ) {
1765                 DRM_ERROR( "sending pending buffer %d\n", elts.idx );
1766                 return DRM_ERR(EINVAL);
1767         }
1768
1769         count = (elts.end - elts.start) / sizeof(u16);
1770         elts.start -= RADEON_INDEX_PRIM_OFFSET;
1771
1772         if ( elts.start & 0x7 ) {
1773                 DRM_ERROR( "misaligned buffer 0x%x\n", elts.start );
1774                 return DRM_ERR(EINVAL);
1775         }
1776         if ( elts.start < buf->used ) {
1777                 DRM_ERROR( "no header 0x%x - 0x%x\n", elts.start, buf->used );
1778                 return DRM_ERR(EINVAL);
1779         }
1780
1781         buf->used = elts.end;
1782
1783         if ( sarea_priv->dirty & ~RADEON_UPLOAD_CLIPRECTS ) {
1784                 if ( radeon_emit_state( dev_priv, filp_priv,
1785                                         &sarea_priv->context_state,
1786                                         sarea_priv->tex_state,
1787                                         sarea_priv->dirty ) ) {
1788                         DRM_ERROR( "radeon_emit_state failed\n" );
1789                         return DRM_ERR( EINVAL );
1790                 }
1791
1792                 sarea_priv->dirty &= ~(RADEON_UPLOAD_TEX0IMAGES |
1793                                        RADEON_UPLOAD_TEX1IMAGES |
1794                                        RADEON_UPLOAD_TEX2IMAGES |
1795                                        RADEON_REQUIRE_QUIESCENCE);
1796         }
1797
1798
1799         /* Build up a prim_t record:
1800          */
1801         prim.start = elts.start;
1802         prim.finish = elts.end;
1803         prim.prim = elts.prim;
1804         prim.offset = 0;        /* offset from start of dma buffers */
1805         prim.numverts = RADEON_MAX_VB_VERTS; /* duh */
1806         prim.vc_format = dev_priv->sarea_priv->vc_format;
1807
1808         radeon_cp_dispatch_indices( dev, buf, &prim );
1809         if (elts.discard) {
1810                 radeon_cp_discard_buffer( dev, buf );
1811         }
1812
1813         COMMIT_RING();
1814         return 0;
1815 }
1816
1817 int radeon_cp_texture( DRM_IOCTL_ARGS )
1818 {
1819         DRM_DEVICE;
1820         drm_radeon_private_t *dev_priv = dev->dev_private;
1821         drm_radeon_texture_t tex;
1822         drm_radeon_tex_image_t image;
1823         int ret;
1824
1825         LOCK_TEST_WITH_RETURN( dev, filp );
1826
1827         DRM_COPY_FROM_USER_IOCTL( tex, (drm_radeon_texture_t __user *)data, sizeof(tex) );
1828
1829         if ( tex.image == NULL ) {
1830                 DRM_ERROR( "null texture image!\n" );
1831                 return DRM_ERR(EINVAL);
1832         }
1833
1834         if ( DRM_COPY_FROM_USER( &image,
1835                              (drm_radeon_tex_image_t __user *)tex.image,
1836                              sizeof(image) ) )
1837                 return DRM_ERR(EFAULT);
1838
1839         RING_SPACE_TEST_WITH_RETURN( dev_priv );
1840         VB_AGE_TEST_WITH_RETURN( dev_priv );
1841
1842         ret = radeon_cp_dispatch_texture( filp, dev, &tex, &image );
1843
1844         COMMIT_RING();
1845         return ret;
1846 }
1847
1848 int radeon_cp_stipple( DRM_IOCTL_ARGS )
1849 {
1850         DRM_DEVICE;
1851         drm_radeon_private_t *dev_priv = dev->dev_private;
1852         drm_radeon_stipple_t stipple;
1853         u32 mask[32];
1854
1855         LOCK_TEST_WITH_RETURN( dev, filp );
1856
1857         DRM_COPY_FROM_USER_IOCTL( stipple, (drm_radeon_stipple_t __user *)data,
1858                              sizeof(stipple) );
1859
1860         if ( DRM_COPY_FROM_USER( &mask, stipple.mask, 32 * sizeof(u32) ) )
1861                 return DRM_ERR(EFAULT);
1862
1863         RING_SPACE_TEST_WITH_RETURN( dev_priv );
1864
1865         radeon_cp_dispatch_stipple( dev, mask );
1866
1867         COMMIT_RING();
1868         return 0;
1869 }
1870
1871 int radeon_cp_indirect( DRM_IOCTL_ARGS )
1872 {
1873         DRM_DEVICE;
1874         drm_radeon_private_t *dev_priv = dev->dev_private;
1875         drm_device_dma_t *dma = dev->dma;
1876         drm_buf_t *buf;
1877         drm_radeon_indirect_t indirect;
1878         RING_LOCALS;
1879
1880         LOCK_TEST_WITH_RETURN( dev, filp );
1881
1882         if ( !dev_priv ) {
1883                 DRM_ERROR( "%s called with no initialization\n", __FUNCTION__ );
1884                 return DRM_ERR(EINVAL);
1885         }
1886
1887         DRM_COPY_FROM_USER_IOCTL( indirect, (drm_radeon_indirect_t __user *)data,
1888                              sizeof(indirect) );
1889
1890         DRM_DEBUG( "indirect: idx=%d s=%d e=%d d=%d\n",
1891                    indirect.idx, indirect.start,
1892                    indirect.end, indirect.discard );
1893
1894         if ( indirect.idx < 0 || indirect.idx >= dma->buf_count ) {
1895                 DRM_ERROR( "buffer index %d (of %d max)\n",
1896                            indirect.idx, dma->buf_count - 1 );
1897                 return DRM_ERR(EINVAL);
1898         }
1899
1900         buf = dma->buflist[indirect.idx];
1901
1902         if ( buf->filp != filp ) {
1903                 DRM_ERROR( "process %d using buffer owned by %p\n",
1904                            DRM_CURRENTPID, buf->filp );
1905                 return DRM_ERR(EINVAL);
1906         }
1907         if ( buf->pending ) {
1908                 DRM_ERROR( "sending pending buffer %d\n", indirect.idx );
1909                 return DRM_ERR(EINVAL);
1910         }
1911
1912         if ( indirect.start < buf->used ) {
1913                 DRM_ERROR( "reusing indirect: start=0x%x actual=0x%x\n",
1914                            indirect.start, buf->used );
1915                 return DRM_ERR(EINVAL);
1916         }
1917
1918         RING_SPACE_TEST_WITH_RETURN( dev_priv );
1919         VB_AGE_TEST_WITH_RETURN( dev_priv );
1920
1921         buf->used = indirect.end;
1922
1923         /* Wait for the 3D stream to idle before the indirect buffer
1924          * containing 2D acceleration commands is processed.
1925          */
1926         BEGIN_RING( 2 );
1927
1928         RADEON_WAIT_UNTIL_3D_IDLE();
1929
1930         ADVANCE_RING();
1931
1932         /* Dispatch the indirect buffer full of commands from the
1933          * X server.  This is insecure and is thus only available to
1934          * privileged clients.
1935          */
1936         radeon_cp_dispatch_indirect( dev, buf, indirect.start, indirect.end );
1937         if (indirect.discard) {
1938                 radeon_cp_discard_buffer( dev, buf );
1939         }
1940
1941
1942         COMMIT_RING();
1943         return 0;
1944 }
1945
1946 int radeon_cp_vertex2( DRM_IOCTL_ARGS )
1947 {
1948         DRM_DEVICE;
1949         drm_radeon_private_t *dev_priv = dev->dev_private;
1950         drm_file_t *filp_priv;
1951         drm_radeon_sarea_t *sarea_priv = dev_priv->sarea_priv;
1952         drm_device_dma_t *dma = dev->dma;
1953         drm_buf_t *buf;
1954         drm_radeon_vertex2_t vertex;
1955         int i;
1956         unsigned char laststate;
1957
1958         LOCK_TEST_WITH_RETURN( dev, filp );
1959
1960         if ( !dev_priv ) {
1961                 DRM_ERROR( "%s called with no initialization\n", __FUNCTION__ );
1962                 return DRM_ERR(EINVAL);
1963         }
1964
1965         DRM_GET_PRIV_WITH_RETURN( filp_priv, filp );
1966
1967         DRM_COPY_FROM_USER_IOCTL( vertex, (drm_radeon_vertex2_t __user *)data,
1968                              sizeof(vertex) );
1969
1970         DRM_DEBUG( "pid=%d index=%d discard=%d\n",
1971                    DRM_CURRENTPID,
1972                    vertex.idx, vertex.discard );
1973
1974         if ( vertex.idx < 0 || vertex.idx >= dma->buf_count ) {
1975                 DRM_ERROR( "buffer index %d (of %d max)\n",
1976                            vertex.idx, dma->buf_count - 1 );
1977                 return DRM_ERR(EINVAL);
1978         }
1979
1980         RING_SPACE_TEST_WITH_RETURN( dev_priv );
1981         VB_AGE_TEST_WITH_RETURN( dev_priv );
1982
1983         buf = dma->buflist[vertex.idx];
1984
1985         if ( buf->filp != filp ) {
1986                 DRM_ERROR( "process %d using buffer owned by %p\n",
1987                            DRM_CURRENTPID, buf->filp );
1988                 return DRM_ERR(EINVAL);
1989         }
1990
1991         if ( buf->pending ) {
1992                 DRM_ERROR( "sending pending buffer %d\n", vertex.idx );
1993                 return DRM_ERR(EINVAL);
1994         }
1995
1996         if (sarea_priv->nbox > RADEON_NR_SAREA_CLIPRECTS)
1997                 return DRM_ERR(EINVAL);
1998
1999         for (laststate = 0xff, i = 0 ; i < vertex.nr_prims ; i++) {
2000                 drm_radeon_prim_t prim;
2001                 drm_radeon_tcl_prim_t tclprim;
2002
2003                 if ( DRM_COPY_FROM_USER( &prim, &vertex.prim[i], sizeof(prim) ) )
2004                         return DRM_ERR(EFAULT);
2005
2006                 if ( prim.stateidx != laststate ) {
2007                         drm_radeon_state_t state;
2008
2009                         if ( DRM_COPY_FROM_USER( &state,
2010                                              &vertex.state[prim.stateidx],
2011                                              sizeof(state) ) )
2012                                 return DRM_ERR(EFAULT);
2013
2014                         if ( radeon_emit_state2( dev_priv, filp_priv, &state ) ) {
2015                                 DRM_ERROR( "radeon_emit_state2 failed\n" );
2016                                 return DRM_ERR( EINVAL );
2017                         }
2018
2019                         laststate = prim.stateidx;
2020                 }
2021
2022                 tclprim.start = prim.start;
2023                 tclprim.finish = prim.finish;
2024                 tclprim.prim = prim.prim;
2025                 tclprim.vc_format = prim.vc_format;
2026
2027                 if ( prim.prim & RADEON_PRIM_WALK_IND ) {
2028                         tclprim.offset = prim.numverts * 64;
2029                         tclprim.numverts = RADEON_MAX_VB_VERTS; /* duh */
2030
2031                         radeon_cp_dispatch_indices( dev, buf, &tclprim );
2032                 } else {
2033                         tclprim.numverts = prim.numverts;
2034                         tclprim.offset = 0; /* not used */
2035
2036                         radeon_cp_dispatch_vertex( dev, buf, &tclprim );
2037                 }
2038
2039                 if (sarea_priv->nbox == 1)
2040                         sarea_priv->nbox = 0;
2041         }
2042
2043         if ( vertex.discard ) {
2044                 radeon_cp_discard_buffer( dev, buf );
2045         }
2046
2047         COMMIT_RING();
2048         return 0;
2049 }
2050
2051
2052 static int radeon_emit_packets(
2053         drm_radeon_private_t *dev_priv,
2054         drm_file_t *filp_priv,
2055         drm_radeon_cmd_header_t header,
2056         drm_radeon_cmd_buffer_t *cmdbuf )
2057 {
2058         int id = (int)header.packet.packet_id;
2059         int sz, reg;
2060         int *data = (int *)cmdbuf->buf;
2061         RING_LOCALS;
2062
2063         if (id >= RADEON_MAX_STATE_PACKETS)
2064                 return DRM_ERR(EINVAL);
2065
2066         sz = packet[id].len;
2067         reg = packet[id].start;
2068
2069         if (sz * sizeof(int) > cmdbuf->bufsz) {
2070                 DRM_ERROR( "Packet size provided larger than data provided\n" );
2071                 return DRM_ERR(EINVAL);
2072         }
2073
2074         if ( radeon_check_and_fixup_packets( dev_priv, filp_priv, id, data ) ) {
2075                 DRM_ERROR( "Packet verification failed\n" );
2076                 return DRM_ERR( EINVAL );
2077         }
2078
2079         BEGIN_RING(sz+1);
2080         OUT_RING( CP_PACKET0( reg, (sz-1) ) );
2081         OUT_RING_TABLE( data, sz );
2082         ADVANCE_RING();
2083
2084         cmdbuf->buf += sz * sizeof(int);
2085         cmdbuf->bufsz -= sz * sizeof(int);
2086         return 0;
2087 }
2088
2089 static __inline__ int radeon_emit_scalars(
2090         drm_radeon_private_t *dev_priv,
2091         drm_radeon_cmd_header_t header,
2092         drm_radeon_cmd_buffer_t *cmdbuf )
2093 {
2094         int sz = header.scalars.count;
2095         int start = header.scalars.offset;
2096         int stride = header.scalars.stride;
2097         RING_LOCALS;
2098
2099         BEGIN_RING( 3+sz );
2100         OUT_RING( CP_PACKET0( RADEON_SE_TCL_SCALAR_INDX_REG, 0 ) );
2101         OUT_RING( start | (stride << RADEON_SCAL_INDX_DWORD_STRIDE_SHIFT));
2102         OUT_RING( CP_PACKET0_TABLE( RADEON_SE_TCL_SCALAR_DATA_REG, sz-1 ) );
2103         OUT_RING_TABLE( cmdbuf->buf, sz );
2104         ADVANCE_RING();
2105         cmdbuf->buf += sz * sizeof(int);
2106         cmdbuf->bufsz -= sz * sizeof(int);
2107         return 0;
2108 }
2109
2110 /* God this is ugly
2111  */
2112 static __inline__ int radeon_emit_scalars2(
2113         drm_radeon_private_t *dev_priv,
2114         drm_radeon_cmd_header_t header,
2115         drm_radeon_cmd_buffer_t *cmdbuf )
2116 {
2117         int sz = header.scalars.count;
2118         int start = ((unsigned int)header.scalars.offset) + 0x100;
2119         int stride = header.scalars.stride;
2120         RING_LOCALS;
2121
2122         BEGIN_RING( 3+sz );
2123         OUT_RING( CP_PACKET0( RADEON_SE_TCL_SCALAR_INDX_REG, 0 ) );
2124         OUT_RING( start | (stride << RADEON_SCAL_INDX_DWORD_STRIDE_SHIFT));
2125         OUT_RING( CP_PACKET0_TABLE( RADEON_SE_TCL_SCALAR_DATA_REG, sz-1 ) );
2126         OUT_RING_TABLE( cmdbuf->buf, sz );
2127         ADVANCE_RING();
2128         cmdbuf->buf += sz * sizeof(int);
2129         cmdbuf->bufsz -= sz * sizeof(int);
2130         return 0;
2131 }
2132
2133 static __inline__ int radeon_emit_vectors(
2134         drm_radeon_private_t *dev_priv,
2135         drm_radeon_cmd_header_t header,
2136         drm_radeon_cmd_buffer_t *cmdbuf )
2137 {
2138         int sz = header.vectors.count;
2139         int start = header.vectors.offset;
2140         int stride = header.vectors.stride;
2141         RING_LOCALS;
2142
2143         BEGIN_RING( 3+sz );
2144         OUT_RING( CP_PACKET0( RADEON_SE_TCL_VECTOR_INDX_REG, 0 ) );
2145         OUT_RING( start | (stride << RADEON_VEC_INDX_OCTWORD_STRIDE_SHIFT));
2146         OUT_RING( CP_PACKET0_TABLE( RADEON_SE_TCL_VECTOR_DATA_REG, (sz-1) ) );
2147         OUT_RING_TABLE( cmdbuf->buf, sz );
2148         ADVANCE_RING();
2149
2150         cmdbuf->buf += sz * sizeof(int);
2151         cmdbuf->bufsz -= sz * sizeof(int);
2152         return 0;
2153 }
2154
2155
2156 static int radeon_emit_packet3( drm_device_t *dev,
2157                                 drm_file_t *filp_priv,
2158                                 drm_radeon_cmd_buffer_t *cmdbuf )
2159 {
2160         drm_radeon_private_t *dev_priv = dev->dev_private;
2161         unsigned int cmdsz;
2162         int ret;
2163         RING_LOCALS;
2164
2165         DRM_DEBUG("\n");
2166
2167         if ( ( ret = radeon_check_and_fixup_packet3( dev_priv, filp_priv,
2168                                                      cmdbuf, &cmdsz ) ) ) {
2169                 DRM_ERROR( "Packet verification failed\n" );
2170                 return ret;
2171         }
2172
2173         BEGIN_RING( cmdsz );
2174         OUT_RING_TABLE( cmdbuf->buf, cmdsz );
2175         ADVANCE_RING();
2176
2177         cmdbuf->buf += cmdsz * 4;
2178         cmdbuf->bufsz -= cmdsz * 4;
2179         return 0;
2180 }
2181
2182
2183 static int radeon_emit_packet3_cliprect( drm_device_t *dev,
2184                                          drm_file_t *filp_priv,
2185                                          drm_radeon_cmd_buffer_t *cmdbuf,
2186                                          int orig_nbox )
2187 {
2188         drm_radeon_private_t *dev_priv = dev->dev_private;
2189         drm_clip_rect_t box;
2190         unsigned int cmdsz;
2191         int ret;
2192         drm_clip_rect_t __user *boxes = cmdbuf->boxes;
2193         int i = 0;
2194         RING_LOCALS;
2195
2196         DRM_DEBUG("\n");
2197
2198         if ( ( ret = radeon_check_and_fixup_packet3( dev_priv, filp_priv,
2199                                                      cmdbuf, &cmdsz ) ) ) {
2200                 DRM_ERROR( "Packet verification failed\n" );
2201                 return ret;
2202         }
2203
2204         if (!orig_nbox)
2205                 goto out;
2206
2207         do {
2208                 if ( i < cmdbuf->nbox ) {
2209                         if (DRM_COPY_FROM_USER( &box, &boxes[i], sizeof(box) ))
2210                                 return DRM_ERR(EFAULT);
2211                         /* FIXME The second and subsequent times round
2212                          * this loop, send a WAIT_UNTIL_3D_IDLE before
2213                          * calling emit_clip_rect(). This fixes a
2214                          * lockup on fast machines when sending
2215                          * several cliprects with a cmdbuf, as when
2216                          * waving a 2D window over a 3D
2217                          * window. Something in the commands from user
2218                          * space seems to hang the card when they're
2219                          * sent several times in a row. That would be
2220                          * the correct place to fix it but this works
2221                          * around it until I can figure that out - Tim
2222                          * Smith */
2223                         if ( i ) {
2224                                 BEGIN_RING( 2 );
2225                                 RADEON_WAIT_UNTIL_3D_IDLE();
2226                                 ADVANCE_RING();
2227                         }
2228                         radeon_emit_clip_rect( dev_priv, &box );
2229                 }
2230
2231                 BEGIN_RING( cmdsz );
2232                 OUT_RING_TABLE( cmdbuf->buf, cmdsz );
2233                 ADVANCE_RING();
2234
2235         } while ( ++i < cmdbuf->nbox );
2236         if (cmdbuf->nbox == 1)
2237                 cmdbuf->nbox = 0;
2238
2239  out:
2240         cmdbuf->buf += cmdsz * 4;
2241         cmdbuf->bufsz -= cmdsz * 4;
2242         return 0;
2243 }
2244
2245
2246 static int radeon_emit_wait( drm_device_t *dev, int flags )
2247 {
2248         drm_radeon_private_t *dev_priv = dev->dev_private;
2249         RING_LOCALS;
2250
2251         DRM_DEBUG("%s: %x\n", __FUNCTION__, flags);
2252         switch (flags) {
2253         case RADEON_WAIT_2D:
2254                 BEGIN_RING( 2 );
2255                 RADEON_WAIT_UNTIL_2D_IDLE();
2256                 ADVANCE_RING();
2257                 break;
2258         case RADEON_WAIT_3D:
2259                 BEGIN_RING( 2 );
2260                 RADEON_WAIT_UNTIL_3D_IDLE();
2261                 ADVANCE_RING();
2262                 break;
2263         case RADEON_WAIT_2D|RADEON_WAIT_3D:
2264                 BEGIN_RING( 2 );
2265                 RADEON_WAIT_UNTIL_IDLE();
2266                 ADVANCE_RING();
2267                 break;
2268         default:
2269                 return DRM_ERR(EINVAL);
2270         }
2271
2272         return 0;
2273 }
2274
2275 int radeon_cp_cmdbuf( DRM_IOCTL_ARGS )
2276 {
2277         DRM_DEVICE;
2278         drm_radeon_private_t *dev_priv = dev->dev_private;
2279         drm_file_t *filp_priv;
2280         drm_device_dma_t *dma = dev->dma;
2281         drm_buf_t *buf = NULL;
2282         int idx;
2283         drm_radeon_cmd_buffer_t cmdbuf;
2284         drm_radeon_cmd_header_t header;
2285         int orig_nbox, orig_bufsz;
2286         char *kbuf=NULL;
2287
2288         LOCK_TEST_WITH_RETURN( dev, filp );
2289
2290         if ( !dev_priv ) {
2291                 DRM_ERROR( "%s called with no initialization\n", __FUNCTION__ );
2292                 return DRM_ERR(EINVAL);
2293         }
2294
2295         DRM_GET_PRIV_WITH_RETURN( filp_priv, filp );
2296
2297         DRM_COPY_FROM_USER_IOCTL( cmdbuf, (drm_radeon_cmd_buffer_t __user *)data,
2298                              sizeof(cmdbuf) );
2299
2300         RING_SPACE_TEST_WITH_RETURN( dev_priv );
2301         VB_AGE_TEST_WITH_RETURN( dev_priv );
2302
2303         if (cmdbuf.bufsz > 64*1024 || cmdbuf.bufsz<0) {
2304                 return DRM_ERR(EINVAL);
2305         }
2306
2307         /* Allocate an in-kernel area and copy in the cmdbuf.  Do this to avoid
2308          * races between checking values and using those values in other code,
2309          * and simply to avoid a lot of function calls to copy in data.
2310          */
2311         orig_bufsz = cmdbuf.bufsz;
2312         if (orig_bufsz != 0) {
2313                 kbuf = kmalloc(cmdbuf.bufsz, GFP_KERNEL);
2314                 if (kbuf == NULL)
2315                         return DRM_ERR(ENOMEM);
2316                 if (DRM_COPY_FROM_USER(kbuf, cmdbuf.buf, cmdbuf.bufsz))
2317                         return DRM_ERR(EFAULT);
2318                 cmdbuf.buf = kbuf;
2319         }
2320
2321         orig_nbox = cmdbuf.nbox;
2322
2323         while ( cmdbuf.bufsz >= sizeof(header) ) {
2324
2325                 header.i = *(int *)cmdbuf.buf;
2326                 cmdbuf.buf += sizeof(header);
2327                 cmdbuf.bufsz -= sizeof(header);
2328
2329                 switch (header.header.cmd_type) {
2330                 case RADEON_CMD_PACKET:
2331                         DRM_DEBUG("RADEON_CMD_PACKET\n");
2332                         if (radeon_emit_packets( dev_priv, filp_priv, header, &cmdbuf )) {
2333                                 DRM_ERROR("radeon_emit_packets failed\n");
2334                                 goto err;
2335                         }
2336                         break;
2337
2338                 case RADEON_CMD_SCALARS:
2339                         DRM_DEBUG("RADEON_CMD_SCALARS\n");
2340                         if (radeon_emit_scalars( dev_priv, header, &cmdbuf )) {
2341                                 DRM_ERROR("radeon_emit_scalars failed\n");
2342                                 goto err;
2343                         }
2344                         break;
2345
2346                 case RADEON_CMD_VECTORS:
2347                         DRM_DEBUG("RADEON_CMD_VECTORS\n");
2348                         if (radeon_emit_vectors( dev_priv, header, &cmdbuf )) {
2349                                 DRM_ERROR("radeon_emit_vectors failed\n");
2350                                 goto err;
2351                         }
2352                         break;
2353
2354                 case RADEON_CMD_DMA_DISCARD:
2355                         DRM_DEBUG("RADEON_CMD_DMA_DISCARD\n");
2356                         idx = header.dma.buf_idx;
2357                         if ( idx < 0 || idx >= dma->buf_count ) {
2358                                 DRM_ERROR( "buffer index %d (of %d max)\n",
2359                                            idx, dma->buf_count - 1 );
2360                                 goto err;
2361                         }
2362
2363                         buf = dma->buflist[idx];
2364                         if ( buf->filp != filp || buf->pending ) {
2365                                 DRM_ERROR( "bad buffer %p %p %d\n",
2366                                            buf->filp, filp, buf->pending);
2367                                 goto err;
2368                         }
2369
2370                         radeon_cp_discard_buffer( dev, buf );
2371                         break;
2372
2373                 case RADEON_CMD_PACKET3:
2374                         DRM_DEBUG("RADEON_CMD_PACKET3\n");
2375                         if (radeon_emit_packet3( dev, filp_priv, &cmdbuf )) {
2376                                 DRM_ERROR("radeon_emit_packet3 failed\n");
2377                                 goto err;
2378                         }
2379                         break;
2380
2381                 case RADEON_CMD_PACKET3_CLIP:
2382                         DRM_DEBUG("RADEON_CMD_PACKET3_CLIP\n");
2383                         if (radeon_emit_packet3_cliprect( dev, filp_priv, &cmdbuf, orig_nbox )) {
2384                                 DRM_ERROR("radeon_emit_packet3_clip failed\n");
2385                                 goto err;
2386                         }
2387                         break;
2388
2389                 case RADEON_CMD_SCALARS2:
2390                         DRM_DEBUG("RADEON_CMD_SCALARS2\n");
2391                         if (radeon_emit_scalars2( dev_priv, header, &cmdbuf )) {
2392                                 DRM_ERROR("radeon_emit_scalars2 failed\n");
2393                                 goto err;
2394                         }
2395                         break;
2396
2397                 case RADEON_CMD_WAIT:
2398                         DRM_DEBUG("RADEON_CMD_WAIT\n");
2399                         if (radeon_emit_wait( dev, header.wait.flags )) {
2400                                 DRM_ERROR("radeon_emit_wait failed\n");
2401                                 goto err;
2402                         }
2403                         break;
2404                 default:
2405                         DRM_ERROR("bad cmd_type %d at %p\n",
2406                                   header.header.cmd_type,
2407                                   cmdbuf.buf - sizeof(header));
2408                         goto err;
2409                 }
2410         }
2411
2412         if (orig_bufsz != 0)
2413                 kfree(kbuf);
2414
2415         DRM_DEBUG("DONE\n");
2416         COMMIT_RING();
2417         return 0;
2418
2419 err:
2420         if (orig_bufsz != 0)
2421                 kfree(kbuf);
2422         return DRM_ERR(EINVAL);
2423 }
2424
2425
2426
2427 int radeon_cp_getparam( DRM_IOCTL_ARGS )
2428 {
2429         DRM_DEVICE;
2430         drm_radeon_private_t *dev_priv = dev->dev_private;
2431         drm_radeon_getparam_t param;
2432         int value;
2433
2434         if ( !dev_priv ) {
2435                 DRM_ERROR( "%s called with no initialization\n", __FUNCTION__ );
2436                 return DRM_ERR(EINVAL);
2437         }
2438
2439         DRM_COPY_FROM_USER_IOCTL( param, (drm_radeon_getparam_t __user *)data,
2440                              sizeof(param) );
2441
2442         DRM_DEBUG( "pid=%d\n", DRM_CURRENTPID );
2443
2444         switch( param.param ) {
2445         case RADEON_PARAM_GART_BUFFER_OFFSET:
2446                 value = dev_priv->gart_buffers_offset;
2447                 break;
2448         case RADEON_PARAM_LAST_FRAME:
2449                 dev_priv->stats.last_frame_reads++;
2450                 value = GET_SCRATCH( 0 );
2451                 break;
2452         case RADEON_PARAM_LAST_DISPATCH:
2453                 value = GET_SCRATCH( 1 );
2454                 break;
2455         case RADEON_PARAM_LAST_CLEAR:
2456                 dev_priv->stats.last_clear_reads++;
2457                 value = GET_SCRATCH( 2 );
2458                 break;
2459         case RADEON_PARAM_IRQ_NR:
2460                 value = dev->irq;
2461                 break;
2462         case RADEON_PARAM_GART_BASE:
2463                 value = dev_priv->gart_vm_start;
2464                 break;
2465         case RADEON_PARAM_REGISTER_HANDLE:
2466                 value = dev_priv->mmio_offset;
2467                 break;
2468         case RADEON_PARAM_STATUS_HANDLE:
2469                 value = dev_priv->ring_rptr_offset;
2470                 break;
2471 #if BITS_PER_LONG == 32
2472         /*
2473          * This ioctl() doesn't work on 64-bit platforms because hw_lock is a
2474          * pointer which can't fit into an int-sized variable.  According to
2475          * Michel Dänzer, the ioctl() is only used on embedded platforms, so
2476          * not supporting it shouldn't be a problem.  If the same functionality
2477          * is needed on 64-bit platforms, a new ioctl() would have to be added,
2478          * so backwards-compatibility for the embedded platforms can be
2479          * maintained.  --davidm 4-Feb-2004.
2480          */
2481         case RADEON_PARAM_SAREA_HANDLE:
2482                 /* The lock is the first dword in the sarea. */
2483                 value = (long)dev->lock.hw_lock;
2484                 break;
2485 #endif
2486         case RADEON_PARAM_GART_TEX_HANDLE:
2487                 value = dev_priv->gart_textures_offset;
2488                 break;
2489         default:
2490                 return DRM_ERR(EINVAL);
2491         }
2492
2493         if ( DRM_COPY_TO_USER( param.value, &value, sizeof(int) ) ) {
2494                 DRM_ERROR( "copy_to_user\n" );
2495                 return DRM_ERR(EFAULT);
2496         }
2497
2498         return 0;
2499 }
2500
2501 int radeon_cp_setparam( DRM_IOCTL_ARGS ) {
2502         DRM_DEVICE;
2503         drm_radeon_private_t *dev_priv = dev->dev_private;
2504         drm_file_t *filp_priv;
2505         drm_radeon_setparam_t sp;
2506         struct drm_radeon_driver_file_fields *radeon_priv;
2507
2508         if ( !dev_priv ) {
2509                 DRM_ERROR( "%s called with no initialization\n", __FUNCTION__ );
2510                 return DRM_ERR( EINVAL );
2511         }
2512
2513         DRM_GET_PRIV_WITH_RETURN( filp_priv, filp );
2514
2515         DRM_COPY_FROM_USER_IOCTL( sp, ( drm_radeon_setparam_t __user * )data,
2516                                   sizeof( sp ) );
2517
2518         switch( sp.param ) {
2519         case RADEON_SETPARAM_FB_LOCATION:
2520                 radeon_priv = filp_priv->driver_priv;
2521                 radeon_priv->radeon_fb_delta = dev_priv->fb_location - sp.value;
2522                 break;
2523         default:
2524                 DRM_DEBUG( "Invalid parameter %d\n", sp.param );
2525                 return DRM_ERR( EINVAL );
2526         }
2527
2528         return 0;
2529 }
2530
2531 /* When a client dies:
2532  *    - Check for and clean up flipped page state
2533  *    - Free any alloced GART memory.
2534  *
2535  * DRM infrastructure takes care of reclaiming dma buffers.
2536  */
2537 static void radeon_driver_prerelease(drm_device_t *dev, DRMFILE filp)
2538 {
2539         if ( dev->dev_private ) {
2540                 drm_radeon_private_t *dev_priv = dev->dev_private;
2541                 if ( dev_priv->page_flipping ) {
2542                         radeon_do_cleanup_pageflip( dev );
2543                 }
2544                 radeon_mem_release( filp, dev_priv->gart_heap );
2545                 radeon_mem_release( filp, dev_priv->fb_heap );
2546         }
2547 }
2548
2549 static void radeon_driver_pretakedown(drm_device_t *dev)
2550 {
2551         radeon_do_release(dev);
2552 }
2553
2554 static int radeon_driver_open_helper(drm_device_t *dev, drm_file_t *filp_priv)
2555 {
2556         drm_radeon_private_t *dev_priv = dev->dev_private;
2557         struct drm_radeon_driver_file_fields *radeon_priv;
2558
2559         radeon_priv = (struct drm_radeon_driver_file_fields *)DRM(alloc)(sizeof(*radeon_priv), DRM_MEM_FILES);
2560
2561         if (!radeon_priv)
2562                 return -ENOMEM;
2563
2564         filp_priv->driver_priv = radeon_priv;
2565         if ( dev_priv )
2566                 radeon_priv->radeon_fb_delta = dev_priv->fb_location;
2567         else
2568                 radeon_priv->radeon_fb_delta = 0;
2569         return 0;
2570 }
2571
2572
2573 static void radeon_driver_free_filp_priv(drm_device_t *dev, drm_file_t *filp_priv)
2574 {
2575          struct drm_radeon_driver_file_fields *radeon_priv = filp_priv->driver_priv;
2576
2577          DRM(free)(radeon_priv, sizeof(*radeon_priv), DRM_MEM_FILES);
2578 }
2579
2580 void radeon_driver_register_fns(struct drm_device *dev)
2581 {
2582         dev->driver_features = DRIVER_USE_AGP | DRIVER_USE_MTRR | DRIVER_PCI_DMA | DRIVER_SG | DRIVER_HAVE_IRQ | DRIVER_HAVE_DMA | DRIVER_IRQ_SHARED | DRIVER_IRQ_VBL;
2583         dev->dev_priv_size = sizeof(drm_radeon_buf_priv_t);
2584         dev->fn_tbl.prerelease = radeon_driver_prerelease;
2585         dev->fn_tbl.pretakedown = radeon_driver_pretakedown;
2586         dev->fn_tbl.open_helper = radeon_driver_open_helper;
2587         dev->fn_tbl.free_filp_priv = radeon_driver_free_filp_priv;
2588         dev->fn_tbl.vblank_wait = radeon_driver_vblank_wait;
2589         dev->fn_tbl.irq_preinstall = radeon_driver_irq_preinstall;
2590         dev->fn_tbl.irq_postinstall = radeon_driver_irq_postinstall;
2591         dev->fn_tbl.irq_uninstall = radeon_driver_irq_uninstall;
2592         dev->fn_tbl.irq_handler = radeon_driver_irq_handler;
2593 }