1 /* radeon_state.c -- State support for Radeon -*- linux-c -*-
3 * Copyright 2000 VA Linux Systems, Inc., Fremont, California.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
21 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
22 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
23 * DEALINGS IN THE SOFTWARE.
26 * Gareth Hughes <gareth@valinux.com>
27 * Kevin E. Martin <martin@valinux.com>
33 #include "drm_sarea.h"
34 #include "radeon_drm.h"
35 #include "radeon_drv.h"
38 /* ================================================================
39 * Helper functions for client state checking and fixup
42 static __inline__ int radeon_check_and_fixup_offset( drm_radeon_private_t *dev_priv,
43 drm_file_t *filp_priv,
47 if ( off >= dev_priv->fb_location &&
48 off < ( dev_priv->gart_vm_start + dev_priv->gart_size ) )
51 off += filp_priv->radeon_fb_delta;
53 DRM_DEBUG( "offset fixed up to 0x%x\n", off );
55 if ( off < dev_priv->fb_location ||
56 off >= ( dev_priv->gart_vm_start + dev_priv->gart_size ) )
57 return DRM_ERR( EINVAL );
64 static __inline__ int radeon_check_and_fixup_offset_user( drm_radeon_private_t *dev_priv,
65 drm_file_t *filp_priv,
66 u32 __user *offset ) {
69 DRM_GET_USER_UNCHECKED( off, offset );
71 if ( radeon_check_and_fixup_offset( dev_priv, filp_priv, &off ) )
72 return DRM_ERR( EINVAL );
74 DRM_PUT_USER_UNCHECKED( offset, off );
79 static __inline__ int radeon_check_and_fixup_packets( drm_radeon_private_t *dev_priv,
80 drm_file_t *filp_priv,
85 case RADEON_EMIT_PP_MISC:
86 if ( radeon_check_and_fixup_offset_user( dev_priv, filp_priv,
87 &data[( RADEON_RB3D_DEPTHOFFSET
88 - RADEON_PP_MISC ) / 4] ) ) {
89 DRM_ERROR( "Invalid depth buffer offset\n" );
90 return DRM_ERR( EINVAL );
94 case RADEON_EMIT_PP_CNTL:
95 if ( radeon_check_and_fixup_offset_user( dev_priv, filp_priv,
96 &data[( RADEON_RB3D_COLOROFFSET
97 - RADEON_PP_CNTL ) / 4] ) ) {
98 DRM_ERROR( "Invalid colour buffer offset\n" );
99 return DRM_ERR( EINVAL );
103 case R200_EMIT_PP_TXOFFSET_0:
104 case R200_EMIT_PP_TXOFFSET_1:
105 case R200_EMIT_PP_TXOFFSET_2:
106 case R200_EMIT_PP_TXOFFSET_3:
107 case R200_EMIT_PP_TXOFFSET_4:
108 case R200_EMIT_PP_TXOFFSET_5:
109 if ( radeon_check_and_fixup_offset_user( dev_priv, filp_priv,
111 DRM_ERROR( "Invalid R200 texture offset\n" );
112 return DRM_ERR( EINVAL );
116 case RADEON_EMIT_PP_TXFILTER_0:
117 case RADEON_EMIT_PP_TXFILTER_1:
118 case RADEON_EMIT_PP_TXFILTER_2:
119 if ( radeon_check_and_fixup_offset_user( dev_priv, filp_priv,
120 &data[( RADEON_PP_TXOFFSET_0
121 - RADEON_PP_TXFILTER_0 ) / 4] ) ) {
122 DRM_ERROR( "Invalid R100 texture offset\n" );
123 return DRM_ERR( EINVAL );
127 case R200_EMIT_PP_CUBIC_OFFSETS_0:
128 case R200_EMIT_PP_CUBIC_OFFSETS_1:
129 case R200_EMIT_PP_CUBIC_OFFSETS_2:
130 case R200_EMIT_PP_CUBIC_OFFSETS_3:
131 case R200_EMIT_PP_CUBIC_OFFSETS_4:
132 case R200_EMIT_PP_CUBIC_OFFSETS_5: {
134 for ( i = 0; i < 5; i++ ) {
135 if ( radeon_check_and_fixup_offset_user( dev_priv,
138 DRM_ERROR( "Invalid R200 cubic texture offset\n" );
139 return DRM_ERR( EINVAL );
145 case RADEON_EMIT_RB3D_COLORPITCH:
146 case RADEON_EMIT_RE_LINE_PATTERN:
147 case RADEON_EMIT_SE_LINE_WIDTH:
148 case RADEON_EMIT_PP_LUM_MATRIX:
149 case RADEON_EMIT_PP_ROT_MATRIX_0:
150 case RADEON_EMIT_RB3D_STENCILREFMASK:
151 case RADEON_EMIT_SE_VPORT_XSCALE:
152 case RADEON_EMIT_SE_CNTL:
153 case RADEON_EMIT_SE_CNTL_STATUS:
154 case RADEON_EMIT_RE_MISC:
155 case RADEON_EMIT_PP_BORDER_COLOR_0:
156 case RADEON_EMIT_PP_BORDER_COLOR_1:
157 case RADEON_EMIT_PP_BORDER_COLOR_2:
158 case RADEON_EMIT_SE_ZBIAS_FACTOR:
159 case RADEON_EMIT_SE_TCL_OUTPUT_VTX_FMT:
160 case RADEON_EMIT_SE_TCL_MATERIAL_EMMISSIVE_RED:
161 case R200_EMIT_PP_TXCBLEND_0:
162 case R200_EMIT_PP_TXCBLEND_1:
163 case R200_EMIT_PP_TXCBLEND_2:
164 case R200_EMIT_PP_TXCBLEND_3:
165 case R200_EMIT_PP_TXCBLEND_4:
166 case R200_EMIT_PP_TXCBLEND_5:
167 case R200_EMIT_PP_TXCBLEND_6:
168 case R200_EMIT_PP_TXCBLEND_7:
169 case R200_EMIT_TCL_LIGHT_MODEL_CTL_0:
170 case R200_EMIT_TFACTOR_0:
171 case R200_EMIT_VTX_FMT_0:
172 case R200_EMIT_VAP_CTL:
173 case R200_EMIT_MATRIX_SELECT_0:
174 case R200_EMIT_TEX_PROC_CTL_2:
175 case R200_EMIT_TCL_UCP_VERT_BLEND_CTL:
176 case R200_EMIT_PP_TXFILTER_0:
177 case R200_EMIT_PP_TXFILTER_1:
178 case R200_EMIT_PP_TXFILTER_2:
179 case R200_EMIT_PP_TXFILTER_3:
180 case R200_EMIT_PP_TXFILTER_4:
181 case R200_EMIT_PP_TXFILTER_5:
182 case R200_EMIT_VTE_CNTL:
183 case R200_EMIT_OUTPUT_VTX_COMP_SEL:
184 case R200_EMIT_PP_TAM_DEBUG3:
185 case R200_EMIT_PP_CNTL_X:
186 case R200_EMIT_RB3D_DEPTHXY_OFFSET:
187 case R200_EMIT_RE_AUX_SCISSOR_CNTL:
188 case R200_EMIT_RE_SCISSOR_TL_0:
189 case R200_EMIT_RE_SCISSOR_TL_1:
190 case R200_EMIT_RE_SCISSOR_TL_2:
191 case R200_EMIT_SE_VAP_CNTL_STATUS:
192 case R200_EMIT_SE_VTX_STATE_CNTL:
193 case R200_EMIT_RE_POINTSIZE:
194 case R200_EMIT_TCL_INPUT_VTX_VECTOR_ADDR_0:
195 case R200_EMIT_PP_CUBIC_FACES_0:
196 case R200_EMIT_PP_CUBIC_FACES_1:
197 case R200_EMIT_PP_CUBIC_FACES_2:
198 case R200_EMIT_PP_CUBIC_FACES_3:
199 case R200_EMIT_PP_CUBIC_FACES_4:
200 case R200_EMIT_PP_CUBIC_FACES_5:
201 case RADEON_EMIT_PP_TEX_SIZE_0:
202 case RADEON_EMIT_PP_TEX_SIZE_1:
203 case RADEON_EMIT_PP_TEX_SIZE_2:
204 case R200_EMIT_RB3D_BLENDCOLOR:
205 /* These packets don't contain memory offsets */
209 DRM_ERROR( "Unknown state packet ID %d\n", id );
210 return DRM_ERR( EINVAL );
216 static __inline__ int radeon_check_and_fixup_packet3( drm_radeon_private_t *dev_priv,
217 drm_file_t *filp_priv,
218 drm_radeon_cmd_buffer_t *cmdbuf,
219 unsigned int *cmdsz ) {
221 u32 __user *cmd = (u32 __user *)cmdbuf->buf;
223 if ( DRM_COPY_FROM_USER_UNCHECKED( tmp, cmd, sizeof( tmp ) ) ) {
224 DRM_ERROR( "Failed to copy data from user space\n" );
225 return DRM_ERR( EFAULT );
228 *cmdsz = 2 + ( ( tmp[0] & RADEON_CP_PACKET_COUNT_MASK ) >> 16 );
230 if ( ( tmp[0] & 0xc0000000 ) != RADEON_CP_PACKET3 ) {
231 DRM_ERROR( "Not a type 3 packet\n" );
232 return DRM_ERR( EINVAL );
235 if ( 4 * *cmdsz > cmdbuf->bufsz ) {
236 DRM_ERROR( "Packet size larger than size of data provided\n" );
237 return DRM_ERR( EINVAL );
240 /* Check client state and fix it up if necessary */
241 if ( tmp[0] & 0x8000 ) { /* MSB of opcode: next DWORD GUI_CNTL */
244 if ( tmp[1] & ( RADEON_GMC_SRC_PITCH_OFFSET_CNTL
245 | RADEON_GMC_DST_PITCH_OFFSET_CNTL ) ) {
246 offset = tmp[2] << 10;
247 if ( radeon_check_and_fixup_offset( dev_priv, filp_priv, &offset ) ) {
248 DRM_ERROR( "Invalid first packet offset\n" );
249 return DRM_ERR( EINVAL );
251 tmp[2] = ( tmp[2] & 0xffc00000 ) | offset >> 10;
254 if ( ( tmp[1] & RADEON_GMC_SRC_PITCH_OFFSET_CNTL ) &&
255 ( tmp[1] & RADEON_GMC_DST_PITCH_OFFSET_CNTL ) ) {
256 offset = tmp[3] << 10;
257 if ( radeon_check_and_fixup_offset( dev_priv, filp_priv, &offset ) ) {
258 DRM_ERROR( "Invalid second packet offset\n" );
259 return DRM_ERR( EINVAL );
261 tmp[3] = ( tmp[3] & 0xffc00000 ) | offset >> 10;
264 if ( DRM_COPY_TO_USER_UNCHECKED( cmd, tmp, sizeof( tmp ) ) ) {
265 DRM_ERROR( "Failed to copy data to user space\n" );
266 return DRM_ERR( EFAULT );
274 /* ================================================================
275 * CP hardware state programming functions
278 static __inline__ void radeon_emit_clip_rect( drm_radeon_private_t *dev_priv,
279 drm_clip_rect_t *box )
283 DRM_DEBUG( " box: x1=%d y1=%d x2=%d y2=%d\n",
284 box->x1, box->y1, box->x2, box->y2 );
287 OUT_RING( CP_PACKET0( RADEON_RE_TOP_LEFT, 0 ) );
288 OUT_RING( (box->y1 << 16) | box->x1 );
289 OUT_RING( CP_PACKET0( RADEON_RE_WIDTH_HEIGHT, 0 ) );
290 OUT_RING( ((box->y2 - 1) << 16) | (box->x2 - 1) );
296 static int radeon_emit_state( drm_radeon_private_t *dev_priv,
297 drm_file_t *filp_priv,
298 drm_radeon_context_regs_t *ctx,
299 drm_radeon_texture_regs_t *tex,
303 DRM_DEBUG( "dirty=0x%08x\n", dirty );
305 if ( dirty & RADEON_UPLOAD_CONTEXT ) {
306 if ( radeon_check_and_fixup_offset( dev_priv, filp_priv,
307 &ctx->rb3d_depthoffset ) ) {
308 DRM_ERROR( "Invalid depth buffer offset\n" );
309 return DRM_ERR( EINVAL );
312 if ( radeon_check_and_fixup_offset( dev_priv, filp_priv,
313 &ctx->rb3d_coloroffset ) ) {
314 DRM_ERROR( "Invalid depth buffer offset\n" );
315 return DRM_ERR( EINVAL );
319 OUT_RING( CP_PACKET0( RADEON_PP_MISC, 6 ) );
320 OUT_RING( ctx->pp_misc );
321 OUT_RING( ctx->pp_fog_color );
322 OUT_RING( ctx->re_solid_color );
323 OUT_RING( ctx->rb3d_blendcntl );
324 OUT_RING( ctx->rb3d_depthoffset );
325 OUT_RING( ctx->rb3d_depthpitch );
326 OUT_RING( ctx->rb3d_zstencilcntl );
327 OUT_RING( CP_PACKET0( RADEON_PP_CNTL, 2 ) );
328 OUT_RING( ctx->pp_cntl );
329 OUT_RING( ctx->rb3d_cntl );
330 OUT_RING( ctx->rb3d_coloroffset );
331 OUT_RING( CP_PACKET0( RADEON_RB3D_COLORPITCH, 0 ) );
332 OUT_RING( ctx->rb3d_colorpitch );
336 if ( dirty & RADEON_UPLOAD_VERTFMT ) {
338 OUT_RING( CP_PACKET0( RADEON_SE_COORD_FMT, 0 ) );
339 OUT_RING( ctx->se_coord_fmt );
343 if ( dirty & RADEON_UPLOAD_LINE ) {
345 OUT_RING( CP_PACKET0( RADEON_RE_LINE_PATTERN, 1 ) );
346 OUT_RING( ctx->re_line_pattern );
347 OUT_RING( ctx->re_line_state );
348 OUT_RING( CP_PACKET0( RADEON_SE_LINE_WIDTH, 0 ) );
349 OUT_RING( ctx->se_line_width );
353 if ( dirty & RADEON_UPLOAD_BUMPMAP ) {
355 OUT_RING( CP_PACKET0( RADEON_PP_LUM_MATRIX, 0 ) );
356 OUT_RING( ctx->pp_lum_matrix );
357 OUT_RING( CP_PACKET0( RADEON_PP_ROT_MATRIX_0, 1 ) );
358 OUT_RING( ctx->pp_rot_matrix_0 );
359 OUT_RING( ctx->pp_rot_matrix_1 );
363 if ( dirty & RADEON_UPLOAD_MASKS ) {
365 OUT_RING( CP_PACKET0( RADEON_RB3D_STENCILREFMASK, 2 ) );
366 OUT_RING( ctx->rb3d_stencilrefmask );
367 OUT_RING( ctx->rb3d_ropcntl );
368 OUT_RING( ctx->rb3d_planemask );
372 if ( dirty & RADEON_UPLOAD_VIEWPORT ) {
374 OUT_RING( CP_PACKET0( RADEON_SE_VPORT_XSCALE, 5 ) );
375 OUT_RING( ctx->se_vport_xscale );
376 OUT_RING( ctx->se_vport_xoffset );
377 OUT_RING( ctx->se_vport_yscale );
378 OUT_RING( ctx->se_vport_yoffset );
379 OUT_RING( ctx->se_vport_zscale );
380 OUT_RING( ctx->se_vport_zoffset );
384 if ( dirty & RADEON_UPLOAD_SETUP ) {
386 OUT_RING( CP_PACKET0( RADEON_SE_CNTL, 0 ) );
387 OUT_RING( ctx->se_cntl );
388 OUT_RING( CP_PACKET0( RADEON_SE_CNTL_STATUS, 0 ) );
389 OUT_RING( ctx->se_cntl_status );
393 if ( dirty & RADEON_UPLOAD_MISC ) {
395 OUT_RING( CP_PACKET0( RADEON_RE_MISC, 0 ) );
396 OUT_RING( ctx->re_misc );
400 if ( dirty & RADEON_UPLOAD_TEX0 ) {
401 if ( radeon_check_and_fixup_offset( dev_priv, filp_priv,
402 &tex[0].pp_txoffset ) ) {
403 DRM_ERROR( "Invalid texture offset for unit 0\n" );
404 return DRM_ERR( EINVAL );
408 OUT_RING( CP_PACKET0( RADEON_PP_TXFILTER_0, 5 ) );
409 OUT_RING( tex[0].pp_txfilter );
410 OUT_RING( tex[0].pp_txformat );
411 OUT_RING( tex[0].pp_txoffset );
412 OUT_RING( tex[0].pp_txcblend );
413 OUT_RING( tex[0].pp_txablend );
414 OUT_RING( tex[0].pp_tfactor );
415 OUT_RING( CP_PACKET0( RADEON_PP_BORDER_COLOR_0, 0 ) );
416 OUT_RING( tex[0].pp_border_color );
420 if ( dirty & RADEON_UPLOAD_TEX1 ) {
421 if ( radeon_check_and_fixup_offset( dev_priv, filp_priv,
422 &tex[1].pp_txoffset ) ) {
423 DRM_ERROR( "Invalid texture offset for unit 1\n" );
424 return DRM_ERR( EINVAL );
428 OUT_RING( CP_PACKET0( RADEON_PP_TXFILTER_1, 5 ) );
429 OUT_RING( tex[1].pp_txfilter );
430 OUT_RING( tex[1].pp_txformat );
431 OUT_RING( tex[1].pp_txoffset );
432 OUT_RING( tex[1].pp_txcblend );
433 OUT_RING( tex[1].pp_txablend );
434 OUT_RING( tex[1].pp_tfactor );
435 OUT_RING( CP_PACKET0( RADEON_PP_BORDER_COLOR_1, 0 ) );
436 OUT_RING( tex[1].pp_border_color );
440 if ( dirty & RADEON_UPLOAD_TEX2 ) {
441 if ( radeon_check_and_fixup_offset( dev_priv, filp_priv,
442 &tex[2].pp_txoffset ) ) {
443 DRM_ERROR( "Invalid texture offset for unit 2\n" );
444 return DRM_ERR( EINVAL );
448 OUT_RING( CP_PACKET0( RADEON_PP_TXFILTER_2, 5 ) );
449 OUT_RING( tex[2].pp_txfilter );
450 OUT_RING( tex[2].pp_txformat );
451 OUT_RING( tex[2].pp_txoffset );
452 OUT_RING( tex[2].pp_txcblend );
453 OUT_RING( tex[2].pp_txablend );
454 OUT_RING( tex[2].pp_tfactor );
455 OUT_RING( CP_PACKET0( RADEON_PP_BORDER_COLOR_2, 0 ) );
456 OUT_RING( tex[2].pp_border_color );
465 static int radeon_emit_state2( drm_radeon_private_t *dev_priv,
466 drm_file_t *filp_priv,
467 drm_radeon_state_t *state )
471 if (state->dirty & RADEON_UPLOAD_ZBIAS) {
473 OUT_RING( CP_PACKET0( RADEON_SE_ZBIAS_FACTOR, 1 ) );
474 OUT_RING( state->context2.se_zbias_factor );
475 OUT_RING( state->context2.se_zbias_constant );
479 return radeon_emit_state( dev_priv, filp_priv, &state->context,
480 state->tex, state->dirty );
483 /* New (1.3) state mechanism. 3 commands (packet, scalar, vector) in
484 * 1.3 cmdbuffers allow all previous state to be updated as well as
485 * the tcl scalar and vector areas.
491 } packet[RADEON_MAX_STATE_PACKETS] = {
492 { RADEON_PP_MISC,7,"RADEON_PP_MISC" },
493 { RADEON_PP_CNTL,3,"RADEON_PP_CNTL" },
494 { RADEON_RB3D_COLORPITCH,1,"RADEON_RB3D_COLORPITCH" },
495 { RADEON_RE_LINE_PATTERN,2,"RADEON_RE_LINE_PATTERN" },
496 { RADEON_SE_LINE_WIDTH,1,"RADEON_SE_LINE_WIDTH" },
497 { RADEON_PP_LUM_MATRIX,1,"RADEON_PP_LUM_MATRIX" },
498 { RADEON_PP_ROT_MATRIX_0,2,"RADEON_PP_ROT_MATRIX_0" },
499 { RADEON_RB3D_STENCILREFMASK,3,"RADEON_RB3D_STENCILREFMASK" },
500 { RADEON_SE_VPORT_XSCALE,6,"RADEON_SE_VPORT_XSCALE" },
501 { RADEON_SE_CNTL,2,"RADEON_SE_CNTL" },
502 { RADEON_SE_CNTL_STATUS,1,"RADEON_SE_CNTL_STATUS" },
503 { RADEON_RE_MISC,1,"RADEON_RE_MISC" },
504 { RADEON_PP_TXFILTER_0,6,"RADEON_PP_TXFILTER_0" },
505 { RADEON_PP_BORDER_COLOR_0,1,"RADEON_PP_BORDER_COLOR_0" },
506 { RADEON_PP_TXFILTER_1,6,"RADEON_PP_TXFILTER_1" },
507 { RADEON_PP_BORDER_COLOR_1,1,"RADEON_PP_BORDER_COLOR_1" },
508 { RADEON_PP_TXFILTER_2,6,"RADEON_PP_TXFILTER_2" },
509 { RADEON_PP_BORDER_COLOR_2,1,"RADEON_PP_BORDER_COLOR_2" },
510 { RADEON_SE_ZBIAS_FACTOR,2,"RADEON_SE_ZBIAS_FACTOR" },
511 { RADEON_SE_TCL_OUTPUT_VTX_FMT,11,"RADEON_SE_TCL_OUTPUT_VTX_FMT" },
512 { RADEON_SE_TCL_MATERIAL_EMMISSIVE_RED,17,"RADEON_SE_TCL_MATERIAL_EMMISSIVE_RED" },
513 { R200_PP_TXCBLEND_0, 4, "R200_PP_TXCBLEND_0" },
514 { R200_PP_TXCBLEND_1, 4, "R200_PP_TXCBLEND_1" },
515 { R200_PP_TXCBLEND_2, 4, "R200_PP_TXCBLEND_2" },
516 { R200_PP_TXCBLEND_3, 4, "R200_PP_TXCBLEND_3" },
517 { R200_PP_TXCBLEND_4, 4, "R200_PP_TXCBLEND_4" },
518 { R200_PP_TXCBLEND_5, 4, "R200_PP_TXCBLEND_5" },
519 { R200_PP_TXCBLEND_6, 4, "R200_PP_TXCBLEND_6" },
520 { R200_PP_TXCBLEND_7, 4, "R200_PP_TXCBLEND_7" },
521 { R200_SE_TCL_LIGHT_MODEL_CTL_0, 6, "R200_SE_TCL_LIGHT_MODEL_CTL_0" },
522 { R200_PP_TFACTOR_0, 6, "R200_PP_TFACTOR_0" },
523 { R200_SE_VTX_FMT_0, 4, "R200_SE_VTX_FMT_0" },
524 { R200_SE_VAP_CNTL, 1, "R200_SE_VAP_CNTL" },
525 { R200_SE_TCL_MATRIX_SEL_0, 5, "R200_SE_TCL_MATRIX_SEL_0" },
526 { R200_SE_TCL_TEX_PROC_CTL_2, 5, "R200_SE_TCL_TEX_PROC_CTL_2" },
527 { R200_SE_TCL_UCP_VERT_BLEND_CTL, 1, "R200_SE_TCL_UCP_VERT_BLEND_CTL" },
528 { R200_PP_TXFILTER_0, 6, "R200_PP_TXFILTER_0" },
529 { R200_PP_TXFILTER_1, 6, "R200_PP_TXFILTER_1" },
530 { R200_PP_TXFILTER_2, 6, "R200_PP_TXFILTER_2" },
531 { R200_PP_TXFILTER_3, 6, "R200_PP_TXFILTER_3" },
532 { R200_PP_TXFILTER_4, 6, "R200_PP_TXFILTER_4" },
533 { R200_PP_TXFILTER_5, 6, "R200_PP_TXFILTER_5" },
534 { R200_PP_TXOFFSET_0, 1, "R200_PP_TXOFFSET_0" },
535 { R200_PP_TXOFFSET_1, 1, "R200_PP_TXOFFSET_1" },
536 { R200_PP_TXOFFSET_2, 1, "R200_PP_TXOFFSET_2" },
537 { R200_PP_TXOFFSET_3, 1, "R200_PP_TXOFFSET_3" },
538 { R200_PP_TXOFFSET_4, 1, "R200_PP_TXOFFSET_4" },
539 { R200_PP_TXOFFSET_5, 1, "R200_PP_TXOFFSET_5" },
540 { R200_SE_VTE_CNTL, 1, "R200_SE_VTE_CNTL" },
541 { R200_SE_TCL_OUTPUT_VTX_COMP_SEL, 1, "R200_SE_TCL_OUTPUT_VTX_COMP_SEL" },
542 { R200_PP_TAM_DEBUG3, 1, "R200_PP_TAM_DEBUG3" },
543 { R200_PP_CNTL_X, 1, "R200_PP_CNTL_X" },
544 { R200_RB3D_DEPTHXY_OFFSET, 1, "R200_RB3D_DEPTHXY_OFFSET" },
545 { R200_RE_AUX_SCISSOR_CNTL, 1, "R200_RE_AUX_SCISSOR_CNTL" },
546 { R200_RE_SCISSOR_TL_0, 2, "R200_RE_SCISSOR_TL_0" },
547 { R200_RE_SCISSOR_TL_1, 2, "R200_RE_SCISSOR_TL_1" },
548 { R200_RE_SCISSOR_TL_2, 2, "R200_RE_SCISSOR_TL_2" },
549 { R200_SE_VAP_CNTL_STATUS, 1, "R200_SE_VAP_CNTL_STATUS" },
550 { R200_SE_VTX_STATE_CNTL, 1, "R200_SE_VTX_STATE_CNTL" },
551 { R200_RE_POINTSIZE, 1, "R200_RE_POINTSIZE" },
552 { R200_SE_TCL_INPUT_VTX_VECTOR_ADDR_0, 4, "R200_SE_TCL_INPUT_VTX_VECTOR_ADDR_0" },
553 { R200_PP_CUBIC_FACES_0, 1, "R200_PP_CUBIC_FACES_0" }, /* 61 */
554 { R200_PP_CUBIC_OFFSET_F1_0, 5, "R200_PP_CUBIC_OFFSET_F1_0" }, /* 62 */
555 { R200_PP_CUBIC_FACES_1, 1, "R200_PP_CUBIC_FACES_1" },
556 { R200_PP_CUBIC_OFFSET_F1_1, 5, "R200_PP_CUBIC_OFFSET_F1_1" },
557 { R200_PP_CUBIC_FACES_2, 1, "R200_PP_CUBIC_FACES_2" },
558 { R200_PP_CUBIC_OFFSET_F1_2, 5, "R200_PP_CUBIC_OFFSET_F1_2" },
559 { R200_PP_CUBIC_FACES_3, 1, "R200_PP_CUBIC_FACES_3" },
560 { R200_PP_CUBIC_OFFSET_F1_3, 5, "R200_PP_CUBIC_OFFSET_F1_3" },
561 { R200_PP_CUBIC_FACES_4, 1, "R200_PP_CUBIC_FACES_4" },
562 { R200_PP_CUBIC_OFFSET_F1_4, 5, "R200_PP_CUBIC_OFFSET_F1_4" },
563 { R200_PP_CUBIC_FACES_5, 1, "R200_PP_CUBIC_FACES_5" },
564 { R200_PP_CUBIC_OFFSET_F1_5, 5, "R200_PP_CUBIC_OFFSET_F1_5" },
565 { RADEON_PP_TEX_SIZE_0, 2, "RADEON_PP_TEX_SIZE_0" },
566 { RADEON_PP_TEX_SIZE_1, 2, "RADEON_PP_TEX_SIZE_1" },
567 { RADEON_PP_TEX_SIZE_2, 2, "RADEON_PP_TEX_SIZE_2" },
568 { R200_RB3D_BLENDCOLOR, 3, "R200_RB3D_BLENDCOLOR" },
573 /* ================================================================
574 * Performance monitoring functions
577 static void radeon_clear_box( drm_radeon_private_t *dev_priv,
578 int x, int y, int w, int h,
579 int r, int g, int b )
584 x += dev_priv->sarea_priv->boxes[0].x1;
585 y += dev_priv->sarea_priv->boxes[0].y1;
587 switch ( dev_priv->color_fmt ) {
588 case RADEON_COLOR_FORMAT_RGB565:
589 color = (((r & 0xf8) << 8) |
593 case RADEON_COLOR_FORMAT_ARGB8888:
595 color = (((0xff) << 24) | (r << 16) | (g << 8) | b);
600 RADEON_WAIT_UNTIL_3D_IDLE();
601 OUT_RING( CP_PACKET0( RADEON_DP_WRITE_MASK, 0 ) );
602 OUT_RING( 0xffffffff );
607 OUT_RING( CP_PACKET3( RADEON_CNTL_PAINT_MULTI, 4 ) );
608 OUT_RING( RADEON_GMC_DST_PITCH_OFFSET_CNTL |
609 RADEON_GMC_BRUSH_SOLID_COLOR |
610 (dev_priv->color_fmt << 8) |
611 RADEON_GMC_SRC_DATATYPE_COLOR |
613 RADEON_GMC_CLR_CMP_CNTL_DIS );
615 if ( dev_priv->page_flipping && dev_priv->current_page == 1 ) {
616 OUT_RING( dev_priv->front_pitch_offset );
618 OUT_RING( dev_priv->back_pitch_offset );
623 OUT_RING( (x << 16) | y );
624 OUT_RING( (w << 16) | h );
629 static void radeon_cp_performance_boxes( drm_radeon_private_t *dev_priv )
631 /* Collapse various things into a wait flag -- trying to
632 * guess if userspase slept -- better just to have them tell us.
634 if (dev_priv->stats.last_frame_reads > 1 ||
635 dev_priv->stats.last_clear_reads > dev_priv->stats.clears) {
636 dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
639 if (dev_priv->stats.freelist_loops) {
640 dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
643 /* Purple box for page flipping
645 if ( dev_priv->stats.boxes & RADEON_BOX_FLIP )
646 radeon_clear_box( dev_priv, 4, 4, 8, 8, 255, 0, 255 );
648 /* Red box if we have to wait for idle at any point
650 if ( dev_priv->stats.boxes & RADEON_BOX_WAIT_IDLE )
651 radeon_clear_box( dev_priv, 16, 4, 8, 8, 255, 0, 0 );
653 /* Blue box: lost context?
656 /* Yellow box for texture swaps
658 if ( dev_priv->stats.boxes & RADEON_BOX_TEXTURE_LOAD )
659 radeon_clear_box( dev_priv, 40, 4, 8, 8, 255, 255, 0 );
661 /* Green box if hardware never idles (as far as we can tell)
663 if ( !(dev_priv->stats.boxes & RADEON_BOX_DMA_IDLE) )
664 radeon_clear_box( dev_priv, 64, 4, 8, 8, 0, 255, 0 );
667 /* Draw bars indicating number of buffers allocated
668 * (not a great measure, easily confused)
670 if (dev_priv->stats.requested_bufs) {
671 if (dev_priv->stats.requested_bufs > 100)
672 dev_priv->stats.requested_bufs = 100;
674 radeon_clear_box( dev_priv, 4, 16,
675 dev_priv->stats.requested_bufs, 4,
679 memset( &dev_priv->stats, 0, sizeof(dev_priv->stats) );
682 /* ================================================================
683 * CP command dispatch functions
686 static void radeon_cp_dispatch_clear( drm_device_t *dev,
687 drm_radeon_clear_t *clear,
688 drm_radeon_clear_rect_t *depth_boxes )
690 drm_radeon_private_t *dev_priv = dev->dev_private;
691 drm_radeon_sarea_t *sarea_priv = dev_priv->sarea_priv;
692 drm_radeon_depth_clear_t *depth_clear = &dev_priv->depth_clear;
693 int nbox = sarea_priv->nbox;
694 drm_clip_rect_t *pbox = sarea_priv->boxes;
695 unsigned int flags = clear->flags;
696 u32 rb3d_cntl = 0, rb3d_stencilrefmask= 0;
699 DRM_DEBUG( "flags = 0x%x\n", flags );
701 dev_priv->stats.clears++;
703 if ( dev_priv->page_flipping && dev_priv->current_page == 1 ) {
704 unsigned int tmp = flags;
706 flags &= ~(RADEON_FRONT | RADEON_BACK);
707 if ( tmp & RADEON_FRONT ) flags |= RADEON_BACK;
708 if ( tmp & RADEON_BACK ) flags |= RADEON_FRONT;
711 if ( flags & (RADEON_FRONT | RADEON_BACK) ) {
715 /* Ensure the 3D stream is idle before doing a
716 * 2D fill to clear the front or back buffer.
718 RADEON_WAIT_UNTIL_3D_IDLE();
720 OUT_RING( CP_PACKET0( RADEON_DP_WRITE_MASK, 0 ) );
721 OUT_RING( clear->color_mask );
725 /* Make sure we restore the 3D state next time.
727 dev_priv->sarea_priv->ctx_owner = 0;
729 for ( i = 0 ; i < nbox ; i++ ) {
732 int w = pbox[i].x2 - x;
733 int h = pbox[i].y2 - y;
735 DRM_DEBUG( "dispatch clear %d,%d-%d,%d flags 0x%x\n",
738 if ( flags & RADEON_FRONT ) {
741 OUT_RING( CP_PACKET3( RADEON_CNTL_PAINT_MULTI, 4 ) );
742 OUT_RING( RADEON_GMC_DST_PITCH_OFFSET_CNTL |
743 RADEON_GMC_BRUSH_SOLID_COLOR |
744 (dev_priv->color_fmt << 8) |
745 RADEON_GMC_SRC_DATATYPE_COLOR |
747 RADEON_GMC_CLR_CMP_CNTL_DIS );
749 OUT_RING( dev_priv->front_pitch_offset );
750 OUT_RING( clear->clear_color );
752 OUT_RING( (x << 16) | y );
753 OUT_RING( (w << 16) | h );
758 if ( flags & RADEON_BACK ) {
761 OUT_RING( CP_PACKET3( RADEON_CNTL_PAINT_MULTI, 4 ) );
762 OUT_RING( RADEON_GMC_DST_PITCH_OFFSET_CNTL |
763 RADEON_GMC_BRUSH_SOLID_COLOR |
764 (dev_priv->color_fmt << 8) |
765 RADEON_GMC_SRC_DATATYPE_COLOR |
767 RADEON_GMC_CLR_CMP_CNTL_DIS );
769 OUT_RING( dev_priv->back_pitch_offset );
770 OUT_RING( clear->clear_color );
772 OUT_RING( (x << 16) | y );
773 OUT_RING( (w << 16) | h );
780 /* We have to clear the depth and/or stencil buffers by
781 * rendering a quad into just those buffers. Thus, we have to
782 * make sure the 3D engine is configured correctly.
784 if ( dev_priv->is_r200 &&
785 (flags & (RADEON_DEPTH | RADEON_STENCIL)) ) {
790 int tempRB3D_ZSTENCILCNTL;
791 int tempRB3D_STENCILREFMASK;
792 int tempRB3D_PLANEMASK;
795 int tempSE_VTX_FMT_0;
796 int tempSE_VTX_FMT_1;
798 int tempRE_AUX_SCISSOR_CNTL;
803 tempRB3D_CNTL = depth_clear->rb3d_cntl;
804 tempRB3D_CNTL &= ~(1<<15); /* unset radeon magic flag */
806 tempRB3D_ZSTENCILCNTL = depth_clear->rb3d_zstencilcntl;
807 tempRB3D_STENCILREFMASK = 0x0;
809 tempSE_CNTL = depth_clear->se_cntl;
815 tempSE_VAP_CNTL = (/* SE_VAP_CNTL__FORCE_W_TO_ONE_MASK | */
816 (0x9 << SE_VAP_CNTL__VF_MAX_VTX_NUM__SHIFT));
818 tempRB3D_PLANEMASK = 0x0;
820 tempRE_AUX_SCISSOR_CNTL = 0x0;
823 SE_VTE_CNTL__VTX_XY_FMT_MASK |
824 SE_VTE_CNTL__VTX_Z_FMT_MASK;
826 /* Vertex format (X, Y, Z, W)*/
828 SE_VTX_FMT_0__VTX_Z0_PRESENT_MASK |
829 SE_VTX_FMT_0__VTX_W0_PRESENT_MASK;
830 tempSE_VTX_FMT_1 = 0x0;
834 * Depth buffer specific enables
836 if (flags & RADEON_DEPTH) {
837 /* Enable depth buffer */
838 tempRB3D_CNTL |= RADEON_Z_ENABLE;
840 /* Disable depth buffer */
841 tempRB3D_CNTL &= ~RADEON_Z_ENABLE;
845 * Stencil buffer specific enables
847 if ( flags & RADEON_STENCIL ) {
848 tempRB3D_CNTL |= RADEON_STENCIL_ENABLE;
849 tempRB3D_STENCILREFMASK = clear->depth_mask;
851 tempRB3D_CNTL &= ~RADEON_STENCIL_ENABLE;
852 tempRB3D_STENCILREFMASK = 0x00000000;
856 RADEON_WAIT_UNTIL_2D_IDLE();
858 OUT_RING_REG( RADEON_PP_CNTL, tempPP_CNTL );
859 OUT_RING_REG( R200_RE_CNTL, tempRE_CNTL );
860 OUT_RING_REG( RADEON_RB3D_CNTL, tempRB3D_CNTL );
861 OUT_RING_REG( RADEON_RB3D_ZSTENCILCNTL,
862 tempRB3D_ZSTENCILCNTL );
863 OUT_RING_REG( RADEON_RB3D_STENCILREFMASK,
864 tempRB3D_STENCILREFMASK );
865 OUT_RING_REG( RADEON_RB3D_PLANEMASK, tempRB3D_PLANEMASK );
866 OUT_RING_REG( RADEON_SE_CNTL, tempSE_CNTL );
867 OUT_RING_REG( R200_SE_VTE_CNTL, tempSE_VTE_CNTL );
868 OUT_RING_REG( R200_SE_VTX_FMT_0, tempSE_VTX_FMT_0 );
869 OUT_RING_REG( R200_SE_VTX_FMT_1, tempSE_VTX_FMT_1 );
870 OUT_RING_REG( R200_SE_VAP_CNTL, tempSE_VAP_CNTL );
871 OUT_RING_REG( R200_RE_AUX_SCISSOR_CNTL,
872 tempRE_AUX_SCISSOR_CNTL );
875 /* Make sure we restore the 3D state next time.
877 dev_priv->sarea_priv->ctx_owner = 0;
879 for ( i = 0 ; i < nbox ; i++ ) {
881 /* Funny that this should be required --
884 radeon_emit_clip_rect( dev_priv,
885 &sarea_priv->boxes[i] );
888 OUT_RING( CP_PACKET3( R200_3D_DRAW_IMMD_2, 12 ) );
889 OUT_RING( (RADEON_PRIM_TYPE_RECT_LIST |
890 RADEON_PRIM_WALK_RING |
891 (3 << RADEON_NUM_VERTICES_SHIFT)) );
892 OUT_RING( depth_boxes[i].ui[CLEAR_X1] );
893 OUT_RING( depth_boxes[i].ui[CLEAR_Y1] );
894 OUT_RING( depth_boxes[i].ui[CLEAR_DEPTH] );
895 OUT_RING( 0x3f800000 );
896 OUT_RING( depth_boxes[i].ui[CLEAR_X1] );
897 OUT_RING( depth_boxes[i].ui[CLEAR_Y2] );
898 OUT_RING( depth_boxes[i].ui[CLEAR_DEPTH] );
899 OUT_RING( 0x3f800000 );
900 OUT_RING( depth_boxes[i].ui[CLEAR_X2] );
901 OUT_RING( depth_boxes[i].ui[CLEAR_Y2] );
902 OUT_RING( depth_boxes[i].ui[CLEAR_DEPTH] );
903 OUT_RING( 0x3f800000 );
907 else if ( (flags & (RADEON_DEPTH | RADEON_STENCIL)) ) {
909 rb3d_cntl = depth_clear->rb3d_cntl;
911 if ( flags & RADEON_DEPTH ) {
912 rb3d_cntl |= RADEON_Z_ENABLE;
914 rb3d_cntl &= ~RADEON_Z_ENABLE;
917 if ( flags & RADEON_STENCIL ) {
918 rb3d_cntl |= RADEON_STENCIL_ENABLE;
919 rb3d_stencilrefmask = clear->depth_mask; /* misnamed field */
921 rb3d_cntl &= ~RADEON_STENCIL_ENABLE;
922 rb3d_stencilrefmask = 0x00000000;
926 RADEON_WAIT_UNTIL_2D_IDLE();
928 OUT_RING( CP_PACKET0( RADEON_PP_CNTL, 1 ) );
929 OUT_RING( 0x00000000 );
930 OUT_RING( rb3d_cntl );
932 OUT_RING_REG( RADEON_RB3D_ZSTENCILCNTL,
933 depth_clear->rb3d_zstencilcntl );
934 OUT_RING_REG( RADEON_RB3D_STENCILREFMASK,
935 rb3d_stencilrefmask );
936 OUT_RING_REG( RADEON_RB3D_PLANEMASK,
938 OUT_RING_REG( RADEON_SE_CNTL,
939 depth_clear->se_cntl );
942 /* Make sure we restore the 3D state next time.
944 dev_priv->sarea_priv->ctx_owner = 0;
946 for ( i = 0 ; i < nbox ; i++ ) {
948 /* Funny that this should be required --
951 radeon_emit_clip_rect( dev_priv,
952 &sarea_priv->boxes[i] );
956 OUT_RING( CP_PACKET3( RADEON_3D_DRAW_IMMD, 13 ) );
957 OUT_RING( RADEON_VTX_Z_PRESENT |
958 RADEON_VTX_PKCOLOR_PRESENT);
959 OUT_RING( (RADEON_PRIM_TYPE_RECT_LIST |
960 RADEON_PRIM_WALK_RING |
962 RADEON_VTX_FMT_RADEON_MODE |
963 (3 << RADEON_NUM_VERTICES_SHIFT)) );
966 OUT_RING( depth_boxes[i].ui[CLEAR_X1] );
967 OUT_RING( depth_boxes[i].ui[CLEAR_Y1] );
968 OUT_RING( depth_boxes[i].ui[CLEAR_DEPTH] );
971 OUT_RING( depth_boxes[i].ui[CLEAR_X1] );
972 OUT_RING( depth_boxes[i].ui[CLEAR_Y2] );
973 OUT_RING( depth_boxes[i].ui[CLEAR_DEPTH] );
976 OUT_RING( depth_boxes[i].ui[CLEAR_X2] );
977 OUT_RING( depth_boxes[i].ui[CLEAR_Y2] );
978 OUT_RING( depth_boxes[i].ui[CLEAR_DEPTH] );
985 /* Increment the clear counter. The client-side 3D driver must
986 * wait on this value before performing the clear ioctl. We
987 * need this because the card's so damned fast...
989 dev_priv->sarea_priv->last_clear++;
993 RADEON_CLEAR_AGE( dev_priv->sarea_priv->last_clear );
994 RADEON_WAIT_UNTIL_IDLE();
999 static void radeon_cp_dispatch_swap( drm_device_t *dev )
1001 drm_radeon_private_t *dev_priv = dev->dev_private;
1002 drm_radeon_sarea_t *sarea_priv = dev_priv->sarea_priv;
1003 int nbox = sarea_priv->nbox;
1004 drm_clip_rect_t *pbox = sarea_priv->boxes;
1009 /* Do some trivial performance monitoring...
1011 if (dev_priv->do_boxes)
1012 radeon_cp_performance_boxes( dev_priv );
1015 /* Wait for the 3D stream to idle before dispatching the bitblt.
1016 * This will prevent data corruption between the two streams.
1020 RADEON_WAIT_UNTIL_3D_IDLE();
1024 for ( i = 0 ; i < nbox ; i++ ) {
1027 int w = pbox[i].x2 - x;
1028 int h = pbox[i].y2 - y;
1030 DRM_DEBUG( "dispatch swap %d,%d-%d,%d\n",
1035 OUT_RING( CP_PACKET3( RADEON_CNTL_BITBLT_MULTI, 5 ) );
1036 OUT_RING( RADEON_GMC_SRC_PITCH_OFFSET_CNTL |
1037 RADEON_GMC_DST_PITCH_OFFSET_CNTL |
1038 RADEON_GMC_BRUSH_NONE |
1039 (dev_priv->color_fmt << 8) |
1040 RADEON_GMC_SRC_DATATYPE_COLOR |
1042 RADEON_DP_SRC_SOURCE_MEMORY |
1043 RADEON_GMC_CLR_CMP_CNTL_DIS |
1044 RADEON_GMC_WR_MSK_DIS );
1046 /* Make this work even if front & back are flipped:
1048 if (dev_priv->current_page == 0) {
1049 OUT_RING( dev_priv->back_pitch_offset );
1050 OUT_RING( dev_priv->front_pitch_offset );
1053 OUT_RING( dev_priv->front_pitch_offset );
1054 OUT_RING( dev_priv->back_pitch_offset );
1057 OUT_RING( (x << 16) | y );
1058 OUT_RING( (x << 16) | y );
1059 OUT_RING( (w << 16) | h );
1064 /* Increment the frame counter. The client-side 3D driver must
1065 * throttle the framerate by waiting for this value before
1066 * performing the swapbuffer ioctl.
1068 dev_priv->sarea_priv->last_frame++;
1072 RADEON_FRAME_AGE( dev_priv->sarea_priv->last_frame );
1073 RADEON_WAIT_UNTIL_2D_IDLE();
1078 static void radeon_cp_dispatch_flip( drm_device_t *dev )
1080 drm_radeon_private_t *dev_priv = dev->dev_private;
1081 drm_sarea_t *sarea = (drm_sarea_t *)dev_priv->sarea->handle;
1082 int offset = (dev_priv->current_page == 1)
1083 ? dev_priv->front_offset : dev_priv->back_offset;
1085 DRM_DEBUG( "%s: page=%d pfCurrentPage=%d\n",
1087 dev_priv->current_page,
1088 dev_priv->sarea_priv->pfCurrentPage);
1090 /* Do some trivial performance monitoring...
1092 if (dev_priv->do_boxes) {
1093 dev_priv->stats.boxes |= RADEON_BOX_FLIP;
1094 radeon_cp_performance_boxes( dev_priv );
1097 /* Update the frame offsets for both CRTCs
1101 RADEON_WAIT_UNTIL_3D_IDLE();
1102 OUT_RING_REG( RADEON_CRTC_OFFSET, ( ( sarea->frame.y * dev_priv->front_pitch
1104 * ( dev_priv->color_fmt - 2 ) ) & ~7 )
1106 OUT_RING_REG( RADEON_CRTC2_OFFSET, dev_priv->sarea_priv->crtc2_base
1111 /* Increment the frame counter. The client-side 3D driver must
1112 * throttle the framerate by waiting for this value before
1113 * performing the swapbuffer ioctl.
1115 dev_priv->sarea_priv->last_frame++;
1116 dev_priv->sarea_priv->pfCurrentPage = dev_priv->current_page =
1117 1 - dev_priv->current_page;
1121 RADEON_FRAME_AGE( dev_priv->sarea_priv->last_frame );
1126 static int bad_prim_vertex_nr( int primitive, int nr )
1128 switch (primitive & RADEON_PRIM_TYPE_MASK) {
1129 case RADEON_PRIM_TYPE_NONE:
1130 case RADEON_PRIM_TYPE_POINT:
1132 case RADEON_PRIM_TYPE_LINE:
1133 return (nr & 1) || nr == 0;
1134 case RADEON_PRIM_TYPE_LINE_STRIP:
1136 case RADEON_PRIM_TYPE_TRI_LIST:
1137 case RADEON_PRIM_TYPE_3VRT_POINT_LIST:
1138 case RADEON_PRIM_TYPE_3VRT_LINE_LIST:
1139 case RADEON_PRIM_TYPE_RECT_LIST:
1140 return nr % 3 || nr == 0;
1141 case RADEON_PRIM_TYPE_TRI_FAN:
1142 case RADEON_PRIM_TYPE_TRI_STRIP:
1153 unsigned int finish;
1155 unsigned int numverts;
1156 unsigned int offset;
1157 unsigned int vc_format;
1158 } drm_radeon_tcl_prim_t;
1160 static void radeon_cp_dispatch_vertex( drm_device_t *dev,
1162 drm_radeon_tcl_prim_t *prim )
1165 drm_radeon_private_t *dev_priv = dev->dev_private;
1166 drm_radeon_sarea_t *sarea_priv = dev_priv->sarea_priv;
1167 int offset = dev_priv->gart_buffers_offset + buf->offset + prim->start;
1168 int numverts = (int)prim->numverts;
1169 int nbox = sarea_priv->nbox;
1173 DRM_DEBUG("hwprim 0x%x vfmt 0x%x %d..%d %d verts\n",
1180 if (bad_prim_vertex_nr( prim->prim, prim->numverts )) {
1181 DRM_ERROR( "bad prim %x numverts %d\n",
1182 prim->prim, prim->numverts );
1187 /* Emit the next cliprect */
1189 radeon_emit_clip_rect( dev_priv,
1190 &sarea_priv->boxes[i] );
1193 /* Emit the vertex buffer rendering commands */
1196 OUT_RING( CP_PACKET3( RADEON_3D_RNDR_GEN_INDX_PRIM, 3 ) );
1198 OUT_RING( numverts );
1199 OUT_RING( prim->vc_format );
1200 OUT_RING( prim->prim | RADEON_PRIM_WALK_LIST |
1201 RADEON_COLOR_ORDER_RGBA |
1202 RADEON_VTX_FMT_RADEON_MODE |
1203 (numverts << RADEON_NUM_VERTICES_SHIFT) );
1208 } while ( i < nbox );
1213 static void radeon_cp_discard_buffer( drm_device_t *dev, drm_buf_t *buf )
1215 drm_radeon_private_t *dev_priv = dev->dev_private;
1216 drm_radeon_buf_priv_t *buf_priv = buf->dev_private;
1219 buf_priv->age = ++dev_priv->sarea_priv->last_dispatch;
1221 /* Emit the vertex buffer age */
1223 RADEON_DISPATCH_AGE( buf_priv->age );
1230 static void radeon_cp_dispatch_indirect( drm_device_t *dev,
1232 int start, int end )
1234 drm_radeon_private_t *dev_priv = dev->dev_private;
1236 DRM_DEBUG( "indirect: buf=%d s=0x%x e=0x%x\n",
1237 buf->idx, start, end );
1239 if ( start != end ) {
1240 int offset = (dev_priv->gart_buffers_offset
1241 + buf->offset + start);
1242 int dwords = (end - start + 3) / sizeof(u32);
1244 /* Indirect buffer data must be an even number of
1245 * dwords, so if we've been given an odd number we must
1246 * pad the data with a Type-2 CP packet.
1250 ((char *)dev_priv->buffers->handle
1251 + buf->offset + start);
1252 data[dwords++] = RADEON_CP_PACKET2;
1255 /* Fire off the indirect buffer */
1258 OUT_RING( CP_PACKET0( RADEON_CP_IB_BASE, 1 ) );
1267 static void radeon_cp_dispatch_indices( drm_device_t *dev,
1269 drm_radeon_tcl_prim_t *prim )
1271 drm_radeon_private_t *dev_priv = dev->dev_private;
1272 drm_radeon_sarea_t *sarea_priv = dev_priv->sarea_priv;
1273 int offset = dev_priv->gart_buffers_offset + prim->offset;
1277 int start = prim->start + RADEON_INDEX_PRIM_OFFSET;
1278 int count = (prim->finish - start) / sizeof(u16);
1279 int nbox = sarea_priv->nbox;
1281 DRM_DEBUG("hwprim 0x%x vfmt 0x%x %d..%d offset: %x nr %d\n",
1289 if (bad_prim_vertex_nr( prim->prim, count )) {
1290 DRM_ERROR( "bad prim %x count %d\n",
1291 prim->prim, count );
1296 if ( start >= prim->finish ||
1297 (prim->start & 0x7) ) {
1298 DRM_ERROR( "buffer prim %d\n", prim->prim );
1302 dwords = (prim->finish - prim->start + 3) / sizeof(u32);
1304 data = (u32 *)((char *)dev_priv->buffers->handle +
1305 elt_buf->offset + prim->start);
1307 data[0] = CP_PACKET3( RADEON_3D_RNDR_GEN_INDX_PRIM, dwords-2 );
1309 data[2] = prim->numverts;
1310 data[3] = prim->vc_format;
1311 data[4] = (prim->prim |
1312 RADEON_PRIM_WALK_IND |
1313 RADEON_COLOR_ORDER_RGBA |
1314 RADEON_VTX_FMT_RADEON_MODE |
1315 (count << RADEON_NUM_VERTICES_SHIFT) );
1319 radeon_emit_clip_rect( dev_priv,
1320 &sarea_priv->boxes[i] );
1322 radeon_cp_dispatch_indirect( dev, elt_buf,
1327 } while ( i < nbox );
1331 #define RADEON_MAX_TEXTURE_SIZE (RADEON_BUFFER_SIZE - 8 * sizeof(u32))
1333 static int radeon_cp_dispatch_texture( DRMFILE filp,
1335 drm_radeon_texture_t *tex,
1336 drm_radeon_tex_image_t *image )
1338 drm_radeon_private_t *dev_priv = dev->dev_private;
1339 drm_file_t *filp_priv;
1343 const u8 __user *data;
1344 int size, dwords, tex_width, blit_width;
1349 DRM_GET_PRIV_WITH_RETURN( filp_priv, filp );
1351 if ( radeon_check_and_fixup_offset( dev_priv, filp_priv, &tex->offset ) ) {
1352 DRM_ERROR( "Invalid destination offset\n" );
1353 return DRM_ERR( EINVAL );
1356 dev_priv->stats.boxes |= RADEON_BOX_TEXTURE_LOAD;
1358 /* Flush the pixel cache. This ensures no pixel data gets mixed
1359 * up with the texture data from the host data blit, otherwise
1360 * part of the texture image may be corrupted.
1363 RADEON_FLUSH_CACHE();
1364 RADEON_WAIT_UNTIL_IDLE();
1368 /* The Mesa texture functions provide the data in little endian as the
1369 * chip wants it, but we need to compensate for the fact that the CP
1370 * ring gets byte-swapped
1373 OUT_RING_REG( RADEON_RBBM_GUICNTL, RADEON_HOST_DATA_SWAP_32BIT );
1378 /* The compiler won't optimize away a division by a variable,
1379 * even if the only legal values are powers of two. Thus, we'll
1380 * use a shift instead.
1382 switch ( tex->format ) {
1383 case RADEON_TXFORMAT_ARGB8888:
1384 case RADEON_TXFORMAT_RGBA8888:
1385 format = RADEON_COLOR_FORMAT_ARGB8888;
1386 tex_width = tex->width * 4;
1387 blit_width = image->width * 4;
1389 case RADEON_TXFORMAT_AI88:
1390 case RADEON_TXFORMAT_ARGB1555:
1391 case RADEON_TXFORMAT_RGB565:
1392 case RADEON_TXFORMAT_ARGB4444:
1393 case RADEON_TXFORMAT_VYUY422:
1394 case RADEON_TXFORMAT_YVYU422:
1395 format = RADEON_COLOR_FORMAT_RGB565;
1396 tex_width = tex->width * 2;
1397 blit_width = image->width * 2;
1399 case RADEON_TXFORMAT_I8:
1400 case RADEON_TXFORMAT_RGB332:
1401 format = RADEON_COLOR_FORMAT_CI8;
1402 tex_width = tex->width * 1;
1403 blit_width = image->width * 1;
1406 DRM_ERROR( "invalid texture format %d\n", tex->format );
1407 return DRM_ERR(EINVAL);
1410 DRM_DEBUG("tex=%dx%d blit=%d\n", tex_width, tex->height, blit_width );
1413 DRM_DEBUG( "tex: ofs=0x%x p=%d f=%d x=%hd y=%hd w=%hd h=%hd\n",
1414 tex->offset >> 10, tex->pitch, tex->format,
1415 image->x, image->y, image->width, image->height );
1417 /* Make a copy of some parameters in case we have to
1418 * update them for a multi-pass texture blit.
1420 height = image->height;
1421 data = (const u8 __user *)image->data;
1423 size = height * blit_width;
1425 if ( size > RADEON_MAX_TEXTURE_SIZE ) {
1426 height = RADEON_MAX_TEXTURE_SIZE / blit_width;
1427 size = height * blit_width;
1428 } else if ( size < 4 && size > 0 ) {
1430 } else if ( size == 0 ) {
1434 buf = radeon_freelist_get( dev );
1436 radeon_do_cp_idle( dev_priv );
1437 buf = radeon_freelist_get( dev );
1440 DRM_DEBUG("radeon_cp_dispatch_texture: EAGAIN\n");
1441 DRM_COPY_TO_USER( tex->image, image, sizeof(*image) );
1442 return DRM_ERR(EAGAIN);
1446 /* Dispatch the indirect buffer.
1448 buffer = (u32*)((char*)dev_priv->buffers->handle + buf->offset);
1450 buffer[0] = CP_PACKET3( RADEON_CNTL_HOSTDATA_BLT, dwords + 6 );
1451 buffer[1] = (RADEON_GMC_DST_PITCH_OFFSET_CNTL |
1452 RADEON_GMC_BRUSH_NONE |
1454 RADEON_GMC_SRC_DATATYPE_COLOR |
1456 RADEON_DP_SRC_SOURCE_HOST_DATA |
1457 RADEON_GMC_CLR_CMP_CNTL_DIS |
1458 RADEON_GMC_WR_MSK_DIS);
1460 buffer[2] = (tex->pitch << 22) | (tex->offset >> 10);
1461 buffer[3] = 0xffffffff;
1462 buffer[4] = 0xffffffff;
1463 buffer[5] = (image->y << 16) | image->x;
1464 buffer[6] = (height << 16) | image->width;
1468 if ( tex_width >= 32 ) {
1469 /* Texture image width is larger than the minimum, so we
1470 * can upload it directly.
1472 if ( DRM_COPY_FROM_USER( buffer, data,
1473 dwords * sizeof(u32) ) ) {
1474 DRM_ERROR( "EFAULT on data, %d dwords\n",
1476 return DRM_ERR(EFAULT);
1479 /* Texture image width is less than the minimum, so we
1480 * need to pad out each image scanline to the minimum
1483 for ( i = 0 ; i < tex->height ; i++ ) {
1484 if ( DRM_COPY_FROM_USER( buffer, data,
1486 DRM_ERROR( "EFAULT on pad, %d bytes\n",
1488 return DRM_ERR(EFAULT);
1496 buf->used = (dwords + 8) * sizeof(u32);
1497 radeon_cp_dispatch_indirect( dev, buf, 0, buf->used );
1498 radeon_cp_discard_buffer( dev, buf );
1500 /* Update the input parameters for next time */
1502 image->height -= height;
1503 image->data = (const u8 __user *)image->data + size;
1504 } while (image->height > 0);
1506 /* Flush the pixel cache after the blit completes. This ensures
1507 * the texture data is written out to memory before rendering
1511 RADEON_FLUSH_CACHE();
1512 RADEON_WAIT_UNTIL_2D_IDLE();
1518 static void radeon_cp_dispatch_stipple( drm_device_t *dev, u32 *stipple )
1520 drm_radeon_private_t *dev_priv = dev->dev_private;
1527 OUT_RING( CP_PACKET0( RADEON_RE_STIPPLE_ADDR, 0 ) );
1528 OUT_RING( 0x00000000 );
1530 OUT_RING( CP_PACKET0_TABLE( RADEON_RE_STIPPLE_DATA, 31 ) );
1531 for ( i = 0 ; i < 32 ; i++ ) {
1532 OUT_RING( stipple[i] );
1539 /* ================================================================
1543 int radeon_cp_clear( DRM_IOCTL_ARGS )
1546 drm_radeon_private_t *dev_priv = dev->dev_private;
1547 drm_radeon_sarea_t *sarea_priv = dev_priv->sarea_priv;
1548 drm_radeon_clear_t clear;
1549 drm_radeon_clear_rect_t depth_boxes[RADEON_NR_SAREA_CLIPRECTS];
1552 LOCK_TEST_WITH_RETURN( dev, filp );
1554 DRM_COPY_FROM_USER_IOCTL( clear, (drm_radeon_clear_t __user *)data,
1557 RING_SPACE_TEST_WITH_RETURN( dev_priv );
1559 if ( sarea_priv->nbox > RADEON_NR_SAREA_CLIPRECTS )
1560 sarea_priv->nbox = RADEON_NR_SAREA_CLIPRECTS;
1562 if ( DRM_COPY_FROM_USER( &depth_boxes, clear.depth_boxes,
1563 sarea_priv->nbox * sizeof(depth_boxes[0]) ) )
1564 return DRM_ERR(EFAULT);
1566 radeon_cp_dispatch_clear( dev, &clear, depth_boxes );
1573 /* Not sure why this isn't set all the time:
1575 static int radeon_do_init_pageflip( drm_device_t *dev )
1577 drm_radeon_private_t *dev_priv = dev->dev_private;
1583 RADEON_WAIT_UNTIL_3D_IDLE();
1584 OUT_RING( CP_PACKET0( RADEON_CRTC_OFFSET_CNTL, 0 ) );
1585 OUT_RING( RADEON_READ( RADEON_CRTC_OFFSET_CNTL ) | RADEON_CRTC_OFFSET_FLIP_CNTL );
1586 OUT_RING( CP_PACKET0( RADEON_CRTC2_OFFSET_CNTL, 0 ) );
1587 OUT_RING( RADEON_READ( RADEON_CRTC2_OFFSET_CNTL ) | RADEON_CRTC_OFFSET_FLIP_CNTL );
1590 dev_priv->page_flipping = 1;
1591 dev_priv->current_page = 0;
1592 dev_priv->sarea_priv->pfCurrentPage = dev_priv->current_page;
1597 /* Called whenever a client dies, from DRM(release).
1598 * NOTE: Lock isn't necessarily held when this is called!
1600 int radeon_do_cleanup_pageflip( drm_device_t *dev )
1602 drm_radeon_private_t *dev_priv = dev->dev_private;
1605 if (dev_priv->current_page != 0)
1606 radeon_cp_dispatch_flip( dev );
1608 dev_priv->page_flipping = 0;
1612 /* Swapping and flipping are different operations, need different ioctls.
1613 * They can & should be intermixed to support multiple 3d windows.
1615 int radeon_cp_flip( DRM_IOCTL_ARGS )
1618 drm_radeon_private_t *dev_priv = dev->dev_private;
1621 LOCK_TEST_WITH_RETURN( dev, filp );
1623 RING_SPACE_TEST_WITH_RETURN( dev_priv );
1625 if (!dev_priv->page_flipping)
1626 radeon_do_init_pageflip( dev );
1628 radeon_cp_dispatch_flip( dev );
1634 int radeon_cp_swap( DRM_IOCTL_ARGS )
1637 drm_radeon_private_t *dev_priv = dev->dev_private;
1638 drm_radeon_sarea_t *sarea_priv = dev_priv->sarea_priv;
1641 LOCK_TEST_WITH_RETURN( dev, filp );
1643 RING_SPACE_TEST_WITH_RETURN( dev_priv );
1645 if ( sarea_priv->nbox > RADEON_NR_SAREA_CLIPRECTS )
1646 sarea_priv->nbox = RADEON_NR_SAREA_CLIPRECTS;
1648 radeon_cp_dispatch_swap( dev );
1649 dev_priv->sarea_priv->ctx_owner = 0;
1655 int radeon_cp_vertex( DRM_IOCTL_ARGS )
1658 drm_radeon_private_t *dev_priv = dev->dev_private;
1659 drm_file_t *filp_priv;
1660 drm_radeon_sarea_t *sarea_priv = dev_priv->sarea_priv;
1661 drm_device_dma_t *dma = dev->dma;
1663 drm_radeon_vertex_t vertex;
1664 drm_radeon_tcl_prim_t prim;
1666 LOCK_TEST_WITH_RETURN( dev, filp );
1669 DRM_ERROR( "%s called with no initialization\n", __FUNCTION__ );
1670 return DRM_ERR(EINVAL);
1673 DRM_GET_PRIV_WITH_RETURN( filp_priv, filp );
1675 DRM_COPY_FROM_USER_IOCTL( vertex, (drm_radeon_vertex_t __user *)data,
1678 DRM_DEBUG( "pid=%d index=%d count=%d discard=%d\n",
1680 vertex.idx, vertex.count, vertex.discard );
1682 if ( vertex.idx < 0 || vertex.idx >= dma->buf_count ) {
1683 DRM_ERROR( "buffer index %d (of %d max)\n",
1684 vertex.idx, dma->buf_count - 1 );
1685 return DRM_ERR(EINVAL);
1687 if ( vertex.prim < 0 ||
1688 vertex.prim > RADEON_PRIM_TYPE_3VRT_LINE_LIST ) {
1689 DRM_ERROR( "buffer prim %d\n", vertex.prim );
1690 return DRM_ERR(EINVAL);
1693 RING_SPACE_TEST_WITH_RETURN( dev_priv );
1694 VB_AGE_TEST_WITH_RETURN( dev_priv );
1696 buf = dma->buflist[vertex.idx];
1698 if ( buf->filp != filp ) {
1699 DRM_ERROR( "process %d using buffer owned by %p\n",
1700 DRM_CURRENTPID, buf->filp );
1701 return DRM_ERR(EINVAL);
1703 if ( buf->pending ) {
1704 DRM_ERROR( "sending pending buffer %d\n", vertex.idx );
1705 return DRM_ERR(EINVAL);
1708 /* Build up a prim_t record:
1711 buf->used = vertex.count; /* not used? */
1713 if ( sarea_priv->dirty & ~RADEON_UPLOAD_CLIPRECTS ) {
1714 if ( radeon_emit_state( dev_priv, filp_priv,
1715 &sarea_priv->context_state,
1716 sarea_priv->tex_state,
1717 sarea_priv->dirty ) ) {
1718 DRM_ERROR( "radeon_emit_state failed\n" );
1719 return DRM_ERR( EINVAL );
1722 sarea_priv->dirty &= ~(RADEON_UPLOAD_TEX0IMAGES |
1723 RADEON_UPLOAD_TEX1IMAGES |
1724 RADEON_UPLOAD_TEX2IMAGES |
1725 RADEON_REQUIRE_QUIESCENCE);
1729 prim.finish = vertex.count; /* unused */
1730 prim.prim = vertex.prim;
1731 prim.numverts = vertex.count;
1732 prim.vc_format = dev_priv->sarea_priv->vc_format;
1734 radeon_cp_dispatch_vertex( dev, buf, &prim );
1737 if (vertex.discard) {
1738 radeon_cp_discard_buffer( dev, buf );
1745 int radeon_cp_indices( DRM_IOCTL_ARGS )
1748 drm_radeon_private_t *dev_priv = dev->dev_private;
1749 drm_file_t *filp_priv;
1750 drm_radeon_sarea_t *sarea_priv = dev_priv->sarea_priv;
1751 drm_device_dma_t *dma = dev->dma;
1753 drm_radeon_indices_t elts;
1754 drm_radeon_tcl_prim_t prim;
1757 LOCK_TEST_WITH_RETURN( dev, filp );
1760 DRM_ERROR( "%s called with no initialization\n", __FUNCTION__ );
1761 return DRM_ERR(EINVAL);
1764 DRM_GET_PRIV_WITH_RETURN( filp_priv, filp );
1766 DRM_COPY_FROM_USER_IOCTL( elts, (drm_radeon_indices_t __user *)data,
1769 DRM_DEBUG( "pid=%d index=%d start=%d end=%d discard=%d\n",
1771 elts.idx, elts.start, elts.end, elts.discard );
1773 if ( elts.idx < 0 || elts.idx >= dma->buf_count ) {
1774 DRM_ERROR( "buffer index %d (of %d max)\n",
1775 elts.idx, dma->buf_count - 1 );
1776 return DRM_ERR(EINVAL);
1778 if ( elts.prim < 0 ||
1779 elts.prim > RADEON_PRIM_TYPE_3VRT_LINE_LIST ) {
1780 DRM_ERROR( "buffer prim %d\n", elts.prim );
1781 return DRM_ERR(EINVAL);
1784 RING_SPACE_TEST_WITH_RETURN( dev_priv );
1785 VB_AGE_TEST_WITH_RETURN( dev_priv );
1787 buf = dma->buflist[elts.idx];
1789 if ( buf->filp != filp ) {
1790 DRM_ERROR( "process %d using buffer owned by %p\n",
1791 DRM_CURRENTPID, buf->filp );
1792 return DRM_ERR(EINVAL);
1794 if ( buf->pending ) {
1795 DRM_ERROR( "sending pending buffer %d\n", elts.idx );
1796 return DRM_ERR(EINVAL);
1799 count = (elts.end - elts.start) / sizeof(u16);
1800 elts.start -= RADEON_INDEX_PRIM_OFFSET;
1802 if ( elts.start & 0x7 ) {
1803 DRM_ERROR( "misaligned buffer 0x%x\n", elts.start );
1804 return DRM_ERR(EINVAL);
1806 if ( elts.start < buf->used ) {
1807 DRM_ERROR( "no header 0x%x - 0x%x\n", elts.start, buf->used );
1808 return DRM_ERR(EINVAL);
1811 buf->used = elts.end;
1813 if ( sarea_priv->dirty & ~RADEON_UPLOAD_CLIPRECTS ) {
1814 if ( radeon_emit_state( dev_priv, filp_priv,
1815 &sarea_priv->context_state,
1816 sarea_priv->tex_state,
1817 sarea_priv->dirty ) ) {
1818 DRM_ERROR( "radeon_emit_state failed\n" );
1819 return DRM_ERR( EINVAL );
1822 sarea_priv->dirty &= ~(RADEON_UPLOAD_TEX0IMAGES |
1823 RADEON_UPLOAD_TEX1IMAGES |
1824 RADEON_UPLOAD_TEX2IMAGES |
1825 RADEON_REQUIRE_QUIESCENCE);
1829 /* Build up a prim_t record:
1831 prim.start = elts.start;
1832 prim.finish = elts.end;
1833 prim.prim = elts.prim;
1834 prim.offset = 0; /* offset from start of dma buffers */
1835 prim.numverts = RADEON_MAX_VB_VERTS; /* duh */
1836 prim.vc_format = dev_priv->sarea_priv->vc_format;
1838 radeon_cp_dispatch_indices( dev, buf, &prim );
1840 radeon_cp_discard_buffer( dev, buf );
1847 int radeon_cp_texture( DRM_IOCTL_ARGS )
1850 drm_radeon_private_t *dev_priv = dev->dev_private;
1851 drm_radeon_texture_t tex;
1852 drm_radeon_tex_image_t image;
1855 LOCK_TEST_WITH_RETURN( dev, filp );
1857 DRM_COPY_FROM_USER_IOCTL( tex, (drm_radeon_texture_t __user *)data, sizeof(tex) );
1859 if ( tex.image == NULL ) {
1860 DRM_ERROR( "null texture image!\n" );
1861 return DRM_ERR(EINVAL);
1864 if ( DRM_COPY_FROM_USER( &image,
1865 (drm_radeon_tex_image_t __user *)tex.image,
1867 return DRM_ERR(EFAULT);
1869 RING_SPACE_TEST_WITH_RETURN( dev_priv );
1870 VB_AGE_TEST_WITH_RETURN( dev_priv );
1872 ret = radeon_cp_dispatch_texture( filp, dev, &tex, &image );
1878 int radeon_cp_stipple( DRM_IOCTL_ARGS )
1881 drm_radeon_private_t *dev_priv = dev->dev_private;
1882 drm_radeon_stipple_t stipple;
1885 LOCK_TEST_WITH_RETURN( dev, filp );
1887 DRM_COPY_FROM_USER_IOCTL( stipple, (drm_radeon_stipple_t __user *)data,
1890 if ( DRM_COPY_FROM_USER( &mask, stipple.mask, 32 * sizeof(u32) ) )
1891 return DRM_ERR(EFAULT);
1893 RING_SPACE_TEST_WITH_RETURN( dev_priv );
1895 radeon_cp_dispatch_stipple( dev, mask );
1901 int radeon_cp_indirect( DRM_IOCTL_ARGS )
1904 drm_radeon_private_t *dev_priv = dev->dev_private;
1905 drm_device_dma_t *dma = dev->dma;
1907 drm_radeon_indirect_t indirect;
1910 LOCK_TEST_WITH_RETURN( dev, filp );
1913 DRM_ERROR( "%s called with no initialization\n", __FUNCTION__ );
1914 return DRM_ERR(EINVAL);
1917 DRM_COPY_FROM_USER_IOCTL( indirect, (drm_radeon_indirect_t __user *)data,
1920 DRM_DEBUG( "indirect: idx=%d s=%d e=%d d=%d\n",
1921 indirect.idx, indirect.start,
1922 indirect.end, indirect.discard );
1924 if ( indirect.idx < 0 || indirect.idx >= dma->buf_count ) {
1925 DRM_ERROR( "buffer index %d (of %d max)\n",
1926 indirect.idx, dma->buf_count - 1 );
1927 return DRM_ERR(EINVAL);
1930 buf = dma->buflist[indirect.idx];
1932 if ( buf->filp != filp ) {
1933 DRM_ERROR( "process %d using buffer owned by %p\n",
1934 DRM_CURRENTPID, buf->filp );
1935 return DRM_ERR(EINVAL);
1937 if ( buf->pending ) {
1938 DRM_ERROR( "sending pending buffer %d\n", indirect.idx );
1939 return DRM_ERR(EINVAL);
1942 if ( indirect.start < buf->used ) {
1943 DRM_ERROR( "reusing indirect: start=0x%x actual=0x%x\n",
1944 indirect.start, buf->used );
1945 return DRM_ERR(EINVAL);
1948 RING_SPACE_TEST_WITH_RETURN( dev_priv );
1949 VB_AGE_TEST_WITH_RETURN( dev_priv );
1951 buf->used = indirect.end;
1953 /* Wait for the 3D stream to idle before the indirect buffer
1954 * containing 2D acceleration commands is processed.
1958 RADEON_WAIT_UNTIL_3D_IDLE();
1962 /* Dispatch the indirect buffer full of commands from the
1963 * X server. This is insecure and is thus only available to
1964 * privileged clients.
1966 radeon_cp_dispatch_indirect( dev, buf, indirect.start, indirect.end );
1967 if (indirect.discard) {
1968 radeon_cp_discard_buffer( dev, buf );
1976 int radeon_cp_vertex2( DRM_IOCTL_ARGS )
1979 drm_radeon_private_t *dev_priv = dev->dev_private;
1980 drm_file_t *filp_priv;
1981 drm_radeon_sarea_t *sarea_priv = dev_priv->sarea_priv;
1982 drm_device_dma_t *dma = dev->dma;
1984 drm_radeon_vertex2_t vertex;
1986 unsigned char laststate;
1988 LOCK_TEST_WITH_RETURN( dev, filp );
1991 DRM_ERROR( "%s called with no initialization\n", __FUNCTION__ );
1992 return DRM_ERR(EINVAL);
1995 DRM_GET_PRIV_WITH_RETURN( filp_priv, filp );
1997 DRM_COPY_FROM_USER_IOCTL( vertex, (drm_radeon_vertex2_t __user *)data,
2000 DRM_DEBUG( "pid=%d index=%d discard=%d\n",
2002 vertex.idx, vertex.discard );
2004 if ( vertex.idx < 0 || vertex.idx >= dma->buf_count ) {
2005 DRM_ERROR( "buffer index %d (of %d max)\n",
2006 vertex.idx, dma->buf_count - 1 );
2007 return DRM_ERR(EINVAL);
2010 RING_SPACE_TEST_WITH_RETURN( dev_priv );
2011 VB_AGE_TEST_WITH_RETURN( dev_priv );
2013 buf = dma->buflist[vertex.idx];
2015 if ( buf->filp != filp ) {
2016 DRM_ERROR( "process %d using buffer owned by %p\n",
2017 DRM_CURRENTPID, buf->filp );
2018 return DRM_ERR(EINVAL);
2021 if ( buf->pending ) {
2022 DRM_ERROR( "sending pending buffer %d\n", vertex.idx );
2023 return DRM_ERR(EINVAL);
2026 if (sarea_priv->nbox > RADEON_NR_SAREA_CLIPRECTS)
2027 return DRM_ERR(EINVAL);
2029 for (laststate = 0xff, i = 0 ; i < vertex.nr_prims ; i++) {
2030 drm_radeon_prim_t prim;
2031 drm_radeon_tcl_prim_t tclprim;
2033 if ( DRM_COPY_FROM_USER( &prim, &vertex.prim[i], sizeof(prim) ) )
2034 return DRM_ERR(EFAULT);
2036 if ( prim.stateidx != laststate ) {
2037 drm_radeon_state_t state;
2039 if ( DRM_COPY_FROM_USER( &state,
2040 &vertex.state[prim.stateidx],
2042 return DRM_ERR(EFAULT);
2044 if ( radeon_emit_state2( dev_priv, filp_priv, &state ) ) {
2045 DRM_ERROR( "radeon_emit_state2 failed\n" );
2046 return DRM_ERR( EINVAL );
2049 laststate = prim.stateidx;
2052 tclprim.start = prim.start;
2053 tclprim.finish = prim.finish;
2054 tclprim.prim = prim.prim;
2055 tclprim.vc_format = prim.vc_format;
2057 if ( prim.prim & RADEON_PRIM_WALK_IND ) {
2058 tclprim.offset = prim.numverts * 64;
2059 tclprim.numverts = RADEON_MAX_VB_VERTS; /* duh */
2061 radeon_cp_dispatch_indices( dev, buf, &tclprim );
2063 tclprim.numverts = prim.numverts;
2064 tclprim.offset = 0; /* not used */
2066 radeon_cp_dispatch_vertex( dev, buf, &tclprim );
2069 if (sarea_priv->nbox == 1)
2070 sarea_priv->nbox = 0;
2073 if ( vertex.discard ) {
2074 radeon_cp_discard_buffer( dev, buf );
2082 static int radeon_emit_packets(
2083 drm_radeon_private_t *dev_priv,
2084 drm_file_t *filp_priv,
2085 drm_radeon_cmd_header_t header,
2086 drm_radeon_cmd_buffer_t *cmdbuf )
2088 int id = (int)header.packet.packet_id;
2090 int __user *data = (int __user *)cmdbuf->buf;
2093 if (id >= RADEON_MAX_STATE_PACKETS)
2094 return DRM_ERR(EINVAL);
2096 sz = packet[id].len;
2097 reg = packet[id].start;
2099 if (sz * sizeof(int) > cmdbuf->bufsz) {
2100 DRM_ERROR( "Packet size provided larger than data provided\n" );
2101 return DRM_ERR(EINVAL);
2104 if ( radeon_check_and_fixup_packets( dev_priv, filp_priv, id, data ) ) {
2105 DRM_ERROR( "Packet verification failed\n" );
2106 return DRM_ERR( EINVAL );
2110 OUT_RING( CP_PACKET0( reg, (sz-1) ) );
2111 OUT_RING_USER_TABLE( data, sz );
2114 cmdbuf->buf += sz * sizeof(int);
2115 cmdbuf->bufsz -= sz * sizeof(int);
2119 static __inline__ int radeon_emit_scalars(
2120 drm_radeon_private_t *dev_priv,
2121 drm_radeon_cmd_header_t header,
2122 drm_radeon_cmd_buffer_t *cmdbuf )
2124 int sz = header.scalars.count;
2125 int __user *data = (int __user *)cmdbuf->buf;
2126 int start = header.scalars.offset;
2127 int stride = header.scalars.stride;
2131 OUT_RING( CP_PACKET0( RADEON_SE_TCL_SCALAR_INDX_REG, 0 ) );
2132 OUT_RING( start | (stride << RADEON_SCAL_INDX_DWORD_STRIDE_SHIFT));
2133 OUT_RING( CP_PACKET0_TABLE( RADEON_SE_TCL_SCALAR_DATA_REG, sz-1 ) );
2134 OUT_RING_USER_TABLE( data, sz );
2136 cmdbuf->buf += sz * sizeof(int);
2137 cmdbuf->bufsz -= sz * sizeof(int);
2143 static __inline__ int radeon_emit_scalars2(
2144 drm_radeon_private_t *dev_priv,
2145 drm_radeon_cmd_header_t header,
2146 drm_radeon_cmd_buffer_t *cmdbuf )
2148 int sz = header.scalars.count;
2149 int __user *data = (int __user *)cmdbuf->buf;
2150 int start = ((unsigned int)header.scalars.offset) + 0x100;
2151 int stride = header.scalars.stride;
2155 OUT_RING( CP_PACKET0( RADEON_SE_TCL_SCALAR_INDX_REG, 0 ) );
2156 OUT_RING( start | (stride << RADEON_SCAL_INDX_DWORD_STRIDE_SHIFT));
2157 OUT_RING( CP_PACKET0_TABLE( RADEON_SE_TCL_SCALAR_DATA_REG, sz-1 ) );
2158 OUT_RING_USER_TABLE( data, sz );
2160 cmdbuf->buf += sz * sizeof(int);
2161 cmdbuf->bufsz -= sz * sizeof(int);
2165 static __inline__ int radeon_emit_vectors(
2166 drm_radeon_private_t *dev_priv,
2167 drm_radeon_cmd_header_t header,
2168 drm_radeon_cmd_buffer_t *cmdbuf )
2170 int sz = header.vectors.count;
2171 int __user *data = (int __user *)cmdbuf->buf;
2172 int start = header.vectors.offset;
2173 int stride = header.vectors.stride;
2177 OUT_RING( CP_PACKET0( RADEON_SE_TCL_VECTOR_INDX_REG, 0 ) );
2178 OUT_RING( start | (stride << RADEON_VEC_INDX_OCTWORD_STRIDE_SHIFT));
2179 OUT_RING( CP_PACKET0_TABLE( RADEON_SE_TCL_VECTOR_DATA_REG, (sz-1) ) );
2180 OUT_RING_USER_TABLE( data, sz );
2183 cmdbuf->buf += sz * sizeof(int);
2184 cmdbuf->bufsz -= sz * sizeof(int);
2189 static int radeon_emit_packet3( drm_device_t *dev,
2190 drm_file_t *filp_priv,
2191 drm_radeon_cmd_buffer_t *cmdbuf )
2193 drm_radeon_private_t *dev_priv = dev->dev_private;
2195 int __user *cmd = (int __user *)cmdbuf->buf;
2201 if ( ( ret = radeon_check_and_fixup_packet3( dev_priv, filp_priv,
2202 cmdbuf, &cmdsz ) ) ) {
2203 DRM_ERROR( "Packet verification failed\n" );
2207 BEGIN_RING( cmdsz );
2208 OUT_RING_USER_TABLE( cmd, cmdsz );
2211 cmdbuf->buf += cmdsz * 4;
2212 cmdbuf->bufsz -= cmdsz * 4;
2217 static int radeon_emit_packet3_cliprect( drm_device_t *dev,
2218 drm_file_t *filp_priv,
2219 drm_radeon_cmd_buffer_t *cmdbuf,
2222 drm_radeon_private_t *dev_priv = dev->dev_private;
2223 drm_clip_rect_t box;
2225 int __user *cmd = (int __user *)cmdbuf->buf;
2227 drm_clip_rect_t __user *boxes = cmdbuf->boxes;
2233 if ( ( ret = radeon_check_and_fixup_packet3( dev_priv, filp_priv,
2234 cmdbuf, &cmdsz ) ) ) {
2235 DRM_ERROR( "Packet verification failed\n" );
2243 if ( i < cmdbuf->nbox ) {
2244 if (DRM_COPY_FROM_USER_UNCHECKED( &box, &boxes[i], sizeof(box) ))
2245 return DRM_ERR(EFAULT);
2246 /* FIXME The second and subsequent times round
2247 * this loop, send a WAIT_UNTIL_3D_IDLE before
2248 * calling emit_clip_rect(). This fixes a
2249 * lockup on fast machines when sending
2250 * several cliprects with a cmdbuf, as when
2251 * waving a 2D window over a 3D
2252 * window. Something in the commands from user
2253 * space seems to hang the card when they're
2254 * sent several times in a row. That would be
2255 * the correct place to fix it but this works
2256 * around it until I can figure that out - Tim
2260 RADEON_WAIT_UNTIL_3D_IDLE();
2263 radeon_emit_clip_rect( dev_priv, &box );
2266 BEGIN_RING( cmdsz );
2267 OUT_RING_USER_TABLE( cmd, cmdsz );
2270 } while ( ++i < cmdbuf->nbox );
2271 if (cmdbuf->nbox == 1)
2275 cmdbuf->buf += cmdsz * 4;
2276 cmdbuf->bufsz -= cmdsz * 4;
2281 static int radeon_emit_wait( drm_device_t *dev, int flags )
2283 drm_radeon_private_t *dev_priv = dev->dev_private;
2286 DRM_DEBUG("%s: %x\n", __FUNCTION__, flags);
2288 case RADEON_WAIT_2D:
2290 RADEON_WAIT_UNTIL_2D_IDLE();
2293 case RADEON_WAIT_3D:
2295 RADEON_WAIT_UNTIL_3D_IDLE();
2298 case RADEON_WAIT_2D|RADEON_WAIT_3D:
2300 RADEON_WAIT_UNTIL_IDLE();
2304 return DRM_ERR(EINVAL);
2310 int radeon_cp_cmdbuf( DRM_IOCTL_ARGS )
2313 drm_radeon_private_t *dev_priv = dev->dev_private;
2314 drm_file_t *filp_priv;
2315 drm_device_dma_t *dma = dev->dma;
2316 drm_buf_t *buf = NULL;
2318 drm_radeon_cmd_buffer_t cmdbuf;
2319 drm_radeon_cmd_header_t header;
2322 LOCK_TEST_WITH_RETURN( dev, filp );
2325 DRM_ERROR( "%s called with no initialization\n", __FUNCTION__ );
2326 return DRM_ERR(EINVAL);
2329 DRM_GET_PRIV_WITH_RETURN( filp_priv, filp );
2331 DRM_COPY_FROM_USER_IOCTL( cmdbuf, (drm_radeon_cmd_buffer_t __user *)data,
2334 RING_SPACE_TEST_WITH_RETURN( dev_priv );
2335 VB_AGE_TEST_WITH_RETURN( dev_priv );
2338 if (DRM_VERIFYAREA_READ( cmdbuf.buf, cmdbuf.bufsz ))
2339 return DRM_ERR(EFAULT);
2342 DRM_VERIFYAREA_READ(cmdbuf.boxes,
2343 cmdbuf.nbox * sizeof(drm_clip_rect_t)))
2344 return DRM_ERR(EFAULT);
2346 orig_nbox = cmdbuf.nbox;
2348 while ( cmdbuf.bufsz >= sizeof(header) ) {
2350 if (DRM_GET_USER_UNCHECKED( header.i, (int __user *)cmdbuf.buf )) {
2351 DRM_ERROR("__get_user %p\n", cmdbuf.buf);
2352 return DRM_ERR(EFAULT);
2355 cmdbuf.buf += sizeof(header);
2356 cmdbuf.bufsz -= sizeof(header);
2358 switch (header.header.cmd_type) {
2359 case RADEON_CMD_PACKET:
2360 DRM_DEBUG("RADEON_CMD_PACKET\n");
2361 if (radeon_emit_packets( dev_priv, filp_priv, header, &cmdbuf )) {
2362 DRM_ERROR("radeon_emit_packets failed\n");
2363 return DRM_ERR(EINVAL);
2367 case RADEON_CMD_SCALARS:
2368 DRM_DEBUG("RADEON_CMD_SCALARS\n");
2369 if (radeon_emit_scalars( dev_priv, header, &cmdbuf )) {
2370 DRM_ERROR("radeon_emit_scalars failed\n");
2371 return DRM_ERR(EINVAL);
2375 case RADEON_CMD_VECTORS:
2376 DRM_DEBUG("RADEON_CMD_VECTORS\n");
2377 if (radeon_emit_vectors( dev_priv, header, &cmdbuf )) {
2378 DRM_ERROR("radeon_emit_vectors failed\n");
2379 return DRM_ERR(EINVAL);
2383 case RADEON_CMD_DMA_DISCARD:
2384 DRM_DEBUG("RADEON_CMD_DMA_DISCARD\n");
2385 idx = header.dma.buf_idx;
2386 if ( idx < 0 || idx >= dma->buf_count ) {
2387 DRM_ERROR( "buffer index %d (of %d max)\n",
2388 idx, dma->buf_count - 1 );
2389 return DRM_ERR(EINVAL);
2392 buf = dma->buflist[idx];
2393 if ( buf->filp != filp || buf->pending ) {
2394 DRM_ERROR( "bad buffer %p %p %d\n",
2395 buf->filp, filp, buf->pending);
2396 return DRM_ERR(EINVAL);
2399 radeon_cp_discard_buffer( dev, buf );
2402 case RADEON_CMD_PACKET3:
2403 DRM_DEBUG("RADEON_CMD_PACKET3\n");
2404 if (radeon_emit_packet3( dev, filp_priv, &cmdbuf )) {
2405 DRM_ERROR("radeon_emit_packet3 failed\n");
2406 return DRM_ERR(EINVAL);
2410 case RADEON_CMD_PACKET3_CLIP:
2411 DRM_DEBUG("RADEON_CMD_PACKET3_CLIP\n");
2412 if (radeon_emit_packet3_cliprect( dev, filp_priv, &cmdbuf, orig_nbox )) {
2413 DRM_ERROR("radeon_emit_packet3_clip failed\n");
2414 return DRM_ERR(EINVAL);
2418 case RADEON_CMD_SCALARS2:
2419 DRM_DEBUG("RADEON_CMD_SCALARS2\n");
2420 if (radeon_emit_scalars2( dev_priv, header, &cmdbuf )) {
2421 DRM_ERROR("radeon_emit_scalars2 failed\n");
2422 return DRM_ERR(EINVAL);
2426 case RADEON_CMD_WAIT:
2427 DRM_DEBUG("RADEON_CMD_WAIT\n");
2428 if (radeon_emit_wait( dev, header.wait.flags )) {
2429 DRM_ERROR("radeon_emit_wait failed\n");
2430 return DRM_ERR(EINVAL);
2434 DRM_ERROR("bad cmd_type %d at %p\n",
2435 header.header.cmd_type,
2436 cmdbuf.buf - sizeof(header));
2437 return DRM_ERR(EINVAL);
2442 DRM_DEBUG("DONE\n");
2449 int radeon_cp_getparam( DRM_IOCTL_ARGS )
2452 drm_radeon_private_t *dev_priv = dev->dev_private;
2453 drm_radeon_getparam_t param;
2457 DRM_ERROR( "%s called with no initialization\n", __FUNCTION__ );
2458 return DRM_ERR(EINVAL);
2461 DRM_COPY_FROM_USER_IOCTL( param, (drm_radeon_getparam_t __user *)data,
2464 DRM_DEBUG( "pid=%d\n", DRM_CURRENTPID );
2466 switch( param.param ) {
2467 case RADEON_PARAM_GART_BUFFER_OFFSET:
2468 value = dev_priv->gart_buffers_offset;
2470 case RADEON_PARAM_LAST_FRAME:
2471 dev_priv->stats.last_frame_reads++;
2472 value = GET_SCRATCH( 0 );
2474 case RADEON_PARAM_LAST_DISPATCH:
2475 value = GET_SCRATCH( 1 );
2477 case RADEON_PARAM_LAST_CLEAR:
2478 dev_priv->stats.last_clear_reads++;
2479 value = GET_SCRATCH( 2 );
2481 case RADEON_PARAM_IRQ_NR:
2484 case RADEON_PARAM_GART_BASE:
2485 value = dev_priv->gart_vm_start;
2487 case RADEON_PARAM_REGISTER_HANDLE:
2488 value = dev_priv->mmio_offset;
2490 case RADEON_PARAM_STATUS_HANDLE:
2491 value = dev_priv->ring_rptr_offset;
2493 #if BITS_PER_LONG == 32
2495 * This ioctl() doesn't work on 64-bit platforms because hw_lock is a
2496 * pointer which can't fit into an int-sized variable. According to
2497 * Michel Dänzer, the ioctl() is only used on embedded platforms, so
2498 * not supporting it shouldn't be a problem. If the same functionality
2499 * is needed on 64-bit platforms, a new ioctl() would have to be added,
2500 * so backwards-compatibility for the embedded platforms can be
2501 * maintained. --davidm 4-Feb-2004.
2503 case RADEON_PARAM_SAREA_HANDLE:
2504 /* The lock is the first dword in the sarea. */
2505 value = (long)dev->lock.hw_lock;
2508 case RADEON_PARAM_GART_TEX_HANDLE:
2509 value = dev_priv->gart_textures_offset;
2512 return DRM_ERR(EINVAL);
2515 if ( DRM_COPY_TO_USER( param.value, &value, sizeof(int) ) ) {
2516 DRM_ERROR( "copy_to_user\n" );
2517 return DRM_ERR(EFAULT);
2523 int radeon_cp_setparam( DRM_IOCTL_ARGS ) {
2525 drm_radeon_private_t *dev_priv = dev->dev_private;
2526 drm_file_t *filp_priv;
2527 drm_radeon_setparam_t sp;
2530 DRM_ERROR( "%s called with no initialization\n", __FUNCTION__ );
2531 return DRM_ERR( EINVAL );
2534 DRM_GET_PRIV_WITH_RETURN( filp_priv, filp );
2536 DRM_COPY_FROM_USER_IOCTL( sp, ( drm_radeon_setparam_t __user * )data,
2539 switch( sp.param ) {
2540 case RADEON_SETPARAM_FB_LOCATION:
2541 filp_priv->radeon_fb_delta = dev_priv->fb_location - sp.value;
2544 DRM_DEBUG( "Invalid parameter %d\n", sp.param );
2545 return DRM_ERR( EINVAL );