2 * RocketPort device driver for Linux
4 * Written by Theodore Ts'o, 1995, 1996, 1997, 1998, 1999, 2000.
6 * Copyright (C) 1995, 1996, 1997, 1998, 1999, 2000, 2003 by Comtrol, Inc.
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of the
11 * License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful, but
14 * WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
16 * General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
24 * Kernel Synchronization:
26 * This driver has 2 kernel control paths - exception handlers (calls into the driver
27 * from user mode) and the timer bottom half (tasklet). This is a polled driver, interrupts
31 * - rp_table[], accessed through passed "info" pointers, is a global (static) array of
32 * serial port state information and the xmit_buf circular buffer. Protected by
33 * a per port spinlock.
34 * - xmit_flags[], an array of ints indexed by line (port) number, indicating that there
35 * is data to be transmitted. Protected by atomic bit operations.
36 * - rp_num_ports, int indicating number of open ports, protected by atomic operations.
38 * rp_write() and rp_write_char() functions use a per port semaphore to protect against
39 * simultaneous access to the same port by more than one process.
42 /****** Defines ******/
43 #ifdef PCI_NUM_RESOURCES
44 #define PCI_BASE_ADDRESS(dev, r) ((dev)->resource[r].start)
46 #define PCI_BASE_ADDRESS(dev, r) ((dev)->base_address[r])
49 #define ROCKET_PARANOIA_CHECK
50 #define ROCKET_DISABLE_SIMUSAGE
52 #undef ROCKET_SOFT_FLOW
53 #undef ROCKET_DEBUG_OPEN
54 #undef ROCKET_DEBUG_INTR
55 #undef ROCKET_DEBUG_WRITE
56 #undef ROCKET_DEBUG_FLOW
57 #undef ROCKET_DEBUG_THROTTLE
58 #undef ROCKET_DEBUG_WAIT_UNTIL_SENT
59 #undef ROCKET_DEBUG_RECEIVE
60 #undef ROCKET_DEBUG_HANGUP
62 #undef ROCKET_DEBUG_IO
64 #define POLL_PERIOD HZ/100 /* Polling period .01 seconds (10ms) */
66 /****** Kernel includes ******/
69 #include <config/modversions.h>
72 #include <linux/module.h>
73 #include <linux/errno.h>
74 #include <linux/major.h>
75 #include <linux/kernel.h>
76 #include <linux/signal.h>
77 #include <linux/slab.h>
79 #include <linux/sched.h>
80 #include <linux/timer.h>
81 #include <linux/interrupt.h>
82 #include <linux/tty.h>
83 #include <linux/tty_driver.h>
84 #include <linux/tty_flip.h>
85 #include <linux/string.h>
86 #include <linux/fcntl.h>
87 #include <linux/ptrace.h>
88 #include <linux/ioport.h>
89 #include <linux/delay.h>
90 #include <linux/wait.h>
91 #include <linux/pci.h>
92 #include <asm/uaccess.h>
93 #include <asm/atomic.h>
94 #include <asm/bitops.h>
95 #include <linux/spinlock.h>
96 #include <asm/semaphore.h>
97 #include <linux/init.h>
99 /****** RocketPort includes ******/
101 #include "rocket_int.h"
104 #define ROCKET_VERSION "2.09"
105 #define ROCKET_DATE "12-June-2003"
107 /****** RocketPort Local Variables ******/
109 static struct tty_driver *rocket_driver;
111 static struct rocket_version driver_version = {
112 ROCKET_VERSION, ROCKET_DATE
115 static struct r_port *rp_table[MAX_RP_PORTS]; /* The main repository of serial port state information. */
116 static unsigned int xmit_flags[NUM_BOARDS]; /* Bit significant, indicates port had data to transmit. */
117 /* eg. Bit 0 indicates port 0 has xmit data, ... */
118 static atomic_t rp_num_ports_open; /* Number of serial ports open */
119 static struct timer_list rocket_timer;
121 static unsigned long board1; /* ISA addresses, retrieved from rocketport.conf */
122 static unsigned long board2;
123 static unsigned long board3;
124 static unsigned long board4;
125 static unsigned long controller;
126 static unsigned long support_low_speed;
127 static unsigned long modem1;
128 static unsigned long modem2;
129 static unsigned long modem3;
130 static unsigned long modem4;
131 static unsigned long pc104_1[8];
132 static unsigned long pc104_2[8];
133 static unsigned long pc104_3[8];
134 static unsigned long pc104_4[8];
135 static unsigned long *pc104[4] = { pc104_1, pc104_2, pc104_3, pc104_4 };
137 static int rp_baud_base[NUM_BOARDS]; /* Board config info (Someday make a per-board structure) */
138 static unsigned long rcktpt_io_addr[NUM_BOARDS];
139 static int rcktpt_type[NUM_BOARDS];
140 static int is_PCI[NUM_BOARDS];
141 static rocketModel_t rocketModel[NUM_BOARDS];
142 static int max_board;
145 * The following arrays define the interrupt bits corresponding to each AIOP.
146 * These bits are different between the ISA and regular PCI boards and the
147 * Universal PCI boards.
150 static Word_t aiop_intr_bits[AIOP_CTL_SIZE] = {
157 static Word_t upci_aiop_intr_bits[AIOP_CTL_SIZE] = {
158 UPCI_AIOP_INTR_BIT_0,
159 UPCI_AIOP_INTR_BIT_1,
160 UPCI_AIOP_INTR_BIT_2,
165 * Line number is the ttySIx number (x), the Minor number. We
166 * assign them sequentially, starting at zero. The following
167 * array keeps track of the line number assigned to a given board/aiop/channel.
169 static unsigned char lineNumbers[MAX_RP_PORTS];
170 static unsigned long nextLineNumber;
172 /***** RocketPort Static Prototypes *********/
173 static int __init init_ISA(int i);
174 static void rp_wait_until_sent(struct tty_struct *tty, int timeout);
175 static void rp_flush_buffer(struct tty_struct *tty);
176 static void rmSpeakerReset(CONTROLLER_T * CtlP, unsigned long model);
177 static unsigned char GetLineNumber(int ctrl, int aiop, int ch);
178 static unsigned char SetLineNumber(int ctrl, int aiop, int ch);
179 static void rp_start(struct tty_struct *tty);
182 MODULE_AUTHOR("Theodore Ts'o");
183 MODULE_DESCRIPTION("Comtrol RocketPort driver");
184 MODULE_PARM(board1, "i");
185 MODULE_PARM_DESC(board1, "I/O port for (ISA) board #1");
186 MODULE_PARM(board2, "i");
187 MODULE_PARM_DESC(board2, "I/O port for (ISA) board #2");
188 MODULE_PARM(board3, "i");
189 MODULE_PARM_DESC(board3, "I/O port for (ISA) board #3");
190 MODULE_PARM(board4, "i");
191 MODULE_PARM_DESC(board4, "I/O port for (ISA) board #4");
192 MODULE_PARM(controller, "i");
193 MODULE_PARM_DESC(controller, "I/O port for (ISA) rocketport controller");
194 MODULE_PARM(support_low_speed, "i");
195 MODULE_PARM_DESC(support_low_speed, "1 means support 50 baud, 0 means support 460400 baud");
196 MODULE_PARM(modem1, "i");
197 MODULE_PARM_DESC(modem1, "1 means (ISA) board #1 is a RocketModem");
198 MODULE_PARM(modem2, "i");
199 MODULE_PARM_DESC(modem2, "1 means (ISA) board #2 is a RocketModem");
200 MODULE_PARM(modem3, "i");
201 MODULE_PARM_DESC(modem3, "1 means (ISA) board #3 is a RocketModem");
202 MODULE_PARM(modem4, "i");
203 MODULE_PARM_DESC(modem4, "1 means (ISA) board #4 is a RocketModem");
204 MODULE_PARM(pc104_1, "1-8i");
205 MODULE_PARM_DESC(pc104_1, "set interface types for ISA(PC104) board #1 (e.g. pc104_1=232,232,485,485,...");
206 MODULE_PARM(pc104_2, "1-8i");
207 MODULE_PARM_DESC(pc104_2, "set interface types for ISA(PC104) board #2 (e.g. pc104_2=232,232,485,485,...");
208 MODULE_PARM(pc104_3, "1-8i");
209 MODULE_PARM_DESC(pc104_3, "set interface types for ISA(PC104) board #3 (e.g. pc104_3=232,232,485,485,...");
210 MODULE_PARM(pc104_4, "1-8i");
211 MODULE_PARM_DESC(pc104_4, "set interface types for ISA(PC104) board #4 (e.g. pc104_4=232,232,485,485,...");
214 static void rp_cleanup_module(void);
216 module_init(rp_init);
217 module_exit(rp_cleanup_module);
221 #ifdef MODULE_LICENSE
222 MODULE_LICENSE("Dual BSD/GPL");
225 /*************************************************************************/
226 /* Module code starts here */
228 static inline int rocket_paranoia_check(struct r_port *info,
231 #ifdef ROCKET_PARANOIA_CHECK
234 if (info->magic != RPORT_MAGIC) {
235 printk(KERN_INFO "Warning: bad magic number for rocketport struct in %s\n",
244 /* Serial port receive data function. Called (from timer poll) when an AIOPIC signals
245 * that receive data is present on a serial port. Pulls data from FIFO, moves it into the
248 static void rp_do_receive(struct r_port *info,
249 struct tty_struct *tty,
250 CHANNEL_t * cp, unsigned int ChanStatus)
252 unsigned int CharNStat;
253 int ToRecv, wRecv, space, count;
257 ToRecv = sGetRxCnt(cp);
258 space = tty->ldisc.receive_room(tty);
259 if (space > 2 * TTY_FLIPBUF_SIZE)
260 space = 2 * TTY_FLIPBUF_SIZE;
261 cbuf = tty->flip.char_buf;
262 fbuf = tty->flip.flag_buf;
264 #ifdef ROCKET_DEBUG_INTR
265 printk(KERN_INFO "rp_do_receive(%d, %d)...", ToRecv, space);
269 * determine how many we can actually read in. If we can't
270 * read any in then we have a software overrun condition.
279 * if status indicates there are errored characters in the
280 * FIFO, then enter status mode (a word in FIFO holds
281 * character and status).
283 if (ChanStatus & (RXFOVERFL | RXBREAK | RXFRAME | RXPARITY)) {
284 if (!(ChanStatus & STATMODE)) {
285 #ifdef ROCKET_DEBUG_RECEIVE
286 printk(KERN_INFO "Entering STATMODE...");
288 ChanStatus |= STATMODE;
294 * if we previously entered status mode, then read down the
295 * FIFO one word at a time, pulling apart the character and
296 * the status. Update error counters depending on status
298 if (ChanStatus & STATMODE) {
299 #ifdef ROCKET_DEBUG_RECEIVE
300 printk(KERN_INFO "Ignore %x, read %x...", info->ignore_status_mask,
301 info->read_status_mask);
304 CharNStat = sInW(sGetTxRxDataIO(cp));
305 #ifdef ROCKET_DEBUG_RECEIVE
306 printk(KERN_INFO "%x...", CharNStat);
308 if (CharNStat & STMBREAKH)
309 CharNStat &= ~(STMFRAMEH | STMPARITYH);
310 if (CharNStat & info->ignore_status_mask) {
314 CharNStat &= info->read_status_mask;
315 if (CharNStat & STMBREAKH)
317 else if (CharNStat & STMPARITYH)
318 *fbuf++ = TTY_PARITY;
319 else if (CharNStat & STMFRAMEH)
321 else if (CharNStat & STMRCVROVRH)
322 *fbuf++ = TTY_OVERRUN;
325 *cbuf++ = CharNStat & 0xff;
331 * after we've emptied the FIFO in status mode, turn
332 * status mode back off
334 if (sGetRxCnt(cp) == 0) {
335 #ifdef ROCKET_DEBUG_RECEIVE
336 printk(KERN_INFO "Status mode off.\n");
338 sDisRxStatusMode(cp);
342 * we aren't in status mode, so read down the FIFO two
343 * characters at time by doing repeated word IO
348 sInStrW(sGetTxRxDataIO(cp), (unsigned short *) cbuf, wRecv);
350 cbuf[ToRecv - 1] = sInB(sGetTxRxDataIO(cp));
351 memset(fbuf, 0, ToRecv);
356 /* Push the data up to the tty layer */
357 tty->ldisc.receive_buf(tty, tty->flip.char_buf, tty->flip.flag_buf, count);
361 * Serial port transmit data function. Called from the timer polling loop as a
362 * result of a bit set in xmit_flags[], indicating data (from the tty layer) is ready
363 * to be sent out the serial port. Data is buffered in rp_table[line].xmit_buf, it is
364 * moved to the port's xmit FIFO. *info is critical data, protected by spinlocks.
366 static void rp_do_transmit(struct r_port *info)
369 CHANNEL_t *cp = &info->channel;
370 struct tty_struct *tty;
373 #ifdef ROCKET_DEBUG_INTR
374 printk(KERN_INFO "rp_do_transmit ");
379 printk(KERN_INFO "rp: WARNING rp_do_transmit called with info->tty==NULL\n");
380 clear_bit((info->aiop * 8) + info->chan, (void *) &xmit_flags[info->board]);
384 spin_lock_irqsave(&info->slock, flags);
386 info->xmit_fifo_room = TXFIFO_SIZE - sGetTxCnt(cp);
388 /* Loop sending data to FIFO until done or FIFO full */
390 if (tty->stopped || tty->hw_stopped)
392 c = MIN(info->xmit_fifo_room, MIN(info->xmit_cnt, XMIT_BUF_SIZE - info->xmit_tail));
393 if (c <= 0 || info->xmit_fifo_room <= 0)
395 sOutStrW(sGetTxRxDataIO(cp), (unsigned short *) (info->xmit_buf + info->xmit_tail), c / 2);
397 sOutB(sGetTxRxDataIO(cp), info->xmit_buf[info->xmit_tail + c - 1]);
398 info->xmit_tail += c;
399 info->xmit_tail &= XMIT_BUF_SIZE - 1;
401 info->xmit_fifo_room -= c;
402 #ifdef ROCKET_DEBUG_INTR
403 printk(KERN_INFO "tx %d chars...", c);
407 if (info->xmit_cnt == 0)
408 clear_bit((info->aiop * 8) + info->chan, (void *) &xmit_flags[info->board]);
410 if (info->xmit_cnt < WAKEUP_CHARS) {
411 if ((tty->flags & (1 << TTY_DO_WRITE_WAKEUP)) && tty->ldisc.write_wakeup)
412 (tty->ldisc.write_wakeup) (tty);
413 wake_up_interruptible(&tty->write_wait);
414 #ifdef ROCKETPORT_HAVE_POLL_WAIT
415 wake_up_interruptible(&tty->poll_wait);
419 spin_unlock_irqrestore(&info->slock, flags);
421 #ifdef ROCKET_DEBUG_INTR
422 printk(KERN_INFO "(%d,%d,%d,%d)...", info->xmit_cnt, info->xmit_head,
423 info->xmit_tail, info->xmit_fifo_room);
428 * Called when a serial port signals it has read data in it's RX FIFO.
429 * It checks what interrupts are pending and services them, including
430 * receiving serial data.
432 static void rp_handle_port(struct r_port *info)
435 struct tty_struct *tty;
436 unsigned int IntMask, ChanStatus;
441 if ((info->flags & ROCKET_INITIALIZED) == 0) {
442 printk(KERN_INFO "rp: WARNING: rp_handle_port called with info->flags & NOT_INIT\n");
446 printk(KERN_INFO "rp: WARNING: rp_handle_port called with info->tty==NULL\n");
452 IntMask = sGetChanIntID(cp) & info->intmask;
453 #ifdef ROCKET_DEBUG_INTR
454 printk(KERN_INFO "rp_interrupt %02x...", IntMask);
456 ChanStatus = sGetChanStatus(cp);
457 if (IntMask & RXF_TRIG) { /* Rx FIFO trigger level */
458 rp_do_receive(info, tty, cp, ChanStatus);
460 if (IntMask & DELTA_CD) { /* CD change */
461 #if (defined(ROCKET_DEBUG_OPEN) || defined(ROCKET_DEBUG_INTR) || defined(ROCKET_DEBUG_HANGUP))
462 printk(KERN_INFO "ttyR%d CD now %s...", info->line,
463 (ChanStatus & CD_ACT) ? "on" : "off");
465 if (!(ChanStatus & CD_ACT) && info->cd_status) {
466 #ifdef ROCKET_DEBUG_HANGUP
467 printk(KERN_INFO "CD drop, calling hangup.\n");
471 info->cd_status = (ChanStatus & CD_ACT) ? 1 : 0;
472 wake_up_interruptible(&info->open_wait);
474 #ifdef ROCKET_DEBUG_INTR
475 if (IntMask & DELTA_CTS) { /* CTS change */
476 printk(KERN_INFO "CTS change...\n");
478 if (IntMask & DELTA_DSR) { /* DSR change */
479 printk(KERN_INFO "DSR change...\n");
485 * The top level polling routine. Repeats every 1/100 HZ (10ms).
487 static void rp_do_poll(unsigned long dummy)
490 int ctrl, aiop, ch, line, i;
491 unsigned int xmitmask;
492 unsigned int CtlMask;
493 unsigned char AiopMask;
496 /* Walk through all the boards (ctrl's) */
497 for (ctrl = 0; ctrl < max_board; ctrl++) {
498 if (rcktpt_io_addr[ctrl] <= 0)
501 /* Get a ptr to the board's control struct */
502 ctlp = sCtlNumToCtlPtr(ctrl);
504 /* Get the interupt status from the board */
506 if (ctlp->BusType == isPCI)
507 CtlMask = sPCIGetControllerIntStatus(ctlp);
510 CtlMask = sGetControllerIntStatus(ctlp);
512 /* Check if any AIOP read bits are set */
513 for (aiop = 0; CtlMask; aiop++) {
514 bit = ctlp->AiopIntrBits[aiop];
517 AiopMask = sGetAiopIntStatus(ctlp, aiop);
519 /* Check if any port read bits are set */
520 for (ch = 0; AiopMask; AiopMask >>= 1, ch++) {
523 /* Get the line number (/dev/ttyRx number). */
524 /* Read the data from the port. */
525 line = GetLineNumber(ctrl, aiop, ch);
526 rp_handle_port(rp_table[line]);
532 xmitmask = xmit_flags[ctrl];
535 * xmit_flags contains bit-significant flags, indicating there is data
536 * to xmit on the port. Bit 0 is port 0 on this board, bit 1 is port
537 * 1, ... (32 total possible). The variable i has the aiop and ch
538 * numbers encoded in it (port 0-7 are aiop0, 8-15 are aiop1, etc).
541 for (i = 0; i < rocketModel[ctrl].numPorts; i++) {
542 if (xmitmask & (1 << i)) {
543 aiop = (i & 0x18) >> 3;
545 line = GetLineNumber(ctrl, aiop, ch);
546 rp_do_transmit(rp_table[line]);
553 * Reset the timer so we get called at the next clock tick (10ms).
555 if (atomic_read(&rp_num_ports_open))
556 mod_timer(&rocket_timer, jiffies + POLL_PERIOD);
560 * Initializes the r_port structure for a port, as well as enabling the port on
562 * Inputs: board, aiop, chan numbers
564 static void init_r_port(int board, int aiop, int chan, struct pci_dev *pci_dev)
571 /* Get the next available line number */
572 line = SetLineNumber(board, aiop, chan);
574 ctlp = sCtlNumToCtlPtr(board);
576 /* Get a r_port struct for the port, fill it in and save it globally, indexed by line number */
577 info = kmalloc(sizeof (struct r_port), GFP_KERNEL);
579 printk(KERN_INFO "Couldn't allocate info struct for line #%d\n", line);
582 memset(info, 0, sizeof (struct r_port));
584 info->magic = RPORT_MAGIC;
590 info->closing_wait = 3000;
591 info->close_delay = 50;
592 init_waitqueue_head(&info->open_wait);
593 init_waitqueue_head(&info->close_wait);
594 info->flags &= ~ROCKET_MODE_MASK;
595 switch (pc104[board][line]) {
597 info->flags |= ROCKET_MODE_RS422;
600 info->flags |= ROCKET_MODE_RS485;
604 info->flags |= ROCKET_MODE_RS232;
608 info->intmask = RXF_TRIG | TXFIFO_MT | SRC_INT | DELTA_CD | DELTA_CTS | DELTA_DSR;
609 if (sInitChan(ctlp, &info->channel, aiop, chan) == 0) {
610 printk(KERN_INFO "RocketPort sInitChan(%d, %d, %d) failed!\n", board, aiop, chan);
615 rocketMode = info->flags & ROCKET_MODE_MASK;
617 if ((info->flags & ROCKET_RTS_TOGGLE) || (rocketMode == ROCKET_MODE_RS485))
618 sEnRTSToggle(&info->channel);
620 sDisRTSToggle(&info->channel);
622 if (ctlp->boardType == ROCKET_TYPE_PC104) {
623 switch (rocketMode) {
624 case ROCKET_MODE_RS485:
625 sSetInterfaceMode(&info->channel, InterfaceModeRS485);
627 case ROCKET_MODE_RS422:
628 sSetInterfaceMode(&info->channel, InterfaceModeRS422);
630 case ROCKET_MODE_RS232:
632 if (info->flags & ROCKET_RTS_TOGGLE)
633 sSetInterfaceMode(&info->channel, InterfaceModeRS232T);
635 sSetInterfaceMode(&info->channel, InterfaceModeRS232);
639 spin_lock_init(&info->slock);
640 sema_init(&info->write_sem, 1);
641 rp_table[line] = info;
643 tty_register_device(rocket_driver, line, &pci_dev->dev);
647 * Configures a rocketport port according to its termio settings. Called from
648 * user mode into the driver (exception handler). *info CD manipulation is spinlock protected.
650 static void configure_r_port(struct r_port *info,
651 struct termios *old_termios)
656 int bits, baud, divisor;
659 if (!info->tty || !info->tty->termios)
662 cflag = info->tty->termios->c_cflag;
664 /* Byte size and parity */
665 if ((cflag & CSIZE) == CS8) {
672 if (cflag & CSTOPB) {
679 if (cflag & PARENB) {
682 if (cflag & PARODD) {
692 baud = tty_get_baud_rate(info->tty);
695 divisor = ((rp_baud_base[info->board] + (baud >> 1)) / baud) - 1;
696 if ((divisor >= 8192 || divisor < 0) && old_termios) {
697 info->tty->termios->c_cflag &= ~CBAUD;
698 info->tty->termios->c_cflag |=
699 (old_termios->c_cflag & CBAUD);
700 baud = tty_get_baud_rate(info->tty);
703 divisor = (rp_baud_base[info->board] / baud) - 1;
705 if (divisor >= 8192 || divisor < 0) {
707 divisor = (rp_baud_base[info->board] / baud) - 1;
709 info->cps = baud / bits;
710 sSetBaud(cp, divisor);
712 if (cflag & CRTSCTS) {
713 info->intmask |= DELTA_CTS;
716 info->intmask &= ~DELTA_CTS;
719 if (cflag & CLOCAL) {
720 info->intmask &= ~DELTA_CD;
722 spin_lock_irqsave(&info->slock, flags);
723 if (sGetChanStatus(cp) & CD_ACT)
727 info->intmask |= DELTA_CD;
728 spin_unlock_irqrestore(&info->slock, flags);
732 * Handle software flow control in the board
734 #ifdef ROCKET_SOFT_FLOW
735 if (I_IXON(info->tty)) {
736 sEnTxSoftFlowCtl(cp);
737 if (I_IXANY(info->tty)) {
742 sSetTxXONChar(cp, START_CHAR(info->tty));
743 sSetTxXOFFChar(cp, STOP_CHAR(info->tty));
745 sDisTxSoftFlowCtl(cp);
752 * Set up ignore/read mask words
754 info->read_status_mask = STMRCVROVRH | 0xFF;
755 if (I_INPCK(info->tty))
756 info->read_status_mask |= STMFRAMEH | STMPARITYH;
757 if (I_BRKINT(info->tty) || I_PARMRK(info->tty))
758 info->read_status_mask |= STMBREAKH;
761 * Characters to ignore
763 info->ignore_status_mask = 0;
764 if (I_IGNPAR(info->tty))
765 info->ignore_status_mask |= STMFRAMEH | STMPARITYH;
766 if (I_IGNBRK(info->tty)) {
767 info->ignore_status_mask |= STMBREAKH;
769 * If we're ignoring parity and break indicators,
770 * ignore overruns too. (For real raw support).
772 if (I_IGNPAR(info->tty))
773 info->ignore_status_mask |= STMRCVROVRH;
776 rocketMode = info->flags & ROCKET_MODE_MASK;
778 if ((info->flags & ROCKET_RTS_TOGGLE)
779 || (rocketMode == ROCKET_MODE_RS485))
784 sSetRTS(&info->channel);
786 if (cp->CtlP->boardType == ROCKET_TYPE_PC104) {
787 switch (rocketMode) {
788 case ROCKET_MODE_RS485:
789 sSetInterfaceMode(cp, InterfaceModeRS485);
791 case ROCKET_MODE_RS422:
792 sSetInterfaceMode(cp, InterfaceModeRS422);
794 case ROCKET_MODE_RS232:
796 if (info->flags & ROCKET_RTS_TOGGLE)
797 sSetInterfaceMode(cp, InterfaceModeRS232T);
799 sSetInterfaceMode(cp, InterfaceModeRS232);
805 /* info->count is considered critical, protected by spinlocks. */
806 static int block_til_ready(struct tty_struct *tty, struct file *filp,
809 DECLARE_WAITQUEUE(wait, current);
811 int do_clocal = 0, extra_count = 0;
815 * If the device is in the middle of being closed, then block
816 * until it's done, and then try again.
818 if (tty_hung_up_p(filp))
819 return ((info->flags & ROCKET_HUP_NOTIFY) ? -EAGAIN : -ERESTARTSYS);
820 if (info->flags & ROCKET_CLOSING) {
821 interruptible_sleep_on(&info->close_wait);
822 return ((info->flags & ROCKET_HUP_NOTIFY) ? -EAGAIN : -ERESTARTSYS);
826 * If non-blocking mode is set, or the port is not enabled,
827 * then make the check up front and then exit.
829 if ((filp->f_flags & O_NONBLOCK) || (tty->flags & (1 << TTY_IO_ERROR))) {
830 info->flags |= ROCKET_NORMAL_ACTIVE;
833 if (tty->termios->c_cflag & CLOCAL)
837 * Block waiting for the carrier detect and the line to become free. While we are in
838 * this loop, info->count is dropped by one, so that rp_close() knows when to free things.
839 * We restore it upon exit, either normal or abnormal.
842 add_wait_queue(&info->open_wait, &wait);
843 #ifdef ROCKET_DEBUG_OPEN
844 printk(KERN_INFO "block_til_ready before block: ttyR%d, count = %d\n", info->line, info->count);
846 spin_lock_irqsave(&info->slock, flags);
848 #ifdef ROCKET_DISABLE_SIMUSAGE
849 info->flags |= ROCKET_NORMAL_ACTIVE;
851 if (!tty_hung_up_p(filp)) {
856 info->blocked_open++;
858 spin_unlock_irqrestore(&info->slock, flags);
861 if (tty->termios->c_cflag & CBAUD) {
862 sSetDTR(&info->channel);
863 sSetRTS(&info->channel);
865 set_current_state(TASK_INTERRUPTIBLE);
866 if (tty_hung_up_p(filp) || !(info->flags & ROCKET_INITIALIZED)) {
867 if (info->flags & ROCKET_HUP_NOTIFY)
870 retval = -ERESTARTSYS;
873 if (!(info->flags & ROCKET_CLOSING) && (do_clocal || (sGetChanStatusLo(&info->channel) & CD_ACT)))
875 if (signal_pending(current)) {
876 retval = -ERESTARTSYS;
879 #ifdef ROCKET_DEBUG_OPEN
880 printk(KERN_INFO "block_til_ready blocking: ttyR%d, count = %d, flags=0x%0x\n",
881 info->line, info->count, info->flags);
883 schedule(); /* Don't hold spinlock here, will hang PC */
885 current->state = TASK_RUNNING;
886 remove_wait_queue(&info->open_wait, &wait);
888 spin_lock_irqsave(&info->slock, flags);
892 info->blocked_open--;
894 spin_unlock_irqrestore(&info->slock, flags);
896 #ifdef ROCKET_DEBUG_OPEN
897 printk(KERN_INFO "block_til_ready after blocking: ttyR%d, count = %d\n",
898 info->line, info->count);
902 info->flags |= ROCKET_NORMAL_ACTIVE;
907 * Exception handler that opens a serial port. Creates xmit_buf storage, fills in
908 * port's r_port struct. Initializes the port hardware.
910 static int rp_open(struct tty_struct *tty, struct file *filp)
913 int line = 0, retval;
917 line = TTY_GET_LINE(tty);
918 if ((line < 0) || (line >= MAX_RP_PORTS) || ((info = rp_table[line]) == NULL))
921 page = __get_free_page(GFP_KERNEL);
925 if (info->flags & ROCKET_CLOSING) {
926 interruptible_sleep_on(&info->close_wait);
928 return ((info->flags & ROCKET_HUP_NOTIFY) ? -EAGAIN : -ERESTARTSYS);
932 * We must not sleep from here until the port is marked fully in use.
937 info->xmit_buf = (unsigned char *) page;
939 tty->driver_data = info;
942 if (info->count++ == 0) {
943 atomic_inc(&rp_num_ports_open);
945 #ifdef ROCKET_DEBUG_OPEN
946 printk(KERN_INFO "rocket mod++ = %d...", atomic_read(&rp_num_ports_open));
949 #ifdef ROCKET_DEBUG_OPEN
950 printk(KERN_INFO "rp_open ttyR%d, count=%d\n", info->line, info->count);
954 * Info->count is now 1; so it's safe to sleep now.
956 info->session = current->signal->session;
957 info->pgrp = process_group(current);
959 if ((info->flags & ROCKET_INITIALIZED) == 0) {
961 sSetRxTrigger(cp, TRIG_1);
962 if (sGetChanStatus(cp) & CD_ACT)
966 sDisRxStatusMode(cp);
970 sEnInterrupts(cp, (TXINT_EN | MCINT_EN | RXINT_EN | SRCINT_EN | CHANINT_EN));
971 sSetRxTrigger(cp, TRIG_1);
974 sDisRxStatusMode(cp);
978 sDisTxSoftFlowCtl(cp);
983 info->flags |= ROCKET_INITIALIZED;
986 * Set up the tty->alt_speed kludge
988 if ((info->flags & ROCKET_SPD_MASK) == ROCKET_SPD_HI)
989 info->tty->alt_speed = 57600;
990 if ((info->flags & ROCKET_SPD_MASK) == ROCKET_SPD_VHI)
991 info->tty->alt_speed = 115200;
992 if ((info->flags & ROCKET_SPD_MASK) == ROCKET_SPD_SHI)
993 info->tty->alt_speed = 230400;
994 if ((info->flags & ROCKET_SPD_MASK) == ROCKET_SPD_WARP)
995 info->tty->alt_speed = 460800;
997 configure_r_port(info, NULL);
998 if (tty->termios->c_cflag & CBAUD) {
1003 /* Starts (or resets) the maint polling loop */
1004 mod_timer(&rocket_timer, jiffies + POLL_PERIOD);
1006 retval = block_til_ready(tty, filp, info);
1008 #ifdef ROCKET_DEBUG_OPEN
1009 printk(KERN_INFO "rp_open returning after block_til_ready with %d\n", retval);
1017 * Exception handler that closes a serial port. info->count is considered critical.
1019 static void rp_close(struct tty_struct *tty, struct file *filp)
1021 struct r_port *info = (struct r_port *) tty->driver_data;
1022 unsigned long flags;
1026 if (rocket_paranoia_check(info, "rp_close"))
1029 #ifdef ROCKET_DEBUG_OPEN
1030 printk(KERN_INFO "rp_close ttyR%d, count = %d\n", info->line, info->count);
1033 if (tty_hung_up_p(filp))
1035 spin_lock_irqsave(&info->slock, flags);
1037 if ((tty->count == 1) && (info->count != 1)) {
1039 * Uh, oh. tty->count is 1, which means that the tty
1040 * structure will be freed. Info->count should always
1041 * be one in these conditions. If it's greater than
1042 * one, we've got real problems, since it means the
1043 * serial port won't be shutdown.
1045 printk(KERN_INFO "rp_close: bad serial port count; tty->count is 1, "
1046 "info->count is %d\n", info->count);
1049 if (--info->count < 0) {
1050 printk(KERN_INFO "rp_close: bad serial port count for ttyR%d: %d\n",
1051 info->line, info->count);
1055 spin_unlock_irqrestore(&info->slock, flags);
1058 info->flags |= ROCKET_CLOSING;
1059 spin_unlock_irqrestore(&info->slock, flags);
1061 cp = &info->channel;
1064 * Notify the line discpline to only process XON/XOFF characters
1069 * If transmission was throttled by the application request,
1070 * just flush the xmit buffer.
1072 if (tty->flow_stopped)
1073 rp_flush_buffer(tty);
1076 * Wait for the transmit buffer to clear
1078 if (info->closing_wait != ROCKET_CLOSING_WAIT_NONE)
1079 tty_wait_until_sent(tty, info->closing_wait);
1081 * Before we drop DTR, make sure the UART transmitter
1082 * has completely drained; this is especially
1083 * important if there is a transmit FIFO!
1085 timeout = (sGetTxCnt(cp) + 1) * HZ / info->cps;
1088 rp_wait_until_sent(tty, timeout);
1089 clear_bit((info->aiop * 8) + info->chan, (void *) &xmit_flags[info->board]);
1092 sDisInterrupts(cp, (TXINT_EN | MCINT_EN | RXINT_EN | SRCINT_EN | CHANINT_EN));
1094 sDisTxSoftFlowCtl(cp);
1102 if (TTY_DRIVER_FLUSH_BUFFER_EXISTS(tty))
1103 TTY_DRIVER_FLUSH_BUFFER(tty);
1104 if (tty->ldisc.flush_buffer)
1105 tty->ldisc.flush_buffer(tty);
1107 clear_bit((info->aiop * 8) + info->chan, (void *) &xmit_flags[info->board]);
1109 if (info->blocked_open) {
1110 if (info->close_delay) {
1111 current->state = TASK_INTERRUPTIBLE;
1112 schedule_timeout(info->close_delay);
1114 wake_up_interruptible(&info->open_wait);
1116 if (info->xmit_buf) {
1117 free_page((unsigned long) info->xmit_buf);
1118 info->xmit_buf = NULL;
1121 info->flags &= ~(ROCKET_INITIALIZED | ROCKET_CLOSING | ROCKET_NORMAL_ACTIVE);
1123 wake_up_interruptible(&info->close_wait);
1124 atomic_dec(&rp_num_ports_open);
1126 #ifdef ROCKET_DEBUG_OPEN
1127 printk(KERN_INFO "rocket mod-- = %d...", atomic_read(&rp_num_ports_open));
1128 printk(KERN_INFO "rp_close ttyR%d complete shutdown\n", info->line);
1133 static void rp_set_termios(struct tty_struct *tty,
1134 struct termios *old_termios)
1136 struct r_port *info = (struct r_port *) tty->driver_data;
1140 if (rocket_paranoia_check(info, "rp_set_termios"))
1143 cflag = tty->termios->c_cflag;
1145 if (cflag == old_termios->c_cflag)
1149 * This driver doesn't support CS5 or CS6
1151 if (((cflag & CSIZE) == CS5) || ((cflag & CSIZE) == CS6))
1152 tty->termios->c_cflag =
1153 ((cflag & ~CSIZE) | (old_termios->c_cflag & CSIZE));
1155 configure_r_port(info, old_termios);
1157 cp = &info->channel;
1159 /* Handle transition to B0 status */
1160 if ((old_termios->c_cflag & CBAUD) && !(tty->termios->c_cflag & CBAUD)) {
1165 /* Handle transition away from B0 status */
1166 if (!(old_termios->c_cflag & CBAUD) && (tty->termios->c_cflag & CBAUD)) {
1167 if (!tty->hw_stopped || !(tty->termios->c_cflag & CRTSCTS))
1172 if ((old_termios->c_cflag & CRTSCTS) && !(tty->termios->c_cflag & CRTSCTS)) {
1173 tty->hw_stopped = 0;
1178 static void rp_break(struct tty_struct *tty, int break_state)
1180 struct r_port *info = (struct r_port *) tty->driver_data;
1181 unsigned long flags;
1183 if (rocket_paranoia_check(info, "rp_break"))
1186 spin_lock_irqsave(&info->slock, flags);
1187 if (break_state == -1)
1188 sSendBreak(&info->channel);
1190 sClrBreak(&info->channel);
1191 spin_unlock_irqrestore(&info->slock, flags);
1195 * sGetChanRI used to be a macro in rocket_int.h. When the functionality for
1196 * the UPCI boards was added, it was decided to make this a function because
1197 * the macro was getting too complicated. All cases except the first one
1198 * (UPCIRingInd) are taken directly from the original macro.
1200 static int sGetChanRI(CHANNEL_T * ChP)
1202 CONTROLLER_t *CtlP = ChP->CtlP;
1203 int ChanNum = ChP->ChanNum;
1206 if (CtlP->UPCIRingInd)
1207 RingInd = !(sInB(CtlP->UPCIRingInd) & sBitMapSetTbl[ChanNum]);
1208 else if (CtlP->AltChanRingIndicator)
1209 RingInd = sInB((ByteIO_t) (ChP->ChanStat + 8)) & DSR_ACT;
1210 else if (CtlP->boardType == ROCKET_TYPE_PC104)
1211 RingInd = !(sInB(CtlP->AiopIO[3]) & sBitMapSetTbl[ChanNum]);
1216 /********************************************************************************************/
1217 /* Here are the routines used by rp_ioctl. These are all called from exception handlers. */
1220 * Returns the state of the serial modem control lines. These next 2 functions
1221 * are the way kernel versions > 2.5 handle modem control lines rather than IOCTLs.
1223 static int rp_tiocmget(struct tty_struct *tty, struct file *file)
1225 struct r_port *info = (struct r_port *)tty->driver_data;
1226 unsigned int control, result, ChanStatus;
1228 ChanStatus = sGetChanStatusLo(&info->channel);
1229 control = info->channel.TxControl[3];
1230 result = ((control & SET_RTS) ? TIOCM_RTS : 0) |
1231 ((control & SET_DTR) ? TIOCM_DTR : 0) |
1232 ((ChanStatus & CD_ACT) ? TIOCM_CAR : 0) |
1233 (sGetChanRI(&info->channel) ? TIOCM_RNG : 0) |
1234 ((ChanStatus & DSR_ACT) ? TIOCM_DSR : 0) |
1235 ((ChanStatus & CTS_ACT) ? TIOCM_CTS : 0);
1241 * Sets the modem control lines
1243 static int rp_tiocmset(struct tty_struct *tty, struct file *file,
1244 unsigned int set, unsigned int clear)
1246 struct r_port *info = (struct r_port *)tty->driver_data;
1248 if (set & TIOCM_RTS)
1249 info->channel.TxControl[3] |= SET_RTS;
1250 if (set & TIOCM_DTR)
1251 info->channel.TxControl[3] |= SET_DTR;
1252 if (clear & TIOCM_RTS)
1253 info->channel.TxControl[3] &= ~SET_RTS;
1254 if (clear & TIOCM_DTR)
1255 info->channel.TxControl[3] &= ~SET_DTR;
1257 sOutDW(info->channel.IndexAddr, *(DWord_t *) & (info->channel.TxControl[0]));
1261 static int get_config(struct r_port *info, struct rocket_config __user *retinfo)
1263 struct rocket_config tmp;
1267 memset(&tmp, 0, sizeof (tmp));
1268 tmp.line = info->line;
1269 tmp.flags = info->flags;
1270 tmp.close_delay = info->close_delay;
1271 tmp.closing_wait = info->closing_wait;
1272 tmp.port = rcktpt_io_addr[(info->line >> 5) & 3];
1274 if (copy_to_user(retinfo, &tmp, sizeof (*retinfo)))
1279 static int set_config(struct r_port *info, struct rocket_config __user *new_info)
1281 struct rocket_config new_serial;
1283 if (copy_from_user(&new_serial, new_info, sizeof (new_serial)))
1286 #ifdef CAP_SYS_ADMIN
1287 if (!capable(CAP_SYS_ADMIN))
1292 if ((new_serial.flags & ~ROCKET_USR_MASK) != (info->flags & ~ROCKET_USR_MASK))
1294 info->flags = ((info->flags & ~ROCKET_USR_MASK) | (new_serial.flags & ROCKET_USR_MASK));
1295 configure_r_port(info, NULL);
1299 info->flags = ((info->flags & ~ROCKET_FLAGS) | (new_serial.flags & ROCKET_FLAGS));
1300 info->close_delay = new_serial.close_delay;
1301 info->closing_wait = new_serial.closing_wait;
1303 if ((info->flags & ROCKET_SPD_MASK) == ROCKET_SPD_HI)
1304 info->tty->alt_speed = 57600;
1305 if ((info->flags & ROCKET_SPD_MASK) == ROCKET_SPD_VHI)
1306 info->tty->alt_speed = 115200;
1307 if ((info->flags & ROCKET_SPD_MASK) == ROCKET_SPD_SHI)
1308 info->tty->alt_speed = 230400;
1309 if ((info->flags & ROCKET_SPD_MASK) == ROCKET_SPD_WARP)
1310 info->tty->alt_speed = 460800;
1312 configure_r_port(info, NULL);
1317 * This function fills in a rocket_ports struct with information
1318 * about what boards/ports are in the system. This info is passed
1319 * to user space. See setrocket.c where the info is used to create
1320 * the /dev/ttyRx ports.
1322 static int get_ports(struct r_port *info, struct rocket_ports __user *retports)
1324 struct rocket_ports tmp;
1329 memset(&tmp, 0, sizeof (tmp));
1330 tmp.tty_major = rocket_driver->major;
1332 for (board = 0; board < 4; board++) {
1333 tmp.rocketModel[board].model = rocketModel[board].model;
1334 strcpy(tmp.rocketModel[board].modelString, rocketModel[board].modelString);
1335 tmp.rocketModel[board].numPorts = rocketModel[board].numPorts;
1336 tmp.rocketModel[board].loadrm2 = rocketModel[board].loadrm2;
1337 tmp.rocketModel[board].startingPortNumber = rocketModel[board].startingPortNumber;
1339 if (copy_to_user(retports, &tmp, sizeof (*retports)))
1344 static int reset_rm2(struct r_port *info, void __user *arg)
1348 if (copy_from_user(&reset, arg, sizeof (int)))
1353 if (rcktpt_type[info->board] != ROCKET_TYPE_MODEMII &&
1354 rcktpt_type[info->board] != ROCKET_TYPE_MODEMIII)
1357 if (info->ctlp->BusType == isISA)
1358 sModemReset(info->ctlp, info->chan, reset);
1360 sPCIModemReset(info->ctlp, info->chan, reset);
1365 static int get_version(struct r_port *info, struct rocket_version __user *retvers)
1367 if (copy_to_user(retvers, &driver_version, sizeof (*retvers)))
1372 /* IOCTL call handler into the driver */
1373 static int rp_ioctl(struct tty_struct *tty, struct file *file,
1374 unsigned int cmd, unsigned long arg)
1376 struct r_port *info = (struct r_port *) tty->driver_data;
1377 void __user *argp = (void __user *)arg;
1379 if (cmd != RCKP_GET_PORTS && rocket_paranoia_check(info, "rp_ioctl"))
1383 case RCKP_GET_STRUCT:
1384 if (copy_to_user(argp, info, sizeof (struct r_port)))
1387 case RCKP_GET_CONFIG:
1388 return get_config(info, argp);
1389 case RCKP_SET_CONFIG:
1390 return set_config(info, argp);
1391 case RCKP_GET_PORTS:
1392 return get_ports(info, argp);
1393 case RCKP_RESET_RM2:
1394 return reset_rm2(info, argp);
1395 case RCKP_GET_VERSION:
1396 return get_version(info, argp);
1398 return -ENOIOCTLCMD;
1403 static void rp_send_xchar(struct tty_struct *tty, char ch)
1405 struct r_port *info = (struct r_port *) tty->driver_data;
1408 if (rocket_paranoia_check(info, "rp_send_xchar"))
1411 cp = &info->channel;
1413 sWriteTxPrioByte(cp, ch);
1415 sWriteTxByte(sGetTxRxDataIO(cp), ch);
1418 static void rp_throttle(struct tty_struct *tty)
1420 struct r_port *info = (struct r_port *) tty->driver_data;
1423 #ifdef ROCKET_DEBUG_THROTTLE
1424 printk(KERN_INFO "throttle %s: %d....\n", tty->name,
1425 tty->ldisc.chars_in_buffer(tty));
1428 if (rocket_paranoia_check(info, "rp_throttle"))
1431 cp = &info->channel;
1433 rp_send_xchar(tty, STOP_CHAR(tty));
1435 sClrRTS(&info->channel);
1438 static void rp_unthrottle(struct tty_struct *tty)
1440 struct r_port *info = (struct r_port *) tty->driver_data;
1442 #ifdef ROCKET_DEBUG_THROTTLE
1443 printk(KERN_INFO "unthrottle %s: %d....\n", tty->name,
1444 tty->ldisc.chars_in_buffer(tty));
1447 if (rocket_paranoia_check(info, "rp_throttle"))
1450 cp = &info->channel;
1452 rp_send_xchar(tty, START_CHAR(tty));
1454 sSetRTS(&info->channel);
1458 * ------------------------------------------------------------
1459 * rp_stop() and rp_start()
1461 * This routines are called before setting or resetting tty->stopped.
1462 * They enable or disable transmitter interrupts, as necessary.
1463 * ------------------------------------------------------------
1465 static void rp_stop(struct tty_struct *tty)
1467 struct r_port *info = (struct r_port *) tty->driver_data;
1469 #ifdef ROCKET_DEBUG_FLOW
1470 printk(KERN_INFO "stop %s: %d %d....\n", tty->name,
1471 info->xmit_cnt, info->xmit_fifo_room);
1474 if (rocket_paranoia_check(info, "rp_stop"))
1477 if (sGetTxCnt(&info->channel))
1478 sDisTransmit(&info->channel);
1481 static void rp_start(struct tty_struct *tty)
1483 struct r_port *info = (struct r_port *) tty->driver_data;
1485 #ifdef ROCKET_DEBUG_FLOW
1486 printk(KERN_INFO "start %s: %d %d....\n", tty->name,
1487 info->xmit_cnt, info->xmit_fifo_room);
1490 if (rocket_paranoia_check(info, "rp_stop"))
1493 sEnTransmit(&info->channel);
1494 set_bit((info->aiop * 8) + info->chan,
1495 (void *) &xmit_flags[info->board]);
1499 * rp_wait_until_sent() --- wait until the transmitter is empty
1501 static void rp_wait_until_sent(struct tty_struct *tty, int timeout)
1503 struct r_port *info = (struct r_port *) tty->driver_data;
1505 unsigned long orig_jiffies;
1506 int check_time, exit_time;
1509 if (rocket_paranoia_check(info, "rp_wait_until_sent"))
1512 cp = &info->channel;
1514 orig_jiffies = jiffies;
1515 #ifdef ROCKET_DEBUG_WAIT_UNTIL_SENT
1516 printk(KERN_INFO "In RP_wait_until_sent(%d) (jiff=%lu)...", timeout,
1518 printk(KERN_INFO "cps=%d...", info->cps);
1521 txcnt = sGetTxCnt(cp);
1523 if (sGetChanStatusLo(cp) & TXSHRMT)
1525 check_time = (HZ / info->cps) / 5;
1527 check_time = HZ * txcnt / info->cps;
1530 exit_time = orig_jiffies + timeout - jiffies;
1533 if (exit_time < check_time)
1534 check_time = exit_time;
1536 if (check_time == 0)
1538 #ifdef ROCKET_DEBUG_WAIT_UNTIL_SENT
1539 printk(KERN_INFO "txcnt = %d (jiff=%lu,check=%d)...", txcnt, jiffies, check_time);
1541 current->state = TASK_INTERRUPTIBLE;
1542 schedule_timeout(check_time);
1543 if (signal_pending(current))
1546 current->state = TASK_RUNNING;
1547 #ifdef ROCKET_DEBUG_WAIT_UNTIL_SENT
1548 printk(KERN_INFO "txcnt = %d (jiff=%lu)...done\n", txcnt, jiffies);
1553 * rp_hangup() --- called by tty_hangup() when a hangup is signaled.
1555 static void rp_hangup(struct tty_struct *tty)
1558 struct r_port *info = (struct r_port *) tty->driver_data;
1560 if (rocket_paranoia_check(info, "rp_hangup"))
1563 #if (defined(ROCKET_DEBUG_OPEN) || defined(ROCKET_DEBUG_HANGUP))
1564 printk(KERN_INFO "rp_hangup of ttyR%d...", info->line);
1566 rp_flush_buffer(tty);
1567 if (info->flags & ROCKET_CLOSING)
1570 atomic_dec(&rp_num_ports_open);
1571 clear_bit((info->aiop * 8) + info->chan, (void *) &xmit_flags[info->board]);
1574 info->flags &= ~ROCKET_NORMAL_ACTIVE;
1577 cp = &info->channel;
1580 sDisInterrupts(cp, (TXINT_EN | MCINT_EN | RXINT_EN | SRCINT_EN | CHANINT_EN));
1582 sDisTxSoftFlowCtl(cp);
1584 info->flags &= ~ROCKET_INITIALIZED;
1586 wake_up_interruptible(&info->open_wait);
1590 * Exception handler - write char routine. The RocketPort driver uses a
1591 * double-buffering strategy, with the twist that if the in-memory CPU
1592 * buffer is empty, and there's space in the transmit FIFO, the
1593 * writing routines will write directly to transmit FIFO.
1594 * Write buffer and counters protected by spinlocks
1596 static void rp_put_char(struct tty_struct *tty, unsigned char ch)
1598 struct r_port *info = (struct r_port *) tty->driver_data;
1600 unsigned long flags;
1602 if (rocket_paranoia_check(info, "rp_put_char"))
1605 /* Grab the port write semaphore, locking out other processes that try to write to this port */
1606 down(&info->write_sem);
1608 #ifdef ROCKET_DEBUG_WRITE
1609 printk(KERN_INFO "rp_put_char %c...", ch);
1612 spin_lock_irqsave(&info->slock, flags);
1613 cp = &info->channel;
1615 if (!tty->stopped && !tty->hw_stopped && info->xmit_fifo_room == 0)
1616 info->xmit_fifo_room = TXFIFO_SIZE - sGetTxCnt(cp);
1618 if (tty->stopped || tty->hw_stopped || info->xmit_fifo_room == 0 || info->xmit_cnt != 0) {
1619 info->xmit_buf[info->xmit_head++] = ch;
1620 info->xmit_head &= XMIT_BUF_SIZE - 1;
1622 set_bit((info->aiop * 8) + info->chan, (void *) &xmit_flags[info->board]);
1624 sOutB(sGetTxRxDataIO(cp), ch);
1625 info->xmit_fifo_room--;
1627 spin_unlock_irqrestore(&info->slock, flags);
1628 up(&info->write_sem);
1632 * Exception handler - write routine, called when user app writes to the device.
1633 * A per port write semaphore is used to protect from another process writing to
1634 * this port at the same time. This other process could be running on the other CPU
1635 * or get control of the CPU if the copy_from_user() blocks due to a page fault (swapped out).
1636 * Spinlocks protect the info xmit members.
1638 static int rp_write(struct tty_struct *tty, int from_user,
1639 const unsigned char *buf, int count)
1641 struct r_port *info = (struct r_port *) tty->driver_data;
1643 const unsigned char *b;
1645 unsigned long flags;
1647 if (count <= 0 || rocket_paranoia_check(info, "rp_write"))
1650 down_interruptible(&info->write_sem);
1652 #ifdef ROCKET_DEBUG_WRITE
1653 printk(KERN_INFO "rp_write %d chars...", count);
1655 cp = &info->channel;
1657 if (!tty->stopped && !tty->hw_stopped && info->xmit_fifo_room < count)
1658 info->xmit_fifo_room = TXFIFO_SIZE - sGetTxCnt(cp);
1661 * If the write queue for the port is empty, and there is FIFO space, stuff bytes
1662 * into FIFO. Use the write queue for temp storage.
1664 if (!tty->stopped && !tty->hw_stopped && info->xmit_cnt == 0 && info->xmit_fifo_room > 0) {
1665 c = MIN(count, info->xmit_fifo_room);
1668 if (copy_from_user(info->xmit_buf, buf, c)) {
1675 c = MIN(c, info->xmit_fifo_room);
1678 /* Push data into FIFO, 2 bytes at a time */
1679 sOutStrW(sGetTxRxDataIO(cp), (unsigned short *) b, c / 2);
1681 /* If there is a byte remaining, write it */
1683 sOutB(sGetTxRxDataIO(cp), b[c - 1]);
1689 spin_lock_irqsave(&info->slock, flags);
1690 info->xmit_fifo_room -= c;
1691 spin_unlock_irqrestore(&info->slock, flags);
1694 /* If count is zero, we wrote it all and are done */
1698 /* Write remaining data into the port's xmit_buf */
1700 if (info->tty == 0) /* Seemingly obligatory check... */
1703 c = MIN(count, MIN(XMIT_BUF_SIZE - info->xmit_cnt - 1, XMIT_BUF_SIZE - info->xmit_head));
1709 if (copy_from_user(info->xmit_buf + info->xmit_head, b, c)) {
1713 memcpy(info->xmit_buf + info->xmit_head, b, c);
1717 spin_lock_irqsave(&info->slock, flags);
1719 (info->xmit_head + c) & (XMIT_BUF_SIZE - 1);
1720 info->xmit_cnt += c;
1721 spin_unlock_irqrestore(&info->slock, flags);
1729 if ((retval > 0) && !tty->stopped && !tty->hw_stopped)
1730 set_bit((info->aiop * 8) + info->chan, (void *) &xmit_flags[info->board]);
1733 if (info->xmit_cnt < WAKEUP_CHARS) {
1734 if ((tty->flags & (1 << TTY_DO_WRITE_WAKEUP)) && tty->ldisc.write_wakeup)
1735 (tty->ldisc.write_wakeup) (tty);
1736 wake_up_interruptible(&tty->write_wait);
1737 #ifdef ROCKETPORT_HAVE_POLL_WAIT
1738 wake_up_interruptible(&tty->poll_wait);
1741 up(&info->write_sem);
1746 * Return the number of characters that can be sent. We estimate
1747 * only using the in-memory transmit buffer only, and ignore the
1748 * potential space in the transmit FIFO.
1750 static int rp_write_room(struct tty_struct *tty)
1752 struct r_port *info = (struct r_port *) tty->driver_data;
1755 if (rocket_paranoia_check(info, "rp_write_room"))
1758 ret = XMIT_BUF_SIZE - info->xmit_cnt - 1;
1761 #ifdef ROCKET_DEBUG_WRITE
1762 printk(KERN_INFO "rp_write_room returns %d...", ret);
1768 * Return the number of characters in the buffer. Again, this only
1769 * counts those characters in the in-memory transmit buffer.
1771 static int rp_chars_in_buffer(struct tty_struct *tty)
1773 struct r_port *info = (struct r_port *) tty->driver_data;
1776 if (rocket_paranoia_check(info, "rp_chars_in_buffer"))
1779 cp = &info->channel;
1781 #ifdef ROCKET_DEBUG_WRITE
1782 printk(KERN_INFO "rp_chars_in_buffer returns %d...", info->xmit_cnt);
1784 return info->xmit_cnt;
1788 * Flushes the TX fifo for a port, deletes data in the xmit_buf stored in the
1789 * r_port struct for the port. Note that spinlock are used to protect info members,
1790 * do not call this function if the spinlock is already held.
1792 static void rp_flush_buffer(struct tty_struct *tty)
1794 struct r_port *info = (struct r_port *) tty->driver_data;
1796 unsigned long flags;
1798 if (rocket_paranoia_check(info, "rp_flush_buffer"))
1801 spin_lock_irqsave(&info->slock, flags);
1802 info->xmit_cnt = info->xmit_head = info->xmit_tail = 0;
1803 spin_unlock_irqrestore(&info->slock, flags);
1805 wake_up_interruptible(&tty->write_wait);
1806 #ifdef ROCKETPORT_HAVE_POLL_WAIT
1807 wake_up_interruptible(&tty->poll_wait);
1809 if ((tty->flags & (1 << TTY_DO_WRITE_WAKEUP)) && tty->ldisc.write_wakeup)
1810 (tty->ldisc.write_wakeup) (tty);
1812 cp = &info->channel;
1819 * Called when a PCI card is found. Retrieves and stores model information,
1820 * init's aiopic and serial port hardware.
1821 * Inputs: i is the board number (0-n)
1823 __init int register_PCI(int i, struct pci_dev *dev)
1825 int num_aiops, aiop, max_num_aiops, num_chan, chan;
1826 unsigned int aiopio[MAX_AIOPS_PER_BOARD];
1827 char *str, *board_type;
1831 int altChanRingIndicator = 0;
1832 int ports_per_aiop = 8;
1834 unsigned int class_rev;
1835 WordIO_t ConfigIO = 0;
1836 ByteIO_t UPCIRingInd = 0;
1838 if (!dev || pci_enable_device(dev))
1841 rcktpt_io_addr[i] = pci_resource_start(dev, 0);
1842 ret = pci_read_config_dword(dev, PCI_CLASS_REVISION, &class_rev);
1845 printk(KERN_INFO " Error during register_PCI(), unable to read config dword \n");
1849 rcktpt_type[i] = ROCKET_TYPE_NORMAL;
1850 rocketModel[i].loadrm2 = 0;
1851 rocketModel[i].startingPortNumber = nextLineNumber;
1853 /* Depending on the model, set up some config variables */
1854 switch (dev->device) {
1855 case PCI_DEVICE_ID_RP4QUAD:
1859 rocketModel[i].model = MODEL_RP4QUAD;
1860 strcpy(rocketModel[i].modelString, "RocketPort 4 port w/quad cable");
1861 rocketModel[i].numPorts = 4;
1863 case PCI_DEVICE_ID_RP8OCTA:
1866 rocketModel[i].model = MODEL_RP8OCTA;
1867 strcpy(rocketModel[i].modelString, "RocketPort 8 port w/octa cable");
1868 rocketModel[i].numPorts = 8;
1870 case PCI_DEVICE_ID_URP8OCTA:
1873 rocketModel[i].model = MODEL_UPCI_RP8OCTA;
1874 strcpy(rocketModel[i].modelString, "RocketPort UPCI 8 port w/octa cable");
1875 rocketModel[i].numPorts = 8;
1877 case PCI_DEVICE_ID_RP8INTF:
1880 rocketModel[i].model = MODEL_RP8INTF;
1881 strcpy(rocketModel[i].modelString, "RocketPort 8 port w/external I/F");
1882 rocketModel[i].numPorts = 8;
1884 case PCI_DEVICE_ID_URP8INTF:
1887 rocketModel[i].model = MODEL_UPCI_RP8INTF;
1888 strcpy(rocketModel[i].modelString, "RocketPort UPCI 8 port w/external I/F");
1889 rocketModel[i].numPorts = 8;
1891 case PCI_DEVICE_ID_RP8J:
1894 rocketModel[i].model = MODEL_RP8J;
1895 strcpy(rocketModel[i].modelString, "RocketPort 8 port w/RJ11 connectors");
1896 rocketModel[i].numPorts = 8;
1898 case PCI_DEVICE_ID_RP4J:
1902 rocketModel[i].model = MODEL_RP4J;
1903 strcpy(rocketModel[i].modelString, "RocketPort 4 port w/RJ45 connectors");
1904 rocketModel[i].numPorts = 4;
1906 case PCI_DEVICE_ID_RP8SNI:
1907 str = "8 (DB78 Custom)";
1909 rocketModel[i].model = MODEL_RP8SNI;
1910 strcpy(rocketModel[i].modelString, "RocketPort 8 port w/ custom DB78");
1911 rocketModel[i].numPorts = 8;
1913 case PCI_DEVICE_ID_RP16SNI:
1914 str = "16 (DB78 Custom)";
1916 rocketModel[i].model = MODEL_RP16SNI;
1917 strcpy(rocketModel[i].modelString, "RocketPort 16 port w/ custom DB78");
1918 rocketModel[i].numPorts = 16;
1920 case PCI_DEVICE_ID_RP16INTF:
1923 rocketModel[i].model = MODEL_RP16INTF;
1924 strcpy(rocketModel[i].modelString, "RocketPort 16 port w/external I/F");
1925 rocketModel[i].numPorts = 16;
1927 case PCI_DEVICE_ID_URP16INTF:
1930 rocketModel[i].model = MODEL_UPCI_RP16INTF;
1931 strcpy(rocketModel[i].modelString, "RocketPort UPCI 16 port w/external I/F");
1932 rocketModel[i].numPorts = 16;
1934 case PCI_DEVICE_ID_CRP16INTF:
1937 rocketModel[i].model = MODEL_CPCI_RP16INTF;
1938 strcpy(rocketModel[i].modelString, "RocketPort Compact PCI 16 port w/external I/F");
1939 rocketModel[i].numPorts = 16;
1941 case PCI_DEVICE_ID_RP32INTF:
1944 rocketModel[i].model = MODEL_RP32INTF;
1945 strcpy(rocketModel[i].modelString, "RocketPort 32 port w/external I/F");
1946 rocketModel[i].numPorts = 32;
1948 case PCI_DEVICE_ID_URP32INTF:
1951 rocketModel[i].model = MODEL_UPCI_RP32INTF;
1952 strcpy(rocketModel[i].modelString, "RocketPort UPCI 32 port w/external I/F");
1953 rocketModel[i].numPorts = 32;
1955 case PCI_DEVICE_ID_RPP4:
1956 str = "Plus Quadcable";
1959 altChanRingIndicator++;
1961 rocketModel[i].model = MODEL_RPP4;
1962 strcpy(rocketModel[i].modelString, "RocketPort Plus 4 port");
1963 rocketModel[i].numPorts = 4;
1965 case PCI_DEVICE_ID_RPP8:
1966 str = "Plus Octacable";
1969 altChanRingIndicator++;
1971 rocketModel[i].model = MODEL_RPP8;
1972 strcpy(rocketModel[i].modelString, "RocketPort Plus 8 port");
1973 rocketModel[i].numPorts = 8;
1975 case PCI_DEVICE_ID_RP2_232:
1976 str = "Plus 2 (RS-232)";
1979 altChanRingIndicator++;
1981 rocketModel[i].model = MODEL_RP2_232;
1982 strcpy(rocketModel[i].modelString, "RocketPort Plus 2 port RS232");
1983 rocketModel[i].numPorts = 2;
1985 case PCI_DEVICE_ID_RP2_422:
1986 str = "Plus 2 (RS-422)";
1989 altChanRingIndicator++;
1991 rocketModel[i].model = MODEL_RP2_422;
1992 strcpy(rocketModel[i].modelString, "RocketPort Plus 2 port RS422");
1993 rocketModel[i].numPorts = 2;
1995 case PCI_DEVICE_ID_RP6M:
2001 /* If class_rev is 1, the rocketmodem flash must be loaded. If it is 2 it is a "socketed" version. */
2002 if ((class_rev & 0xFF) == 1) {
2003 rcktpt_type[i] = ROCKET_TYPE_MODEMII;
2004 rocketModel[i].loadrm2 = 1;
2006 rcktpt_type[i] = ROCKET_TYPE_MODEM;
2009 rocketModel[i].model = MODEL_RP6M;
2010 strcpy(rocketModel[i].modelString, "RocketModem 6 port");
2011 rocketModel[i].numPorts = 6;
2013 case PCI_DEVICE_ID_RP4M:
2017 if ((class_rev & 0xFF) == 1) {
2018 rcktpt_type[i] = ROCKET_TYPE_MODEMII;
2019 rocketModel[i].loadrm2 = 1;
2021 rcktpt_type[i] = ROCKET_TYPE_MODEM;
2024 rocketModel[i].model = MODEL_RP4M;
2025 strcpy(rocketModel[i].modelString, "RocketModem 4 port");
2026 rocketModel[i].numPorts = 4;
2029 str = "(unknown/unsupported)";
2035 * Check for UPCI boards.
2038 switch (dev->device) {
2039 case PCI_DEVICE_ID_URP32INTF:
2040 case PCI_DEVICE_ID_URP8INTF:
2041 case PCI_DEVICE_ID_URP16INTF:
2042 case PCI_DEVICE_ID_CRP16INTF:
2043 case PCI_DEVICE_ID_URP8OCTA:
2044 rcktpt_io_addr[i] = pci_resource_start(dev, 2);
2045 ConfigIO = pci_resource_start(dev, 1);
2046 if (dev->device == PCI_DEVICE_ID_URP8OCTA) {
2047 UPCIRingInd = rcktpt_io_addr[i] + _PCI_9030_RING_IND;
2050 * Check for octa or quad cable.
2053 (sInW(ConfigIO + _PCI_9030_GPIO_CTRL) &
2054 PCI_GPIO_CTRL_8PORT)) {
2057 rocketModel[i].numPorts = 4;
2061 case PCI_DEVICE_ID_UPCI_RM3_8PORT:
2064 rocketModel[i].model = MODEL_UPCI_RM3_8PORT;
2065 strcpy(rocketModel[i].modelString, "RocketModem III 8 port");
2066 rocketModel[i].numPorts = 8;
2067 rcktpt_io_addr[i] = pci_resource_start(dev, 2);
2068 UPCIRingInd = rcktpt_io_addr[i] + _PCI_9030_RING_IND;
2069 ConfigIO = pci_resource_start(dev, 1);
2070 rcktpt_type[i] = ROCKET_TYPE_MODEMIII;
2072 case PCI_DEVICE_ID_UPCI_RM3_4PORT:
2075 rocketModel[i].model = MODEL_UPCI_RM3_4PORT;
2076 strcpy(rocketModel[i].modelString, "RocketModem III 4 port");
2077 rocketModel[i].numPorts = 4;
2078 rcktpt_io_addr[i] = pci_resource_start(dev, 2);
2079 UPCIRingInd = rcktpt_io_addr[i] + _PCI_9030_RING_IND;
2080 ConfigIO = pci_resource_start(dev, 1);
2081 rcktpt_type[i] = ROCKET_TYPE_MODEMIII;
2087 switch (rcktpt_type[i]) {
2088 case ROCKET_TYPE_MODEM:
2089 board_type = "RocketModem";
2091 case ROCKET_TYPE_MODEMII:
2092 board_type = "RocketModem II";
2094 case ROCKET_TYPE_MODEMIII:
2095 board_type = "RocketModem III";
2098 board_type = "RocketPort";
2103 sClockPrescale = 0x12; /* mod 2 (divide by 3) */
2104 rp_baud_base[i] = 921600;
2107 * If support_low_speed is set, use the slow clock
2108 * prescale, which supports 50 bps
2110 if (support_low_speed) {
2111 /* mod 9 (divide by 10) prescale */
2112 sClockPrescale = 0x19;
2113 rp_baud_base[i] = 230400;
2115 /* mod 4 (devide by 5) prescale */
2116 sClockPrescale = 0x14;
2117 rp_baud_base[i] = 460800;
2121 for (aiop = 0; aiop < max_num_aiops; aiop++)
2122 aiopio[aiop] = rcktpt_io_addr[i] + (aiop * 0x40);
2123 ctlp = sCtlNumToCtlPtr(i);
2124 num_aiops = sPCIInitController(ctlp, i, aiopio, max_num_aiops, ConfigIO, 0, FREQ_DIS, 0, altChanRingIndicator, UPCIRingInd);
2125 for (aiop = 0; aiop < max_num_aiops; aiop++)
2126 ctlp->AiopNumChan[aiop] = ports_per_aiop;
2128 printk("Comtrol PCI controller #%d ID 0x%x found in bus:slot:fn %s at address %04lx, "
2129 "%d AIOP(s) (%s)\n", i, dev->device, pci_name(dev),
2130 rcktpt_io_addr[i], num_aiops, rocketModel[i].modelString);
2131 printk(KERN_INFO "Installing %s, creating /dev/ttyR%d - %ld\n",
2132 rocketModel[i].modelString,
2133 rocketModel[i].startingPortNumber,
2134 rocketModel[i].startingPortNumber +
2135 rocketModel[i].numPorts - 1);
2137 if (num_aiops <= 0) {
2138 rcktpt_io_addr[i] = 0;
2143 /* Reset the AIOPIC, init the serial ports */
2144 for (aiop = 0; aiop < num_aiops; aiop++) {
2145 sResetAiopByNum(ctlp, aiop);
2146 num_chan = ports_per_aiop;
2147 for (chan = 0; chan < num_chan; chan++)
2148 init_r_port(i, aiop, chan, dev);
2151 /* Rocket modems must be reset */
2152 if ((rcktpt_type[i] == ROCKET_TYPE_MODEM) ||
2153 (rcktpt_type[i] == ROCKET_TYPE_MODEMII) ||
2154 (rcktpt_type[i] == ROCKET_TYPE_MODEMIII)) {
2155 num_chan = ports_per_aiop;
2156 for (chan = 0; chan < num_chan; chan++)
2157 sPCIModemReset(ctlp, chan, 1);
2159 for (chan = 0; chan < num_chan; chan++)
2160 sPCIModemReset(ctlp, chan, 0);
2162 rmSpeakerReset(ctlp, rocketModel[i].model);
2168 * Probes for PCI cards, inits them if found
2169 * Input: board_found = number of ISA boards already found, or the
2170 * starting board number
2171 * Returns: Number of PCI boards found
2173 static int __init init_PCI(int boards_found)
2175 struct pci_dev *dev = NULL;
2178 /* Work through the PCI device list, pulling out ours */
2179 while ((dev = pci_find_device(PCI_VENDOR_ID_RP, PCI_ANY_ID, dev))) {
2180 if (register_PCI(count + boards_found, dev))
2186 #endif /* CONFIG_PCI */
2189 * Probes for ISA cards
2190 * Input: i = the board number to look for
2191 * Returns: 1 if board found, 0 else
2193 static int __init init_ISA(int i)
2195 int num_aiops, num_chan = 0, total_num_chan = 0;
2197 unsigned int aiopio[MAX_AIOPS_PER_BOARD];
2201 /* If io_addr is zero, no board configured */
2202 if (rcktpt_io_addr[i] == 0)
2205 /* Reserve the IO region */
2206 if (!request_region(rcktpt_io_addr[i], 64, "Comtrol RocketPort")) {
2207 printk(KERN_INFO "Unable to reserve IO region for configured ISA RocketPort at address 0x%lx, board not installed...\n", rcktpt_io_addr[i]);
2208 rcktpt_io_addr[i] = 0;
2212 ctlp = sCtlNumToCtlPtr(i);
2214 ctlp->boardType = rcktpt_type[i];
2216 switch (rcktpt_type[i]) {
2217 case ROCKET_TYPE_PC104:
2218 type_string = "(PC104)";
2220 case ROCKET_TYPE_MODEM:
2221 type_string = "(RocketModem)";
2223 case ROCKET_TYPE_MODEMII:
2224 type_string = "(RocketModem II)";
2232 * If support_low_speed is set, use the slow clock prescale,
2233 * which supports 50 bps
2235 if (support_low_speed) {
2236 sClockPrescale = 0x19; /* mod 9 (divide by 10) prescale */
2237 rp_baud_base[i] = 230400;
2239 sClockPrescale = 0x14; /* mod 4 (devide by 5) prescale */
2240 rp_baud_base[i] = 460800;
2243 for (aiop = 0; aiop < MAX_AIOPS_PER_BOARD; aiop++)
2244 aiopio[aiop] = rcktpt_io_addr[i] + (aiop * 0x400);
2246 num_aiops = sInitController(ctlp, i, controller + (i * 0x400), aiopio, MAX_AIOPS_PER_BOARD, 0, FREQ_DIS, 0);
2248 if (ctlp->boardType == ROCKET_TYPE_PC104) {
2249 sEnAiop(ctlp, 2); /* only one AIOPIC, but these */
2250 sEnAiop(ctlp, 3); /* CSels used for other stuff */
2253 /* If something went wrong initing the AIOP's release the ISA IO memory */
2254 if (num_aiops <= 0) {
2255 release_region(rcktpt_io_addr[i], 64);
2256 rcktpt_io_addr[i] = 0;
2260 rocketModel[i].startingPortNumber = nextLineNumber;
2262 for (aiop = 0; aiop < num_aiops; aiop++) {
2263 sResetAiopByNum(ctlp, aiop);
2264 sEnAiop(ctlp, aiop);
2265 num_chan = sGetAiopNumChan(ctlp, aiop);
2266 total_num_chan += num_chan;
2267 for (chan = 0; chan < num_chan; chan++)
2268 init_r_port(i, aiop, chan, NULL);
2271 if ((rcktpt_type[i] == ROCKET_TYPE_MODEM) || (rcktpt_type[i] == ROCKET_TYPE_MODEMII)) {
2272 num_chan = sGetAiopNumChan(ctlp, 0);
2273 total_num_chan = num_chan;
2274 for (chan = 0; chan < num_chan; chan++)
2275 sModemReset(ctlp, chan, 1);
2277 for (chan = 0; chan < num_chan; chan++)
2278 sModemReset(ctlp, chan, 0);
2280 strcpy(rocketModel[i].modelString, "RocketModem ISA");
2282 strcpy(rocketModel[i].modelString, "RocketPort ISA");
2284 rocketModel[i].numPorts = total_num_chan;
2285 rocketModel[i].model = MODEL_ISA;
2287 printk(KERN_INFO "RocketPort ISA card #%d found at 0x%lx - %d AIOPs %s\n",
2288 i, rcktpt_io_addr[i], num_aiops, type_string);
2290 printk(KERN_INFO "Installing %s, creating /dev/ttyR%d - %ld\n",
2291 rocketModel[i].modelString,
2292 rocketModel[i].startingPortNumber,
2293 rocketModel[i].startingPortNumber +
2294 rocketModel[i].numPorts - 1);
2299 static struct tty_operations rocket_ops = {
2303 .put_char = rp_put_char,
2304 .write_room = rp_write_room,
2305 .chars_in_buffer = rp_chars_in_buffer,
2306 .flush_buffer = rp_flush_buffer,
2308 .throttle = rp_throttle,
2309 .unthrottle = rp_unthrottle,
2310 .set_termios = rp_set_termios,
2313 .hangup = rp_hangup,
2314 .break_ctl = rp_break,
2315 .send_xchar = rp_send_xchar,
2316 .wait_until_sent = rp_wait_until_sent,
2317 .tiocmget = rp_tiocmget,
2318 .tiocmset = rp_tiocmset,
2322 * The module "startup" routine; it's run when the module is loaded.
2324 int __init rp_init(void)
2326 int retval, pci_boards_found, isa_boards_found, i;
2328 printk(KERN_INFO "RocketPort device driver module, version %s, %s\n",
2329 ROCKET_VERSION, ROCKET_DATE);
2331 rocket_driver = alloc_tty_driver(MAX_RP_PORTS);
2336 * Set up the timer channel.
2338 init_timer(&rocket_timer);
2339 rocket_timer.function = rp_do_poll;
2342 * Initialize the array of pointers to our own internal state
2345 memset(rp_table, 0, sizeof (rp_table));
2346 memset(xmit_flags, 0, sizeof (xmit_flags));
2348 for (i = 0; i < MAX_RP_PORTS; i++)
2351 memset(rocketModel, 0, sizeof (rocketModel));
2354 * If board 1 is non-zero, there is at least one ISA configured. If controller is
2355 * zero, use the default controller IO address of board1 + 0x40.
2358 if (controller == 0)
2359 controller = board1 + 0x40;
2361 controller = 0; /* Used as a flag, meaning no ISA boards */
2364 /* If an ISA card is configured, reserve the 4 byte IO space for the Mudbac controller */
2365 if (controller && (!request_region(controller, 4, "Comtrol RocketPort"))) {
2366 printk(KERN_INFO "Unable to reserve IO region for first configured ISA RocketPort controller 0x%lx. Driver exiting \n", controller);
2370 /* Store ISA variable retrieved from command line or .conf file. */
2371 rcktpt_io_addr[0] = board1;
2372 rcktpt_io_addr[1] = board2;
2373 rcktpt_io_addr[2] = board3;
2374 rcktpt_io_addr[3] = board4;
2376 rcktpt_type[0] = modem1 ? ROCKET_TYPE_MODEM : ROCKET_TYPE_NORMAL;
2377 rcktpt_type[0] = pc104_1[0] ? ROCKET_TYPE_PC104 : rcktpt_type[0];
2378 rcktpt_type[1] = modem2 ? ROCKET_TYPE_MODEM : ROCKET_TYPE_NORMAL;
2379 rcktpt_type[1] = pc104_2[0] ? ROCKET_TYPE_PC104 : rcktpt_type[1];
2380 rcktpt_type[2] = modem3 ? ROCKET_TYPE_MODEM : ROCKET_TYPE_NORMAL;
2381 rcktpt_type[2] = pc104_3[0] ? ROCKET_TYPE_PC104 : rcktpt_type[2];
2382 rcktpt_type[3] = modem4 ? ROCKET_TYPE_MODEM : ROCKET_TYPE_NORMAL;
2383 rcktpt_type[3] = pc104_4[0] ? ROCKET_TYPE_PC104 : rcktpt_type[3];
2386 * Set up the tty driver structure and then register this
2387 * driver with the tty layer.
2390 rocket_driver->owner = THIS_MODULE;
2391 rocket_driver->flags = TTY_DRIVER_NO_DEVFS;
2392 rocket_driver->devfs_name = "tts/R";
2393 rocket_driver->name = "ttyR";
2394 rocket_driver->driver_name = "Comtrol RocketPort";
2395 rocket_driver->major = TTY_ROCKET_MAJOR;
2396 rocket_driver->minor_start = 0;
2397 rocket_driver->type = TTY_DRIVER_TYPE_SERIAL;
2398 rocket_driver->subtype = SERIAL_TYPE_NORMAL;
2399 rocket_driver->init_termios = tty_std_termios;
2400 rocket_driver->init_termios.c_cflag =
2401 B9600 | CS8 | CREAD | HUPCL | CLOCAL;
2402 #ifdef ROCKET_SOFT_FLOW
2403 rocket_driver->flags |= TTY_DRIVER_REAL_RAW | TTY_DRIVER_NO_DEVFS;
2405 tty_set_operations(rocket_driver, &rocket_ops);
2407 retval = tty_register_driver(rocket_driver);
2409 printk(KERN_INFO "Couldn't install tty RocketPort driver (error %d)\n", -retval);
2410 put_tty_driver(rocket_driver);
2414 #ifdef ROCKET_DEBUG_OPEN
2415 printk(KERN_INFO "RocketPort driver is major %d\n", rocket_driver.major);
2419 * OK, let's probe each of the controllers looking for boards. Any boards found
2420 * will be initialized here.
2422 isa_boards_found = 0;
2423 pci_boards_found = 0;
2425 for (i = 0; i < NUM_BOARDS; i++) {
2431 if (isa_boards_found < NUM_BOARDS)
2432 pci_boards_found = init_PCI(isa_boards_found);
2435 max_board = pci_boards_found + isa_boards_found;
2437 if (max_board == 0) {
2438 printk(KERN_INFO "No rocketport ports found; unloading driver.\n");
2439 del_timer_sync(&rocket_timer);
2440 tty_unregister_driver(rocket_driver);
2441 put_tty_driver(rocket_driver);
2450 static void rp_cleanup_module(void)
2455 del_timer_sync(&rocket_timer);
2457 retval = tty_unregister_driver(rocket_driver);
2459 printk(KERN_INFO "Error %d while trying to unregister "
2460 "rocketport driver\n", -retval);
2461 put_tty_driver(rocket_driver);
2463 for (i = 0; i < MAX_RP_PORTS; i++) {
2468 for (i = 0; i < NUM_BOARDS; i++) {
2469 if (rcktpt_io_addr[i] <= 0 || is_PCI[i])
2471 release_region(rcktpt_io_addr[i], 64);
2474 release_region(controller, 4);
2478 /***********************************************************************
2479 Copyright 1994 Comtrol Corporation.
2480 All Rights Reserved.
2482 The following source code is subject to Comtrol Corporation's
2483 Developer's License Agreement.
2485 This source code is protected by United States copyright law and
2486 international copyright treaties.
2488 This source code may only be used to develop software products that
2489 will operate with Comtrol brand hardware.
2491 You may not reproduce nor distribute this source code in its original
2492 form but must produce a derivative work which includes portions of
2493 this source code only.
2495 The portions of this source code which you use in your derivative
2496 work must bear Comtrol's copyright notice:
2498 Copyright 1994 Comtrol Corporation.
2500 ***********************************************************************/
2510 static Byte_t RData[RDATASIZE] = {
2511 0x00, 0x09, 0xf6, 0x82,
2512 0x02, 0x09, 0x86, 0xfb,
2513 0x04, 0x09, 0x00, 0x0a,
2514 0x06, 0x09, 0x01, 0x0a,
2515 0x08, 0x09, 0x8a, 0x13,
2516 0x0a, 0x09, 0xc5, 0x11,
2517 0x0c, 0x09, 0x86, 0x85,
2518 0x0e, 0x09, 0x20, 0x0a,
2519 0x10, 0x09, 0x21, 0x0a,
2520 0x12, 0x09, 0x41, 0xff,
2521 0x14, 0x09, 0x82, 0x00,
2522 0x16, 0x09, 0x82, 0x7b,
2523 0x18, 0x09, 0x8a, 0x7d,
2524 0x1a, 0x09, 0x88, 0x81,
2525 0x1c, 0x09, 0x86, 0x7a,
2526 0x1e, 0x09, 0x84, 0x81,
2527 0x20, 0x09, 0x82, 0x7c,
2528 0x22, 0x09, 0x0a, 0x0a
2531 static Byte_t RRegData[RREGDATASIZE] = {
2532 0x00, 0x09, 0xf6, 0x82, /* 00: Stop Rx processor */
2533 0x08, 0x09, 0x8a, 0x13, /* 04: Tx software flow control */
2534 0x0a, 0x09, 0xc5, 0x11, /* 08: XON char */
2535 0x0c, 0x09, 0x86, 0x85, /* 0c: XANY */
2536 0x12, 0x09, 0x41, 0xff, /* 10: Rx mask char */
2537 0x14, 0x09, 0x82, 0x00, /* 14: Compare/Ignore #0 */
2538 0x16, 0x09, 0x82, 0x7b, /* 18: Compare #1 */
2539 0x18, 0x09, 0x8a, 0x7d, /* 1c: Compare #2 */
2540 0x1a, 0x09, 0x88, 0x81, /* 20: Interrupt #1 */
2541 0x1c, 0x09, 0x86, 0x7a, /* 24: Ignore/Replace #1 */
2542 0x1e, 0x09, 0x84, 0x81, /* 28: Interrupt #2 */
2543 0x20, 0x09, 0x82, 0x7c, /* 2c: Ignore/Replace #2 */
2544 0x22, 0x09, 0x0a, 0x0a /* 30: Rx FIFO Enable */
2547 CONTROLLER_T sController[CTL_SIZE] = {
2548 {-1, -1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, {0, 0, 0, 0},
2549 {0, 0, 0, 0}, {-1, -1, -1, -1}, {0, 0, 0, 0}},
2550 {-1, -1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, {0, 0, 0, 0},
2551 {0, 0, 0, 0}, {-1, -1, -1, -1}, {0, 0, 0, 0}},
2552 {-1, -1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, {0, 0, 0, 0},
2553 {0, 0, 0, 0}, {-1, -1, -1, -1}, {0, 0, 0, 0}},
2554 {-1, -1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, {0, 0, 0, 0},
2555 {0, 0, 0, 0}, {-1, -1, -1, -1}, {0, 0, 0, 0}}
2558 Byte_t sBitMapClrTbl[8] = {
2559 0xfe, 0xfd, 0xfb, 0xf7, 0xef, 0xdf, 0xbf, 0x7f
2562 Byte_t sBitMapSetTbl[8] = {
2563 0x01, 0x02, 0x04, 0x08, 0x10, 0x20, 0x40, 0x80
2566 int sClockPrescale = 0x14;
2568 /***************************************************************************
2569 Function: sInitController
2570 Purpose: Initialization of controller global registers and controller
2572 Call: sInitController(CtlP,CtlNum,MudbacIO,AiopIOList,AiopIOListSize,
2573 IRQNum,Frequency,PeriodicOnly)
2574 CONTROLLER_T *CtlP; Ptr to controller structure
2575 int CtlNum; Controller number
2576 ByteIO_t MudbacIO; Mudbac base I/O address.
2577 ByteIO_t *AiopIOList; List of I/O addresses for each AIOP.
2578 This list must be in the order the AIOPs will be found on the
2579 controller. Once an AIOP in the list is not found, it is
2580 assumed that there are no more AIOPs on the controller.
2581 int AiopIOListSize; Number of addresses in AiopIOList
2582 int IRQNum; Interrupt Request number. Can be any of the following:
2583 0: Disable global interrupts
2592 Byte_t Frequency: A flag identifying the frequency
2593 of the periodic interrupt, can be any one of the following:
2594 FREQ_DIS - periodic interrupt disabled
2595 FREQ_137HZ - 137 Hertz
2596 FREQ_69HZ - 69 Hertz
2597 FREQ_34HZ - 34 Hertz
2598 FREQ_17HZ - 17 Hertz
2601 If IRQNum is set to 0 the Frequency parameter is
2602 overidden, it is forced to a value of FREQ_DIS.
2603 int PeriodicOnly: TRUE if all interrupts except the periodic
2604 interrupt are to be blocked.
2605 FALSE is both the periodic interrupt and
2606 other channel interrupts are allowed.
2607 If IRQNum is set to 0 the PeriodicOnly parameter is
2608 overidden, it is forced to a value of FALSE.
2609 Return: int: Number of AIOPs on the controller, or CTLID_NULL if controller
2610 initialization failed.
2613 If periodic interrupts are to be disabled but AIOP interrupts
2614 are allowed, set Frequency to FREQ_DIS and PeriodicOnly to FALSE.
2616 If interrupts are to be completely disabled set IRQNum to 0.
2618 Setting Frequency to FREQ_DIS and PeriodicOnly to TRUE is an
2619 invalid combination.
2621 This function performs initialization of global interrupt modes,
2622 but it does not actually enable global interrupts. To enable
2623 and disable global interrupts use functions sEnGlobalInt() and
2624 sDisGlobalInt(). Enabling of global interrupts is normally not
2625 done until all other initializations are complete.
2627 Even if interrupts are globally enabled, they must also be
2628 individually enabled for each channel that is to generate
2631 Warnings: No range checking on any of the parameters is done.
2633 No context switches are allowed while executing this function.
2635 After this function all AIOPs on the controller are disabled,
2636 they can be enabled with sEnAiop().
2638 int sInitController(CONTROLLER_T * CtlP, int CtlNum, ByteIO_t MudbacIO,
2639 ByteIO_t * AiopIOList, int AiopIOListSize, int IRQNum,
2640 Byte_t Frequency, int PeriodicOnly)
2646 CtlP->AiopIntrBits = aiop_intr_bits;
2647 CtlP->AltChanRingIndicator = 0;
2648 CtlP->CtlNum = CtlNum;
2649 CtlP->CtlID = CTLID_0001; /* controller release 1 */
2650 CtlP->BusType = isISA;
2651 CtlP->MBaseIO = MudbacIO;
2652 CtlP->MReg1IO = MudbacIO + 1;
2653 CtlP->MReg2IO = MudbacIO + 2;
2654 CtlP->MReg3IO = MudbacIO + 3;
2656 CtlP->MReg2 = 0; /* interrupt disable */
2657 CtlP->MReg3 = 0; /* no periodic interrupts */
2659 if (sIRQMap[IRQNum] == 0) { /* interrupts globally disabled */
2660 CtlP->MReg2 = 0; /* interrupt disable */
2661 CtlP->MReg3 = 0; /* no periodic interrupts */
2663 CtlP->MReg2 = sIRQMap[IRQNum]; /* set IRQ number */
2664 CtlP->MReg3 = Frequency; /* set frequency */
2665 if (PeriodicOnly) { /* periodic interrupt only */
2666 CtlP->MReg3 |= PERIODIC_ONLY;
2670 sOutB(CtlP->MReg2IO, CtlP->MReg2);
2671 sOutB(CtlP->MReg3IO, CtlP->MReg3);
2672 sControllerEOI(CtlP); /* clear EOI if warm init */
2675 for (i = done = 0; i < AiopIOListSize; i++) {
2677 CtlP->AiopIO[i] = (WordIO_t) io;
2678 CtlP->AiopIntChanIO[i] = io + _INT_CHAN;
2679 sOutB(CtlP->MReg2IO, CtlP->MReg2 | (i & 0x03)); /* AIOP index */
2680 sOutB(MudbacIO, (Byte_t) (io >> 6)); /* set up AIOP I/O in MUDBAC */
2683 sEnAiop(CtlP, i); /* enable the AIOP */
2684 CtlP->AiopID[i] = sReadAiopID(io); /* read AIOP ID */
2685 if (CtlP->AiopID[i] == AIOPID_NULL) /* if AIOP does not exist */
2686 done = 1; /* done looking for AIOPs */
2688 CtlP->AiopNumChan[i] = sReadAiopNumChan((WordIO_t) io); /* num channels in AIOP */
2689 sOutW((WordIO_t) io + _INDX_ADDR, _CLK_PRE); /* clock prescaler */
2690 sOutB(io + _INDX_DATA, sClockPrescale);
2691 CtlP->NumAiop++; /* bump count of AIOPs */
2693 sDisAiop(CtlP, i); /* disable AIOP */
2696 if (CtlP->NumAiop == 0)
2699 return (CtlP->NumAiop);
2702 /***************************************************************************
2703 Function: sPCIInitController
2704 Purpose: Initialization of controller global registers and controller
2706 Call: sPCIInitController(CtlP,CtlNum,AiopIOList,AiopIOListSize,
2707 IRQNum,Frequency,PeriodicOnly)
2708 CONTROLLER_T *CtlP; Ptr to controller structure
2709 int CtlNum; Controller number
2710 ByteIO_t *AiopIOList; List of I/O addresses for each AIOP.
2711 This list must be in the order the AIOPs will be found on the
2712 controller. Once an AIOP in the list is not found, it is
2713 assumed that there are no more AIOPs on the controller.
2714 int AiopIOListSize; Number of addresses in AiopIOList
2715 int IRQNum; Interrupt Request number. Can be any of the following:
2716 0: Disable global interrupts
2725 Byte_t Frequency: A flag identifying the frequency
2726 of the periodic interrupt, can be any one of the following:
2727 FREQ_DIS - periodic interrupt disabled
2728 FREQ_137HZ - 137 Hertz
2729 FREQ_69HZ - 69 Hertz
2730 FREQ_34HZ - 34 Hertz
2731 FREQ_17HZ - 17 Hertz
2734 If IRQNum is set to 0 the Frequency parameter is
2735 overidden, it is forced to a value of FREQ_DIS.
2736 int PeriodicOnly: TRUE if all interrupts except the periodic
2737 interrupt are to be blocked.
2738 FALSE is both the periodic interrupt and
2739 other channel interrupts are allowed.
2740 If IRQNum is set to 0 the PeriodicOnly parameter is
2741 overidden, it is forced to a value of FALSE.
2742 Return: int: Number of AIOPs on the controller, or CTLID_NULL if controller
2743 initialization failed.
2746 If periodic interrupts are to be disabled but AIOP interrupts
2747 are allowed, set Frequency to FREQ_DIS and PeriodicOnly to FALSE.
2749 If interrupts are to be completely disabled set IRQNum to 0.
2751 Setting Frequency to FREQ_DIS and PeriodicOnly to TRUE is an
2752 invalid combination.
2754 This function performs initialization of global interrupt modes,
2755 but it does not actually enable global interrupts. To enable
2756 and disable global interrupts use functions sEnGlobalInt() and
2757 sDisGlobalInt(). Enabling of global interrupts is normally not
2758 done until all other initializations are complete.
2760 Even if interrupts are globally enabled, they must also be
2761 individually enabled for each channel that is to generate
2764 Warnings: No range checking on any of the parameters is done.
2766 No context switches are allowed while executing this function.
2768 After this function all AIOPs on the controller are disabled,
2769 they can be enabled with sEnAiop().
2771 int sPCIInitController(CONTROLLER_T * CtlP, int CtlNum,
2772 ByteIO_t * AiopIOList, int AiopIOListSize,
2773 WordIO_t ConfigIO, int IRQNum, Byte_t Frequency,
2774 int PeriodicOnly, int altChanRingIndicator,
2780 CtlP->AltChanRingIndicator = altChanRingIndicator;
2781 CtlP->UPCIRingInd = UPCIRingInd;
2782 CtlP->CtlNum = CtlNum;
2783 CtlP->CtlID = CTLID_0001; /* controller release 1 */
2784 CtlP->BusType = isPCI; /* controller release 1 */
2788 CtlP->PCIIO = ConfigIO + _PCI_9030_INT_CTRL;
2789 CtlP->PCIIO2 = ConfigIO + _PCI_9030_GPIO_CTRL;
2790 CtlP->AiopIntrBits = upci_aiop_intr_bits;
2794 (WordIO_t) ((ByteIO_t) AiopIOList[0] + _PCI_INT_FUNC);
2795 CtlP->AiopIntrBits = aiop_intr_bits;
2798 sPCIControllerEOI(CtlP); /* clear EOI if warm init */
2801 for (i = 0; i < AiopIOListSize; i++) {
2803 CtlP->AiopIO[i] = (WordIO_t) io;
2804 CtlP->AiopIntChanIO[i] = io + _INT_CHAN;
2806 CtlP->AiopID[i] = sReadAiopID(io); /* read AIOP ID */
2807 if (CtlP->AiopID[i] == AIOPID_NULL) /* if AIOP does not exist */
2808 break; /* done looking for AIOPs */
2810 CtlP->AiopNumChan[i] = sReadAiopNumChan((WordIO_t) io); /* num channels in AIOP */
2811 sOutW((WordIO_t) io + _INDX_ADDR, _CLK_PRE); /* clock prescaler */
2812 sOutB(io + _INDX_DATA, sClockPrescale);
2813 CtlP->NumAiop++; /* bump count of AIOPs */
2816 if (CtlP->NumAiop == 0)
2819 return (CtlP->NumAiop);
2822 /***************************************************************************
2823 Function: sReadAiopID
2824 Purpose: Read the AIOP idenfication number directly from an AIOP.
2825 Call: sReadAiopID(io)
2826 ByteIO_t io: AIOP base I/O address
2827 Return: int: Flag AIOPID_XXXX if a valid AIOP is found, where X
2828 is replace by an identifying number.
2829 Flag AIOPID_NULL if no valid AIOP is found
2830 Warnings: No context switches are allowed while executing this function.
2833 int sReadAiopID(ByteIO_t io)
2835 Byte_t AiopID; /* ID byte from AIOP */
2837 sOutB(io + _CMD_REG, RESET_ALL); /* reset AIOP */
2838 sOutB(io + _CMD_REG, 0x0);
2839 AiopID = sInW(io + _CHN_STAT0) & 0x07;
2842 else /* AIOP does not exist */
2846 /***************************************************************************
2847 Function: sReadAiopNumChan
2848 Purpose: Read the number of channels available in an AIOP directly from
2850 Call: sReadAiopNumChan(io)
2851 WordIO_t io: AIOP base I/O address
2852 Return: int: The number of channels available
2853 Comments: The number of channels is determined by write/reads from identical
2854 offsets within the SRAM address spaces for channels 0 and 4.
2855 If the channel 4 space is mirrored to channel 0 it is a 4 channel
2856 AIOP, otherwise it is an 8 channel.
2857 Warnings: No context switches are allowed while executing this function.
2859 int sReadAiopNumChan(WordIO_t io)
2862 static Byte_t R[4] = { 0x00, 0x00, 0x34, 0x12 };
2864 /* write to chan 0 SRAM */
2865 sOutDW((DWordIO_t) io + _INDX_ADDR, *((DWord_t *) & R[0]));
2866 sOutW(io + _INDX_ADDR, 0); /* read from SRAM, chan 0 */
2867 x = sInW(io + _INDX_DATA);
2868 sOutW(io + _INDX_ADDR, 0x4000); /* read from SRAM, chan 4 */
2869 if (x != sInW(io + _INDX_DATA)) /* if different must be 8 chan */
2875 /***************************************************************************
2877 Purpose: Initialization of a channel and channel structure
2878 Call: sInitChan(CtlP,ChP,AiopNum,ChanNum)
2879 CONTROLLER_T *CtlP; Ptr to controller structure
2880 CHANNEL_T *ChP; Ptr to channel structure
2881 int AiopNum; AIOP number within controller
2882 int ChanNum; Channel number within AIOP
2883 Return: int: TRUE if initialization succeeded, FALSE if it fails because channel
2884 number exceeds number of channels available in AIOP.
2885 Comments: This function must be called before a channel can be used.
2886 Warnings: No range checking on any of the parameters is done.
2888 No context switches are allowed while executing this function.
2890 int sInitChan(CONTROLLER_T * CtlP, CHANNEL_T * ChP, int AiopNum,
2901 if (ChanNum >= CtlP->AiopNumChan[AiopNum])
2902 return (FALSE); /* exceeds num chans in AIOP */
2904 /* Channel, AIOP, and controller identifiers */
2906 ChP->ChanID = CtlP->AiopID[AiopNum];
2907 ChP->AiopNum = AiopNum;
2908 ChP->ChanNum = ChanNum;
2910 /* Global direct addresses */
2911 AiopIO = CtlP->AiopIO[AiopNum];
2912 ChP->Cmd = (ByteIO_t) AiopIO + _CMD_REG;
2913 ChP->IntChan = (ByteIO_t) AiopIO + _INT_CHAN;
2914 ChP->IntMask = (ByteIO_t) AiopIO + _INT_MASK;
2915 ChP->IndexAddr = (DWordIO_t) AiopIO + _INDX_ADDR;
2916 ChP->IndexData = AiopIO + _INDX_DATA;
2918 /* Channel direct addresses */
2919 ChIOOff = AiopIO + ChP->ChanNum * 2;
2920 ChP->TxRxData = ChIOOff + _TD0;
2921 ChP->ChanStat = ChIOOff + _CHN_STAT0;
2922 ChP->TxRxCount = ChIOOff + _FIFO_CNT0;
2923 ChP->IntID = (ByteIO_t) AiopIO + ChP->ChanNum + _INT_ID0;
2925 /* Initialize the channel from the RData array */
2926 for (i = 0; i < RDATASIZE; i += 4) {
2928 R[1] = RData[i + 1] + 0x10 * ChanNum;
2929 R[2] = RData[i + 2];
2930 R[3] = RData[i + 3];
2931 sOutDW(ChP->IndexAddr, *((DWord_t *) & R[0]));
2935 for (i = 0; i < RREGDATASIZE; i += 4) {
2936 ChR[i] = RRegData[i];
2937 ChR[i + 1] = RRegData[i + 1] + 0x10 * ChanNum;
2938 ChR[i + 2] = RRegData[i + 2];
2939 ChR[i + 3] = RRegData[i + 3];
2942 /* Indexed registers */
2943 ChOff = (Word_t) ChanNum *0x1000;
2945 if (sClockPrescale == 0x14)
2950 ChP->BaudDiv[0] = (Byte_t) (ChOff + _BAUD);
2951 ChP->BaudDiv[1] = (Byte_t) ((ChOff + _BAUD) >> 8);
2952 ChP->BaudDiv[2] = (Byte_t) brd9600;
2953 ChP->BaudDiv[3] = (Byte_t) (brd9600 >> 8);
2954 sOutDW(ChP->IndexAddr, *(DWord_t *) & ChP->BaudDiv[0]);
2956 ChP->TxControl[0] = (Byte_t) (ChOff + _TX_CTRL);
2957 ChP->TxControl[1] = (Byte_t) ((ChOff + _TX_CTRL) >> 8);
2958 ChP->TxControl[2] = 0;
2959 ChP->TxControl[3] = 0;
2960 sOutDW(ChP->IndexAddr, *(DWord_t *) & ChP->TxControl[0]);
2962 ChP->RxControl[0] = (Byte_t) (ChOff + _RX_CTRL);
2963 ChP->RxControl[1] = (Byte_t) ((ChOff + _RX_CTRL) >> 8);
2964 ChP->RxControl[2] = 0;
2965 ChP->RxControl[3] = 0;
2966 sOutDW(ChP->IndexAddr, *(DWord_t *) & ChP->RxControl[0]);
2968 ChP->TxEnables[0] = (Byte_t) (ChOff + _TX_ENBLS);
2969 ChP->TxEnables[1] = (Byte_t) ((ChOff + _TX_ENBLS) >> 8);
2970 ChP->TxEnables[2] = 0;
2971 ChP->TxEnables[3] = 0;
2972 sOutDW(ChP->IndexAddr, *(DWord_t *) & ChP->TxEnables[0]);
2974 ChP->TxCompare[0] = (Byte_t) (ChOff + _TXCMP1);
2975 ChP->TxCompare[1] = (Byte_t) ((ChOff + _TXCMP1) >> 8);
2976 ChP->TxCompare[2] = 0;
2977 ChP->TxCompare[3] = 0;
2978 sOutDW(ChP->IndexAddr, *(DWord_t *) & ChP->TxCompare[0]);
2980 ChP->TxReplace1[0] = (Byte_t) (ChOff + _TXREP1B1);
2981 ChP->TxReplace1[1] = (Byte_t) ((ChOff + _TXREP1B1) >> 8);
2982 ChP->TxReplace1[2] = 0;
2983 ChP->TxReplace1[3] = 0;
2984 sOutDW(ChP->IndexAddr, *(DWord_t *) & ChP->TxReplace1[0]);
2986 ChP->TxReplace2[0] = (Byte_t) (ChOff + _TXREP2);
2987 ChP->TxReplace2[1] = (Byte_t) ((ChOff + _TXREP2) >> 8);
2988 ChP->TxReplace2[2] = 0;
2989 ChP->TxReplace2[3] = 0;
2990 sOutDW(ChP->IndexAddr, *(DWord_t *) & ChP->TxReplace2[0]);
2992 ChP->TxFIFOPtrs = ChOff + _TXF_OUTP;
2993 ChP->TxFIFO = ChOff + _TX_FIFO;
2995 sOutB(ChP->Cmd, (Byte_t) ChanNum | RESTXFCNT); /* apply reset Tx FIFO count */
2996 sOutB(ChP->Cmd, (Byte_t) ChanNum); /* remove reset Tx FIFO count */
2997 sOutW((WordIO_t) ChP->IndexAddr, ChP->TxFIFOPtrs); /* clear Tx in/out ptrs */
2998 sOutW(ChP->IndexData, 0);
2999 ChP->RxFIFOPtrs = ChOff + _RXF_OUTP;
3000 ChP->RxFIFO = ChOff + _RX_FIFO;
3002 sOutB(ChP->Cmd, (Byte_t) ChanNum | RESRXFCNT); /* apply reset Rx FIFO count */
3003 sOutB(ChP->Cmd, (Byte_t) ChanNum); /* remove reset Rx FIFO count */
3004 sOutW((WordIO_t) ChP->IndexAddr, ChP->RxFIFOPtrs); /* clear Rx out ptr */
3005 sOutW(ChP->IndexData, 0);
3006 sOutW((WordIO_t) ChP->IndexAddr, ChP->RxFIFOPtrs + 2); /* clear Rx in ptr */
3007 sOutW(ChP->IndexData, 0);
3008 ChP->TxPrioCnt = ChOff + _TXP_CNT;
3009 sOutW((WordIO_t) ChP->IndexAddr, ChP->TxPrioCnt);
3010 sOutB(ChP->IndexData, 0);
3011 ChP->TxPrioPtr = ChOff + _TXP_PNTR;
3012 sOutW((WordIO_t) ChP->IndexAddr, ChP->TxPrioPtr);
3013 sOutB(ChP->IndexData, 0);
3014 ChP->TxPrioBuf = ChOff + _TXP_BUF;
3015 sEnRxProcessor(ChP); /* start the Rx processor */
3020 /***************************************************************************
3021 Function: sStopRxProcessor
3022 Purpose: Stop the receive processor from processing a channel.
3023 Call: sStopRxProcessor(ChP)
3024 CHANNEL_T *ChP; Ptr to channel structure
3026 Comments: The receive processor can be started again with sStartRxProcessor().
3027 This function causes the receive processor to skip over the
3028 stopped channel. It does not stop it from processing other channels.
3030 Warnings: No context switches are allowed while executing this function.
3032 Do not leave the receive processor stopped for more than one
3035 After calling this function a delay of 4 uS is required to ensure
3036 that the receive processor is no longer processing this channel.
3038 void sStopRxProcessor(CHANNEL_T * ChP)
3046 sOutDW(ChP->IndexAddr, *(DWord_t *) & R[0]);
3049 /***************************************************************************
3050 Function: sFlushRxFIFO
3051 Purpose: Flush the Rx FIFO
3052 Call: sFlushRxFIFO(ChP)
3053 CHANNEL_T *ChP; Ptr to channel structure
3055 Comments: To prevent data from being enqueued or dequeued in the Tx FIFO
3056 while it is being flushed the receive processor is stopped
3057 and the transmitter is disabled. After these operations a
3058 4 uS delay is done before clearing the pointers to allow
3059 the receive processor to stop. These items are handled inside
3061 Warnings: No context switches are allowed while executing this function.
3063 void sFlushRxFIFO(CHANNEL_T * ChP)
3066 Byte_t Ch; /* channel number within AIOP */
3067 int RxFIFOEnabled; /* TRUE if Rx FIFO enabled */
3069 if (sGetRxCnt(ChP) == 0) /* Rx FIFO empty */
3070 return; /* don't need to flush */
3072 RxFIFOEnabled = FALSE;
3073 if (ChP->R[0x32] == 0x08) { /* Rx FIFO is enabled */
3074 RxFIFOEnabled = TRUE;
3075 sDisRxFIFO(ChP); /* disable it */
3076 for (i = 0; i < 2000 / 200; i++) /* delay 2 uS to allow proc to disable FIFO */
3077 sInB(ChP->IntChan); /* depends on bus i/o timing */
3079 sGetChanStatus(ChP); /* clear any pending Rx errors in chan stat */
3080 Ch = (Byte_t) sGetChanNum(ChP);
3081 sOutB(ChP->Cmd, Ch | RESRXFCNT); /* apply reset Rx FIFO count */
3082 sOutB(ChP->Cmd, Ch); /* remove reset Rx FIFO count */
3083 sOutW((WordIO_t) ChP->IndexAddr, ChP->RxFIFOPtrs); /* clear Rx out ptr */
3084 sOutW(ChP->IndexData, 0);
3085 sOutW((WordIO_t) ChP->IndexAddr, ChP->RxFIFOPtrs + 2); /* clear Rx in ptr */
3086 sOutW(ChP->IndexData, 0);
3088 sEnRxFIFO(ChP); /* enable Rx FIFO */
3091 /***************************************************************************
3092 Function: sFlushTxFIFO
3093 Purpose: Flush the Tx FIFO
3094 Call: sFlushTxFIFO(ChP)
3095 CHANNEL_T *ChP; Ptr to channel structure
3097 Comments: To prevent data from being enqueued or dequeued in the Tx FIFO
3098 while it is being flushed the receive processor is stopped
3099 and the transmitter is disabled. After these operations a
3100 4 uS delay is done before clearing the pointers to allow
3101 the receive processor to stop. These items are handled inside
3103 Warnings: No context switches are allowed while executing this function.
3105 void sFlushTxFIFO(CHANNEL_T * ChP)
3108 Byte_t Ch; /* channel number within AIOP */
3109 int TxEnabled; /* TRUE if transmitter enabled */
3111 if (sGetTxCnt(ChP) == 0) /* Tx FIFO empty */
3112 return; /* don't need to flush */
3115 if (ChP->TxControl[3] & TX_ENABLE) {
3117 sDisTransmit(ChP); /* disable transmitter */
3119 sStopRxProcessor(ChP); /* stop Rx processor */
3120 for (i = 0; i < 4000 / 200; i++) /* delay 4 uS to allow proc to stop */
3121 sInB(ChP->IntChan); /* depends on bus i/o timing */
3122 Ch = (Byte_t) sGetChanNum(ChP);
3123 sOutB(ChP->Cmd, Ch | RESTXFCNT); /* apply reset Tx FIFO count */
3124 sOutB(ChP->Cmd, Ch); /* remove reset Tx FIFO count */
3125 sOutW((WordIO_t) ChP->IndexAddr, ChP->TxFIFOPtrs); /* clear Tx in/out ptrs */
3126 sOutW(ChP->IndexData, 0);
3128 sEnTransmit(ChP); /* enable transmitter */
3129 sStartRxProcessor(ChP); /* restart Rx processor */
3132 /***************************************************************************
3133 Function: sWriteTxPrioByte
3134 Purpose: Write a byte of priority transmit data to a channel
3135 Call: sWriteTxPrioByte(ChP,Data)
3136 CHANNEL_T *ChP; Ptr to channel structure
3137 Byte_t Data; The transmit data byte
3139 Return: int: 1 if the bytes is successfully written, otherwise 0.
3141 Comments: The priority byte is transmitted before any data in the Tx FIFO.
3143 Warnings: No context switches are allowed while executing this function.
3145 int sWriteTxPrioByte(CHANNEL_T * ChP, Byte_t Data)
3147 Byte_t DWBuf[4]; /* buffer for double word writes */
3148 Word_t *WordPtr; /* must be far because Win SS != DS */
3149 register DWordIO_t IndexAddr;
3151 if (sGetTxCnt(ChP) > 1) { /* write it to Tx priority buffer */
3152 IndexAddr = ChP->IndexAddr;
3153 sOutW((WordIO_t) IndexAddr, ChP->TxPrioCnt); /* get priority buffer status */
3154 if (sInB((ByteIO_t) ChP->IndexData) & PRI_PEND) /* priority buffer busy */
3155 return (0); /* nothing sent */
3157 WordPtr = (Word_t *) (&DWBuf[0]);
3158 *WordPtr = ChP->TxPrioBuf; /* data byte address */
3160 DWBuf[2] = Data; /* data byte value */
3161 sOutDW(IndexAddr, *((DWord_t *) (&DWBuf[0]))); /* write it out */
3163 *WordPtr = ChP->TxPrioCnt; /* Tx priority count address */
3165 DWBuf[2] = PRI_PEND + 1; /* indicate 1 byte pending */
3166 DWBuf[3] = 0; /* priority buffer pointer */
3167 sOutDW(IndexAddr, *((DWord_t *) (&DWBuf[0]))); /* write it out */
3168 } else { /* write it to Tx FIFO */
3170 sWriteTxByte(sGetTxRxDataIO(ChP), Data);
3172 return (1); /* 1 byte sent */
3175 /***************************************************************************
3176 Function: sEnInterrupts
3177 Purpose: Enable one or more interrupts for a channel
3178 Call: sEnInterrupts(ChP,Flags)
3179 CHANNEL_T *ChP; Ptr to channel structure
3180 Word_t Flags: Interrupt enable flags, can be any combination
3181 of the following flags:
3182 TXINT_EN: Interrupt on Tx FIFO empty
3183 RXINT_EN: Interrupt on Rx FIFO at trigger level (see
3185 SRCINT_EN: Interrupt on SRC (Special Rx Condition)
3186 MCINT_EN: Interrupt on modem input change
3187 CHANINT_EN: Allow channel interrupt signal to the AIOP's
3188 Interrupt Channel Register.
3190 Comments: If an interrupt enable flag is set in Flags, that interrupt will be
3191 enabled. If an interrupt enable flag is not set in Flags, that
3192 interrupt will not be changed. Interrupts can be disabled with
3193 function sDisInterrupts().
3195 This function sets the appropriate bit for the channel in the AIOP's
3196 Interrupt Mask Register if the CHANINT_EN flag is set. This allows
3197 this channel's bit to be set in the AIOP's Interrupt Channel Register.
3199 Interrupts must also be globally enabled before channel interrupts
3200 will be passed on to the host. This is done with function
3203 In some cases it may be desirable to disable interrupts globally but
3204 enable channel interrupts. This would allow the global interrupt
3205 status register to be used to determine which AIOPs need service.
3207 void sEnInterrupts(CHANNEL_T * ChP, Word_t Flags)
3209 Byte_t Mask; /* Interrupt Mask Register */
3211 ChP->RxControl[2] |=
3212 ((Byte_t) Flags & (RXINT_EN | SRCINT_EN | MCINT_EN));
3214 sOutDW(ChP->IndexAddr, *(DWord_t *) & ChP->RxControl[0]);
3216 ChP->TxControl[2] |= ((Byte_t) Flags & TXINT_EN);
3218 sOutDW(ChP->IndexAddr, *(DWord_t *) & ChP->TxControl[0]);
3220 if (Flags & CHANINT_EN) {
3221 Mask = sInB(ChP->IntMask) | sBitMapSetTbl[ChP->ChanNum];
3222 sOutB(ChP->IntMask, Mask);
3226 /***************************************************************************
3227 Function: sDisInterrupts
3228 Purpose: Disable one or more interrupts for a channel
3229 Call: sDisInterrupts(ChP,Flags)
3230 CHANNEL_T *ChP; Ptr to channel structure
3231 Word_t Flags: Interrupt flags, can be any combination
3232 of the following flags:
3233 TXINT_EN: Interrupt on Tx FIFO empty
3234 RXINT_EN: Interrupt on Rx FIFO at trigger level (see
3236 SRCINT_EN: Interrupt on SRC (Special Rx Condition)
3237 MCINT_EN: Interrupt on modem input change
3238 CHANINT_EN: Disable channel interrupt signal to the
3239 AIOP's Interrupt Channel Register.
3241 Comments: If an interrupt flag is set in Flags, that interrupt will be
3242 disabled. If an interrupt flag is not set in Flags, that
3243 interrupt will not be changed. Interrupts can be enabled with
3244 function sEnInterrupts().
3246 This function clears the appropriate bit for the channel in the AIOP's
3247 Interrupt Mask Register if the CHANINT_EN flag is set. This blocks
3248 this channel's bit from being set in the AIOP's Interrupt Channel
3251 void sDisInterrupts(CHANNEL_T * ChP, Word_t Flags)
3253 Byte_t Mask; /* Interrupt Mask Register */
3255 ChP->RxControl[2] &=
3256 ~((Byte_t) Flags & (RXINT_EN | SRCINT_EN | MCINT_EN));
3257 sOutDW(ChP->IndexAddr, *(DWord_t *) & ChP->RxControl[0]);
3258 ChP->TxControl[2] &= ~((Byte_t) Flags & TXINT_EN);
3259 sOutDW(ChP->IndexAddr, *(DWord_t *) & ChP->TxControl[0]);
3261 if (Flags & CHANINT_EN) {
3262 Mask = sInB(ChP->IntMask) & sBitMapClrTbl[ChP->ChanNum];
3263 sOutB(ChP->IntMask, Mask);
3267 void sSetInterfaceMode(CHANNEL_T * ChP, Byte_t mode)
3269 sOutB(ChP->CtlP->AiopIO[2], (mode & 0x18) | ChP->ChanNum);
3273 * Not an official SSCI function, but how to reset RocketModems.
3276 void sModemReset(CONTROLLER_T * CtlP, int chan, int on)
3281 addr = CtlP->AiopIO[0] + 0x400;
3282 val = sInB(CtlP->MReg3IO);
3283 /* if AIOP[1] is not enabled, enable it */
3284 if ((val & 2) == 0) {
3285 val = sInB(CtlP->MReg2IO);
3286 sOutB(CtlP->MReg2IO, (val & 0xfc) | (1 & 0x03));
3287 sOutB(CtlP->MBaseIO, (unsigned char) (addr >> 6));
3293 sOutB(addr + chan, 0); /* apply or remove reset */
3298 * Not an official SSCI function, but how to reset RocketModems.
3301 void sPCIModemReset(CONTROLLER_T * CtlP, int chan, int on)
3305 addr = CtlP->AiopIO[0] + 0x40; /* 2nd AIOP */
3308 sOutB(addr + chan, 0); /* apply or remove reset */
3311 /* Resets the speaker controller on RocketModem II and III devices */
3312 static void rmSpeakerReset(CONTROLLER_T * CtlP, unsigned long model)
3316 /* RocketModem II speaker control is at the 8th port location of offset 0x40 */
3317 if ((model == MODEL_RP4M) || (model == MODEL_RP6M)) {
3318 addr = CtlP->AiopIO[0] + 0x4F;
3322 /* RocketModem III speaker control is at the 1st port location of offset 0x80 */
3323 if ((model == MODEL_UPCI_RM3_8PORT)
3324 || (model == MODEL_UPCI_RM3_4PORT)) {
3325 addr = CtlP->AiopIO[0] + 0x88;
3330 /* Returns the line number given the controller (board), aiop and channel number */
3331 static unsigned char GetLineNumber(int ctrl, int aiop, int ch)
3333 return lineNumbers[(ctrl << 5) | (aiop << 3) | ch];
3337 * Stores the line number associated with a given controller (board), aiop
3338 * and channel number.
3339 * Returns: The line number assigned
3341 static unsigned char SetLineNumber(int ctrl, int aiop, int ch)
3343 lineNumbers[(ctrl << 5) | (aiop << 3) | ch] = nextLineNumber++;
3344 return (nextLineNumber - 1);