1 /* $Id: sh-sci.h,v 1.7 2004/02/10 17:04:17 lethal Exp $
3 * linux/drivers/char/sh-sci.h
5 * SuperH on-chip serial module support. (SCI with no FIFO / with FIFO)
6 * Copyright (C) 1999, 2000 Niibe Yutaka
7 * Copyright (C) 2000 Greg Banks
8 * Modified to support multiple serial ports. Stuart Menefy (May 2000).
9 * Modified to support SH7760 SCIF. Paul Mundt (Oct 2003).
10 * Modified to support H8/300 Serise Yoshinori Sato (Feb 2004).
13 #include <linux/config.h>
15 #if defined(__H8300H__) || defined(__H8300S__)
17 #if defined(CONFIG_H83007) || defined(CONFIG_H83068)
18 #include <asm/regs306x.h>
20 #if defined(CONFIG_H8S2678)
21 #include <asm/regs267x.h>
25 /* Values for sci_port->type */
28 #define PORT_IRDA 1 /* XXX: temporary assignment */
30 /* Offsets into the sci_port->irqs array */
31 #define SCIx_ERI_IRQ 0
32 #define SCIx_RXI_IRQ 1
33 #define SCIx_TXI_IRQ 2
35 /* ERI, RXI, TXI, BRI */
36 #define SCI_IRQS { 23, 24, 25, 0 }
37 #define SH3_SCIF_IRQS { 56, 57, 59, 58 }
38 #define SH3_IRDA_IRQS { 52, 53, 55, 54 }
39 #define SH4_SCIF_IRQS { 40, 41, 43, 42 }
40 #define STB1_SCIF1_IRQS {23, 24, 26, 25 }
41 #define SH7760_SCIF0_IRQS { 52, 53, 55, 54 }
42 #define SH7760_SCIF1_IRQS { 72, 73, 75, 74 }
43 #define SH7760_SCIF2_IRQS { 76, 77, 79, 78 }
44 #define H8300H_SCI_IRQS0 {52, 53, 54, 0 }
45 #define H8300H_SCI_IRQS1 {56, 57, 58, 0 }
46 #define H8300H_SCI_IRQS2 {60, 61, 62, 0 }
47 #define H8S_SCI_IRQS0 {88, 89, 90, 0 }
48 #define H8S_SCI_IRQS1 {92, 93, 94, 0 }
49 #define H8S_SCI_IRQS2 {96, 97, 98, 0 }
51 #if defined(CONFIG_CPU_SUBTYPE_SH7708)
54 { {}, PORT_SCI, 0xfffffe80, SCI_IRQS, sci_init_pins_sci } \
56 # define SCSPTR 0xffffff7c /* 8 bit */
57 # define SCSCR_INIT(port) 0x30 /* TIE=0,RIE=0,TE=1,RE=1 */
59 #elif defined(CONFIG_CPU_SUBTYPE_SH7707) || defined(CONFIG_CPU_SUBTYPE_SH7709)
62 { {}, PORT_SCI, 0xfffffe80, SCI_IRQS, sci_init_pins_sci }, \
63 { {}, PORT_SCIF, 0xA4000150, SH3_SCIF_IRQS, sci_init_pins_scif }, \
64 { {}, PORT_SCIF, 0xA4000140, SH3_IRDA_IRQS, sci_init_pins_irda } \
66 # define SCPCR 0xA4000116 /* 16 bit SCI and SCIF */
67 # define SCPDR 0xA4000136 /* 8 bit SCI and SCIF */
68 # define SCSCR_INIT(port) 0x30 /* TIE=0,RIE=0,TE=1,RE=1 */
70 #elif defined(CONFIG_CPU_SUBTYPE_SH7750) || defined(CONFIG_CPU_SUBTYPE_SH7751)
73 { {}, PORT_SCI, 0xffe00000, SCI_IRQS, sci_init_pins_sci }, \
74 { {}, PORT_SCIF, 0xFFE80000, SH4_SCIF_IRQS, sci_init_pins_scif } \
76 # define SCSPTR1 0xffe0001c /* 8 bit SCI */
77 # define SCSPTR2 0xFFE80020 /* 16 bit SCIF */
78 # define SCIF_ORER 0x0001 /* overrun error bit */
79 # define SCSCR_INIT(port) (((port)->type == PORT_SCI) ? \
80 0x30 /* TIE=0,RIE=0,TE=1,RE=1 */ : \
81 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */ )
83 #elif defined(CONFIG_CPU_SUBTYPE_SH7760)
86 { {}, PORT_SCIF, 0xfe600000, SH7760_SCIF0_IRQS, sci_init_pins_scif }, \
87 { {}, PORT_SCIF, 0xfe610000, SH7760_SCIF1_IRQS, sci_init_pins_scif }, \
88 { {}, PORT_SCIF, 0xfe620000, SH7760_SCIF2_IRQS, sci_init_pins_scif } \
90 # define SCSPTR0 0xfe600024 /* 16 bit SCIF */
91 # define SCSPTR1 0xfe610024 /* 16 bit SCIF */
92 # define SCSPTR2 0xfe620024 /* 16 bit SCIF */
93 # define SCIF_ORDER 0x0001 /* overrun error bit */
94 # define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
96 #elif defined(CONFIG_CPU_SUBTYPE_ST40STB1)
99 { {}, PORT_SCIF, 0xffe00000, STB1_SCIF1_IRQS, sci_init_pins_scif }, \
100 { {}, PORT_SCIF, 0xffe80000, SH4_SCIF_IRQS, sci_init_pins_scif } \
102 # define SCSPTR1 0xffe00020 /* 16 bit SCIF */
103 # define SCSPTR2 0xffe80020 /* 16 bit SCIF */
104 # define SCIF_ORER 0x0001 /* overrun error bit */
105 # define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
107 #elif defined(CONFIG_H83007) || defined(CONFIG_H83068)
108 # define SCI_NPORTS 3
109 # define SCI_INIT { \
110 { {}, PORT_SCI, 0x00ffffb0, H8300H_SCI_IRQS0, sci_init_pins_sci }, \
111 { {}, PORT_SCI, 0x00ffffb8, H8300H_SCI_IRQS1, sci_init_pins_sci }, \
112 { {}, PORT_SCI, 0x00ffffc0, H8300H_SCI_IRQS2, sci_init_pins_sci } \
114 # define SCSCR_INIT(port) 0x30 /* TIE=0,RIE=0,TE=1,RE=1 */
116 # define H8300_SCI_DR(ch) *(volatile char *)(P1DR + h8300_sci_pins[ch].port)
117 #elif defined(CONFIG_H8S2678)
118 # define SCI_NPORTS 3
119 # define SCI_INIT { \
120 { {}, PORT_SCI, 0x00ffff78, H8S_SCI_IRQS0, sci_init_pins_sci }, \
121 { {}, PORT_SCI, 0x00ffff80, H8S_SCI_IRQS1, sci_init_pins_sci }, \
122 { {}, PORT_SCI, 0x00ffff88, H8S_SCI_IRQS2, sci_init_pins_sci } \
124 # define SCSCR_INIT(port) 0x30 /* TIE=0,RIE=0,TE=1,RE=1 */
126 # define H8300_SCI_DR(ch) *(volatile char *)(P1DR + h8300_sci_pins[ch].port)
128 # error CPU subtype not defined
132 #define SCI_CTRL_FLAGS_TIE 0x80 /* all */
133 #define SCI_CTRL_FLAGS_RIE 0x40 /* all */
134 #define SCI_CTRL_FLAGS_TE 0x20 /* all */
135 #define SCI_CTRL_FLAGS_RE 0x10 /* all */
136 /* SCI_CTRL_FLAGS_REIE 0x08 * 7750 SCIF */
137 /* SCI_CTRL_FLAGS_MPIE 0x08 * 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
138 /* SCI_CTRL_FLAGS_TEIE 0x04 * 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
139 /* SCI_CTRL_FLAGS_CKE1 0x02 * all */
140 /* SCI_CTRL_FLAGS_CKE0 0x01 * 7707 SCI/SCIF, 7708 SCI, 7709 SCI/SCIF, 7750 SCI */
143 #define SCI_TDRE 0x80 /* 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
144 #define SCI_RDRF 0x40 /* 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
145 #define SCI_ORER 0x20 /* 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
146 #define SCI_FER 0x10 /* 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
147 #define SCI_PER 0x08 /* 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
148 #define SCI_TEND 0x04 /* 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
149 /* SCI_MPB 0x02 * 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
150 /* SCI_MPBT 0x01 * 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */
152 #define SCI_ERRORS ( SCI_PER | SCI_FER | SCI_ORER)
155 #define SCIF_ER 0x0080 /* 7707 SCIF, 7709 SCIF, 7750 SCIF */
156 #define SCIF_TEND 0x0040 /* 7707 SCIF, 7709 SCIF, 7750 SCIF */
157 #define SCIF_TDFE 0x0020 /* 7707 SCIF, 7709 SCIF, 7750 SCIF */
158 #define SCIF_BRK 0x0010 /* 7707 SCIF, 7709 SCIF, 7750 SCIF */
159 #define SCIF_FER 0x0008 /* 7707 SCIF, 7709 SCIF, 7750 SCIF */
160 #define SCIF_PER 0x0004 /* 7707 SCIF, 7709 SCIF, 7750 SCIF */
161 #define SCIF_RDF 0x0002 /* 7707 SCIF, 7709 SCIF, 7750 SCIF */
162 #define SCIF_DR 0x0001 /* 7707 SCIF, 7709 SCIF, 7750 SCIF */
164 #define SCIF_ERRORS ( SCIF_PER | SCIF_FER | SCIF_ER | SCIF_BRK)
166 #if defined(SCI_ONLY)
167 # define SCxSR_TEND(port) SCI_TEND
168 # define SCxSR_ERRORS(port) SCI_ERRORS
169 # define SCxSR_RDxF(port) SCI_RDRF
170 # define SCxSR_TDxE(port) SCI_TDRE
171 # define SCxSR_ORER(port) SCI_ORER
172 # define SCxSR_FER(port) SCI_FER
173 # define SCxSR_PER(port) SCI_PER
174 # define SCxSR_BRK(port) 0x00
175 # define SCxSR_RDxF_CLEAR(port) 0xbc
176 # define SCxSR_ERROR_CLEAR(port) 0xc4
177 # define SCxSR_TDxE_CLEAR(port) 0x78
178 # define SCxSR_BREAK_CLEAR(port) 0xc4
179 #elif defined(SCIF_ONLY)
180 # define SCxSR_TEND(port) SCIF_TEND
181 # define SCxSR_ERRORS(port) SCIF_ERRORS
182 # define SCxSR_RDxF(port) SCIF_RDF
183 # define SCxSR_TDxE(port) SCIF_TDFE
184 # define SCxSR_ORER(port) 0x0000
185 # define SCxSR_FER(port) SCIF_FER
186 # define SCxSR_PER(port) SCIF_PER
187 # define SCxSR_BRK(port) SCIF_BRK
188 # define SCxSR_RDxF_CLEAR(port) 0x00fc
189 # define SCxSR_ERROR_CLEAR(port) 0x0073
190 # define SCxSR_TDxE_CLEAR(port) 0x00df
191 # define SCxSR_BREAK_CLEAR(port) 0x00e3
193 # define SCxSR_TEND(port) (((port)->type == PORT_SCI) ? SCI_TEND : SCIF_TEND)
194 # define SCxSR_ERRORS(port) (((port)->type == PORT_SCI) ? SCI_ERRORS : SCIF_ERRORS)
195 # define SCxSR_RDxF(port) (((port)->type == PORT_SCI) ? SCI_RDRF : SCIF_RDF)
196 # define SCxSR_TDxE(port) (((port)->type == PORT_SCI) ? SCI_TDRE : SCIF_TDFE)
197 # define SCxSR_ORER(port) (((port)->type == PORT_SCI) ? SCI_ORER : 0x0000)
198 # define SCxSR_FER(port) (((port)->type == PORT_SCI) ? SCI_FER : SCIF_FER)
199 # define SCxSR_PER(port) (((port)->type == PORT_SCI) ? SCI_PER : SCIF_PER)
200 # define SCxSR_BRK(port) (((port)->type == PORT_SCI) ? 0x00 : SCIF_BRK)
201 # define SCxSR_RDxF_CLEAR(port) (((port)->type == PORT_SCI) ? 0xbc : 0x00fc)
202 # define SCxSR_ERROR_CLEAR(port) (((port)->type == PORT_SCI) ? 0xc4 : 0x0073)
203 # define SCxSR_TDxE_CLEAR(port) (((port)->type == PORT_SCI) ? 0x78 : 0x00df)
204 # define SCxSR_BREAK_CLEAR(port) (((port)->type == PORT_SCI) ? 0xc4 : 0x00e3)
208 #define SCFCR_RFRST 0x0002
209 #define SCFCR_TFRST 0x0004
210 #define SCFCR_MCE 0x0008
212 #define SCI_MAJOR 204
213 #define SCI_MINOR_START 8
215 /* Generic serial flags */
216 #define SCI_RX_THROTTLE 0x0000001
218 #define SCI_MAGIC 0xbabeface
221 * Events are used to schedule things to happen at timer-interrupt
222 * time, instead of at rs interrupt time.
224 #define SCI_EVENT_WRITE_WAKEUP 0
230 unsigned char irqs[4]; /* ERI, RXI, TXI, BRI */
231 void (*init_pins)(struct sci_port* port, unsigned int cflag);
232 unsigned int old_cflag;
233 struct async_icount icount;
234 struct work_struct tqueue;
239 #define SCI_IN(size, offset) \
240 unsigned int addr = port->base + (offset); \
242 return ctrl_inb(addr); \
244 return ctrl_inw(addr); \
246 #define SCI_OUT(size, offset, value) \
247 unsigned int addr = port->base + (offset); \
249 ctrl_outb(value, addr); \
251 ctrl_outw(value, addr); \
254 #define CPU_SCIx_FNS(name, sci_offset, sci_size, scif_offset, scif_size)\
255 static inline unsigned int sci_##name##_in(struct sci_port* port) \
257 if (port->type == PORT_SCI) { \
258 SCI_IN(sci_size, sci_offset) \
260 SCI_IN(scif_size, scif_offset); \
263 static inline void sci_##name##_out(struct sci_port* port, unsigned int value) \
265 if (port->type == PORT_SCI) { \
266 SCI_OUT(sci_size, sci_offset, value) \
268 SCI_OUT(scif_size, scif_offset, value); \
272 #define CPU_SCIF_FNS(name, scif_offset, scif_size) \
273 static inline unsigned int sci_##name##_in(struct sci_port* port) \
275 SCI_IN(scif_size, scif_offset); \
277 static inline void sci_##name##_out(struct sci_port* port, unsigned int value) \
279 SCI_OUT(scif_size, scif_offset, value); \
282 #define CPU_SCI_FNS(name, sci_offset, sci_size) \
283 static inline unsigned int sci_##name##_in(struct sci_port* port) \
285 SCI_IN(sci_size, sci_offset); \
287 static inline void sci_##name##_out(struct sci_port* port, unsigned int value) \
289 SCI_OUT(sci_size, sci_offset, value); \
292 #ifdef CONFIG_CPU_SH3
293 #define SCIx_FNS(name, sh3_sci_offset, sh3_sci_size, sh4_sci_offset, sh4_sci_size, \
294 sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size, \
295 h8_sci_offset, h8_sci_size) \
296 CPU_SCIx_FNS(name, sh3_sci_offset, sh3_sci_size, sh3_scif_offset, sh3_scif_size)
297 #define SCIF_FNS(name, sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size) \
298 CPU_SCIF_FNS(name, sh3_scif_offset, sh3_scif_size)
299 #elif defined(__H8300H__) || defined(__H8300S__)
300 #define SCIx_FNS(name, sh3_sci_offset, sh3_sci_size, sh4_sci_offset, sh4_sci_size, \
301 sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size, \
302 h8_sci_offset, h8_sci_size) \
303 CPU_SCI_FNS(name, h8_sci_offset, h8_sci_size)
304 #define SCIF_FNS(name, sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size)
306 #define SCIx_FNS(name, sh3_sci_offset, sh3_sci_size, sh4_sci_offset, sh4_sci_size, \
307 sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size, \
308 h8_sci_offset, h8_sci_size) \
309 CPU_SCIx_FNS(name, sh4_sci_offset, sh4_sci_size, sh4_scif_offset, sh4_scif_size)
310 #define SCIF_FNS(name, sh3_scif_offset, sh3_scif_size, sh4_scif_offset, sh4_scif_size) \
311 CPU_SCIF_FNS(name, sh4_scif_offset, sh4_scif_size)
314 /* reg SCI/SH3 SCI/SH4 SCIF/SH3 SCIF/SH4 SCI/H8*/
315 /* name off sz off sz off sz off sz off sz*/
316 SCIx_FNS(SCSMR, 0x00, 8, 0x00, 8, 0x00, 8, 0x00, 16, 0x00, 8)
317 SCIx_FNS(SCBRR, 0x02, 8, 0x04, 8, 0x02, 8, 0x04, 8, 0x01, 8)
318 SCIx_FNS(SCSCR, 0x04, 8, 0x08, 8, 0x04, 8, 0x08, 16, 0x02, 8)
319 SCIx_FNS(SCxTDR, 0x06, 8, 0x0c, 8, 0x06, 8, 0x0C, 8, 0x03, 8)
320 SCIx_FNS(SCxSR, 0x08, 8, 0x10, 8, 0x08, 16, 0x10, 16, 0x04, 8)
321 SCIx_FNS(SCxRDR, 0x0a, 8, 0x14, 8, 0x0A, 8, 0x14, 8, 0x05, 8)
322 SCIF_FNS(SCFCR, 0x0c, 8, 0x18, 16)
323 SCIF_FNS(SCFDR, 0x0e, 16, 0x1C, 16)
324 SCIF_FNS(SCLSR, 0, 0, 0x24, 16)
326 #define sci_in(port, reg) sci_##reg##_in(port)
327 #define sci_out(port, reg, value) sci_##reg##_out(port, value)
329 /* H8/300 series SCI pins assignment */
330 #if defined(__H8300H__) || defined(__H8300S__)
331 static const struct __attribute__((packed))
333 int port; /* GPIO port no */
334 unsigned short rx,tx; /* GPIO bit no */
337 #if defined(CONFIG_H83007) || defined(CONFIG_H83068)
339 .port = H8300_GPIO_P9,
344 .port = H8300_GPIO_P9,
349 .port = H8300_GPIO_PB,
353 #elif defined(CONFIG_H8S2678)
355 .port = H8300_GPIO_P3,
360 .port = H8300_GPIO_P3,
365 .port = H8300_GPIO_P5,
373 #if defined(CONFIG_CPU_SUBTYPE_SH7708)
374 static inline int sci_rxd_in(struct sci_port *port)
376 if (port->base == 0xfffffe80)
377 return ctrl_inb(SCSPTR)&0x01 ? 1 : 0; /* SCI */
380 #elif defined(CONFIG_CPU_SUBTYPE_SH7707) || defined(CONFIG_CPU_SUBTYPE_SH7709)
381 static inline int sci_rxd_in(struct sci_port *port)
383 if (port->base == 0xfffffe80)
384 return ctrl_inb(SCPDR)&0x01 ? 1 : 0; /* SCI */
385 if (port->base == 0xa4000150)
386 return ctrl_inb(SCPDR)&0x10 ? 1 : 0; /* SCIF */
387 if (port->base == 0xa4000140)
388 return ctrl_inb(SCPDR)&0x04 ? 1 : 0; /* IRDA */
391 #elif defined(CONFIG_CPU_SUBTYPE_SH7750) || defined(CONFIG_CPU_SUBTYPE_SH7751)
392 static inline int sci_rxd_in(struct sci_port *port)
395 if (port->base == 0xffe00000)
396 return ctrl_inb(SCSPTR1)&0x01 ? 1 : 0; /* SCI */
399 if (port->base == 0xffe80000)
400 return ctrl_inw(SCSPTR2)&0x0001 ? 1 : 0; /* SCIF */
404 #elif defined(CONFIG_CPU_SUBTYPE_SH7760)
405 static inline int sci_rxd_in(struct sci_port *port)
407 if (port->base == 0xfe600000)
408 return ctrl_inw(SCSPTR0) & 0x0001 ? 1 : 0; /* SCIF */
409 if (port->base == 0xfe610000)
410 return ctrl_inw(SCSPTR1) & 0x0001 ? 1 : 0; /* SCIF */
411 if (port->base == 0xfe620000)
412 return ctrl_inw(SCSPTR2) & 0x0001 ? 1 : 0; /* SCIF */
414 #elif defined(CONFIG_CPU_SUBTYPE_ST40STB1)
415 static inline int sci_rxd_in(struct sci_port *port)
417 if (port->base == 0xffe00000)
418 return ctrl_inw(SCSPTR1)&0x0001 ? 1 : 0; /* SCIF */
420 return ctrl_inw(SCSPTR2)&0x0001 ? 1 : 0; /* SCIF */
423 #elif defined(__H8300H__) || defined(__H8300S__)
424 static inline int sci_rxd_in(struct sci_port *port)
426 int ch = (port->base - SMR0) >> 3;
427 return (H8300_SCI_DR(ch) & h8300_sci_pins[ch].rx) ? 1 : 0;
432 * Values for the BitRate Register (SCBRR)
434 * The values are actually divisors for a frequency which can
435 * be internal to the SH3 (14.7456MHz) or derived from an external
436 * clock source. This driver assumes the internal clock is used;
437 * to support using an external clock source, config options or
438 * possibly command-line options would need to be added.
440 * Also, to support speeds below 2400 (why?) the lower 2 bits of
441 * the SCSMR register would also need to be set to non-zero values.
443 * -- Greg Banks 27Feb2000
445 * Answer: The SCBRR register is only eight bits, and the value in
446 * it gets larger with lower baud rates. At around 2400 (depending on
447 * the peripherial module clock) you run out of bits. However the
448 * lower two bits of SCSMR allow the module clock to be divided down,
449 * scaling the value which is needed in SCBRR.
451 * -- Stuart Menefy - 23 May 2000
453 * I meant, why would anyone bother with bitrates below 2400.
455 * -- Greg Banks - 7Jul2000
457 * You "speedist"! How will I use my 110bps ASR-33 teletype with paper
458 * tape reader as a console!
460 * -- Mitch Davis - 15 Jul 2000
463 #define PCLK (current_cpu_data.module_clock)
465 #if !defined(__H8300H__) && !defined(__H8300S__)
466 #define SCBRR_VALUE(bps) ((PCLK+16*bps)/(32*bps)-1)
468 #define SCBRR_VALUE(bps) (((CONFIG_CPU_CLOCK*1000/32)/bps)-1)
470 #define BPS_2400 SCBRR_VALUE(2400)
471 #define BPS_4800 SCBRR_VALUE(4800)
472 #define BPS_9600 SCBRR_VALUE(9600)
473 #define BPS_19200 SCBRR_VALUE(19200)
474 #define BPS_38400 SCBRR_VALUE(38400)
475 #define BPS_57600 SCBRR_VALUE(57600)
476 #define BPS_115200 SCBRR_VALUE(115200)
477 #define BPS_230400 SCBRR_VALUE(230400)