2 * linux/drivers/char/synclink.c
4 * $Id: synclink.c,v 4.28 2004/08/11 19:30:01 paulkf Exp $
6 * Device driver for Microgate SyncLink ISA and PCI
7 * high speed multiprotocol serial adapters.
9 * written by Paul Fulghum for Microgate Corporation
10 * paulkf@microgate.com
12 * Microgate and SyncLink are trademarks of Microgate Corporation
14 * Derived from serial.c written by Theodore Ts'o and Linus Torvalds
16 * Original release 01/11/99
18 * This code is released under the GNU General Public License (GPL)
20 * This driver is primarily intended for use in synchronous
21 * HDLC mode. Asynchronous mode is also provided.
23 * When operating in synchronous mode, each call to mgsl_write()
24 * contains exactly one complete HDLC frame. Calling mgsl_put_char
25 * will start assembling an HDLC frame that will not be sent until
26 * mgsl_flush_chars or mgsl_write is called.
28 * Synchronous receive data is reported as complete frames. To accomplish
29 * this, the TTY flip buffer is bypassed (too small to hold largest
30 * frame and may fragment frames) and the line discipline
31 * receive entry point is called directly.
33 * This driver has been tested with a slightly modified ppp.c driver
34 * for synchronous PPP.
37 * Added interface for syncppp.c driver (an alternate synchronous PPP
38 * implementation that also supports Cisco HDLC). Each device instance
39 * registers as a tty device AND a network device (if dosyncppp option
40 * is set for the device). The functionality is determined by which
41 * device interface is opened.
43 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
44 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
45 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
46 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
47 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
48 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
49 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
50 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
51 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
52 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
53 * OF THE POSSIBILITY OF SUCH DAMAGE.
57 # define BREAKPOINT() asm(" int $3");
59 # define BREAKPOINT() { }
62 #define MAX_ISA_DEVICES 10
63 #define MAX_PCI_DEVICES 10
64 #define MAX_TOTAL_DEVICES 20
66 #include <linux/config.h>
67 #include <linux/module.h>
68 #include <linux/errno.h>
69 #include <linux/signal.h>
70 #include <linux/sched.h>
71 #include <linux/timer.h>
72 #include <linux/interrupt.h>
73 #include <linux/pci.h>
74 #include <linux/tty.h>
75 #include <linux/tty_flip.h>
76 #include <linux/serial.h>
77 #include <linux/major.h>
78 #include <linux/string.h>
79 #include <linux/fcntl.h>
80 #include <linux/ptrace.h>
81 #include <linux/ioport.h>
83 #include <linux/slab.h>
84 #include <linux/delay.h>
86 #include <linux/netdevice.h>
88 #include <linux/vmalloc.h>
89 #include <linux/init.h>
90 #include <asm/serial.h>
92 #include <linux/delay.h>
93 #include <linux/ioctl.h>
95 #include <asm/system.h>
99 #include <linux/bitops.h>
100 #include <asm/types.h>
101 #include <linux/termios.h>
102 #include <linux/workqueue.h>
103 #include <linux/hdlc.h>
105 #ifdef CONFIG_HDLC_MODULE
106 #define CONFIG_HDLC 1
109 #define GET_USER(error,value,addr) error = get_user(value,addr)
110 #define COPY_FROM_USER(error,dest,src,size) error = copy_from_user(dest,src,size) ? -EFAULT : 0
111 #define PUT_USER(error,value,addr) error = put_user(value,addr)
112 #define COPY_TO_USER(error,dest,src,size) error = copy_to_user(dest,src,size) ? -EFAULT : 0
114 #include <asm/uaccess.h>
116 #include "linux/synclink.h"
118 #define RCLRVALUE 0xffff
120 static MGSL_PARAMS default_params = {
121 MGSL_MODE_HDLC, /* unsigned long mode */
122 0, /* unsigned char loopback; */
123 HDLC_FLAG_UNDERRUN_ABORT15, /* unsigned short flags; */
124 HDLC_ENCODING_NRZI_SPACE, /* unsigned char encoding; */
125 0, /* unsigned long clock_speed; */
126 0xff, /* unsigned char addr_filter; */
127 HDLC_CRC_16_CCITT, /* unsigned short crc_type; */
128 HDLC_PREAMBLE_LENGTH_8BITS, /* unsigned char preamble_length; */
129 HDLC_PREAMBLE_PATTERN_NONE, /* unsigned char preamble; */
130 9600, /* unsigned long data_rate; */
131 8, /* unsigned char data_bits; */
132 1, /* unsigned char stop_bits; */
133 ASYNC_PARITY_NONE /* unsigned char parity; */
136 #define SHARED_MEM_ADDRESS_SIZE 0x40000
137 #define BUFFERLISTSIZE (PAGE_SIZE)
138 #define DMABUFFERSIZE (PAGE_SIZE)
139 #define MAXRXFRAMES 7
141 typedef struct _DMABUFFERENTRY
143 u32 phys_addr; /* 32-bit flat physical address of data buffer */
144 u16 count; /* buffer size/data count */
145 u16 status; /* Control/status field */
146 u16 rcc; /* character count field */
147 u16 reserved; /* padding required by 16C32 */
148 u32 link; /* 32-bit flat link to next buffer entry */
149 char *virt_addr; /* virtual address of data buffer */
150 u32 phys_entry; /* physical address of this buffer entry */
151 } DMABUFFERENTRY, *DMAPBUFFERENTRY;
153 /* The queue of BH actions to be performed */
156 #define BH_TRANSMIT 2
159 #define IO_PIN_SHUTDOWN_LIMIT 100
161 #define RELEVANT_IFLAG(iflag) (iflag & (IGNBRK|BRKINT|IGNPAR|PARMRK|INPCK))
163 struct _input_signal_events {
174 /* transmit holding buffer definitions*/
175 #define MAX_TX_HOLDING_BUFFERS 5
176 struct tx_holding_buffer {
178 unsigned char * buffer;
183 * Device instance data structure
189 int count; /* count of opens */
192 unsigned short close_delay;
193 unsigned short closing_wait; /* time to wait before closing */
195 struct mgsl_icount icount;
197 struct tty_struct *tty;
199 int x_char; /* xon/xoff character */
200 int blocked_open; /* # of blocked opens */
201 u16 read_status_mask;
202 u16 ignore_status_mask;
203 unsigned char *xmit_buf;
208 wait_queue_head_t open_wait;
209 wait_queue_head_t close_wait;
211 wait_queue_head_t status_event_wait_q;
212 wait_queue_head_t event_wait_q;
213 struct timer_list tx_timer; /* HDLC transmit timeout timer */
214 struct mgsl_struct *next_device; /* device list link */
216 spinlock_t irq_spinlock; /* spinlock for synchronizing with ISR */
217 struct work_struct task; /* task structure for scheduling bh */
219 u32 EventMask; /* event trigger mask */
220 u32 RecordedEvents; /* pending events */
222 u32 max_frame_size; /* as set by device config */
226 int bh_running; /* Protection from multiple */
230 int dcd_chkcount; /* check counts to prevent */
231 int cts_chkcount; /* too many IRQs if a signal */
232 int dsr_chkcount; /* is floating */
235 char *buffer_list; /* virtual address of Rx & Tx buffer lists */
236 unsigned long buffer_list_phys;
238 unsigned int rx_buffer_count; /* count of total allocated Rx buffers */
239 DMABUFFERENTRY *rx_buffer_list; /* list of receive buffer entries */
240 unsigned int current_rx_buffer;
242 int num_tx_dma_buffers; /* number of tx dma frames required */
243 int tx_dma_buffers_used;
244 unsigned int tx_buffer_count; /* count of total allocated Tx buffers */
245 DMABUFFERENTRY *tx_buffer_list; /* list of transmit buffer entries */
246 int start_tx_dma_buffer; /* tx dma buffer to start tx dma operation */
247 int current_tx_buffer; /* next tx dma buffer to be loaded */
249 unsigned char *intermediate_rxbuffer;
251 int num_tx_holding_buffers; /* number of tx holding buffer allocated */
252 int get_tx_holding_index; /* next tx holding buffer for adapter to load */
253 int put_tx_holding_index; /* next tx holding buffer to store user request */
254 int tx_holding_count; /* number of tx holding buffers waiting */
255 struct tx_holding_buffer tx_holding_buffers[MAX_TX_HOLDING_BUFFERS];
268 char device_name[25]; /* device instance name */
270 unsigned int bus_type; /* expansion bus type (ISA,EISA,PCI) */
271 unsigned char bus; /* expansion bus number (zero based) */
272 unsigned char function; /* PCI device number */
274 unsigned int io_base; /* base I/O address of adapter */
275 unsigned int io_addr_size; /* size of the I/O address range */
276 int io_addr_requested; /* nonzero if I/O address requested */
278 unsigned int irq_level; /* interrupt level */
279 unsigned long irq_flags;
280 int irq_requested; /* nonzero if IRQ requested */
282 unsigned int dma_level; /* DMA channel */
283 int dma_requested; /* nonzero if dma channel requested */
289 MGSL_PARAMS params; /* communications parameters */
291 unsigned char serial_signals; /* current serial signal states */
293 int irq_occurred; /* for diagnostics use */
294 unsigned int init_error; /* Initialization startup error (DIAGS) */
295 int fDiagnosticsmode; /* Driver in Diagnostic mode? (DIAGS) */
298 unsigned char* memory_base; /* shared memory address (PCI only) */
299 u32 phys_memory_base;
300 int shared_mem_requested;
302 unsigned char* lcr_base; /* local config registers (PCI only) */
305 int lcr_mem_requested;
308 char flag_buf[MAX_ASYNC_BUFFER_SIZE];
309 char char_buf[MAX_ASYNC_BUFFER_SIZE];
310 BOOLEAN drop_rts_on_tx_done;
312 BOOLEAN loopmode_insert_requested;
313 BOOLEAN loopmode_send_done_requested;
315 struct _input_signal_events input_signal_events;
317 /* generic HDLC device parts */
323 struct net_device *netdev;
327 #define MGSL_MAGIC 0x5401
330 * The size of the serial xmit buffer is 1 page, or 4096 bytes
332 #ifndef SERIAL_XMIT_SIZE
333 #define SERIAL_XMIT_SIZE 4096
337 * These macros define the offsets used in calculating the
338 * I/O address of the specified USC registers.
342 #define DCPIN 2 /* Bit 1 of I/O address */
343 #define SDPIN 4 /* Bit 2 of I/O address */
345 #define DCAR 0 /* DMA command/address register */
346 #define CCAR SDPIN /* channel command/address register */
347 #define DATAREG DCPIN + SDPIN /* serial data register */
352 * These macros define the register address (ordinal number)
353 * used for writing address/value pairs to the USC.
356 #define CMR 0x02 /* Channel mode Register */
357 #define CCSR 0x04 /* Channel Command/status Register */
358 #define CCR 0x06 /* Channel Control Register */
359 #define PSR 0x08 /* Port status Register */
360 #define PCR 0x0a /* Port Control Register */
361 #define TMDR 0x0c /* Test mode Data Register */
362 #define TMCR 0x0e /* Test mode Control Register */
363 #define CMCR 0x10 /* Clock mode Control Register */
364 #define HCR 0x12 /* Hardware Configuration Register */
365 #define IVR 0x14 /* Interrupt Vector Register */
366 #define IOCR 0x16 /* Input/Output Control Register */
367 #define ICR 0x18 /* Interrupt Control Register */
368 #define DCCR 0x1a /* Daisy Chain Control Register */
369 #define MISR 0x1c /* Misc Interrupt status Register */
370 #define SICR 0x1e /* status Interrupt Control Register */
371 #define RDR 0x20 /* Receive Data Register */
372 #define RMR 0x22 /* Receive mode Register */
373 #define RCSR 0x24 /* Receive Command/status Register */
374 #define RICR 0x26 /* Receive Interrupt Control Register */
375 #define RSR 0x28 /* Receive Sync Register */
376 #define RCLR 0x2a /* Receive count Limit Register */
377 #define RCCR 0x2c /* Receive Character count Register */
378 #define TC0R 0x2e /* Time Constant 0 Register */
379 #define TDR 0x30 /* Transmit Data Register */
380 #define TMR 0x32 /* Transmit mode Register */
381 #define TCSR 0x34 /* Transmit Command/status Register */
382 #define TICR 0x36 /* Transmit Interrupt Control Register */
383 #define TSR 0x38 /* Transmit Sync Register */
384 #define TCLR 0x3a /* Transmit count Limit Register */
385 #define TCCR 0x3c /* Transmit Character count Register */
386 #define TC1R 0x3e /* Time Constant 1 Register */
390 * MACRO DEFINITIONS FOR DMA REGISTERS
393 #define DCR 0x06 /* DMA Control Register (shared) */
394 #define DACR 0x08 /* DMA Array count Register (shared) */
395 #define BDCR 0x12 /* Burst/Dwell Control Register (shared) */
396 #define DIVR 0x14 /* DMA Interrupt Vector Register (shared) */
397 #define DICR 0x18 /* DMA Interrupt Control Register (shared) */
398 #define CDIR 0x1a /* Clear DMA Interrupt Register (shared) */
399 #define SDIR 0x1c /* Set DMA Interrupt Register (shared) */
401 #define TDMR 0x02 /* Transmit DMA mode Register */
402 #define TDIAR 0x1e /* Transmit DMA Interrupt Arm Register */
403 #define TBCR 0x2a /* Transmit Byte count Register */
404 #define TARL 0x2c /* Transmit Address Register (low) */
405 #define TARU 0x2e /* Transmit Address Register (high) */
406 #define NTBCR 0x3a /* Next Transmit Byte count Register */
407 #define NTARL 0x3c /* Next Transmit Address Register (low) */
408 #define NTARU 0x3e /* Next Transmit Address Register (high) */
410 #define RDMR 0x82 /* Receive DMA mode Register (non-shared) */
411 #define RDIAR 0x9e /* Receive DMA Interrupt Arm Register */
412 #define RBCR 0xaa /* Receive Byte count Register */
413 #define RARL 0xac /* Receive Address Register (low) */
414 #define RARU 0xae /* Receive Address Register (high) */
415 #define NRBCR 0xba /* Next Receive Byte count Register */
416 #define NRARL 0xbc /* Next Receive Address Register (low) */
417 #define NRARU 0xbe /* Next Receive Address Register (high) */
421 * MACRO DEFINITIONS FOR MODEM STATUS BITS
424 #define MODEMSTATUS_DTR 0x80
425 #define MODEMSTATUS_DSR 0x40
426 #define MODEMSTATUS_RTS 0x20
427 #define MODEMSTATUS_CTS 0x10
428 #define MODEMSTATUS_RI 0x04
429 #define MODEMSTATUS_DCD 0x01
433 * Channel Command/Address Register (CCAR) Command Codes
436 #define RTCmd_Null 0x0000
437 #define RTCmd_ResetHighestIus 0x1000
438 #define RTCmd_TriggerChannelLoadDma 0x2000
439 #define RTCmd_TriggerRxDma 0x2800
440 #define RTCmd_TriggerTxDma 0x3000
441 #define RTCmd_TriggerRxAndTxDma 0x3800
442 #define RTCmd_PurgeRxFifo 0x4800
443 #define RTCmd_PurgeTxFifo 0x5000
444 #define RTCmd_PurgeRxAndTxFifo 0x5800
445 #define RTCmd_LoadRcc 0x6800
446 #define RTCmd_LoadTcc 0x7000
447 #define RTCmd_LoadRccAndTcc 0x7800
448 #define RTCmd_LoadTC0 0x8800
449 #define RTCmd_LoadTC1 0x9000
450 #define RTCmd_LoadTC0AndTC1 0x9800
451 #define RTCmd_SerialDataLSBFirst 0xa000
452 #define RTCmd_SerialDataMSBFirst 0xa800
453 #define RTCmd_SelectBigEndian 0xb000
454 #define RTCmd_SelectLittleEndian 0xb800
458 * DMA Command/Address Register (DCAR) Command Codes
461 #define DmaCmd_Null 0x0000
462 #define DmaCmd_ResetTxChannel 0x1000
463 #define DmaCmd_ResetRxChannel 0x1200
464 #define DmaCmd_StartTxChannel 0x2000
465 #define DmaCmd_StartRxChannel 0x2200
466 #define DmaCmd_ContinueTxChannel 0x3000
467 #define DmaCmd_ContinueRxChannel 0x3200
468 #define DmaCmd_PauseTxChannel 0x4000
469 #define DmaCmd_PauseRxChannel 0x4200
470 #define DmaCmd_AbortTxChannel 0x5000
471 #define DmaCmd_AbortRxChannel 0x5200
472 #define DmaCmd_InitTxChannel 0x7000
473 #define DmaCmd_InitRxChannel 0x7200
474 #define DmaCmd_ResetHighestDmaIus 0x8000
475 #define DmaCmd_ResetAllChannels 0x9000
476 #define DmaCmd_StartAllChannels 0xa000
477 #define DmaCmd_ContinueAllChannels 0xb000
478 #define DmaCmd_PauseAllChannels 0xc000
479 #define DmaCmd_AbortAllChannels 0xd000
480 #define DmaCmd_InitAllChannels 0xf000
482 #define TCmd_Null 0x0000
483 #define TCmd_ClearTxCRC 0x2000
484 #define TCmd_SelectTicrTtsaData 0x4000
485 #define TCmd_SelectTicrTxFifostatus 0x5000
486 #define TCmd_SelectTicrIntLevel 0x6000
487 #define TCmd_SelectTicrdma_level 0x7000
488 #define TCmd_SendFrame 0x8000
489 #define TCmd_SendAbort 0x9000
490 #define TCmd_EnableDleInsertion 0xc000
491 #define TCmd_DisableDleInsertion 0xd000
492 #define TCmd_ClearEofEom 0xe000
493 #define TCmd_SetEofEom 0xf000
495 #define RCmd_Null 0x0000
496 #define RCmd_ClearRxCRC 0x2000
497 #define RCmd_EnterHuntmode 0x3000
498 #define RCmd_SelectRicrRtsaData 0x4000
499 #define RCmd_SelectRicrRxFifostatus 0x5000
500 #define RCmd_SelectRicrIntLevel 0x6000
501 #define RCmd_SelectRicrdma_level 0x7000
504 * Bits for enabling and disabling IRQs in Interrupt Control Register (ICR)
507 #define RECEIVE_STATUS BIT5
508 #define RECEIVE_DATA BIT4
509 #define TRANSMIT_STATUS BIT3
510 #define TRANSMIT_DATA BIT2
516 * Receive status Bits in Receive Command/status Register RCSR
519 #define RXSTATUS_SHORT_FRAME BIT8
520 #define RXSTATUS_CODE_VIOLATION BIT8
521 #define RXSTATUS_EXITED_HUNT BIT7
522 #define RXSTATUS_IDLE_RECEIVED BIT6
523 #define RXSTATUS_BREAK_RECEIVED BIT5
524 #define RXSTATUS_ABORT_RECEIVED BIT5
525 #define RXSTATUS_RXBOUND BIT4
526 #define RXSTATUS_CRC_ERROR BIT3
527 #define RXSTATUS_FRAMING_ERROR BIT3
528 #define RXSTATUS_ABORT BIT2
529 #define RXSTATUS_PARITY_ERROR BIT2
530 #define RXSTATUS_OVERRUN BIT1
531 #define RXSTATUS_DATA_AVAILABLE BIT0
532 #define RXSTATUS_ALL 0x01f6
533 #define usc_UnlatchRxstatusBits(a,b) usc_OutReg( (a), RCSR, (u16)((b) & RXSTATUS_ALL) )
536 * Values for setting transmit idle mode in
537 * Transmit Control/status Register (TCSR)
539 #define IDLEMODE_FLAGS 0x0000
540 #define IDLEMODE_ALT_ONE_ZERO 0x0100
541 #define IDLEMODE_ZERO 0x0200
542 #define IDLEMODE_ONE 0x0300
543 #define IDLEMODE_ALT_MARK_SPACE 0x0500
544 #define IDLEMODE_SPACE 0x0600
545 #define IDLEMODE_MARK 0x0700
546 #define IDLEMODE_MASK 0x0700
549 * IUSC revision identifiers
551 #define IUSC_SL1660 0x4d44
552 #define IUSC_PRE_SL1660 0x4553
555 * Transmit status Bits in Transmit Command/status Register (TCSR)
558 #define TCSR_PRESERVE 0x0F00
560 #define TCSR_UNDERWAIT BIT11
561 #define TXSTATUS_PREAMBLE_SENT BIT7
562 #define TXSTATUS_IDLE_SENT BIT6
563 #define TXSTATUS_ABORT_SENT BIT5
564 #define TXSTATUS_EOF_SENT BIT4
565 #define TXSTATUS_EOM_SENT BIT4
566 #define TXSTATUS_CRC_SENT BIT3
567 #define TXSTATUS_ALL_SENT BIT2
568 #define TXSTATUS_UNDERRUN BIT1
569 #define TXSTATUS_FIFO_EMPTY BIT0
570 #define TXSTATUS_ALL 0x00fa
571 #define usc_UnlatchTxstatusBits(a,b) usc_OutReg( (a), TCSR, (u16)((a)->tcsr_value + ((b) & 0x00FF)) )
574 #define MISCSTATUS_RXC_LATCHED BIT15
575 #define MISCSTATUS_RXC BIT14
576 #define MISCSTATUS_TXC_LATCHED BIT13
577 #define MISCSTATUS_TXC BIT12
578 #define MISCSTATUS_RI_LATCHED BIT11
579 #define MISCSTATUS_RI BIT10
580 #define MISCSTATUS_DSR_LATCHED BIT9
581 #define MISCSTATUS_DSR BIT8
582 #define MISCSTATUS_DCD_LATCHED BIT7
583 #define MISCSTATUS_DCD BIT6
584 #define MISCSTATUS_CTS_LATCHED BIT5
585 #define MISCSTATUS_CTS BIT4
586 #define MISCSTATUS_RCC_UNDERRUN BIT3
587 #define MISCSTATUS_DPLL_NO_SYNC BIT2
588 #define MISCSTATUS_BRG1_ZERO BIT1
589 #define MISCSTATUS_BRG0_ZERO BIT0
591 #define usc_UnlatchIostatusBits(a,b) usc_OutReg((a),MISR,(u16)((b) & 0xaaa0))
592 #define usc_UnlatchMiscstatusBits(a,b) usc_OutReg((a),MISR,(u16)((b) & 0x000f))
594 #define SICR_RXC_ACTIVE BIT15
595 #define SICR_RXC_INACTIVE BIT14
596 #define SICR_RXC (BIT15+BIT14)
597 #define SICR_TXC_ACTIVE BIT13
598 #define SICR_TXC_INACTIVE BIT12
599 #define SICR_TXC (BIT13+BIT12)
600 #define SICR_RI_ACTIVE BIT11
601 #define SICR_RI_INACTIVE BIT10
602 #define SICR_RI (BIT11+BIT10)
603 #define SICR_DSR_ACTIVE BIT9
604 #define SICR_DSR_INACTIVE BIT8
605 #define SICR_DSR (BIT9+BIT8)
606 #define SICR_DCD_ACTIVE BIT7
607 #define SICR_DCD_INACTIVE BIT6
608 #define SICR_DCD (BIT7+BIT6)
609 #define SICR_CTS_ACTIVE BIT5
610 #define SICR_CTS_INACTIVE BIT4
611 #define SICR_CTS (BIT5+BIT4)
612 #define SICR_RCC_UNDERFLOW BIT3
613 #define SICR_DPLL_NO_SYNC BIT2
614 #define SICR_BRG1_ZERO BIT1
615 #define SICR_BRG0_ZERO BIT0
617 void usc_DisableMasterIrqBit( struct mgsl_struct *info );
618 void usc_EnableMasterIrqBit( struct mgsl_struct *info );
619 void usc_EnableInterrupts( struct mgsl_struct *info, u16 IrqMask );
620 void usc_DisableInterrupts( struct mgsl_struct *info, u16 IrqMask );
621 void usc_ClearIrqPendingBits( struct mgsl_struct *info, u16 IrqMask );
623 #define usc_EnableInterrupts( a, b ) \
624 usc_OutReg( (a), ICR, (u16)((usc_InReg((a),ICR) & 0xff00) + 0xc0 + (b)) )
626 #define usc_DisableInterrupts( a, b ) \
627 usc_OutReg( (a), ICR, (u16)((usc_InReg((a),ICR) & 0xff00) + 0x80 + (b)) )
629 #define usc_EnableMasterIrqBit(a) \
630 usc_OutReg( (a), ICR, (u16)((usc_InReg((a),ICR) & 0x0f00) + 0xb000) )
632 #define usc_DisableMasterIrqBit(a) \
633 usc_OutReg( (a), ICR, (u16)(usc_InReg((a),ICR) & 0x7f00) )
635 #define usc_ClearIrqPendingBits( a, b ) usc_OutReg( (a), DCCR, 0x40 + (b) )
638 * Transmit status Bits in Transmit Control status Register (TCSR)
639 * and Transmit Interrupt Control Register (TICR) (except BIT2, BIT0)
642 #define TXSTATUS_PREAMBLE_SENT BIT7
643 #define TXSTATUS_IDLE_SENT BIT6
644 #define TXSTATUS_ABORT_SENT BIT5
645 #define TXSTATUS_EOF BIT4
646 #define TXSTATUS_CRC_SENT BIT3
647 #define TXSTATUS_ALL_SENT BIT2
648 #define TXSTATUS_UNDERRUN BIT1
649 #define TXSTATUS_FIFO_EMPTY BIT0
651 #define DICR_MASTER BIT15
652 #define DICR_TRANSMIT BIT0
653 #define DICR_RECEIVE BIT1
655 #define usc_EnableDmaInterrupts(a,b) \
656 usc_OutDmaReg( (a), DICR, (u16)(usc_InDmaReg((a),DICR) | (b)) )
658 #define usc_DisableDmaInterrupts(a,b) \
659 usc_OutDmaReg( (a), DICR, (u16)(usc_InDmaReg((a),DICR) & ~(b)) )
661 #define usc_EnableStatusIrqs(a,b) \
662 usc_OutReg( (a), SICR, (u16)(usc_InReg((a),SICR) | (b)) )
664 #define usc_DisablestatusIrqs(a,b) \
665 usc_OutReg( (a), SICR, (u16)(usc_InReg((a),SICR) & ~(b)) )
667 /* Transmit status Bits in Transmit Control status Register (TCSR) */
668 /* and Transmit Interrupt Control Register (TICR) (except BIT2, BIT0) */
671 #define DISABLE_UNCONDITIONAL 0
672 #define DISABLE_END_OF_FRAME 1
673 #define ENABLE_UNCONDITIONAL 2
674 #define ENABLE_AUTO_CTS 3
675 #define ENABLE_AUTO_DCD 3
676 #define usc_EnableTransmitter(a,b) \
677 usc_OutReg( (a), TMR, (u16)((usc_InReg((a),TMR) & 0xfffc) | (b)) )
678 #define usc_EnableReceiver(a,b) \
679 usc_OutReg( (a), RMR, (u16)((usc_InReg((a),RMR) & 0xfffc) | (b)) )
681 static u16 usc_InDmaReg( struct mgsl_struct *info, u16 Port );
682 static void usc_OutDmaReg( struct mgsl_struct *info, u16 Port, u16 Value );
683 static void usc_DmaCmd( struct mgsl_struct *info, u16 Cmd );
685 static u16 usc_InReg( struct mgsl_struct *info, u16 Port );
686 static void usc_OutReg( struct mgsl_struct *info, u16 Port, u16 Value );
687 static void usc_RTCmd( struct mgsl_struct *info, u16 Cmd );
688 void usc_RCmd( struct mgsl_struct *info, u16 Cmd );
689 void usc_TCmd( struct mgsl_struct *info, u16 Cmd );
691 #define usc_TCmd(a,b) usc_OutReg((a), TCSR, (u16)((a)->tcsr_value + (b)))
692 #define usc_RCmd(a,b) usc_OutReg((a), RCSR, (b))
694 #define usc_SetTransmitSyncChars(a,s0,s1) usc_OutReg((a), TSR, (u16)(((u16)s0<<8)|(u16)s1))
696 static void usc_process_rxoverrun_sync( struct mgsl_struct *info );
697 static void usc_start_receiver( struct mgsl_struct *info );
698 static void usc_stop_receiver( struct mgsl_struct *info );
700 static void usc_start_transmitter( struct mgsl_struct *info );
701 static void usc_stop_transmitter( struct mgsl_struct *info );
702 static void usc_set_txidle( struct mgsl_struct *info );
703 static void usc_load_txfifo( struct mgsl_struct *info );
705 static void usc_enable_aux_clock( struct mgsl_struct *info, u32 DataRate );
706 static void usc_enable_loopback( struct mgsl_struct *info, int enable );
708 static void usc_get_serial_signals( struct mgsl_struct *info );
709 static void usc_set_serial_signals( struct mgsl_struct *info );
711 static void usc_reset( struct mgsl_struct *info );
713 static void usc_set_sync_mode( struct mgsl_struct *info );
714 static void usc_set_sdlc_mode( struct mgsl_struct *info );
715 static void usc_set_async_mode( struct mgsl_struct *info );
716 static void usc_enable_async_clock( struct mgsl_struct *info, u32 DataRate );
718 static void usc_loopback_frame( struct mgsl_struct *info );
720 static void mgsl_tx_timeout(unsigned long context);
723 static void usc_loopmode_cancel_transmit( struct mgsl_struct * info );
724 static void usc_loopmode_insert_request( struct mgsl_struct * info );
725 static int usc_loopmode_active( struct mgsl_struct * info);
726 static void usc_loopmode_send_done( struct mgsl_struct * info );
728 static int mgsl_ioctl_common(struct mgsl_struct *info, unsigned int cmd, unsigned long arg);
731 #define dev_to_port(D) (dev_to_hdlc(D)->priv)
732 static void hdlcdev_tx_done(struct mgsl_struct *info);
733 static void hdlcdev_rx(struct mgsl_struct *info, char *buf, int size);
734 static int hdlcdev_init(struct mgsl_struct *info);
735 static void hdlcdev_exit(struct mgsl_struct *info);
739 * Defines a BUS descriptor value for the PCI adapter
740 * local bus address ranges.
743 #define BUS_DESCRIPTOR( WrHold, WrDly, RdDly, Nwdd, Nwad, Nxda, Nrdd, Nrad ) \
754 static void mgsl_trace_block(struct mgsl_struct *info,const char* data, int count, int xmit);
757 * Adapter diagnostic routines
759 static BOOLEAN mgsl_register_test( struct mgsl_struct *info );
760 static BOOLEAN mgsl_irq_test( struct mgsl_struct *info );
761 static BOOLEAN mgsl_dma_test( struct mgsl_struct *info );
762 static BOOLEAN mgsl_memory_test( struct mgsl_struct *info );
763 static int mgsl_adapter_test( struct mgsl_struct *info );
766 * device and resource management routines
768 static int mgsl_claim_resources(struct mgsl_struct *info);
769 static void mgsl_release_resources(struct mgsl_struct *info);
770 static void mgsl_add_device(struct mgsl_struct *info);
771 static struct mgsl_struct* mgsl_allocate_device(void);
774 * DMA buffer manupulation functions.
776 static void mgsl_free_rx_frame_buffers( struct mgsl_struct *info, unsigned int StartIndex, unsigned int EndIndex );
777 static int mgsl_get_rx_frame( struct mgsl_struct *info );
778 static int mgsl_get_raw_rx_frame( struct mgsl_struct *info );
779 static void mgsl_reset_rx_dma_buffers( struct mgsl_struct *info );
780 static void mgsl_reset_tx_dma_buffers( struct mgsl_struct *info );
781 static int num_free_tx_dma_buffers(struct mgsl_struct *info);
782 static void mgsl_load_tx_dma_buffer( struct mgsl_struct *info, const char *Buffer, unsigned int BufferSize);
783 static void mgsl_load_pci_memory(char* TargetPtr, const char* SourcePtr, unsigned short count);
786 * DMA and Shared Memory buffer allocation and formatting
788 static int mgsl_allocate_dma_buffers(struct mgsl_struct *info);
789 static void mgsl_free_dma_buffers(struct mgsl_struct *info);
790 static int mgsl_alloc_frame_memory(struct mgsl_struct *info, DMABUFFERENTRY *BufferList,int Buffercount);
791 static void mgsl_free_frame_memory(struct mgsl_struct *info, DMABUFFERENTRY *BufferList,int Buffercount);
792 static int mgsl_alloc_buffer_list_memory(struct mgsl_struct *info);
793 static void mgsl_free_buffer_list_memory(struct mgsl_struct *info);
794 static int mgsl_alloc_intermediate_rxbuffer_memory(struct mgsl_struct *info);
795 static void mgsl_free_intermediate_rxbuffer_memory(struct mgsl_struct *info);
796 static int mgsl_alloc_intermediate_txbuffer_memory(struct mgsl_struct *info);
797 static void mgsl_free_intermediate_txbuffer_memory(struct mgsl_struct *info);
798 static int load_next_tx_holding_buffer(struct mgsl_struct *info);
799 static int save_tx_buffer_request(struct mgsl_struct *info,const char *Buffer, unsigned int BufferSize);
802 * Bottom half interrupt handlers
804 static void mgsl_bh_handler(void* Context);
805 static void mgsl_bh_receive(struct mgsl_struct *info);
806 static void mgsl_bh_transmit(struct mgsl_struct *info);
807 static void mgsl_bh_status(struct mgsl_struct *info);
810 * Interrupt handler routines and dispatch table.
812 static void mgsl_isr_null( struct mgsl_struct *info );
813 static void mgsl_isr_transmit_data( struct mgsl_struct *info );
814 static void mgsl_isr_receive_data( struct mgsl_struct *info );
815 static void mgsl_isr_receive_status( struct mgsl_struct *info );
816 static void mgsl_isr_transmit_status( struct mgsl_struct *info );
817 static void mgsl_isr_io_pin( struct mgsl_struct *info );
818 static void mgsl_isr_misc( struct mgsl_struct *info );
819 static void mgsl_isr_receive_dma( struct mgsl_struct *info );
820 static void mgsl_isr_transmit_dma( struct mgsl_struct *info );
822 typedef void (*isr_dispatch_func)(struct mgsl_struct *);
824 static isr_dispatch_func UscIsrTable[7] =
829 mgsl_isr_transmit_data,
830 mgsl_isr_transmit_status,
831 mgsl_isr_receive_data,
832 mgsl_isr_receive_status
836 * ioctl call handlers
838 static int tiocmget(struct tty_struct *tty, struct file *file);
839 static int tiocmset(struct tty_struct *tty, struct file *file,
840 unsigned int set, unsigned int clear);
841 static int mgsl_get_stats(struct mgsl_struct * info, struct mgsl_icount
842 __user *user_icount);
843 static int mgsl_get_params(struct mgsl_struct * info, MGSL_PARAMS __user *user_params);
844 static int mgsl_set_params(struct mgsl_struct * info, MGSL_PARAMS __user *new_params);
845 static int mgsl_get_txidle(struct mgsl_struct * info, int __user *idle_mode);
846 static int mgsl_set_txidle(struct mgsl_struct * info, int idle_mode);
847 static int mgsl_txenable(struct mgsl_struct * info, int enable);
848 static int mgsl_txabort(struct mgsl_struct * info);
849 static int mgsl_rxenable(struct mgsl_struct * info, int enable);
850 static int mgsl_wait_event(struct mgsl_struct * info, int __user *mask);
851 static int mgsl_loopmode_send_done( struct mgsl_struct * info );
853 /* set non-zero on successful registration with PCI subsystem */
854 static int pci_registered;
857 * Global linked list of SyncLink devices
859 static struct mgsl_struct *mgsl_device_list;
860 static int mgsl_device_count;
863 * Set this param to non-zero to load eax with the
864 * .text section address and breakpoint on module load.
865 * This is useful for use with gdb and add-symbol-file command.
867 static int break_on_load;
870 * Driver major number, defaults to zero to get auto
871 * assigned major number. May be forced as module parameter.
876 * Array of user specified options for ISA adapters.
878 static int io[MAX_ISA_DEVICES];
879 static int irq[MAX_ISA_DEVICES];
880 static int dma[MAX_ISA_DEVICES];
881 static int debug_level;
882 static int maxframe[MAX_TOTAL_DEVICES];
883 static int dosyncppp[MAX_TOTAL_DEVICES];
884 static int txdmabufs[MAX_TOTAL_DEVICES];
885 static int txholdbufs[MAX_TOTAL_DEVICES];
887 module_param(break_on_load, bool, 0);
888 module_param(ttymajor, int, 0);
889 module_param_array(io, int, NULL, 0);
890 module_param_array(irq, int, NULL, 0);
891 module_param_array(dma, int, NULL, 0);
892 module_param(debug_level, int, 0);
893 module_param_array(maxframe, int, NULL, 0);
894 module_param_array(dosyncppp, int, NULL, 0);
895 module_param_array(txdmabufs, int, NULL, 0);
896 module_param_array(txholdbufs, int, NULL, 0);
898 static char *driver_name = "SyncLink serial driver";
899 static char *driver_version = "$Revision: 4.28 $";
901 static int synclink_init_one (struct pci_dev *dev,
902 const struct pci_device_id *ent);
903 static void synclink_remove_one (struct pci_dev *dev);
905 static struct pci_device_id synclink_pci_tbl[] = {
906 { PCI_VENDOR_ID_MICROGATE, PCI_DEVICE_ID_MICROGATE_USC, PCI_ANY_ID, PCI_ANY_ID, },
907 { PCI_VENDOR_ID_MICROGATE, 0x0210, PCI_ANY_ID, PCI_ANY_ID, },
908 { 0, }, /* terminate list */
910 MODULE_DEVICE_TABLE(pci, synclink_pci_tbl);
912 MODULE_LICENSE("GPL");
914 static struct pci_driver synclink_pci_driver = {
916 .id_table = synclink_pci_tbl,
917 .probe = synclink_init_one,
918 .remove = __devexit_p(synclink_remove_one),
921 static struct tty_driver *serial_driver;
923 /* number of characters left in xmit buffer before we ask for more */
924 #define WAKEUP_CHARS 256
927 static void mgsl_change_params(struct mgsl_struct *info);
928 static void mgsl_wait_until_sent(struct tty_struct *tty, int timeout);
931 * 1st function defined in .text section. Calling this function in
932 * init_module() followed by a breakpoint allows a remote debugger
933 * (gdb) to get the .text address for the add-symbol-file command.
934 * This allows remote debugging of dynamically loadable modules.
936 static void* mgsl_get_text_ptr(void)
938 return mgsl_get_text_ptr;
942 * tmp_buf is used as a temporary buffer by mgsl_write. We need to
943 * lock it in case the COPY_FROM_USER blocks while swapping in a page,
944 * and some other program tries to do a serial write at the same time.
945 * Since the lock will only come under contention when the system is
946 * swapping and available memory is low, it makes sense to share one
947 * buffer across all the serial ioports, since it significantly saves
948 * memory if large numbers of serial ports are open.
950 static unsigned char *tmp_buf;
951 static DECLARE_MUTEX(tmp_buf_sem);
953 static inline int mgsl_paranoia_check(struct mgsl_struct *info,
954 char *name, const char *routine)
956 #ifdef MGSL_PARANOIA_CHECK
957 static const char *badmagic =
958 "Warning: bad magic number for mgsl struct (%s) in %s\n";
959 static const char *badinfo =
960 "Warning: null mgsl_struct for (%s) in %s\n";
963 printk(badinfo, name, routine);
966 if (info->magic != MGSL_MAGIC) {
967 printk(badmagic, name, routine);
978 * line discipline callback wrappers
980 * The wrappers maintain line discipline references
981 * while calling into the line discipline.
983 * ldisc_receive_buf - pass receive data to line discipline
986 static void ldisc_receive_buf(struct tty_struct *tty,
987 const __u8 *data, char *flags, int count)
989 struct tty_ldisc *ld;
992 ld = tty_ldisc_ref(tty);
995 ld->receive_buf(tty, data, flags, count);
1000 /* mgsl_stop() throttle (stop) transmitter
1002 * Arguments: tty pointer to tty info structure
1003 * Return Value: None
1005 static void mgsl_stop(struct tty_struct *tty)
1007 struct mgsl_struct *info = (struct mgsl_struct *)tty->driver_data;
1008 unsigned long flags;
1010 if (mgsl_paranoia_check(info, tty->name, "mgsl_stop"))
1013 if ( debug_level >= DEBUG_LEVEL_INFO )
1014 printk("mgsl_stop(%s)\n",info->device_name);
1016 spin_lock_irqsave(&info->irq_spinlock,flags);
1017 if (info->tx_enabled)
1018 usc_stop_transmitter(info);
1019 spin_unlock_irqrestore(&info->irq_spinlock,flags);
1021 } /* end of mgsl_stop() */
1023 /* mgsl_start() release (start) transmitter
1025 * Arguments: tty pointer to tty info structure
1026 * Return Value: None
1028 static void mgsl_start(struct tty_struct *tty)
1030 struct mgsl_struct *info = (struct mgsl_struct *)tty->driver_data;
1031 unsigned long flags;
1033 if (mgsl_paranoia_check(info, tty->name, "mgsl_start"))
1036 if ( debug_level >= DEBUG_LEVEL_INFO )
1037 printk("mgsl_start(%s)\n",info->device_name);
1039 spin_lock_irqsave(&info->irq_spinlock,flags);
1040 if (!info->tx_enabled)
1041 usc_start_transmitter(info);
1042 spin_unlock_irqrestore(&info->irq_spinlock,flags);
1044 } /* end of mgsl_start() */
1047 * Bottom half work queue access functions
1050 /* mgsl_bh_action() Return next bottom half action to perform.
1051 * Return Value: BH action code or 0 if nothing to do.
1053 static int mgsl_bh_action(struct mgsl_struct *info)
1055 unsigned long flags;
1058 spin_lock_irqsave(&info->irq_spinlock,flags);
1060 if (info->pending_bh & BH_RECEIVE) {
1061 info->pending_bh &= ~BH_RECEIVE;
1063 } else if (info->pending_bh & BH_TRANSMIT) {
1064 info->pending_bh &= ~BH_TRANSMIT;
1066 } else if (info->pending_bh & BH_STATUS) {
1067 info->pending_bh &= ~BH_STATUS;
1072 /* Mark BH routine as complete */
1073 info->bh_running = 0;
1074 info->bh_requested = 0;
1077 spin_unlock_irqrestore(&info->irq_spinlock,flags);
1083 * Perform bottom half processing of work items queued by ISR.
1085 static void mgsl_bh_handler(void* Context)
1087 struct mgsl_struct *info = (struct mgsl_struct*)Context;
1093 if ( debug_level >= DEBUG_LEVEL_BH )
1094 printk( "%s(%d):mgsl_bh_handler(%s) entry\n",
1095 __FILE__,__LINE__,info->device_name);
1097 info->bh_running = 1;
1099 while((action = mgsl_bh_action(info)) != 0) {
1101 /* Process work item */
1102 if ( debug_level >= DEBUG_LEVEL_BH )
1103 printk( "%s(%d):mgsl_bh_handler() work item action=%d\n",
1104 __FILE__,__LINE__,action);
1109 mgsl_bh_receive(info);
1112 mgsl_bh_transmit(info);
1115 mgsl_bh_status(info);
1118 /* unknown work item ID */
1119 printk("Unknown work item ID=%08X!\n", action);
1124 if ( debug_level >= DEBUG_LEVEL_BH )
1125 printk( "%s(%d):mgsl_bh_handler(%s) exit\n",
1126 __FILE__,__LINE__,info->device_name);
1129 static void mgsl_bh_receive(struct mgsl_struct *info)
1131 int (*get_rx_frame)(struct mgsl_struct *info) =
1132 (info->params.mode == MGSL_MODE_HDLC ? mgsl_get_rx_frame : mgsl_get_raw_rx_frame);
1134 if ( debug_level >= DEBUG_LEVEL_BH )
1135 printk( "%s(%d):mgsl_bh_receive(%s)\n",
1136 __FILE__,__LINE__,info->device_name);
1140 if (info->rx_rcc_underrun) {
1141 unsigned long flags;
1142 spin_lock_irqsave(&info->irq_spinlock,flags);
1143 usc_start_receiver(info);
1144 spin_unlock_irqrestore(&info->irq_spinlock,flags);
1147 } while(get_rx_frame(info));
1150 static void mgsl_bh_transmit(struct mgsl_struct *info)
1152 struct tty_struct *tty = info->tty;
1153 unsigned long flags;
1155 if ( debug_level >= DEBUG_LEVEL_BH )
1156 printk( "%s(%d):mgsl_bh_transmit() entry on %s\n",
1157 __FILE__,__LINE__,info->device_name);
1161 wake_up_interruptible(&tty->write_wait);
1164 /* if transmitter idle and loopmode_send_done_requested
1165 * then start echoing RxD to TxD
1167 spin_lock_irqsave(&info->irq_spinlock,flags);
1168 if ( !info->tx_active && info->loopmode_send_done_requested )
1169 usc_loopmode_send_done( info );
1170 spin_unlock_irqrestore(&info->irq_spinlock,flags);
1173 static void mgsl_bh_status(struct mgsl_struct *info)
1175 if ( debug_level >= DEBUG_LEVEL_BH )
1176 printk( "%s(%d):mgsl_bh_status() entry on %s\n",
1177 __FILE__,__LINE__,info->device_name);
1179 info->ri_chkcount = 0;
1180 info->dsr_chkcount = 0;
1181 info->dcd_chkcount = 0;
1182 info->cts_chkcount = 0;
1185 /* mgsl_isr_receive_status()
1187 * Service a receive status interrupt. The type of status
1188 * interrupt is indicated by the state of the RCSR.
1189 * This is only used for HDLC mode.
1191 * Arguments: info pointer to device instance data
1192 * Return Value: None
1194 static void mgsl_isr_receive_status( struct mgsl_struct *info )
1196 u16 status = usc_InReg( info, RCSR );
1198 if ( debug_level >= DEBUG_LEVEL_ISR )
1199 printk("%s(%d):mgsl_isr_receive_status status=%04X\n",
1200 __FILE__,__LINE__,status);
1202 if ( (status & RXSTATUS_ABORT_RECEIVED) &&
1203 info->loopmode_insert_requested &&
1204 usc_loopmode_active(info) )
1206 ++info->icount.rxabort;
1207 info->loopmode_insert_requested = FALSE;
1209 /* clear CMR:13 to start echoing RxD to TxD */
1210 info->cmr_value &= ~BIT13;
1211 usc_OutReg(info, CMR, info->cmr_value);
1213 /* disable received abort irq (no longer required) */
1214 usc_OutReg(info, RICR,
1215 (usc_InReg(info, RICR) & ~RXSTATUS_ABORT_RECEIVED));
1218 if (status & (RXSTATUS_EXITED_HUNT + RXSTATUS_IDLE_RECEIVED)) {
1219 if (status & RXSTATUS_EXITED_HUNT)
1220 info->icount.exithunt++;
1221 if (status & RXSTATUS_IDLE_RECEIVED)
1222 info->icount.rxidle++;
1223 wake_up_interruptible(&info->event_wait_q);
1226 if (status & RXSTATUS_OVERRUN){
1227 info->icount.rxover++;
1228 usc_process_rxoverrun_sync( info );
1231 usc_ClearIrqPendingBits( info, RECEIVE_STATUS );
1232 usc_UnlatchRxstatusBits( info, status );
1234 } /* end of mgsl_isr_receive_status() */
1236 /* mgsl_isr_transmit_status()
1238 * Service a transmit status interrupt
1239 * HDLC mode :end of transmit frame
1240 * Async mode:all data is sent
1241 * transmit status is indicated by bits in the TCSR.
1243 * Arguments: info pointer to device instance data
1244 * Return Value: None
1246 static void mgsl_isr_transmit_status( struct mgsl_struct *info )
1248 u16 status = usc_InReg( info, TCSR );
1250 if ( debug_level >= DEBUG_LEVEL_ISR )
1251 printk("%s(%d):mgsl_isr_transmit_status status=%04X\n",
1252 __FILE__,__LINE__,status);
1254 usc_ClearIrqPendingBits( info, TRANSMIT_STATUS );
1255 usc_UnlatchTxstatusBits( info, status );
1257 if ( status & (TXSTATUS_UNDERRUN | TXSTATUS_ABORT_SENT) )
1259 /* finished sending HDLC abort. This may leave */
1260 /* the TxFifo with data from the aborted frame */
1261 /* so purge the TxFifo. Also shutdown the DMA */
1262 /* channel in case there is data remaining in */
1263 /* the DMA buffer */
1264 usc_DmaCmd( info, DmaCmd_ResetTxChannel );
1265 usc_RTCmd( info, RTCmd_PurgeTxFifo );
1268 if ( status & TXSTATUS_EOF_SENT )
1269 info->icount.txok++;
1270 else if ( status & TXSTATUS_UNDERRUN )
1271 info->icount.txunder++;
1272 else if ( status & TXSTATUS_ABORT_SENT )
1273 info->icount.txabort++;
1275 info->icount.txunder++;
1277 info->tx_active = 0;
1278 info->xmit_cnt = info->xmit_head = info->xmit_tail = 0;
1279 del_timer(&info->tx_timer);
1281 if ( info->drop_rts_on_tx_done ) {
1282 usc_get_serial_signals( info );
1283 if ( info->serial_signals & SerialSignal_RTS ) {
1284 info->serial_signals &= ~SerialSignal_RTS;
1285 usc_set_serial_signals( info );
1287 info->drop_rts_on_tx_done = 0;
1292 hdlcdev_tx_done(info);
1296 if (info->tty->stopped || info->tty->hw_stopped) {
1297 usc_stop_transmitter(info);
1300 info->pending_bh |= BH_TRANSMIT;
1303 } /* end of mgsl_isr_transmit_status() */
1305 /* mgsl_isr_io_pin()
1307 * Service an Input/Output pin interrupt. The type of
1308 * interrupt is indicated by bits in the MISR
1310 * Arguments: info pointer to device instance data
1311 * Return Value: None
1313 static void mgsl_isr_io_pin( struct mgsl_struct *info )
1315 struct mgsl_icount *icount;
1316 u16 status = usc_InReg( info, MISR );
1318 if ( debug_level >= DEBUG_LEVEL_ISR )
1319 printk("%s(%d):mgsl_isr_io_pin status=%04X\n",
1320 __FILE__,__LINE__,status);
1322 usc_ClearIrqPendingBits( info, IO_PIN );
1323 usc_UnlatchIostatusBits( info, status );
1325 if (status & (MISCSTATUS_CTS_LATCHED | MISCSTATUS_DCD_LATCHED |
1326 MISCSTATUS_DSR_LATCHED | MISCSTATUS_RI_LATCHED) ) {
1327 icount = &info->icount;
1328 /* update input line counters */
1329 if (status & MISCSTATUS_RI_LATCHED) {
1330 if ((info->ri_chkcount)++ >= IO_PIN_SHUTDOWN_LIMIT)
1331 usc_DisablestatusIrqs(info,SICR_RI);
1333 if ( status & MISCSTATUS_RI )
1334 info->input_signal_events.ri_up++;
1336 info->input_signal_events.ri_down++;
1338 if (status & MISCSTATUS_DSR_LATCHED) {
1339 if ((info->dsr_chkcount)++ >= IO_PIN_SHUTDOWN_LIMIT)
1340 usc_DisablestatusIrqs(info,SICR_DSR);
1342 if ( status & MISCSTATUS_DSR )
1343 info->input_signal_events.dsr_up++;
1345 info->input_signal_events.dsr_down++;
1347 if (status & MISCSTATUS_DCD_LATCHED) {
1348 if ((info->dcd_chkcount)++ >= IO_PIN_SHUTDOWN_LIMIT)
1349 usc_DisablestatusIrqs(info,SICR_DCD);
1351 if (status & MISCSTATUS_DCD) {
1352 info->input_signal_events.dcd_up++;
1354 info->input_signal_events.dcd_down++;
1357 hdlc_set_carrier(status & MISCSTATUS_DCD, info->netdev);
1360 if (status & MISCSTATUS_CTS_LATCHED)
1362 if ((info->cts_chkcount)++ >= IO_PIN_SHUTDOWN_LIMIT)
1363 usc_DisablestatusIrqs(info,SICR_CTS);
1365 if ( status & MISCSTATUS_CTS )
1366 info->input_signal_events.cts_up++;
1368 info->input_signal_events.cts_down++;
1370 wake_up_interruptible(&info->status_event_wait_q);
1371 wake_up_interruptible(&info->event_wait_q);
1373 if ( (info->flags & ASYNC_CHECK_CD) &&
1374 (status & MISCSTATUS_DCD_LATCHED) ) {
1375 if ( debug_level >= DEBUG_LEVEL_ISR )
1376 printk("%s CD now %s...", info->device_name,
1377 (status & MISCSTATUS_DCD) ? "on" : "off");
1378 if (status & MISCSTATUS_DCD)
1379 wake_up_interruptible(&info->open_wait);
1381 if ( debug_level >= DEBUG_LEVEL_ISR )
1382 printk("doing serial hangup...");
1384 tty_hangup(info->tty);
1388 if ( (info->flags & ASYNC_CTS_FLOW) &&
1389 (status & MISCSTATUS_CTS_LATCHED) ) {
1390 if (info->tty->hw_stopped) {
1391 if (status & MISCSTATUS_CTS) {
1392 if ( debug_level >= DEBUG_LEVEL_ISR )
1393 printk("CTS tx start...");
1395 info->tty->hw_stopped = 0;
1396 usc_start_transmitter(info);
1397 info->pending_bh |= BH_TRANSMIT;
1401 if (!(status & MISCSTATUS_CTS)) {
1402 if ( debug_level >= DEBUG_LEVEL_ISR )
1403 printk("CTS tx stop...");
1405 info->tty->hw_stopped = 1;
1406 usc_stop_transmitter(info);
1412 info->pending_bh |= BH_STATUS;
1414 /* for diagnostics set IRQ flag */
1415 if ( status & MISCSTATUS_TXC_LATCHED ){
1416 usc_OutReg( info, SICR,
1417 (unsigned short)(usc_InReg(info,SICR) & ~(SICR_TXC_ACTIVE+SICR_TXC_INACTIVE)) );
1418 usc_UnlatchIostatusBits( info, MISCSTATUS_TXC_LATCHED );
1419 info->irq_occurred = 1;
1422 } /* end of mgsl_isr_io_pin() */
1424 /* mgsl_isr_transmit_data()
1426 * Service a transmit data interrupt (async mode only).
1428 * Arguments: info pointer to device instance data
1429 * Return Value: None
1431 static void mgsl_isr_transmit_data( struct mgsl_struct *info )
1433 if ( debug_level >= DEBUG_LEVEL_ISR )
1434 printk("%s(%d):mgsl_isr_transmit_data xmit_cnt=%d\n",
1435 __FILE__,__LINE__,info->xmit_cnt);
1437 usc_ClearIrqPendingBits( info, TRANSMIT_DATA );
1439 if (info->tty->stopped || info->tty->hw_stopped) {
1440 usc_stop_transmitter(info);
1444 if ( info->xmit_cnt )
1445 usc_load_txfifo( info );
1447 info->tx_active = 0;
1449 if (info->xmit_cnt < WAKEUP_CHARS)
1450 info->pending_bh |= BH_TRANSMIT;
1452 } /* end of mgsl_isr_transmit_data() */
1454 /* mgsl_isr_receive_data()
1456 * Service a receive data interrupt. This occurs
1457 * when operating in asynchronous interrupt transfer mode.
1458 * The receive data FIFO is flushed to the receive data buffers.
1460 * Arguments: info pointer to device instance data
1461 * Return Value: None
1463 static void mgsl_isr_receive_data( struct mgsl_struct *info )
1467 unsigned char DataByte;
1468 struct tty_struct *tty = info->tty;
1469 struct mgsl_icount *icount = &info->icount;
1471 if ( debug_level >= DEBUG_LEVEL_ISR )
1472 printk("%s(%d):mgsl_isr_receive_data\n",
1475 usc_ClearIrqPendingBits( info, RECEIVE_DATA );
1477 /* select FIFO status for RICR readback */
1478 usc_RCmd( info, RCmd_SelectRicrRxFifostatus );
1480 /* clear the Wordstatus bit so that status readback */
1481 /* only reflects the status of this byte */
1482 usc_OutReg( info, RICR+LSBONLY, (u16)(usc_InReg(info, RICR+LSBONLY) & ~BIT3 ));
1484 /* flush the receive FIFO */
1486 while( (Fifocount = (usc_InReg(info,RICR) >> 8)) ) {
1487 /* read one byte from RxFIFO */
1488 outw( (inw(info->io_base + CCAR) & 0x0780) | (RDR+LSBONLY),
1489 info->io_base + CCAR );
1490 DataByte = inb( info->io_base + CCAR );
1492 /* get the status of the received byte */
1493 status = usc_InReg(info, RCSR);
1494 if ( status & (RXSTATUS_FRAMING_ERROR + RXSTATUS_PARITY_ERROR +
1495 RXSTATUS_OVERRUN + RXSTATUS_BREAK_RECEIVED) )
1496 usc_UnlatchRxstatusBits(info,RXSTATUS_ALL);
1498 if (tty->flip.count >= TTY_FLIPBUF_SIZE)
1501 *tty->flip.char_buf_ptr = DataByte;
1504 *tty->flip.flag_buf_ptr = 0;
1505 if ( status & (RXSTATUS_FRAMING_ERROR + RXSTATUS_PARITY_ERROR +
1506 RXSTATUS_OVERRUN + RXSTATUS_BREAK_RECEIVED) ) {
1507 printk("rxerr=%04X\n",status);
1508 /* update error statistics */
1509 if ( status & RXSTATUS_BREAK_RECEIVED ) {
1510 status &= ~(RXSTATUS_FRAMING_ERROR + RXSTATUS_PARITY_ERROR);
1512 } else if (status & RXSTATUS_PARITY_ERROR)
1514 else if (status & RXSTATUS_FRAMING_ERROR)
1516 else if (status & RXSTATUS_OVERRUN) {
1517 /* must issue purge fifo cmd before */
1518 /* 16C32 accepts more receive chars */
1519 usc_RTCmd(info,RTCmd_PurgeRxFifo);
1523 /* discard char if tty control flags say so */
1524 if (status & info->ignore_status_mask)
1527 status &= info->read_status_mask;
1529 if (status & RXSTATUS_BREAK_RECEIVED) {
1530 *tty->flip.flag_buf_ptr = TTY_BREAK;
1531 if (info->flags & ASYNC_SAK)
1533 } else if (status & RXSTATUS_PARITY_ERROR)
1534 *tty->flip.flag_buf_ptr = TTY_PARITY;
1535 else if (status & RXSTATUS_FRAMING_ERROR)
1536 *tty->flip.flag_buf_ptr = TTY_FRAME;
1537 if (status & RXSTATUS_OVERRUN) {
1538 /* Overrun is special, since it's
1539 * reported immediately, and doesn't
1540 * affect the current character
1542 if (tty->flip.count < TTY_FLIPBUF_SIZE) {
1544 tty->flip.flag_buf_ptr++;
1545 tty->flip.char_buf_ptr++;
1546 *tty->flip.flag_buf_ptr = TTY_OVERRUN;
1549 } /* end of if (error) */
1551 tty->flip.flag_buf_ptr++;
1552 tty->flip.char_buf_ptr++;
1556 if ( debug_level >= DEBUG_LEVEL_ISR ) {
1557 printk("%s(%d):mgsl_isr_receive_data flip count=%d\n",
1558 __FILE__,__LINE__,tty->flip.count);
1559 printk("%s(%d):rx=%d brk=%d parity=%d frame=%d overrun=%d\n",
1560 __FILE__,__LINE__,icount->rx,icount->brk,
1561 icount->parity,icount->frame,icount->overrun);
1564 if ( tty->flip.count )
1565 tty_flip_buffer_push(tty);
1570 * Service a miscellaneos interrupt source.
1572 * Arguments: info pointer to device extension (instance data)
1573 * Return Value: None
1575 static void mgsl_isr_misc( struct mgsl_struct *info )
1577 u16 status = usc_InReg( info, MISR );
1579 if ( debug_level >= DEBUG_LEVEL_ISR )
1580 printk("%s(%d):mgsl_isr_misc status=%04X\n",
1581 __FILE__,__LINE__,status);
1583 if ((status & MISCSTATUS_RCC_UNDERRUN) &&
1584 (info->params.mode == MGSL_MODE_HDLC)) {
1586 /* turn off receiver and rx DMA */
1587 usc_EnableReceiver(info,DISABLE_UNCONDITIONAL);
1588 usc_DmaCmd(info, DmaCmd_ResetRxChannel);
1589 usc_UnlatchRxstatusBits(info, RXSTATUS_ALL);
1590 usc_ClearIrqPendingBits(info, RECEIVE_DATA + RECEIVE_STATUS);
1591 usc_DisableInterrupts(info, RECEIVE_DATA + RECEIVE_STATUS);
1593 /* schedule BH handler to restart receiver */
1594 info->pending_bh |= BH_RECEIVE;
1595 info->rx_rcc_underrun = 1;
1598 usc_ClearIrqPendingBits( info, MISC );
1599 usc_UnlatchMiscstatusBits( info, status );
1601 } /* end of mgsl_isr_misc() */
1605 * Services undefined interrupt vectors from the
1606 * USC. (hence this function SHOULD never be called)
1608 * Arguments: info pointer to device extension (instance data)
1609 * Return Value: None
1611 static void mgsl_isr_null( struct mgsl_struct *info )
1614 } /* end of mgsl_isr_null() */
1616 /* mgsl_isr_receive_dma()
1618 * Service a receive DMA channel interrupt.
1619 * For this driver there are two sources of receive DMA interrupts
1620 * as identified in the Receive DMA mode Register (RDMR):
1622 * BIT3 EOA/EOL End of List, all receive buffers in receive
1623 * buffer list have been filled (no more free buffers
1624 * available). The DMA controller has shut down.
1626 * BIT2 EOB End of Buffer. This interrupt occurs when a receive
1627 * DMA buffer is terminated in response to completion
1628 * of a good frame or a frame with errors. The status
1629 * of the frame is stored in the buffer entry in the
1630 * list of receive buffer entries.
1632 * Arguments: info pointer to device instance data
1633 * Return Value: None
1635 static void mgsl_isr_receive_dma( struct mgsl_struct *info )
1639 /* clear interrupt pending and IUS bit for Rx DMA IRQ */
1640 usc_OutDmaReg( info, CDIR, BIT9+BIT1 );
1642 /* Read the receive DMA status to identify interrupt type. */
1643 /* This also clears the status bits. */
1644 status = usc_InDmaReg( info, RDMR );
1646 if ( debug_level >= DEBUG_LEVEL_ISR )
1647 printk("%s(%d):mgsl_isr_receive_dma(%s) status=%04X\n",
1648 __FILE__,__LINE__,info->device_name,status);
1650 info->pending_bh |= BH_RECEIVE;
1652 if ( status & BIT3 ) {
1653 info->rx_overflow = 1;
1654 info->icount.buf_overrun++;
1657 } /* end of mgsl_isr_receive_dma() */
1659 /* mgsl_isr_transmit_dma()
1661 * This function services a transmit DMA channel interrupt.
1663 * For this driver there is one source of transmit DMA interrupts
1664 * as identified in the Transmit DMA Mode Register (TDMR):
1666 * BIT2 EOB End of Buffer. This interrupt occurs when a
1667 * transmit DMA buffer has been emptied.
1669 * The driver maintains enough transmit DMA buffers to hold at least
1670 * one max frame size transmit frame. When operating in a buffered
1671 * transmit mode, there may be enough transmit DMA buffers to hold at
1672 * least two or more max frame size frames. On an EOB condition,
1673 * determine if there are any queued transmit buffers and copy into
1674 * transmit DMA buffers if we have room.
1676 * Arguments: info pointer to device instance data
1677 * Return Value: None
1679 static void mgsl_isr_transmit_dma( struct mgsl_struct *info )
1683 /* clear interrupt pending and IUS bit for Tx DMA IRQ */
1684 usc_OutDmaReg(info, CDIR, BIT8+BIT0 );
1686 /* Read the transmit DMA status to identify interrupt type. */
1687 /* This also clears the status bits. */
1689 status = usc_InDmaReg( info, TDMR );
1691 if ( debug_level >= DEBUG_LEVEL_ISR )
1692 printk("%s(%d):mgsl_isr_transmit_dma(%s) status=%04X\n",
1693 __FILE__,__LINE__,info->device_name,status);
1695 if ( status & BIT2 ) {
1696 --info->tx_dma_buffers_used;
1698 /* if there are transmit frames queued,
1699 * try to load the next one
1701 if ( load_next_tx_holding_buffer(info) ) {
1702 /* if call returns non-zero value, we have
1703 * at least one free tx holding buffer
1705 info->pending_bh |= BH_TRANSMIT;
1709 } /* end of mgsl_isr_transmit_dma() */
1713 * Interrupt service routine entry point.
1717 * irq interrupt number that caused interrupt
1718 * dev_id device ID supplied during interrupt registration
1719 * regs interrupted processor context
1721 * Return Value: None
1723 static irqreturn_t mgsl_interrupt(int irq, void *dev_id, struct pt_regs * regs)
1725 struct mgsl_struct * info;
1729 if ( debug_level >= DEBUG_LEVEL_ISR )
1730 printk("%s(%d):mgsl_interrupt(%d)entry.\n",
1731 __FILE__,__LINE__,irq);
1733 info = (struct mgsl_struct *)dev_id;
1737 spin_lock(&info->irq_spinlock);
1740 /* Read the interrupt vectors from hardware. */
1741 UscVector = usc_InReg(info, IVR) >> 9;
1742 DmaVector = usc_InDmaReg(info, DIVR);
1744 if ( debug_level >= DEBUG_LEVEL_ISR )
1745 printk("%s(%d):%s UscVector=%08X DmaVector=%08X\n",
1746 __FILE__,__LINE__,info->device_name,UscVector,DmaVector);
1748 if ( !UscVector && !DmaVector )
1751 /* Dispatch interrupt vector */
1753 (*UscIsrTable[UscVector])(info);
1754 else if ( (DmaVector&(BIT10|BIT9)) == BIT10)
1755 mgsl_isr_transmit_dma(info);
1757 mgsl_isr_receive_dma(info);
1759 if ( info->isr_overflow ) {
1760 printk(KERN_ERR"%s(%d):%s isr overflow irq=%d\n",
1761 __FILE__,__LINE__,info->device_name, irq);
1762 usc_DisableMasterIrqBit(info);
1763 usc_DisableDmaInterrupts(info,DICR_MASTER);
1768 /* Request bottom half processing if there's something
1769 * for it to do and the bh is not already running
1772 if ( info->pending_bh && !info->bh_running && !info->bh_requested ) {
1773 if ( debug_level >= DEBUG_LEVEL_ISR )
1774 printk("%s(%d):%s queueing bh task.\n",
1775 __FILE__,__LINE__,info->device_name);
1776 schedule_work(&info->task);
1777 info->bh_requested = 1;
1780 spin_unlock(&info->irq_spinlock);
1782 if ( debug_level >= DEBUG_LEVEL_ISR )
1783 printk("%s(%d):mgsl_interrupt(%d)exit.\n",
1784 __FILE__,__LINE__,irq);
1786 } /* end of mgsl_interrupt() */
1790 * Initialize and start device.
1792 * Arguments: info pointer to device instance data
1793 * Return Value: 0 if success, otherwise error code
1795 static int startup(struct mgsl_struct * info)
1799 if ( debug_level >= DEBUG_LEVEL_INFO )
1800 printk("%s(%d):mgsl_startup(%s)\n",__FILE__,__LINE__,info->device_name);
1802 if (info->flags & ASYNC_INITIALIZED)
1805 if (!info->xmit_buf) {
1806 /* allocate a page of memory for a transmit buffer */
1807 info->xmit_buf = (unsigned char *)get_zeroed_page(GFP_KERNEL);
1808 if (!info->xmit_buf) {
1809 printk(KERN_ERR"%s(%d):%s can't allocate transmit buffer\n",
1810 __FILE__,__LINE__,info->device_name);
1815 info->pending_bh = 0;
1817 init_timer(&info->tx_timer);
1818 info->tx_timer.data = (unsigned long)info;
1819 info->tx_timer.function = mgsl_tx_timeout;
1821 /* Allocate and claim adapter resources */
1822 retval = mgsl_claim_resources(info);
1824 /* perform existence check and diagnostics */
1826 retval = mgsl_adapter_test(info);
1829 if (capable(CAP_SYS_ADMIN) && info->tty)
1830 set_bit(TTY_IO_ERROR, &info->tty->flags);
1831 mgsl_release_resources(info);
1835 /* program hardware for current parameters */
1836 mgsl_change_params(info);
1839 clear_bit(TTY_IO_ERROR, &info->tty->flags);
1841 info->flags |= ASYNC_INITIALIZED;
1845 } /* end of startup() */
1849 * Called by mgsl_close() and mgsl_hangup() to shutdown hardware
1851 * Arguments: info pointer to device instance data
1852 * Return Value: None
1854 static void shutdown(struct mgsl_struct * info)
1856 unsigned long flags;
1858 if (!(info->flags & ASYNC_INITIALIZED))
1861 if (debug_level >= DEBUG_LEVEL_INFO)
1862 printk("%s(%d):mgsl_shutdown(%s)\n",
1863 __FILE__,__LINE__, info->device_name );
1865 /* clear status wait queue because status changes */
1866 /* can't happen after shutting down the hardware */
1867 wake_up_interruptible(&info->status_event_wait_q);
1868 wake_up_interruptible(&info->event_wait_q);
1870 del_timer(&info->tx_timer);
1872 if (info->xmit_buf) {
1873 free_page((unsigned long) info->xmit_buf);
1874 info->xmit_buf = NULL;
1877 spin_lock_irqsave(&info->irq_spinlock,flags);
1878 usc_DisableMasterIrqBit(info);
1879 usc_stop_receiver(info);
1880 usc_stop_transmitter(info);
1881 usc_DisableInterrupts(info,RECEIVE_DATA + RECEIVE_STATUS +
1882 TRANSMIT_DATA + TRANSMIT_STATUS + IO_PIN + MISC );
1883 usc_DisableDmaInterrupts(info,DICR_MASTER + DICR_TRANSMIT + DICR_RECEIVE);
1885 /* Disable DMAEN (Port 7, Bit 14) */
1886 /* This disconnects the DMA request signal from the ISA bus */
1887 /* on the ISA adapter. This has no effect for the PCI adapter */
1888 usc_OutReg(info, PCR, (u16)((usc_InReg(info, PCR) | BIT15) | BIT14));
1890 /* Disable INTEN (Port 6, Bit12) */
1891 /* This disconnects the IRQ request signal to the ISA bus */
1892 /* on the ISA adapter. This has no effect for the PCI adapter */
1893 usc_OutReg(info, PCR, (u16)((usc_InReg(info, PCR) | BIT13) | BIT12));
1895 if (!info->tty || info->tty->termios->c_cflag & HUPCL) {
1896 info->serial_signals &= ~(SerialSignal_DTR + SerialSignal_RTS);
1897 usc_set_serial_signals(info);
1900 spin_unlock_irqrestore(&info->irq_spinlock,flags);
1902 mgsl_release_resources(info);
1905 set_bit(TTY_IO_ERROR, &info->tty->flags);
1907 info->flags &= ~ASYNC_INITIALIZED;
1909 } /* end of shutdown() */
1911 static void mgsl_program_hw(struct mgsl_struct *info)
1913 unsigned long flags;
1915 spin_lock_irqsave(&info->irq_spinlock,flags);
1917 usc_stop_receiver(info);
1918 usc_stop_transmitter(info);
1919 info->xmit_cnt = info->xmit_head = info->xmit_tail = 0;
1921 if (info->params.mode == MGSL_MODE_HDLC ||
1922 info->params.mode == MGSL_MODE_RAW ||
1924 usc_set_sync_mode(info);
1926 usc_set_async_mode(info);
1928 usc_set_serial_signals(info);
1930 info->dcd_chkcount = 0;
1931 info->cts_chkcount = 0;
1932 info->ri_chkcount = 0;
1933 info->dsr_chkcount = 0;
1935 usc_EnableStatusIrqs(info,SICR_CTS+SICR_DSR+SICR_DCD+SICR_RI);
1936 usc_EnableInterrupts(info, IO_PIN);
1937 usc_get_serial_signals(info);
1939 if (info->netcount || info->tty->termios->c_cflag & CREAD)
1940 usc_start_receiver(info);
1942 spin_unlock_irqrestore(&info->irq_spinlock,flags);
1945 /* Reconfigure adapter based on new parameters
1947 static void mgsl_change_params(struct mgsl_struct *info)
1952 if (!info->tty || !info->tty->termios)
1955 if (debug_level >= DEBUG_LEVEL_INFO)
1956 printk("%s(%d):mgsl_change_params(%s)\n",
1957 __FILE__,__LINE__, info->device_name );
1959 cflag = info->tty->termios->c_cflag;
1961 /* if B0 rate (hangup) specified then negate DTR and RTS */
1962 /* otherwise assert DTR and RTS */
1964 info->serial_signals |= SerialSignal_RTS + SerialSignal_DTR;
1966 info->serial_signals &= ~(SerialSignal_RTS + SerialSignal_DTR);
1968 /* byte size and parity */
1970 switch (cflag & CSIZE) {
1971 case CS5: info->params.data_bits = 5; break;
1972 case CS6: info->params.data_bits = 6; break;
1973 case CS7: info->params.data_bits = 7; break;
1974 case CS8: info->params.data_bits = 8; break;
1975 /* Never happens, but GCC is too dumb to figure it out */
1976 default: info->params.data_bits = 7; break;
1980 info->params.stop_bits = 2;
1982 info->params.stop_bits = 1;
1984 info->params.parity = ASYNC_PARITY_NONE;
1985 if (cflag & PARENB) {
1987 info->params.parity = ASYNC_PARITY_ODD;
1989 info->params.parity = ASYNC_PARITY_EVEN;
1992 info->params.parity = ASYNC_PARITY_SPACE;
1996 /* calculate number of jiffies to transmit a full
1997 * FIFO (32 bytes) at specified data rate
1999 bits_per_char = info->params.data_bits +
2000 info->params.stop_bits + 1;
2002 /* if port data rate is set to 460800 or less then
2003 * allow tty settings to override, otherwise keep the
2004 * current data rate.
2006 if (info->params.data_rate <= 460800)
2007 info->params.data_rate = tty_get_baud_rate(info->tty);
2009 if ( info->params.data_rate ) {
2010 info->timeout = (32*HZ*bits_per_char) /
2011 info->params.data_rate;
2013 info->timeout += HZ/50; /* Add .02 seconds of slop */
2015 if (cflag & CRTSCTS)
2016 info->flags |= ASYNC_CTS_FLOW;
2018 info->flags &= ~ASYNC_CTS_FLOW;
2021 info->flags &= ~ASYNC_CHECK_CD;
2023 info->flags |= ASYNC_CHECK_CD;
2025 /* process tty input control flags */
2027 info->read_status_mask = RXSTATUS_OVERRUN;
2028 if (I_INPCK(info->tty))
2029 info->read_status_mask |= RXSTATUS_PARITY_ERROR | RXSTATUS_FRAMING_ERROR;
2030 if (I_BRKINT(info->tty) || I_PARMRK(info->tty))
2031 info->read_status_mask |= RXSTATUS_BREAK_RECEIVED;
2033 if (I_IGNPAR(info->tty))
2034 info->ignore_status_mask |= RXSTATUS_PARITY_ERROR | RXSTATUS_FRAMING_ERROR;
2035 if (I_IGNBRK(info->tty)) {
2036 info->ignore_status_mask |= RXSTATUS_BREAK_RECEIVED;
2037 /* If ignoring parity and break indicators, ignore
2038 * overruns too. (For real raw support).
2040 if (I_IGNPAR(info->tty))
2041 info->ignore_status_mask |= RXSTATUS_OVERRUN;
2044 mgsl_program_hw(info);
2046 } /* end of mgsl_change_params() */
2050 * Add a character to the transmit buffer.
2052 * Arguments: tty pointer to tty information structure
2053 * ch character to add to transmit buffer
2055 * Return Value: None
2057 static void mgsl_put_char(struct tty_struct *tty, unsigned char ch)
2059 struct mgsl_struct *info = (struct mgsl_struct *)tty->driver_data;
2060 unsigned long flags;
2062 if ( debug_level >= DEBUG_LEVEL_INFO ) {
2063 printk( "%s(%d):mgsl_put_char(%d) on %s\n",
2064 __FILE__,__LINE__,ch,info->device_name);
2067 if (mgsl_paranoia_check(info, tty->name, "mgsl_put_char"))
2070 if (!tty || !info->xmit_buf)
2073 spin_lock_irqsave(&info->irq_spinlock,flags);
2075 if ( (info->params.mode == MGSL_MODE_ASYNC ) || !info->tx_active ) {
2077 if (info->xmit_cnt < SERIAL_XMIT_SIZE - 1) {
2078 info->xmit_buf[info->xmit_head++] = ch;
2079 info->xmit_head &= SERIAL_XMIT_SIZE-1;
2084 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2086 } /* end of mgsl_put_char() */
2088 /* mgsl_flush_chars()
2090 * Enable transmitter so remaining characters in the
2091 * transmit buffer are sent.
2093 * Arguments: tty pointer to tty information structure
2094 * Return Value: None
2096 static void mgsl_flush_chars(struct tty_struct *tty)
2098 struct mgsl_struct *info = (struct mgsl_struct *)tty->driver_data;
2099 unsigned long flags;
2101 if ( debug_level >= DEBUG_LEVEL_INFO )
2102 printk( "%s(%d):mgsl_flush_chars() entry on %s xmit_cnt=%d\n",
2103 __FILE__,__LINE__,info->device_name,info->xmit_cnt);
2105 if (mgsl_paranoia_check(info, tty->name, "mgsl_flush_chars"))
2108 if (info->xmit_cnt <= 0 || tty->stopped || tty->hw_stopped ||
2112 if ( debug_level >= DEBUG_LEVEL_INFO )
2113 printk( "%s(%d):mgsl_flush_chars() entry on %s starting transmitter\n",
2114 __FILE__,__LINE__,info->device_name );
2116 spin_lock_irqsave(&info->irq_spinlock,flags);
2118 if (!info->tx_active) {
2119 if ( (info->params.mode == MGSL_MODE_HDLC ||
2120 info->params.mode == MGSL_MODE_RAW) && info->xmit_cnt ) {
2121 /* operating in synchronous (frame oriented) mode */
2122 /* copy data from circular xmit_buf to */
2123 /* transmit DMA buffer. */
2124 mgsl_load_tx_dma_buffer(info,
2125 info->xmit_buf,info->xmit_cnt);
2127 usc_start_transmitter(info);
2130 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2132 } /* end of mgsl_flush_chars() */
2136 * Send a block of data
2140 * tty pointer to tty information structure
2141 * buf pointer to buffer containing send data
2142 * count size of send data in bytes
2144 * Return Value: number of characters written
2146 static int mgsl_write(struct tty_struct * tty,
2147 const unsigned char *buf, int count)
2150 struct mgsl_struct *info = (struct mgsl_struct *)tty->driver_data;
2151 unsigned long flags;
2153 if ( debug_level >= DEBUG_LEVEL_INFO )
2154 printk( "%s(%d):mgsl_write(%s) count=%d\n",
2155 __FILE__,__LINE__,info->device_name,count);
2157 if (mgsl_paranoia_check(info, tty->name, "mgsl_write"))
2160 if (!tty || !info->xmit_buf || !tmp_buf)
2163 if ( info->params.mode == MGSL_MODE_HDLC ||
2164 info->params.mode == MGSL_MODE_RAW ) {
2165 /* operating in synchronous (frame oriented) mode */
2166 /* operating in synchronous (frame oriented) mode */
2167 if (info->tx_active) {
2169 if ( info->params.mode == MGSL_MODE_HDLC ) {
2173 /* transmitter is actively sending data -
2174 * if we have multiple transmit dma and
2175 * holding buffers, attempt to queue this
2176 * frame for transmission at a later time.
2178 if (info->tx_holding_count >= info->num_tx_holding_buffers ) {
2179 /* no tx holding buffers available */
2184 /* queue transmit frame request */
2186 save_tx_buffer_request(info,buf,count);
2188 /* if we have sufficient tx dma buffers,
2189 * load the next buffered tx request
2191 spin_lock_irqsave(&info->irq_spinlock,flags);
2192 load_next_tx_holding_buffer(info);
2193 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2197 /* if operating in HDLC LoopMode and the adapter */
2198 /* has yet to be inserted into the loop, we can't */
2201 if ( (info->params.flags & HDLC_FLAG_HDLC_LOOPMODE) &&
2202 !usc_loopmode_active(info) )
2208 if ( info->xmit_cnt ) {
2209 /* Send accumulated from send_char() calls */
2210 /* as frame and wait before accepting more data. */
2213 /* copy data from circular xmit_buf to */
2214 /* transmit DMA buffer. */
2215 mgsl_load_tx_dma_buffer(info,
2216 info->xmit_buf,info->xmit_cnt);
2217 if ( debug_level >= DEBUG_LEVEL_INFO )
2218 printk( "%s(%d):mgsl_write(%s) sync xmit_cnt flushing\n",
2219 __FILE__,__LINE__,info->device_name);
2221 if ( debug_level >= DEBUG_LEVEL_INFO )
2222 printk( "%s(%d):mgsl_write(%s) sync transmit accepted\n",
2223 __FILE__,__LINE__,info->device_name);
2225 info->xmit_cnt = count;
2226 mgsl_load_tx_dma_buffer(info,buf,count);
2230 spin_lock_irqsave(&info->irq_spinlock,flags);
2231 c = min_t(int, count,
2232 min(SERIAL_XMIT_SIZE - info->xmit_cnt - 1,
2233 SERIAL_XMIT_SIZE - info->xmit_head));
2235 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2238 memcpy(info->xmit_buf + info->xmit_head, buf, c);
2239 info->xmit_head = ((info->xmit_head + c) &
2240 (SERIAL_XMIT_SIZE-1));
2241 info->xmit_cnt += c;
2242 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2249 if (info->xmit_cnt && !tty->stopped && !tty->hw_stopped) {
2250 spin_lock_irqsave(&info->irq_spinlock,flags);
2251 if (!info->tx_active)
2252 usc_start_transmitter(info);
2253 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2256 if ( debug_level >= DEBUG_LEVEL_INFO )
2257 printk( "%s(%d):mgsl_write(%s) returning=%d\n",
2258 __FILE__,__LINE__,info->device_name,ret);
2262 } /* end of mgsl_write() */
2264 /* mgsl_write_room()
2266 * Return the count of free bytes in transmit buffer
2268 * Arguments: tty pointer to tty info structure
2269 * Return Value: None
2271 static int mgsl_write_room(struct tty_struct *tty)
2273 struct mgsl_struct *info = (struct mgsl_struct *)tty->driver_data;
2276 if (mgsl_paranoia_check(info, tty->name, "mgsl_write_room"))
2278 ret = SERIAL_XMIT_SIZE - info->xmit_cnt - 1;
2282 if (debug_level >= DEBUG_LEVEL_INFO)
2283 printk("%s(%d):mgsl_write_room(%s)=%d\n",
2284 __FILE__,__LINE__, info->device_name,ret );
2286 if ( info->params.mode == MGSL_MODE_HDLC ||
2287 info->params.mode == MGSL_MODE_RAW ) {
2288 /* operating in synchronous (frame oriented) mode */
2289 if ( info->tx_active )
2292 return HDLC_MAX_FRAME_SIZE;
2297 } /* end of mgsl_write_room() */
2299 /* mgsl_chars_in_buffer()
2301 * Return the count of bytes in transmit buffer
2303 * Arguments: tty pointer to tty info structure
2304 * Return Value: None
2306 static int mgsl_chars_in_buffer(struct tty_struct *tty)
2308 struct mgsl_struct *info = (struct mgsl_struct *)tty->driver_data;
2310 if (debug_level >= DEBUG_LEVEL_INFO)
2311 printk("%s(%d):mgsl_chars_in_buffer(%s)\n",
2312 __FILE__,__LINE__, info->device_name );
2314 if (mgsl_paranoia_check(info, tty->name, "mgsl_chars_in_buffer"))
2317 if (debug_level >= DEBUG_LEVEL_INFO)
2318 printk("%s(%d):mgsl_chars_in_buffer(%s)=%d\n",
2319 __FILE__,__LINE__, info->device_name,info->xmit_cnt );
2321 if ( info->params.mode == MGSL_MODE_HDLC ||
2322 info->params.mode == MGSL_MODE_RAW ) {
2323 /* operating in synchronous (frame oriented) mode */
2324 if ( info->tx_active )
2325 return info->max_frame_size;
2330 return info->xmit_cnt;
2331 } /* end of mgsl_chars_in_buffer() */
2333 /* mgsl_flush_buffer()
2335 * Discard all data in the send buffer
2337 * Arguments: tty pointer to tty info structure
2338 * Return Value: None
2340 static void mgsl_flush_buffer(struct tty_struct *tty)
2342 struct mgsl_struct *info = (struct mgsl_struct *)tty->driver_data;
2343 unsigned long flags;
2345 if (debug_level >= DEBUG_LEVEL_INFO)
2346 printk("%s(%d):mgsl_flush_buffer(%s) entry\n",
2347 __FILE__,__LINE__, info->device_name );
2349 if (mgsl_paranoia_check(info, tty->name, "mgsl_flush_buffer"))
2352 spin_lock_irqsave(&info->irq_spinlock,flags);
2353 info->xmit_cnt = info->xmit_head = info->xmit_tail = 0;
2354 del_timer(&info->tx_timer);
2355 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2357 wake_up_interruptible(&tty->write_wait);
2361 /* mgsl_send_xchar()
2363 * Send a high-priority XON/XOFF character
2365 * Arguments: tty pointer to tty info structure
2366 * ch character to send
2367 * Return Value: None
2369 static void mgsl_send_xchar(struct tty_struct *tty, char ch)
2371 struct mgsl_struct *info = (struct mgsl_struct *)tty->driver_data;
2372 unsigned long flags;
2374 if (debug_level >= DEBUG_LEVEL_INFO)
2375 printk("%s(%d):mgsl_send_xchar(%s,%d)\n",
2376 __FILE__,__LINE__, info->device_name, ch );
2378 if (mgsl_paranoia_check(info, tty->name, "mgsl_send_xchar"))
2383 /* Make sure transmit interrupts are on */
2384 spin_lock_irqsave(&info->irq_spinlock,flags);
2385 if (!info->tx_enabled)
2386 usc_start_transmitter(info);
2387 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2389 } /* end of mgsl_send_xchar() */
2393 * Signal remote device to throttle send data (our receive data)
2395 * Arguments: tty pointer to tty info structure
2396 * Return Value: None
2398 static void mgsl_throttle(struct tty_struct * tty)
2400 struct mgsl_struct *info = (struct mgsl_struct *)tty->driver_data;
2401 unsigned long flags;
2403 if (debug_level >= DEBUG_LEVEL_INFO)
2404 printk("%s(%d):mgsl_throttle(%s) entry\n",
2405 __FILE__,__LINE__, info->device_name );
2407 if (mgsl_paranoia_check(info, tty->name, "mgsl_throttle"))
2411 mgsl_send_xchar(tty, STOP_CHAR(tty));
2413 if (tty->termios->c_cflag & CRTSCTS) {
2414 spin_lock_irqsave(&info->irq_spinlock,flags);
2415 info->serial_signals &= ~SerialSignal_RTS;
2416 usc_set_serial_signals(info);
2417 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2419 } /* end of mgsl_throttle() */
2421 /* mgsl_unthrottle()
2423 * Signal remote device to stop throttling send data (our receive data)
2425 * Arguments: tty pointer to tty info structure
2426 * Return Value: None
2428 static void mgsl_unthrottle(struct tty_struct * tty)
2430 struct mgsl_struct *info = (struct mgsl_struct *)tty->driver_data;
2431 unsigned long flags;
2433 if (debug_level >= DEBUG_LEVEL_INFO)
2434 printk("%s(%d):mgsl_unthrottle(%s) entry\n",
2435 __FILE__,__LINE__, info->device_name );
2437 if (mgsl_paranoia_check(info, tty->name, "mgsl_unthrottle"))
2444 mgsl_send_xchar(tty, START_CHAR(tty));
2447 if (tty->termios->c_cflag & CRTSCTS) {
2448 spin_lock_irqsave(&info->irq_spinlock,flags);
2449 info->serial_signals |= SerialSignal_RTS;
2450 usc_set_serial_signals(info);
2451 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2454 } /* end of mgsl_unthrottle() */
2458 * get the current serial parameters information
2460 * Arguments: info pointer to device instance data
2461 * user_icount pointer to buffer to hold returned stats
2463 * Return Value: 0 if success, otherwise error code
2465 static int mgsl_get_stats(struct mgsl_struct * info, struct mgsl_icount __user *user_icount)
2469 if (debug_level >= DEBUG_LEVEL_INFO)
2470 printk("%s(%d):mgsl_get_params(%s)\n",
2471 __FILE__,__LINE__, info->device_name);
2473 COPY_TO_USER(err,user_icount, &info->icount, sizeof(struct mgsl_icount));
2475 if ( debug_level >= DEBUG_LEVEL_INFO )
2476 printk( "%s(%d):mgsl_get_stats(%s) user buffer copy failed\n",
2477 __FILE__,__LINE__,info->device_name);
2483 } /* end of mgsl_get_stats() */
2485 /* mgsl_get_params()
2487 * get the current serial parameters information
2489 * Arguments: info pointer to device instance data
2490 * user_params pointer to buffer to hold returned params
2492 * Return Value: 0 if success, otherwise error code
2494 static int mgsl_get_params(struct mgsl_struct * info, MGSL_PARAMS __user *user_params)
2497 if (debug_level >= DEBUG_LEVEL_INFO)
2498 printk("%s(%d):mgsl_get_params(%s)\n",
2499 __FILE__,__LINE__, info->device_name);
2501 COPY_TO_USER(err,user_params, &info->params, sizeof(MGSL_PARAMS));
2503 if ( debug_level >= DEBUG_LEVEL_INFO )
2504 printk( "%s(%d):mgsl_get_params(%s) user buffer copy failed\n",
2505 __FILE__,__LINE__,info->device_name);
2511 } /* end of mgsl_get_params() */
2513 /* mgsl_set_params()
2515 * set the serial parameters
2519 * info pointer to device instance data
2520 * new_params user buffer containing new serial params
2522 * Return Value: 0 if success, otherwise error code
2524 static int mgsl_set_params(struct mgsl_struct * info, MGSL_PARAMS __user *new_params)
2526 unsigned long flags;
2527 MGSL_PARAMS tmp_params;
2530 if (debug_level >= DEBUG_LEVEL_INFO)
2531 printk("%s(%d):mgsl_set_params %s\n", __FILE__,__LINE__,
2532 info->device_name );
2533 COPY_FROM_USER(err,&tmp_params, new_params, sizeof(MGSL_PARAMS));
2535 if ( debug_level >= DEBUG_LEVEL_INFO )
2536 printk( "%s(%d):mgsl_set_params(%s) user buffer copy failed\n",
2537 __FILE__,__LINE__,info->device_name);
2541 spin_lock_irqsave(&info->irq_spinlock,flags);
2542 memcpy(&info->params,&tmp_params,sizeof(MGSL_PARAMS));
2543 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2545 mgsl_change_params(info);
2549 } /* end of mgsl_set_params() */
2551 /* mgsl_get_txidle()
2553 * get the current transmit idle mode
2555 * Arguments: info pointer to device instance data
2556 * idle_mode pointer to buffer to hold returned idle mode
2558 * Return Value: 0 if success, otherwise error code
2560 static int mgsl_get_txidle(struct mgsl_struct * info, int __user *idle_mode)
2564 if (debug_level >= DEBUG_LEVEL_INFO)
2565 printk("%s(%d):mgsl_get_txidle(%s)=%d\n",
2566 __FILE__,__LINE__, info->device_name, info->idle_mode);
2568 COPY_TO_USER(err,idle_mode, &info->idle_mode, sizeof(int));
2570 if ( debug_level >= DEBUG_LEVEL_INFO )
2571 printk( "%s(%d):mgsl_get_txidle(%s) user buffer copy failed\n",
2572 __FILE__,__LINE__,info->device_name);
2578 } /* end of mgsl_get_txidle() */
2580 /* mgsl_set_txidle() service ioctl to set transmit idle mode
2582 * Arguments: info pointer to device instance data
2583 * idle_mode new idle mode
2585 * Return Value: 0 if success, otherwise error code
2587 static int mgsl_set_txidle(struct mgsl_struct * info, int idle_mode)
2589 unsigned long flags;
2591 if (debug_level >= DEBUG_LEVEL_INFO)
2592 printk("%s(%d):mgsl_set_txidle(%s,%d)\n", __FILE__,__LINE__,
2593 info->device_name, idle_mode );
2595 spin_lock_irqsave(&info->irq_spinlock,flags);
2596 info->idle_mode = idle_mode;
2597 usc_set_txidle( info );
2598 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2601 } /* end of mgsl_set_txidle() */
2605 * enable or disable the transmitter
2609 * info pointer to device instance data
2610 * enable 1 = enable, 0 = disable
2612 * Return Value: 0 if success, otherwise error code
2614 static int mgsl_txenable(struct mgsl_struct * info, int enable)
2616 unsigned long flags;
2618 if (debug_level >= DEBUG_LEVEL_INFO)
2619 printk("%s(%d):mgsl_txenable(%s,%d)\n", __FILE__,__LINE__,
2620 info->device_name, enable);
2622 spin_lock_irqsave(&info->irq_spinlock,flags);
2624 if ( !info->tx_enabled ) {
2626 usc_start_transmitter(info);
2627 /*--------------------------------------------------
2628 * if HDLC/SDLC Loop mode, attempt to insert the
2629 * station in the 'loop' by setting CMR:13. Upon
2630 * receipt of the next GoAhead (RxAbort) sequence,
2631 * the OnLoop indicator (CCSR:7) should go active
2632 * to indicate that we are on the loop
2633 *--------------------------------------------------*/
2634 if ( info->params.flags & HDLC_FLAG_HDLC_LOOPMODE )
2635 usc_loopmode_insert_request( info );
2638 if ( info->tx_enabled )
2639 usc_stop_transmitter(info);
2641 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2644 } /* end of mgsl_txenable() */
2646 /* mgsl_txabort() abort send HDLC frame
2648 * Arguments: info pointer to device instance data
2649 * Return Value: 0 if success, otherwise error code
2651 static int mgsl_txabort(struct mgsl_struct * info)
2653 unsigned long flags;
2655 if (debug_level >= DEBUG_LEVEL_INFO)
2656 printk("%s(%d):mgsl_txabort(%s)\n", __FILE__,__LINE__,
2659 spin_lock_irqsave(&info->irq_spinlock,flags);
2660 if ( info->tx_active && info->params.mode == MGSL_MODE_HDLC )
2662 if ( info->params.flags & HDLC_FLAG_HDLC_LOOPMODE )
2663 usc_loopmode_cancel_transmit( info );
2665 usc_TCmd(info,TCmd_SendAbort);
2667 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2670 } /* end of mgsl_txabort() */
2672 /* mgsl_rxenable() enable or disable the receiver
2674 * Arguments: info pointer to device instance data
2675 * enable 1 = enable, 0 = disable
2676 * Return Value: 0 if success, otherwise error code
2678 static int mgsl_rxenable(struct mgsl_struct * info, int enable)
2680 unsigned long flags;
2682 if (debug_level >= DEBUG_LEVEL_INFO)
2683 printk("%s(%d):mgsl_rxenable(%s,%d)\n", __FILE__,__LINE__,
2684 info->device_name, enable);
2686 spin_lock_irqsave(&info->irq_spinlock,flags);
2688 if ( !info->rx_enabled )
2689 usc_start_receiver(info);
2691 if ( info->rx_enabled )
2692 usc_stop_receiver(info);
2694 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2697 } /* end of mgsl_rxenable() */
2699 /* mgsl_wait_event() wait for specified event to occur
2701 * Arguments: info pointer to device instance data
2702 * mask pointer to bitmask of events to wait for
2703 * Return Value: 0 if successful and bit mask updated with
2704 * of events triggerred,
2705 * otherwise error code
2707 static int mgsl_wait_event(struct mgsl_struct * info, int __user * mask_ptr)
2709 unsigned long flags;
2712 struct mgsl_icount cprev, cnow;
2715 struct _input_signal_events oldsigs, newsigs;
2716 DECLARE_WAITQUEUE(wait, current);
2718 COPY_FROM_USER(rc,&mask, mask_ptr, sizeof(int));
2723 if (debug_level >= DEBUG_LEVEL_INFO)
2724 printk("%s(%d):mgsl_wait_event(%s,%d)\n", __FILE__,__LINE__,
2725 info->device_name, mask);
2727 spin_lock_irqsave(&info->irq_spinlock,flags);
2729 /* return immediately if state matches requested events */
2730 usc_get_serial_signals(info);
2731 s = info->serial_signals;
2733 ( ((s & SerialSignal_DSR) ? MgslEvent_DsrActive:MgslEvent_DsrInactive) +
2734 ((s & SerialSignal_DCD) ? MgslEvent_DcdActive:MgslEvent_DcdInactive) +
2735 ((s & SerialSignal_CTS) ? MgslEvent_CtsActive:MgslEvent_CtsInactive) +
2736 ((s & SerialSignal_RI) ? MgslEvent_RiActive :MgslEvent_RiInactive) );
2738 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2742 /* save current irq counts */
2743 cprev = info->icount;
2744 oldsigs = info->input_signal_events;
2746 /* enable hunt and idle irqs if needed */
2747 if (mask & (MgslEvent_ExitHuntMode + MgslEvent_IdleReceived)) {
2748 u16 oldreg = usc_InReg(info,RICR);
2749 u16 newreg = oldreg +
2750 (mask & MgslEvent_ExitHuntMode ? RXSTATUS_EXITED_HUNT:0) +
2751 (mask & MgslEvent_IdleReceived ? RXSTATUS_IDLE_RECEIVED:0);
2752 if (oldreg != newreg)
2753 usc_OutReg(info, RICR, newreg);
2756 set_current_state(TASK_INTERRUPTIBLE);
2757 add_wait_queue(&info->event_wait_q, &wait);
2759 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2764 if (signal_pending(current)) {
2769 /* get current irq counts */
2770 spin_lock_irqsave(&info->irq_spinlock,flags);
2771 cnow = info->icount;
2772 newsigs = info->input_signal_events;
2773 set_current_state(TASK_INTERRUPTIBLE);
2774 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2776 /* if no change, wait aborted for some reason */
2777 if (newsigs.dsr_up == oldsigs.dsr_up &&
2778 newsigs.dsr_down == oldsigs.dsr_down &&
2779 newsigs.dcd_up == oldsigs.dcd_up &&
2780 newsigs.dcd_down == oldsigs.dcd_down &&
2781 newsigs.cts_up == oldsigs.cts_up &&
2782 newsigs.cts_down == oldsigs.cts_down &&
2783 newsigs.ri_up == oldsigs.ri_up &&
2784 newsigs.ri_down == oldsigs.ri_down &&
2785 cnow.exithunt == cprev.exithunt &&
2786 cnow.rxidle == cprev.rxidle) {
2792 ( (newsigs.dsr_up != oldsigs.dsr_up ? MgslEvent_DsrActive:0) +
2793 (newsigs.dsr_down != oldsigs.dsr_down ? MgslEvent_DsrInactive:0) +
2794 (newsigs.dcd_up != oldsigs.dcd_up ? MgslEvent_DcdActive:0) +
2795 (newsigs.dcd_down != oldsigs.dcd_down ? MgslEvent_DcdInactive:0) +
2796 (newsigs.cts_up != oldsigs.cts_up ? MgslEvent_CtsActive:0) +
2797 (newsigs.cts_down != oldsigs.cts_down ? MgslEvent_CtsInactive:0) +
2798 (newsigs.ri_up != oldsigs.ri_up ? MgslEvent_RiActive:0) +
2799 (newsigs.ri_down != oldsigs.ri_down ? MgslEvent_RiInactive:0) +
2800 (cnow.exithunt != cprev.exithunt ? MgslEvent_ExitHuntMode:0) +
2801 (cnow.rxidle != cprev.rxidle ? MgslEvent_IdleReceived:0) );
2809 remove_wait_queue(&info->event_wait_q, &wait);
2810 set_current_state(TASK_RUNNING);
2812 if (mask & (MgslEvent_ExitHuntMode + MgslEvent_IdleReceived)) {
2813 spin_lock_irqsave(&info->irq_spinlock,flags);
2814 if (!waitqueue_active(&info->event_wait_q)) {
2815 /* disable enable exit hunt mode/idle rcvd IRQs */
2816 usc_OutReg(info, RICR, usc_InReg(info,RICR) &
2817 ~(RXSTATUS_EXITED_HUNT + RXSTATUS_IDLE_RECEIVED));
2819 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2823 PUT_USER(rc, events, mask_ptr);
2827 } /* end of mgsl_wait_event() */
2829 static int modem_input_wait(struct mgsl_struct *info,int arg)
2831 unsigned long flags;
2833 struct mgsl_icount cprev, cnow;
2834 DECLARE_WAITQUEUE(wait, current);
2836 /* save current irq counts */
2837 spin_lock_irqsave(&info->irq_spinlock,flags);
2838 cprev = info->icount;
2839 add_wait_queue(&info->status_event_wait_q, &wait);
2840 set_current_state(TASK_INTERRUPTIBLE);
2841 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2845 if (signal_pending(current)) {
2850 /* get new irq counts */
2851 spin_lock_irqsave(&info->irq_spinlock,flags);
2852 cnow = info->icount;
2853 set_current_state(TASK_INTERRUPTIBLE);
2854 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2856 /* if no change, wait aborted for some reason */
2857 if (cnow.rng == cprev.rng && cnow.dsr == cprev.dsr &&
2858 cnow.dcd == cprev.dcd && cnow.cts == cprev.cts) {
2863 /* check for change in caller specified modem input */
2864 if ((arg & TIOCM_RNG && cnow.rng != cprev.rng) ||
2865 (arg & TIOCM_DSR && cnow.dsr != cprev.dsr) ||
2866 (arg & TIOCM_CD && cnow.dcd != cprev.dcd) ||
2867 (arg & TIOCM_CTS && cnow.cts != cprev.cts)) {
2874 remove_wait_queue(&info->status_event_wait_q, &wait);
2875 set_current_state(TASK_RUNNING);
2879 /* return the state of the serial control and status signals
2881 static int tiocmget(struct tty_struct *tty, struct file *file)
2883 struct mgsl_struct *info = (struct mgsl_struct *)tty->driver_data;
2884 unsigned int result;
2885 unsigned long flags;
2887 spin_lock_irqsave(&info->irq_spinlock,flags);
2888 usc_get_serial_signals(info);
2889 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2891 result = ((info->serial_signals & SerialSignal_RTS) ? TIOCM_RTS:0) +
2892 ((info->serial_signals & SerialSignal_DTR) ? TIOCM_DTR:0) +
2893 ((info->serial_signals & SerialSignal_DCD) ? TIOCM_CAR:0) +
2894 ((info->serial_signals & SerialSignal_RI) ? TIOCM_RNG:0) +
2895 ((info->serial_signals & SerialSignal_DSR) ? TIOCM_DSR:0) +
2896 ((info->serial_signals & SerialSignal_CTS) ? TIOCM_CTS:0);
2898 if (debug_level >= DEBUG_LEVEL_INFO)
2899 printk("%s(%d):%s tiocmget() value=%08X\n",
2900 __FILE__,__LINE__, info->device_name, result );
2904 /* set modem control signals (DTR/RTS)
2906 static int tiocmset(struct tty_struct *tty, struct file *file,
2907 unsigned int set, unsigned int clear)
2909 struct mgsl_struct *info = (struct mgsl_struct *)tty->driver_data;
2910 unsigned long flags;
2912 if (debug_level >= DEBUG_LEVEL_INFO)
2913 printk("%s(%d):%s tiocmset(%x,%x)\n",
2914 __FILE__,__LINE__,info->device_name, set, clear);
2916 if (set & TIOCM_RTS)
2917 info->serial_signals |= SerialSignal_RTS;
2918 if (set & TIOCM_DTR)
2919 info->serial_signals |= SerialSignal_DTR;
2920 if (clear & TIOCM_RTS)
2921 info->serial_signals &= ~SerialSignal_RTS;
2922 if (clear & TIOCM_DTR)
2923 info->serial_signals &= ~SerialSignal_DTR;
2925 spin_lock_irqsave(&info->irq_spinlock,flags);
2926 usc_set_serial_signals(info);
2927 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2932 /* mgsl_break() Set or clear transmit break condition
2934 * Arguments: tty pointer to tty instance data
2935 * break_state -1=set break condition, 0=clear
2936 * Return Value: None
2938 static void mgsl_break(struct tty_struct *tty, int break_state)
2940 struct mgsl_struct * info = (struct mgsl_struct *)tty->driver_data;
2941 unsigned long flags;
2943 if (debug_level >= DEBUG_LEVEL_INFO)
2944 printk("%s(%d):mgsl_break(%s,%d)\n",
2945 __FILE__,__LINE__, info->device_name, break_state);
2947 if (mgsl_paranoia_check(info, tty->name, "mgsl_break"))
2950 spin_lock_irqsave(&info->irq_spinlock,flags);
2951 if (break_state == -1)
2952 usc_OutReg(info,IOCR,(u16)(usc_InReg(info,IOCR) | BIT7));
2954 usc_OutReg(info,IOCR,(u16)(usc_InReg(info,IOCR) & ~BIT7));
2955 spin_unlock_irqrestore(&info->irq_spinlock,flags);
2957 } /* end of mgsl_break() */
2959 /* mgsl_ioctl() Service an IOCTL request
2963 * tty pointer to tty instance data
2964 * file pointer to associated file object for device
2965 * cmd IOCTL command code
2966 * arg command argument/context
2968 * Return Value: 0 if success, otherwise error code
2970 static int mgsl_ioctl(struct tty_struct *tty, struct file * file,
2971 unsigned int cmd, unsigned long arg)
2973 struct mgsl_struct * info = (struct mgsl_struct *)tty->driver_data;
2975 if (debug_level >= DEBUG_LEVEL_INFO)
2976 printk("%s(%d):mgsl_ioctl %s cmd=%08X\n", __FILE__,__LINE__,
2977 info->device_name, cmd );
2979 if (mgsl_paranoia_check(info, tty->name, "mgsl_ioctl"))
2982 if ((cmd != TIOCGSERIAL) && (cmd != TIOCSSERIAL) &&
2983 (cmd != TIOCMIWAIT) && (cmd != TIOCGICOUNT)) {
2984 if (tty->flags & (1 << TTY_IO_ERROR))
2988 return mgsl_ioctl_common(info, cmd, arg);
2991 static int mgsl_ioctl_common(struct mgsl_struct *info, unsigned int cmd, unsigned long arg)
2994 struct mgsl_icount cnow; /* kernel counter temps */
2995 void __user *argp = (void __user *)arg;
2996 struct serial_icounter_struct __user *p_cuser; /* user space */
2997 unsigned long flags;
3000 case MGSL_IOCGPARAMS:
3001 return mgsl_get_params(info, argp);
3002 case MGSL_IOCSPARAMS:
3003 return mgsl_set_params(info, argp);
3004 case MGSL_IOCGTXIDLE:
3005 return mgsl_get_txidle(info, argp);
3006 case MGSL_IOCSTXIDLE:
3007 return mgsl_set_txidle(info,(int)arg);
3008 case MGSL_IOCTXENABLE:
3009 return mgsl_txenable(info,(int)arg);
3010 case MGSL_IOCRXENABLE:
3011 return mgsl_rxenable(info,(int)arg);
3012 case MGSL_IOCTXABORT:
3013 return mgsl_txabort(info);
3014 case MGSL_IOCGSTATS:
3015 return mgsl_get_stats(info, argp);
3016 case MGSL_IOCWAITEVENT:
3017 return mgsl_wait_event(info, argp);
3018 case MGSL_IOCLOOPTXDONE:
3019 return mgsl_loopmode_send_done(info);
3020 /* Wait for modem input (DCD,RI,DSR,CTS) change
3021 * as specified by mask in arg (TIOCM_RNG/DSR/CD/CTS)
3024 return modem_input_wait(info,(int)arg);
3027 * Get counter of input serial line interrupts (DCD,RI,DSR,CTS)
3028 * Return: write counters to the user passed counter struct
3029 * NB: both 1->0 and 0->1 transitions are counted except for
3030 * RI where only 0->1 is counted.
3033 spin_lock_irqsave(&info->irq_spinlock,flags);
3034 cnow = info->icount;
3035 spin_unlock_irqrestore(&info->irq_spinlock,flags);
3037 PUT_USER(error,cnow.cts, &p_cuser->cts);
3038 if (error) return error;
3039 PUT_USER(error,cnow.dsr, &p_cuser->dsr);
3040 if (error) return error;
3041 PUT_USER(error,cnow.rng, &p_cuser->rng);
3042 if (error) return error;
3043 PUT_USER(error,cnow.dcd, &p_cuser->dcd);
3044 if (error) return error;
3045 PUT_USER(error,cnow.rx, &p_cuser->rx);
3046 if (error) return error;
3047 PUT_USER(error,cnow.tx, &p_cuser->tx);
3048 if (error) return error;
3049 PUT_USER(error,cnow.frame, &p_cuser->frame);
3050 if (error) return error;
3051 PUT_USER(error,cnow.overrun, &p_cuser->overrun);
3052 if (error) return error;
3053 PUT_USER(error,cnow.parity, &p_cuser->parity);
3054 if (error) return error;
3055 PUT_USER(error,cnow.brk, &p_cuser->brk);
3056 if (error) return error;
3057 PUT_USER(error,cnow.buf_overrun, &p_cuser->buf_overrun);
3058 if (error) return error;
3061 return -ENOIOCTLCMD;
3066 /* mgsl_set_termios()
3068 * Set new termios settings
3072 * tty pointer to tty structure
3073 * termios pointer to buffer to hold returned old termios
3075 * Return Value: None
3077 static void mgsl_set_termios(struct tty_struct *tty, struct termios *old_termios)
3079 struct mgsl_struct *info = (struct mgsl_struct *)tty->driver_data;
3080 unsigned long flags;
3082 if (debug_level >= DEBUG_LEVEL_INFO)
3083 printk("%s(%d):mgsl_set_termios %s\n", __FILE__,__LINE__,
3084 tty->driver->name );
3086 /* just return if nothing has changed */
3087 if ((tty->termios->c_cflag == old_termios->c_cflag)
3088 && (RELEVANT_IFLAG(tty->termios->c_iflag)
3089 == RELEVANT_IFLAG(old_termios->c_iflag)))
3092 mgsl_change_params(info);
3094 /* Handle transition to B0 status */
3095 if (old_termios->c_cflag & CBAUD &&
3096 !(tty->termios->c_cflag & CBAUD)) {
3097 info->serial_signals &= ~(SerialSignal_RTS + SerialSignal_DTR);
3098 spin_lock_irqsave(&info->irq_spinlock,flags);
3099 usc_set_serial_signals(info);
3100 spin_unlock_irqrestore(&info->irq_spinlock,flags);
3103 /* Handle transition away from B0 status */
3104 if (!(old_termios->c_cflag & CBAUD) &&
3105 tty->termios->c_cflag & CBAUD) {
3106 info->serial_signals |= SerialSignal_DTR;
3107 if (!(tty->termios->c_cflag & CRTSCTS) ||
3108 !test_bit(TTY_THROTTLED, &tty->flags)) {
3109 info->serial_signals |= SerialSignal_RTS;
3111 spin_lock_irqsave(&info->irq_spinlock,flags);
3112 usc_set_serial_signals(info);
3113 spin_unlock_irqrestore(&info->irq_spinlock,flags);
3116 /* Handle turning off CRTSCTS */
3117 if (old_termios->c_cflag & CRTSCTS &&
3118 !(tty->termios->c_cflag & CRTSCTS)) {
3119 tty->hw_stopped = 0;
3123 } /* end of mgsl_set_termios() */
3127 * Called when port is closed. Wait for remaining data to be
3128 * sent. Disable port and free resources.
3132 * tty pointer to open tty structure
3133 * filp pointer to open file object
3135 * Return Value: None
3137 static void mgsl_close(struct tty_struct *tty, struct file * filp)
3139 struct mgsl_struct * info = (struct mgsl_struct *)tty->driver_data;
3141 if (mgsl_paranoia_check(info, tty->name, "mgsl_close"))
3144 if (debug_level >= DEBUG_LEVEL_INFO)
3145 printk("%s(%d):mgsl_close(%s) entry, count=%d\n",
3146 __FILE__,__LINE__, info->device_name, info->count);
3151 if (tty_hung_up_p(filp))
3154 if ((tty->count == 1) && (info->count != 1)) {
3156 * tty->count is 1 and the tty structure will be freed.
3157 * info->count should be one in this case.
3158 * if it's not, correct it so that the port is shutdown.
3160 printk("mgsl_close: bad refcount; tty->count is 1, "
3161 "info->count is %d\n", info->count);
3167 /* if at least one open remaining, leave hardware active */
3171 info->flags |= ASYNC_CLOSING;
3173 /* set tty->closing to notify line discipline to
3174 * only process XON/XOFF characters. Only the N_TTY
3175 * discipline appears to use this (ppp does not).
3179 /* wait for transmit data to clear all layers */
3181 if (info->closing_wait != ASYNC_CLOSING_WAIT_NONE) {
3182 if (debug_level >= DEBUG_LEVEL_INFO)
3183 printk("%s(%d):mgsl_close(%s) calling tty_wait_until_sent\n",
3184 __FILE__,__LINE__, info->device_name );
3185 tty_wait_until_sent(tty, info->closing_wait);
3188 if (info->flags & ASYNC_INITIALIZED)
3189 mgsl_wait_until_sent(tty, info->timeout);
3191 if (tty->driver->flush_buffer)
3192 tty->driver->flush_buffer(tty);
3194 tty_ldisc_flush(tty);
3201 if (info->blocked_open) {
3202 if (info->close_delay) {
3203 msleep_interruptible(jiffies_to_msecs(info->close_delay));
3205 wake_up_interruptible(&info->open_wait);
3208 info->flags &= ~(ASYNC_NORMAL_ACTIVE|ASYNC_CLOSING);
3210 wake_up_interruptible(&info->close_wait);
3213 if (debug_level >= DEBUG_LEVEL_INFO)
3214 printk("%s(%d):mgsl_close(%s) exit, count=%d\n", __FILE__,__LINE__,
3215 tty->driver->name, info->count);
3217 } /* end of mgsl_close() */
3219 /* mgsl_wait_until_sent()
3221 * Wait until the transmitter is empty.
3225 * tty pointer to tty info structure
3226 * timeout time to wait for send completion
3228 * Return Value: None
3230 static void mgsl_wait_until_sent(struct tty_struct *tty, int timeout)
3232 struct mgsl_struct * info = (struct mgsl_struct *)tty->driver_data;
3233 unsigned long orig_jiffies, char_time;
3238 if (debug_level >= DEBUG_LEVEL_INFO)
3239 printk("%s(%d):mgsl_wait_until_sent(%s) entry\n",
3240 __FILE__,__LINE__, info->device_name );
3242 if (mgsl_paranoia_check(info, tty->name, "mgsl_wait_until_sent"))
3245 if (!(info->flags & ASYNC_INITIALIZED))
3248 orig_jiffies = jiffies;
3250 /* Set check interval to 1/5 of estimated time to
3251 * send a character, and make it at least 1. The check
3252 * interval should also be less than the timeout.
3253 * Note: use tight timings here to satisfy the NIST-PCTS.
3256 if ( info->params.data_rate ) {
3257 char_time = info->timeout/(32 * 5);
3264 char_time = min_t(unsigned long, char_time, timeout);
3266 if ( info->params.mode == MGSL_MODE_HDLC ||
3267 info->params.mode == MGSL_MODE_RAW ) {
3268 while (info->tx_active) {
3269 msleep_interruptible(jiffies_to_msecs(char_time));
3270 if (signal_pending(current))
3272 if (timeout && time_after(jiffies, orig_jiffies + timeout))
3276 while (!(usc_InReg(info,TCSR) & TXSTATUS_ALL_SENT) &&
3278 msleep_interruptible(jiffies_to_msecs(char_time));
3279 if (signal_pending(current))
3281 if (timeout && time_after(jiffies, orig_jiffies + timeout))
3287 if (debug_level >= DEBUG_LEVEL_INFO)
3288 printk("%s(%d):mgsl_wait_until_sent(%s) exit\n",
3289 __FILE__,__LINE__, info->device_name );
3291 } /* end of mgsl_wait_until_sent() */
3295 * Called by tty_hangup() when a hangup is signaled.
3296 * This is the same as to closing all open files for the port.
3298 * Arguments: tty pointer to associated tty object
3299 * Return Value: None
3301 static void mgsl_hangup(struct tty_struct *tty)
3303 struct mgsl_struct * info = (struct mgsl_struct *)tty->driver_data;
3305 if (debug_level >= DEBUG_LEVEL_INFO)
3306 printk("%s(%d):mgsl_hangup(%s)\n",
3307 __FILE__,__LINE__, info->device_name );
3309 if (mgsl_paranoia_check(info, tty->name, "mgsl_hangup"))
3312 mgsl_flush_buffer(tty);
3316 info->flags &= ~ASYNC_NORMAL_ACTIVE;
3319 wake_up_interruptible(&info->open_wait);
3321 } /* end of mgsl_hangup() */
3323 /* block_til_ready()
3325 * Block the current process until the specified port
3326 * is ready to be opened.
3330 * tty pointer to tty info structure
3331 * filp pointer to open file object
3332 * info pointer to device instance data
3334 * Return Value: 0 if success, otherwise error code
3336 static int block_til_ready(struct tty_struct *tty, struct file * filp,
3337 struct mgsl_struct *info)
3339 DECLARE_WAITQUEUE(wait, current);
3341 int do_clocal = 0, extra_count = 0;
3342 unsigned long flags;
3344 if (debug_level >= DEBUG_LEVEL_INFO)
3345 printk("%s(%d):block_til_ready on %s\n",
3346 __FILE__,__LINE__, tty->driver->name );
3348 if (filp->f_flags & O_NONBLOCK || tty->flags & (1 << TTY_IO_ERROR)){
3349 /* nonblock mode is set or port is not enabled */
3350 info->flags |= ASYNC_NORMAL_ACTIVE;
3354 if (tty->termios->c_cflag & CLOCAL)
3357 /* Wait for carrier detect and the line to become
3358 * free (i.e., not in use by the callout). While we are in
3359 * this loop, info->count is dropped by one, so that
3360 * mgsl_close() knows when to free things. We restore it upon
3361 * exit, either normal or abnormal.
3365 add_wait_queue(&info->open_wait, &wait);
3367 if (debug_level >= DEBUG_LEVEL_INFO)
3368 printk("%s(%d):block_til_ready before block on %s count=%d\n",
3369 __FILE__,__LINE__, tty->driver->name, info->count );
3371 spin_lock_irqsave(&info->irq_spinlock, flags);
3372 if (!tty_hung_up_p(filp)) {
3376 spin_unlock_irqrestore(&info->irq_spinlock, flags);
3377 info->blocked_open++;
3380 if (tty->termios->c_cflag & CBAUD) {
3381 spin_lock_irqsave(&info->irq_spinlock,flags);
3382 info->serial_signals |= SerialSignal_RTS + SerialSignal_DTR;
3383 usc_set_serial_signals(info);
3384 spin_unlock_irqrestore(&info->irq_spinlock,flags);
3387 set_current_state(TASK_INTERRUPTIBLE);
3389 if (tty_hung_up_p(filp) || !(info->flags & ASYNC_INITIALIZED)){
3390 retval = (info->flags & ASYNC_HUP_NOTIFY) ?
3391 -EAGAIN : -ERESTARTSYS;
3395 spin_lock_irqsave(&info->irq_spinlock,flags);
3396 usc_get_serial_signals(info);
3397 spin_unlock_irqrestore(&info->irq_spinlock,flags);
3399 if (!(info->flags & ASYNC_CLOSING) &&
3400 (do_clocal || (info->serial_signals & SerialSignal_DCD)) ) {
3404 if (signal_pending(current)) {
3405 retval = -ERESTARTSYS;
3409 if (debug_level >= DEBUG_LEVEL_INFO)
3410 printk("%s(%d):block_til_ready blocking on %s count=%d\n",
3411 __FILE__,__LINE__, tty->driver->name, info->count );
3416 set_current_state(TASK_RUNNING);
3417 remove_wait_queue(&info->open_wait, &wait);
3421 info->blocked_open--;
3423 if (debug_level >= DEBUG_LEVEL_INFO)
3424 printk("%s(%d):block_til_ready after blocking on %s count=%d\n",
3425 __FILE__,__LINE__, tty->driver->name, info->count );
3428 info->flags |= ASYNC_NORMAL_ACTIVE;
3432 } /* end of block_til_ready() */
3436 * Called when a port is opened. Init and enable port.
3437 * Perform serial-specific initialization for the tty structure.
3439 * Arguments: tty pointer to tty info structure
3440 * filp associated file pointer
3442 * Return Value: 0 if success, otherwise error code
3444 static int mgsl_open(struct tty_struct *tty, struct file * filp)
3446 struct mgsl_struct *info;
3449 unsigned long flags;
3451 /* verify range of specified line number */
3453 if ((line < 0) || (line >= mgsl_device_count)) {
3454 printk("%s(%d):mgsl_open with invalid line #%d.\n",
3455 __FILE__,__LINE__,line);
3459 /* find the info structure for the specified line */
3460 info = mgsl_device_list;
3461 while(info && info->line != line)
3462 info = info->next_device;
3463 if (mgsl_paranoia_check(info, tty->name, "mgsl_open"))
3466 tty->driver_data = info;
3469 if (debug_level >= DEBUG_LEVEL_INFO)
3470 printk("%s(%d):mgsl_open(%s), old ref count = %d\n",
3471 __FILE__,__LINE__,tty->driver->name, info->count);
3473 /* If port is closing, signal caller to try again */
3474 if (tty_hung_up_p(filp) || info->flags & ASYNC_CLOSING){
3475 if (info->flags & ASYNC_CLOSING)
3476 interruptible_sleep_on(&info->close_wait);
3477 retval = ((info->flags & ASYNC_HUP_NOTIFY) ?
3478 -EAGAIN : -ERESTARTSYS);
3483 page = get_zeroed_page(GFP_KERNEL);
3491 tmp_buf = (unsigned char *) page;
3494 info->tty->low_latency = (info->flags & ASYNC_LOW_LATENCY) ? 1 : 0;
3496 spin_lock_irqsave(&info->netlock, flags);
3497 if (info->netcount) {
3499 spin_unlock_irqrestore(&info->netlock, flags);
3503 spin_unlock_irqrestore(&info->netlock, flags);
3505 if (info->count == 1) {
3506 /* 1st open on this device, init hardware */
3507 retval = startup(info);
3512 retval = block_til_ready(tty, filp, info);
3514 if (debug_level >= DEBUG_LEVEL_INFO)
3515 printk("%s(%d):block_til_ready(%s) returned %d\n",
3516 __FILE__,__LINE__, info->device_name, retval);
3520 if (debug_level >= DEBUG_LEVEL_INFO)
3521 printk("%s(%d):mgsl_open(%s) success\n",
3522 __FILE__,__LINE__, info->device_name);
3527 if (tty->count == 1)
3528 info->tty = NULL; /* tty layer will release tty struct */
3535 } /* end of mgsl_open() */
3538 * /proc fs routines....
3541 static inline int line_info(char *buf, struct mgsl_struct *info)
3545 unsigned long flags;
3547 if (info->bus_type == MGSL_BUS_TYPE_PCI) {
3548 ret = sprintf(buf, "%s:PCI io:%04X irq:%d mem:%08X lcr:%08X",
3549 info->device_name, info->io_base, info->irq_level,
3550 info->phys_memory_base, info->phys_lcr_base);
3552 ret = sprintf(buf, "%s:(E)ISA io:%04X irq:%d dma:%d",
3553 info->device_name, info->io_base,
3554 info->irq_level, info->dma_level);
3557 /* output current serial signal states */
3558 spin_lock_irqsave(&info->irq_spinlock,flags);
3559 usc_get_serial_signals(info);
3560 spin_unlock_irqrestore(&info->irq_spinlock,flags);
3564 if (info->serial_signals & SerialSignal_RTS)
3565 strcat(stat_buf, "|RTS");
3566 if (info->serial_signals & SerialSignal_CTS)
3567 strcat(stat_buf, "|CTS");
3568 if (info->serial_signals & SerialSignal_DTR)
3569 strcat(stat_buf, "|DTR");
3570 if (info->serial_signals & SerialSignal_DSR)
3571 strcat(stat_buf, "|DSR");
3572 if (info->serial_signals & SerialSignal_DCD)
3573 strcat(stat_buf, "|CD");
3574 if (info->serial_signals & SerialSignal_RI)
3575 strcat(stat_buf, "|RI");
3577 if (info->params.mode == MGSL_MODE_HDLC ||
3578 info->params.mode == MGSL_MODE_RAW ) {
3579 ret += sprintf(buf+ret, " HDLC txok:%d rxok:%d",
3580 info->icount.txok, info->icount.rxok);
3581 if (info->icount.txunder)
3582 ret += sprintf(buf+ret, " txunder:%d", info->icount.txunder);
3583 if (info->icount.txabort)
3584 ret += sprintf(buf+ret, " txabort:%d", info->icount.txabort);
3585 if (info->icount.rxshort)
3586 ret += sprintf(buf+ret, " rxshort:%d", info->icount.rxshort);
3587 if (info->icount.rxlong)
3588 ret += sprintf(buf+ret, " rxlong:%d", info->icount.rxlong);
3589 if (info->icount.rxover)
3590 ret += sprintf(buf+ret, " rxover:%d", info->icount.rxover);
3591 if (info->icount.rxcrc)
3592 ret += sprintf(buf+ret, " rxcrc:%d", info->icount.rxcrc);
3594 ret += sprintf(buf+ret, " ASYNC tx:%d rx:%d",
3595 info->icount.tx, info->icount.rx);
3596 if (info->icount.frame)
3597 ret += sprintf(buf+ret, " fe:%d", info->icount.frame);
3598 if (info->icount.parity)
3599 ret += sprintf(buf+ret, " pe:%d", info->icount.parity);
3600 if (info->icount.brk)
3601 ret += sprintf(buf+ret, " brk:%d", info->icount.brk);
3602 if (info->icount.overrun)
3603 ret += sprintf(buf+ret, " oe:%d", info->icount.overrun);
3606 /* Append serial signal status to end */
3607 ret += sprintf(buf+ret, " %s\n", stat_buf+1);
3609 ret += sprintf(buf+ret, "txactive=%d bh_req=%d bh_run=%d pending_bh=%x\n",
3610 info->tx_active,info->bh_requested,info->bh_running,
3613 spin_lock_irqsave(&info->irq_spinlock,flags);
3615 u16 Tcsr = usc_InReg( info, TCSR );
3616 u16 Tdmr = usc_InDmaReg( info, TDMR );
3617 u16 Ticr = usc_InReg( info, TICR );
3618 u16 Rscr = usc_InReg( info, RCSR );
3619 u16 Rdmr = usc_InDmaReg( info, RDMR );
3620 u16 Ricr = usc_InReg( info, RICR );
3621 u16 Icr = usc_InReg( info, ICR );
3622 u16 Dccr = usc_InReg( info, DCCR );
3623 u16 Tmr = usc_InReg( info, TMR );
3624 u16 Tccr = usc_InReg( info, TCCR );
3625 u16 Ccar = inw( info->io_base + CCAR );
3626 ret += sprintf(buf+ret, "tcsr=%04X tdmr=%04X ticr=%04X rcsr=%04X rdmr=%04X\n"
3627 "ricr=%04X icr =%04X dccr=%04X tmr=%04X tccr=%04X ccar=%04X\n",
3628 Tcsr,Tdmr,Ticr,Rscr,Rdmr,Ricr,Icr,Dccr,Tmr,Tccr,Ccar );
3630 spin_unlock_irqrestore(&info->irq_spinlock,flags);
3634 } /* end of line_info() */
3638 * Called to print information about devices
3641 * page page of memory to hold returned info
3650 static int mgsl_read_proc(char *page, char **start, off_t off, int count,
3651 int *eof, void *data)
3655 struct mgsl_struct *info;
3657 len += sprintf(page, "synclink driver:%s\n", driver_version);
3659 info = mgsl_device_list;
3661 l = line_info(page + len, info);
3663 if (len+begin > off+count)
3665 if (len+begin < off) {
3669 info = info->next_device;
3674 if (off >= len+begin)
3676 *start = page + (off-begin);
3677 return ((count < begin+len-off) ? count : begin+len-off);
3679 } /* end of mgsl_read_proc() */
3681 /* mgsl_allocate_dma_buffers()
3683 * Allocate and format DMA buffers (ISA adapter)
3684 * or format shared memory buffers (PCI adapter).
3686 * Arguments: info pointer to device instance data
3687 * Return Value: 0 if success, otherwise error
3689 static int mgsl_allocate_dma_buffers(struct mgsl_struct *info)
3691 unsigned short BuffersPerFrame;
3693 info->last_mem_alloc = 0;
3695 /* Calculate the number of DMA buffers necessary to hold the */
3696 /* largest allowable frame size. Note: If the max frame size is */
3697 /* not an even multiple of the DMA buffer size then we need to */
3698 /* round the buffer count per frame up one. */
3700 BuffersPerFrame = (unsigned short)(info->max_frame_size/DMABUFFERSIZE);
3701 if ( info->max_frame_size % DMABUFFERSIZE )
3704 if ( info->bus_type == MGSL_BUS_TYPE_PCI ) {
3706 * The PCI adapter has 256KBytes of shared memory to use.
3707 * This is 64 PAGE_SIZE buffers.
3709 * The first page is used for padding at this time so the
3710 * buffer list does not begin at offset 0 of the PCI
3711 * adapter's shared memory.
3713 * The 2nd page is used for the buffer list. A 4K buffer
3714 * list can hold 128 DMA_BUFFER structures at 32 bytes
3717 * This leaves 62 4K pages.
3719 * The next N pages are used for transmit frame(s). We
3720 * reserve enough 4K page blocks to hold the required
3721 * number of transmit dma buffers (num_tx_dma_buffers),
3722 * each of MaxFrameSize size.
3724 * Of the remaining pages (62-N), determine how many can
3725 * be used to receive full MaxFrameSize inbound frames
3727 info->tx_buffer_count = info->num_tx_dma_buffers * BuffersPerFrame;
3728 info->rx_buffer_count = 62 - info->tx_buffer_count;
3730 /* Calculate the number of PAGE_SIZE buffers needed for */
3731 /* receive and transmit DMA buffers. */
3734 /* Calculate the number of DMA buffers necessary to */
3735 /* hold 7 max size receive frames and one max size transmit frame. */
3736 /* The receive buffer count is bumped by one so we avoid an */
3737 /* End of List condition if all receive buffers are used when */
3738 /* using linked list DMA buffers. */
3740 info->tx_buffer_count = info->num_tx_dma_buffers * BuffersPerFrame;
3741 info->rx_buffer_count = (BuffersPerFrame * MAXRXFRAMES) + 6;
3744 * limit total TxBuffers & RxBuffers to 62 4K total
3745 * (ala PCI Allocation)
3748 if ( (info->tx_buffer_count + info->rx_buffer_count) > 62 )
3749 info->rx_buffer_count = 62 - info->tx_buffer_count;
3753 if ( debug_level >= DEBUG_LEVEL_INFO )
3754 printk("%s(%d):Allocating %d TX and %d RX DMA buffers.\n",
3755 __FILE__,__LINE__, info->tx_buffer_count,info->rx_buffer_count);
3757 if ( mgsl_alloc_buffer_list_memory( info ) < 0 ||
3758 mgsl_alloc_frame_memory(info, info->rx_buffer_list, info->rx_buffer_count) < 0 ||
3759 mgsl_alloc_frame_memory(info, info->tx_buffer_list, info->tx_buffer_count) < 0 ||
3760 mgsl_alloc_intermediate_rxbuffer_memory(info) < 0 ||
3761 mgsl_alloc_intermediate_txbuffer_memory(info) < 0 ) {
3762 printk("%s(%d):Can't allocate DMA buffer memory\n",__FILE__,__LINE__);
3766 mgsl_reset_rx_dma_buffers( info );
3767 mgsl_reset_tx_dma_buffers( info );
3771 } /* end of mgsl_allocate_dma_buffers() */
3774 * mgsl_alloc_buffer_list_memory()
3776 * Allocate a common DMA buffer for use as the
3777 * receive and transmit buffer lists.
3779 * A buffer list is a set of buffer entries where each entry contains
3780 * a pointer to an actual buffer and a pointer to the next buffer entry
3781 * (plus some other info about the buffer).
3783 * The buffer entries for a list are built to form a circular list so
3784 * that when the entire list has been traversed you start back at the
3787 * This function allocates memory for just the buffer entries.
3788 * The links (pointer to next entry) are filled in with the physical
3789 * address of the next entry so the adapter can navigate the list
3790 * using bus master DMA. The pointers to the actual buffers are filled
3791 * out later when the actual buffers are allocated.
3793 * Arguments: info pointer to device instance data
3794 * Return Value: 0 if success, otherwise error
3796 static int mgsl_alloc_buffer_list_memory( struct mgsl_struct *info )
3800 if ( info->bus_type == MGSL_BUS_TYPE_PCI ) {
3801 /* PCI adapter uses shared memory. */
3802 info->buffer_list = info->memory_base + info->last_mem_alloc;
3803 info->buffer_list_phys = info->last_mem_alloc;
3804 info->last_mem_alloc += BUFFERLISTSIZE;
3806 /* ISA adapter uses system memory. */
3807 /* The buffer lists are allocated as a common buffer that both */
3808 /* the processor and adapter can access. This allows the driver to */
3809 /* inspect portions of the buffer while other portions are being */
3810 /* updated by the adapter using Bus Master DMA. */
3812 info->buffer_list = kmalloc(BUFFERLISTSIZE, GFP_KERNEL | GFP_DMA);
3813 if ( info->buffer_list == NULL )
3816 info->buffer_list_phys = isa_virt_to_bus(info->buffer_list);
3819 /* We got the memory for the buffer entry lists. */
3820 /* Initialize the memory block to all zeros. */
3821 memset( info->buffer_list, 0, BUFFERLISTSIZE );
3823 /* Save virtual address pointers to the receive and */
3824 /* transmit buffer lists. (Receive 1st). These pointers will */
3825 /* be used by the processor to access the lists. */
3826 info->rx_buffer_list = (DMABUFFERENTRY *)info->buffer_list;
3827 info->tx_buffer_list = (DMABUFFERENTRY *)info->buffer_list;
3828 info->tx_buffer_list += info->rx_buffer_count;
3831 * Build the links for the buffer entry lists such that
3832 * two circular lists are built. (Transmit and Receive).
3834 * Note: the links are physical addresses
3835 * which are read by the adapter to determine the next
3836 * buffer entry to use.
3839 for ( i = 0; i < info->rx_buffer_count; i++ ) {
3840 /* calculate and store physical address of this buffer entry */
3841 info->rx_buffer_list[i].phys_entry =
3842 info->buffer_list_phys + (i * sizeof(DMABUFFERENTRY));
3844 /* calculate and store physical address of */
3845 /* next entry in cirular list of entries */
3847 info->rx_buffer_list[i].link = info->buffer_list_phys;
3849 if ( i < info->rx_buffer_count - 1 )
3850 info->rx_buffer_list[i].link += (i + 1) * sizeof(DMABUFFERENTRY);
3853 for ( i = 0; i < info->tx_buffer_count; i++ ) {
3854 /* calculate and store physical address of this buffer entry */
3855 info->tx_buffer_list[i].phys_entry = info->buffer_list_phys +
3856 ((info->rx_buffer_count + i) * sizeof(DMABUFFERENTRY));
3858 /* calculate and store physical address of */
3859 /* next entry in cirular list of entries */
3861 info->tx_buffer_list[i].link = info->buffer_list_phys +
3862 info->rx_buffer_count * sizeof(DMABUFFERENTRY);
3864 if ( i < info->tx_buffer_count - 1 )
3865 info->tx_buffer_list[i].link += (i + 1) * sizeof(DMABUFFERENTRY);
3870 } /* end of mgsl_alloc_buffer_list_memory() */
3872 /* Free DMA buffers allocated for use as the
3873 * receive and transmit buffer lists.
3876 * The data transfer buffers associated with the buffer list
3877 * MUST be freed before freeing the buffer list itself because
3878 * the buffer list contains the information necessary to free
3879 * the individual buffers!
3881 static void mgsl_free_buffer_list_memory( struct mgsl_struct *info )
3883 if ( info->buffer_list && info->bus_type != MGSL_BUS_TYPE_PCI )
3884 kfree(info->buffer_list);
3886 info->buffer_list = NULL;
3887 info->rx_buffer_list = NULL;
3888 info->tx_buffer_list = NULL;
3890 } /* end of mgsl_free_buffer_list_memory() */
3893 * mgsl_alloc_frame_memory()
3895 * Allocate the frame DMA buffers used by the specified buffer list.
3896 * Each DMA buffer will be one memory page in size. This is necessary
3897 * because memory can fragment enough that it may be impossible
3902 * info pointer to device instance data
3903 * BufferList pointer to list of buffer entries
3904 * Buffercount count of buffer entries in buffer list
3906 * Return Value: 0 if success, otherwise -ENOMEM
3908 static int mgsl_alloc_frame_memory(struct mgsl_struct *info,DMABUFFERENTRY *BufferList,int Buffercount)
3911 unsigned long phys_addr;
3913 /* Allocate page sized buffers for the receive buffer list */
3915 for ( i = 0; i < Buffercount; i++ ) {
3916 if ( info->bus_type == MGSL_BUS_TYPE_PCI ) {
3917 /* PCI adapter uses shared memory buffers. */
3918 BufferList[i].virt_addr = info->memory_base + info->last_mem_alloc;
3919 phys_addr = info->last_mem_alloc;
3920 info->last_mem_alloc += DMABUFFERSIZE;
3922 /* ISA adapter uses system memory. */
3923 BufferList[i].virt_addr =
3924 kmalloc(DMABUFFERSIZE, GFP_KERNEL | GFP_DMA);
3925 if ( BufferList[i].virt_addr == NULL )
3927 phys_addr = isa_virt_to_bus(BufferList[i].virt_addr);
3929 BufferList[i].phys_addr = phys_addr;
3934 } /* end of mgsl_alloc_frame_memory() */
3937 * mgsl_free_frame_memory()
3939 * Free the buffers associated with
3940 * each buffer entry of a buffer list.
3944 * info pointer to device instance data
3945 * BufferList pointer to list of buffer entries
3946 * Buffercount count of buffer entries in buffer list
3948 * Return Value: None
3950 static void mgsl_free_frame_memory(struct mgsl_struct *info, DMABUFFERENTRY *BufferList, int Buffercount)
3955 for ( i = 0 ; i < Buffercount ; i++ ) {
3956 if ( BufferList[i].virt_addr ) {
3957 if ( info->bus_type != MGSL_BUS_TYPE_PCI )
3958 kfree(BufferList[i].virt_addr);
3959 BufferList[i].virt_addr = NULL;
3964 } /* end of mgsl_free_frame_memory() */
3966 /* mgsl_free_dma_buffers()
3970 * Arguments: info pointer to device instance data
3971 * Return Value: None
3973 static void mgsl_free_dma_buffers( struct mgsl_struct *info )
3975 mgsl_free_frame_memory( info, info->rx_buffer_list, info->rx_buffer_count );
3976 mgsl_free_frame_memory( info, info->tx_buffer_list, info->tx_buffer_count );
3977 mgsl_free_buffer_list_memory( info );
3979 } /* end of mgsl_free_dma_buffers() */
3983 * mgsl_alloc_intermediate_rxbuffer_memory()
3985 * Allocate a buffer large enough to hold max_frame_size. This buffer
3986 * is used to pass an assembled frame to the line discipline.
3990 * info pointer to device instance data
3992 * Return Value: 0 if success, otherwise -ENOMEM
3994 static int mgsl_alloc_intermediate_rxbuffer_memory(struct mgsl_struct *info)
3996 info->intermediate_rxbuffer = kmalloc(info->max_frame_size, GFP_KERNEL | GFP_DMA);
3997 if ( info->intermediate_rxbuffer == NULL )
4002 } /* end of mgsl_alloc_intermediate_rxbuffer_memory() */
4005 * mgsl_free_intermediate_rxbuffer_memory()
4010 * info pointer to device instance data
4012 * Return Value: None
4014 static void mgsl_free_intermediate_rxbuffer_memory(struct mgsl_struct *info)
4016 if ( info->intermediate_rxbuffer )
4017 kfree(info->intermediate_rxbuffer);
4019 info->intermediate_rxbuffer = NULL;
4021 } /* end of mgsl_free_intermediate_rxbuffer_memory() */
4024 * mgsl_alloc_intermediate_txbuffer_memory()
4026 * Allocate intermdiate transmit buffer(s) large enough to hold max_frame_size.
4027 * This buffer is used to load transmit frames into the adapter's dma transfer
4028 * buffers when there is sufficient space.
4032 * info pointer to device instance data
4034 * Return Value: 0 if success, otherwise -ENOMEM
4036 static int mgsl_alloc_intermediate_txbuffer_memory(struct mgsl_struct *info)
4040 if ( debug_level >= DEBUG_LEVEL_INFO )
4041 printk("%s %s(%d) allocating %d tx holding buffers\n",
4042 info->device_name, __FILE__,__LINE__,info->num_tx_holding_buffers);
4044 memset(info->tx_holding_buffers,0,sizeof(info->tx_holding_buffers));
4046 for ( i=0; i<info->num_tx_holding_buffers; ++i) {
4047 info->tx_holding_buffers[i].buffer =
4048 kmalloc(info->max_frame_size, GFP_KERNEL);
4049 if ( info->tx_holding_buffers[i].buffer == NULL )
4055 } /* end of mgsl_alloc_intermediate_txbuffer_memory() */
4058 * mgsl_free_intermediate_txbuffer_memory()
4063 * info pointer to device instance data
4065 * Return Value: None
4067 static void mgsl_free_intermediate_txbuffer_memory(struct mgsl_struct *info)
4071 for ( i=0; i<info->num_tx_holding_buffers; ++i ) {
4072 if ( info->tx_holding_buffers[i].buffer ) {
4073 kfree(info->tx_holding_buffers[i].buffer);
4074 info->tx_holding_buffers[i].buffer=NULL;
4078 info->get_tx_holding_index = 0;
4079 info->put_tx_holding_index = 0;
4080 info->tx_holding_count = 0;
4082 } /* end of mgsl_free_intermediate_txbuffer_memory() */
4086 * load_next_tx_holding_buffer()
4088 * attempts to load the next buffered tx request into the
4093 * info pointer to device instance data
4095 * Return Value: 1 if next buffered tx request loaded
4096 * into adapter's tx dma buffer,
4099 static int load_next_tx_holding_buffer(struct mgsl_struct *info)
4103 if ( info->tx_holding_count ) {
4104 /* determine if we have enough tx dma buffers
4105 * to accommodate the next tx frame
4107 struct tx_holding_buffer *ptx =
4108 &info->tx_holding_buffers[info->get_tx_holding_index];
4109 int num_free = num_free_tx_dma_buffers(info);
4110 int num_needed = ptx->buffer_size / DMABUFFERSIZE;
4111 if ( ptx->buffer_size % DMABUFFERSIZE )
4114 if (num_needed <= num_free) {
4115 info->xmit_cnt = ptx->buffer_size;
4116 mgsl_load_tx_dma_buffer(info,ptx->buffer,ptx->buffer_size);
4118 --info->tx_holding_count;
4119 if ( ++info->get_tx_holding_index >= info->num_tx_holding_buffers)
4120 info->get_tx_holding_index=0;
4122 /* restart transmit timer */
4123 mod_timer(&info->tx_timer, jiffies + msecs_to_jiffies(5000));
4133 * save_tx_buffer_request()
4135 * attempt to store transmit frame request for later transmission
4139 * info pointer to device instance data
4140 * Buffer pointer to buffer containing frame to load
4141 * BufferSize size in bytes of frame in Buffer
4143 * Return Value: 1 if able to store, 0 otherwise
4145 static int save_tx_buffer_request(struct mgsl_struct *info,const char *Buffer, unsigned int BufferSize)
4147 struct tx_holding_buffer *ptx;
4149 if ( info->tx_holding_count >= info->num_tx_holding_buffers ) {
4150 return 0; /* all buffers in use */
4153 ptx = &info->tx_holding_buffers[info->put_tx_holding_index];
4154 ptx->buffer_size = BufferSize;
4155 memcpy( ptx->buffer, Buffer, BufferSize);
4157 ++info->tx_holding_count;
4158 if ( ++info->put_tx_holding_index >= info->num_tx_holding_buffers)
4159 info->put_tx_holding_index=0;
4164 static int mgsl_claim_resources(struct mgsl_struct *info)
4166 if (request_region(info->io_base,info->io_addr_size,"synclink") == NULL) {
4167 printk( "%s(%d):I/O address conflict on device %s Addr=%08X\n",
4168 __FILE__,__LINE__,info->device_name, info->io_base);
4171 info->io_addr_requested = 1;
4173 if ( request_irq(info->irq_level,mgsl_interrupt,info->irq_flags,
4174 info->device_name, info ) < 0 ) {
4175 printk( "%s(%d):Cant request interrupt on device %s IRQ=%d\n",
4176 __FILE__,__LINE__,info->device_name, info->irq_level );
4179 info->irq_requested = 1;
4181 if ( info->bus_type == MGSL_BUS_TYPE_PCI ) {
4182 if (request_mem_region(info->phys_memory_base,0x40000,"synclink") == NULL) {
4183 printk( "%s(%d):mem addr conflict device %s Addr=%08X\n",
4184 __FILE__,__LINE__,info->device_name, info->phys_memory_base);
4187 info->shared_mem_requested = 1;
4188 if (request_mem_region(info->phys_lcr_base + info->lcr_offset,128,"synclink") == NULL) {
4189 printk( "%s(%d):lcr mem addr conflict device %s Addr=%08X\n",
4190 __FILE__,__LINE__,info->device_name, info->phys_lcr_base + info->lcr_offset);
4193 info->lcr_mem_requested = 1;
4195 info->memory_base = ioremap(info->phys_memory_base,0x40000);
4196 if (!info->memory_base) {
4197 printk( "%s(%d):Cant map shared memory on device %s MemAddr=%08X\n",
4198 __FILE__,__LINE__,info->device_name, info->phys_memory_base );
4202 if ( !mgsl_memory_test(info) ) {
4203 printk( "%s(%d):Failed shared memory test %s MemAddr=%08X\n",
4204 __FILE__,__LINE__,info->device_name, info->phys_memory_base );
4208 info->lcr_base = ioremap(info->phys_lcr_base,PAGE_SIZE) + info->lcr_offset;
4209 if (!info->lcr_base) {
4210 printk( "%s(%d):Cant map LCR memory on device %s MemAddr=%08X\n",
4211 __FILE__,__LINE__,info->device_name, info->phys_lcr_base );
4216 /* claim DMA channel */
4218 if (request_dma(info->dma_level,info->device_name) < 0){
4219 printk( "%s(%d):Cant request DMA channel on device %s DMA=%d\n",
4220 __FILE__,__LINE__,info->device_name, info->dma_level );
4221 mgsl_release_resources( info );
4224 info->dma_requested = 1;
4226 /* ISA adapter uses bus master DMA */
4227 set_dma_mode(info->dma_level,DMA_MODE_CASCADE);
4228 enable_dma(info->dma_level);
4231 if ( mgsl_allocate_dma_buffers(info) < 0 ) {
4232 printk( "%s(%d):Cant allocate DMA buffers on device %s DMA=%d\n",
4233 __FILE__,__LINE__,info->device_name, info->dma_level );
4239 mgsl_release_resources(info);
4242 } /* end of mgsl_claim_resources() */
4244 static void mgsl_release_resources(struct mgsl_struct *info)
4246 if ( debug_level >= DEBUG_LEVEL_INFO )
4247 printk( "%s(%d):mgsl_release_resources(%s) entry\n",
4248 __FILE__,__LINE__,info->device_name );
4250 if ( info->irq_requested ) {
4251 free_irq(info->irq_level, info);
4252 info->irq_requested = 0;
4254 if ( info->dma_requested ) {
4255 disable_dma(info->dma_level);
4256 free_dma(info->dma_level);
4257 info->dma_requested = 0;
4259 mgsl_free_dma_buffers(info);
4260 mgsl_free_intermediate_rxbuffer_memory(info);
4261 mgsl_free_intermediate_txbuffer_memory(info);
4263 if ( info->io_addr_requested ) {
4264 release_region(info->io_base,info->io_addr_size);
4265 info->io_addr_requested = 0;
4267 if ( info->shared_mem_requested ) {
4268 release_mem_region(info->phys_memory_base,0x40000);
4269 info->shared_mem_requested = 0;
4271 if ( info->lcr_mem_requested ) {
4272 release_mem_region(info->phys_lcr_base + info->lcr_offset,128);
4273 info->lcr_mem_requested = 0;
4275 if (info->memory_base){
4276 iounmap(info->memory_base);
4277 info->memory_base = NULL;
4279 if (info->lcr_base){
4280 iounmap(info->lcr_base - info->lcr_offset);
4281 info->lcr_base = NULL;
4284 if ( debug_level >= DEBUG_LEVEL_INFO )
4285 printk( "%s(%d):mgsl_release_resources(%s) exit\n",
4286 __FILE__,__LINE__,info->device_name );
4288 } /* end of mgsl_release_resources() */
4290 /* mgsl_add_device()
4292 * Add the specified device instance data structure to the
4293 * global linked list of devices and increment the device count.
4295 * Arguments: info pointer to device instance data
4296 * Return Value: None
4298 static void mgsl_add_device( struct mgsl_struct *info )
4300 info->next_device = NULL;
4301 info->line = mgsl_device_count;
4302 sprintf(info->device_name,"ttySL%d",info->line);
4304 if (info->line < MAX_TOTAL_DEVICES) {
4305 if (maxframe[info->line])
4306 info->max_frame_size = maxframe[info->line];
4307 info->dosyncppp = dosyncppp[info->line];
4309 if (txdmabufs[info->line]) {
4310 info->num_tx_dma_buffers = txdmabufs[info->line];
4311 if (info->num_tx_dma_buffers < 1)
4312 info->num_tx_dma_buffers = 1;
4315 if (txholdbufs[info->line]) {
4316 info->num_tx_holding_buffers = txholdbufs[info->line];
4317 if (info->num_tx_holding_buffers < 1)
4318 info->num_tx_holding_buffers = 1;
4319 else if (info->num_tx_holding_buffers > MAX_TX_HOLDING_BUFFERS)
4320 info->num_tx_holding_buffers = MAX_TX_HOLDING_BUFFERS;
4324 mgsl_device_count++;
4326 if ( !mgsl_device_list )
4327 mgsl_device_list = info;
4329 struct mgsl_struct *current_dev = mgsl_device_list;
4330 while( current_dev->next_device )
4331 current_dev = current_dev->next_device;
4332 current_dev->next_device = info;
4335 if ( info->max_frame_size < 4096 )
4336 info->max_frame_size = 4096;
4337 else if ( info->max_frame_size > 65535 )
4338 info->max_frame_size = 65535;
4340 if ( info->bus_type == MGSL_BUS_TYPE_PCI ) {
4341 printk( "SyncLink PCI v%d %s: IO=%04X IRQ=%d Mem=%08X,%08X MaxFrameSize=%u\n",
4342 info->hw_version + 1, info->device_name, info->io_base, info->irq_level,
4343 info->phys_memory_base, info->phys_lcr_base,
4344 info->max_frame_size );
4346 printk( "SyncLink ISA %s: IO=%04X IRQ=%d DMA=%d MaxFrameSize=%u\n",
4347 info->device_name, info->io_base, info->irq_level, info->dma_level,
4348 info->max_frame_size );
4355 } /* end of mgsl_add_device() */
4357 /* mgsl_allocate_device()
4359 * Allocate and initialize a device instance structure
4362 * Return Value: pointer to mgsl_struct if success, otherwise NULL
4364 static struct mgsl_struct* mgsl_allocate_device(void)
4366 struct mgsl_struct *info;
4368 info = (struct mgsl_struct *)kmalloc(sizeof(struct mgsl_struct),
4372 printk("Error can't allocate device instance data\n");
4374 memset(info, 0, sizeof(struct mgsl_struct));
4375 info->magic = MGSL_MAGIC;
4376 INIT_WORK(&info->task, mgsl_bh_handler, info);
4377 info->max_frame_size = 4096;
4378 info->close_delay = 5*HZ/10;
4380 info->closing_wait = 30*HZ;
4382 info->closing_wait = 65534;
4384 init_waitqueue_head(&info->open_wait);
4385 init_waitqueue_head(&info->close_wait);
4386 init_waitqueue_head(&info->status_event_wait_q);
4387 init_waitqueue_head(&info->event_wait_q);
4388 spin_lock_init(&info->irq_spinlock);
4389 spin_lock_init(&info->netlock);
4390 memcpy(&info->params,&default_params,sizeof(MGSL_PARAMS));
4391 info->idle_mode = HDLC_TXIDLE_FLAGS;
4392 info->num_tx_dma_buffers = 1;
4393 info->num_tx_holding_buffers = 0;
4398 } /* end of mgsl_allocate_device()*/
4400 static struct tty_operations mgsl_ops = {
4402 .close = mgsl_close,
4403 .write = mgsl_write,
4404 .put_char = mgsl_put_char,
4405 .flush_chars = mgsl_flush_chars,
4406 .write_room = mgsl_write_room,
4407 .chars_in_buffer = mgsl_chars_in_buffer,
4408 .flush_buffer = mgsl_flush_buffer,
4409 .ioctl = mgsl_ioctl,
4410 .throttle = mgsl_throttle,
4411 .unthrottle = mgsl_unthrottle,
4412 .send_xchar = mgsl_send_xchar,
4413 .break_ctl = mgsl_break,
4414 .wait_until_sent = mgsl_wait_until_sent,
4415 .read_proc = mgsl_read_proc,
4416 .set_termios = mgsl_set_termios,
4418 .start = mgsl_start,
4419 .hangup = mgsl_hangup,
4420 .tiocmget = tiocmget,
4421 .tiocmset = tiocmset,
4425 * perform tty device initialization
4427 static int mgsl_init_tty(void)
4431 serial_driver = alloc_tty_driver(128);
4435 serial_driver->owner = THIS_MODULE;
4436 serial_driver->driver_name = "synclink";
4437 serial_driver->name = "ttySL";
4438 serial_driver->major = ttymajor;
4439 serial_driver->minor_start = 64;
4440 serial_driver->type = TTY_DRIVER_TYPE_SERIAL;
4441 serial_driver->subtype = SERIAL_TYPE_NORMAL;
4442 serial_driver->init_termios = tty_std_termios;
4443 serial_driver->init_termios.c_cflag =
4444 B9600 | CS8 | CREAD | HUPCL | CLOCAL;
4445 serial_driver->flags = TTY_DRIVER_REAL_RAW;
4446 tty_set_operations(serial_driver, &mgsl_ops);
4447 if ((rc = tty_register_driver(serial_driver)) < 0) {
4448 printk("%s(%d):Couldn't register serial driver\n",
4450 put_tty_driver(serial_driver);
4451 serial_driver = NULL;
4455 printk("%s %s, tty major#%d\n",
4456 driver_name, driver_version,
4457 serial_driver->major);
4461 /* enumerate user specified ISA adapters
4463 static void mgsl_enum_isa_devices(void)
4465 struct mgsl_struct *info;
4468 /* Check for user specified ISA devices */
4470 for (i=0 ;(i < MAX_ISA_DEVICES) && io[i] && irq[i]; i++){
4471 if ( debug_level >= DEBUG_LEVEL_INFO )
4472 printk("ISA device specified io=%04X,irq=%d,dma=%d\n",
4473 io[i], irq[i], dma[i] );
4475 info = mgsl_allocate_device();
4477 /* error allocating device instance data */
4478 if ( debug_level >= DEBUG_LEVEL_ERROR )
4479 printk( "can't allocate device instance data.\n");
4483 /* Copy user configuration info to device instance data */
4484 info->io_base = (unsigned int)io[i];
4485 info->irq_level = (unsigned int)irq[i];
4486 info->irq_level = irq_canonicalize(info->irq_level);
4487 info->dma_level = (unsigned int)dma[i];
4488 info->bus_type = MGSL_BUS_TYPE_ISA;
4489 info->io_addr_size = 16;
4490 info->irq_flags = 0;
4492 mgsl_add_device( info );
4496 static void synclink_cleanup(void)
4499 struct mgsl_struct *info;
4500 struct mgsl_struct *tmp;
4502 printk("Unloading %s: %s\n", driver_name, driver_version);
4504 if (serial_driver) {
4505 if ((rc = tty_unregister_driver(serial_driver)))
4506 printk("%s(%d) failed to unregister tty driver err=%d\n",
4507 __FILE__,__LINE__,rc);
4508 put_tty_driver(serial_driver);
4511 info = mgsl_device_list;
4516 mgsl_release_resources(info);
4518 info = info->next_device;
4523 free_page((unsigned long) tmp_buf);
4528 pci_unregister_driver(&synclink_pci_driver);
4531 static int __init synclink_init(void)
4535 if (break_on_load) {
4536 mgsl_get_text_ptr();
4540 printk("%s %s\n", driver_name, driver_version);
4542 mgsl_enum_isa_devices();
4543 if ((rc = pci_register_driver(&synclink_pci_driver)) < 0)
4544 printk("%s:failed to register PCI driver, error=%d\n",__FILE__,rc);
4548 if ((rc = mgsl_init_tty()) < 0)
4558 static void __exit synclink_exit(void)
4563 module_init(synclink_init);
4564 module_exit(synclink_exit);
4569 * Issue a USC Receive/Transmit command to the
4570 * Channel Command/Address Register (CCAR).
4574 * The command is encoded in the most significant 5 bits <15..11>
4575 * of the CCAR value. Bits <10..7> of the CCAR must be preserved
4576 * and Bits <6..0> must be written as zeros.
4580 * info pointer to device information structure
4581 * Cmd command mask (use symbolic macros)
4587 static void usc_RTCmd( struct mgsl_struct *info, u16 Cmd )
4589 /* output command to CCAR in bits <15..11> */
4590 /* preserve bits <10..7>, bits <6..0> must be zero */
4592 outw( Cmd + info->loopback_bits, info->io_base + CCAR );
4594 /* Read to flush write to CCAR */
4595 if ( info->bus_type == MGSL_BUS_TYPE_PCI )
4596 inw( info->io_base + CCAR );
4598 } /* end of usc_RTCmd() */
4603 * Issue a DMA command to the DMA Command/Address Register (DCAR).
4607 * info pointer to device information structure
4608 * Cmd DMA command mask (usc_DmaCmd_XX Macros)
4614 static void usc_DmaCmd( struct mgsl_struct *info, u16 Cmd )
4616 /* write command mask to DCAR */
4617 outw( Cmd + info->mbre_bit, info->io_base );
4619 /* Read to flush write to DCAR */
4620 if ( info->bus_type == MGSL_BUS_TYPE_PCI )
4621 inw( info->io_base );
4623 } /* end of usc_DmaCmd() */
4628 * Write a 16-bit value to a USC DMA register
4632 * info pointer to device info structure
4633 * RegAddr register address (number) for write
4634 * RegValue 16-bit value to write to register
4641 static void usc_OutDmaReg( struct mgsl_struct *info, u16 RegAddr, u16 RegValue )
4643 /* Note: The DCAR is located at the adapter base address */
4644 /* Note: must preserve state of BIT8 in DCAR */
4646 outw( RegAddr + info->mbre_bit, info->io_base );
4647 outw( RegValue, info->io_base );
4649 /* Read to flush write to DCAR */
4650 if ( info->bus_type == MGSL_BUS_TYPE_PCI )
4651 inw( info->io_base );
4653 } /* end of usc_OutDmaReg() */
4658 * Read a 16-bit value from a DMA register
4662 * info pointer to device info structure
4663 * RegAddr register address (number) to read from
4667 * The 16-bit value read from register
4670 static u16 usc_InDmaReg( struct mgsl_struct *info, u16 RegAddr )
4672 /* Note: The DCAR is located at the adapter base address */
4673 /* Note: must preserve state of BIT8 in DCAR */
4675 outw( RegAddr + info->mbre_bit, info->io_base );
4676 return inw( info->io_base );
4678 } /* end of usc_InDmaReg() */
4684 * Write a 16-bit value to a USC serial channel register
4688 * info pointer to device info structure
4689 * RegAddr register address (number) to write to
4690 * RegValue 16-bit value to write to register
4697 static void usc_OutReg( struct mgsl_struct *info, u16 RegAddr, u16 RegValue )
4699 outw( RegAddr + info->loopback_bits, info->io_base + CCAR );
4700 outw( RegValue, info->io_base + CCAR );
4702 /* Read to flush write to CCAR */
4703 if ( info->bus_type == MGSL_BUS_TYPE_PCI )
4704 inw( info->io_base + CCAR );
4706 } /* end of usc_OutReg() */
4711 * Reads a 16-bit value from a USC serial channel register
4715 * info pointer to device extension
4716 * RegAddr register address (number) to read from
4720 * 16-bit value read from register
4722 static u16 usc_InReg( struct mgsl_struct *info, u16 RegAddr )
4724 outw( RegAddr + info->loopback_bits, info->io_base + CCAR );
4725 return inw( info->io_base + CCAR );
4727 } /* end of usc_InReg() */
4729 /* usc_set_sdlc_mode()
4731 * Set up the adapter for SDLC DMA communications.
4733 * Arguments: info pointer to device instance data
4734 * Return Value: NONE
4736 static void usc_set_sdlc_mode( struct mgsl_struct *info )
4742 * determine if the IUSC on the adapter is pre-SL1660. If
4743 * not, take advantage of the UnderWait feature of more
4744 * modern chips. If an underrun occurs and this bit is set,
4745 * the transmitter will idle the programmed idle pattern
4746 * until the driver has time to service the underrun. Otherwise,
4747 * the dma controller may get the cycles previously requested
4748 * and begin transmitting queued tx data.
4750 usc_OutReg(info,TMCR,0x1f);
4751 RegValue=usc_InReg(info,TMDR);
4752 if ( RegValue == IUSC_PRE_SL1660 )
4758 if ( info->params.flags & HDLC_FLAG_HDLC_LOOPMODE )
4761 ** Channel Mode Register (CMR)
4763 ** <15..14> 10 Tx Sub Modes, Send Flag on Underrun
4764 ** <13> 0 0 = Transmit Disabled (initially)
4765 ** <12> 0 1 = Consecutive Idles share common 0
4766 ** <11..8> 1110 Transmitter Mode = HDLC/SDLC Loop
4767 ** <7..4> 0000 Rx Sub Modes, addr/ctrl field handling
4768 ** <3..0> 0110 Receiver Mode = HDLC/SDLC
4770 ** 1000 1110 0000 0110 = 0x8e06
4774 /*--------------------------------------------------
4775 * ignore user options for UnderRun Actions and
4777 *--------------------------------------------------*/
4781 /* Channel mode Register (CMR)
4783 * <15..14> 00 Tx Sub modes, Underrun Action
4784 * <13> 0 1 = Send Preamble before opening flag
4785 * <12> 0 1 = Consecutive Idles share common 0
4786 * <11..8> 0110 Transmitter mode = HDLC/SDLC
4787 * <7..4> 0000 Rx Sub modes, addr/ctrl field handling
4788 * <3..0> 0110 Receiver mode = HDLC/SDLC
4790 * 0000 0110 0000 0110 = 0x0606
4792 if (info->params.mode == MGSL_MODE_RAW) {
4793 RegValue = 0x0001; /* Set Receive mode = external sync */
4795 usc_OutReg( info, IOCR, /* Set IOCR DCD is RxSync Detect Input */
4796 (unsigned short)((usc_InReg(info, IOCR) & ~(BIT13|BIT12)) | BIT12));
4800 * CMR <15> 0 Don't send CRC on Tx Underrun
4801 * CMR <14> x undefined
4802 * CMR <13> 0 Send preamble before openning sync
4803 * CMR <12> 0 Send 8-bit syncs, 1=send Syncs per TxLength
4806 * CMR <11-8) 0100 MonoSync
4808 * 0x00 0100 xxxx xxxx 04xx
4816 if ( info->params.flags & HDLC_FLAG_UNDERRUN_ABORT15 )
4818 else if ( info->params.flags & HDLC_FLAG_UNDERRUN_FLAG )
4820 else if ( info->params.flags & HDLC_FLAG_UNDERRUN_CRC )
4821 RegValue |= BIT15 + BIT14;
4824 if ( info->params.preamble != HDLC_PREAMBLE_PATTERN_NONE )
4828 if ( info->params.mode == MGSL_MODE_HDLC &&
4829 (info->params.flags & HDLC_FLAG_SHARE_ZERO) )
4832 if ( info->params.addr_filter != 0xff )
4834 /* set up receive address filtering */
4835 usc_OutReg( info, RSR, info->params.addr_filter );
4839 usc_OutReg( info, CMR, RegValue );
4840 info->cmr_value = RegValue;
4842 /* Receiver mode Register (RMR)
4844 * <15..13> 000 encoding
4845 * <12..11> 00 FCS = 16bit CRC CCITT (x15 + x12 + x5 + 1)
4846 * <10> 1 1 = Set CRC to all 1s (use for SDLC/HDLC)
4847 * <9> 0 1 = Include Receive chars in CRC
4848 * <8> 1 1 = Use Abort/PE bit as abort indicator
4849 * <7..6> 00 Even parity
4850 * <5> 0 parity disabled
4851 * <4..2> 000 Receive Char Length = 8 bits
4852 * <1..0> 00 Disable Receiver
4854 * 0000 0101 0000 0000 = 0x0500
4859 switch ( info->params.encoding ) {
4860 case HDLC_ENCODING_NRZB: RegValue |= BIT13; break;
4861 case HDLC_ENCODING_NRZI_MARK: RegValue |= BIT14; break;
4862 case HDLC_ENCODING_NRZI_SPACE: RegValue |= BIT14 + BIT13; break;
4863 case HDLC_ENCODING_BIPHASE_MARK: RegValue |= BIT15; break;
4864 case HDLC_ENCODING_BIPHASE_SPACE: RegValue |= BIT15 + BIT13; break;
4865 case HDLC_ENCODING_BIPHASE_LEVEL: RegValue |= BIT15 + BIT14; break;
4866 case HDLC_ENCODING_DIFF_BIPHASE_LEVEL: RegValue |= BIT15 + BIT14 + BIT13; break;
4869 if ( (info->params.crc_type & HDLC_CRC_MASK) == HDLC_CRC_16_CCITT )
4871 else if ( (info->params.crc_type & HDLC_CRC_MASK) == HDLC_CRC_32_CCITT )
4872 RegValue |= ( BIT12 | BIT10 | BIT9 );
4874 usc_OutReg( info, RMR, RegValue );
4876 /* Set the Receive count Limit Register (RCLR) to 0xffff. */
4877 /* When an opening flag of an SDLC frame is recognized the */
4878 /* Receive Character count (RCC) is loaded with the value in */
4879 /* RCLR. The RCC is decremented for each received byte. The */
4880 /* value of RCC is stored after the closing flag of the frame */
4881 /* allowing the frame size to be computed. */
4883 usc_OutReg( info, RCLR, RCLRVALUE );
4885 usc_RCmd( info, RCmd_SelectRicrdma_level );
4887 /* Receive Interrupt Control Register (RICR)
4889 * <15..8> ? RxFIFO DMA Request Level
4890 * <7> 0 Exited Hunt IA (Interrupt Arm)
4891 * <6> 0 Idle Received IA
4892 * <5> 0 Break/Abort IA
4894 * <3> 1 Queued status reflects oldest 2 bytes in FIFO
4896 * <1> 1 Rx Overrun IA
4897 * <0> 0 Select TC0 value for readback
4899 * 0000 0000 0000 1000 = 0x000a
4902 /* Carry over the Exit Hunt and Idle Received bits */
4903 /* in case they have been armed by usc_ArmEvents. */
4905 RegValue = usc_InReg( info, RICR ) & 0xc0;
4907 if ( info->bus_type == MGSL_BUS_TYPE_PCI )
4908 usc_OutReg( info, RICR, (u16)(0x030a | RegValue) );
4910 usc_OutReg( info, RICR, (u16)(0x140a | RegValue) );
4912 /* Unlatch all Rx status bits and clear Rx status IRQ Pending */
4914 usc_UnlatchRxstatusBits( info, RXSTATUS_ALL );
4915 usc_ClearIrqPendingBits( info, RECEIVE_STATUS );
4917 /* Transmit mode Register (TMR)
4919 * <15..13> 000 encoding
4920 * <12..11> 00 FCS = 16bit CRC CCITT (x15 + x12 + x5 + 1)
4921 * <10> 1 1 = Start CRC as all 1s (use for SDLC/HDLC)
4922 * <9> 0 1 = Tx CRC Enabled
4923 * <8> 0 1 = Append CRC to end of transmit frame
4924 * <7..6> 00 Transmit parity Even
4925 * <5> 0 Transmit parity Disabled
4926 * <4..2> 000 Tx Char Length = 8 bits
4927 * <1..0> 00 Disable Transmitter
4929 * 0000 0100 0000 0000 = 0x0400
4934 switch ( info->params.encoding ) {
4935 case HDLC_ENCODING_NRZB: RegValue |= BIT13; break;
4936 case HDLC_ENCODING_NRZI_MARK: RegValue |= BIT14; break;
4937 case HDLC_ENCODING_NRZI_SPACE: RegValue |= BIT14 + BIT13; break;
4938 case HDLC_ENCODING_BIPHASE_MARK: RegValue |= BIT15; break;
4939 case HDLC_ENCODING_BIPHASE_SPACE: RegValue |= BIT15 + BIT13; break;
4940 case HDLC_ENCODING_BIPHASE_LEVEL: RegValue |= BIT15 + BIT14; break;
4941 case HDLC_ENCODING_DIFF_BIPHASE_LEVEL: RegValue |= BIT15 + BIT14 + BIT13; break;
4944 if ( (info->params.crc_type & HDLC_CRC_MASK) == HDLC_CRC_16_CCITT )
4945 RegValue |= BIT9 + BIT8;
4946 else if ( (info->params.crc_type & HDLC_CRC_MASK) == HDLC_CRC_32_CCITT )
4947 RegValue |= ( BIT12 | BIT10 | BIT9 | BIT8);
4949 usc_OutReg( info, TMR, RegValue );
4951 usc_set_txidle( info );
4954 usc_TCmd( info, TCmd_SelectTicrdma_level );
4956 /* Transmit Interrupt Control Register (TICR)
4958 * <15..8> ? Transmit FIFO DMA Level
4959 * <7> 0 Present IA (Interrupt Arm)
4960 * <6> 0 Idle Sent IA
4961 * <5> 1 Abort Sent IA
4962 * <4> 1 EOF/EOM Sent IA
4964 * <2> 1 1 = Wait for SW Trigger to Start Frame
4965 * <1> 1 Tx Underrun IA
4966 * <0> 0 TC0 constant on read back
4968 * 0000 0000 0011 0110 = 0x0036
4971 if ( info->bus_type == MGSL_BUS_TYPE_PCI )
4972 usc_OutReg( info, TICR, 0x0736 );
4974 usc_OutReg( info, TICR, 0x1436 );
4976 usc_UnlatchTxstatusBits( info, TXSTATUS_ALL );
4977 usc_ClearIrqPendingBits( info, TRANSMIT_STATUS );
4980 ** Transmit Command/Status Register (TCSR)
4982 ** <15..12> 0000 TCmd
4983 ** <11> 0/1 UnderWait
4984 ** <10..08> 000 TxIdle
4988 ** <4> x EOF/EOM Sent
4994 ** 0000 0000 0000 0000 = 0x0000
4996 info->tcsr_value = 0;
4999 info->tcsr_value |= TCSR_UNDERWAIT;
5001 usc_OutReg( info, TCSR, info->tcsr_value );
5003 /* Clock mode Control Register (CMCR)
5005 * <15..14> 00 counter 1 Source = Disabled
5006 * <13..12> 00 counter 0 Source = Disabled
5007 * <11..10> 11 BRG1 Input is TxC Pin
5008 * <9..8> 11 BRG0 Input is TxC Pin
5009 * <7..6> 01 DPLL Input is BRG1 Output
5010 * <5..3> XXX TxCLK comes from Port 0
5011 * <2..0> XXX RxCLK comes from Port 1
5013 * 0000 1111 0111 0111 = 0x0f77
5018 if ( info->params.flags & HDLC_FLAG_RXC_DPLL )
5019 RegValue |= 0x0003; /* RxCLK from DPLL */
5020 else if ( info->params.flags & HDLC_FLAG_RXC_BRG )
5021 RegValue |= 0x0004; /* RxCLK from BRG0 */
5022 else if ( info->params.flags & HDLC_FLAG_RXC_TXCPIN)
5023 RegValue |= 0x0006; /* RxCLK from TXC Input */
5025 RegValue |= 0x0007; /* RxCLK from Port1 */
5027 if ( info->params.flags & HDLC_FLAG_TXC_DPLL )
5028 RegValue |= 0x0018; /* TxCLK from DPLL */
5029 else if ( info->params.flags & HDLC_FLAG_TXC_BRG )
5030 RegValue |= 0x0020; /* TxCLK from BRG0 */
5031 else if ( info->params.flags & HDLC_FLAG_TXC_RXCPIN)
5032 RegValue |= 0x0038; /* RxCLK from TXC Input */
5034 RegValue |= 0x0030; /* TxCLK from Port0 */
5036 usc_OutReg( info, CMCR, RegValue );
5039 /* Hardware Configuration Register (HCR)
5041 * <15..14> 00 CTR0 Divisor:00=32,01=16,10=8,11=4
5042 * <13> 0 CTR1DSel:0=CTR0Div determines CTR0Div
5043 * <12> 0 CVOK:0=report code violation in biphase
5044 * <11..10> 00 DPLL Divisor:00=32,01=16,10=8,11=4
5045 * <9..8> XX DPLL mode:00=disable,01=NRZ,10=Biphase,11=Biphase Level
5046 * <7..6> 00 reserved
5047 * <5> 0 BRG1 mode:0=continuous,1=single cycle
5049 * <3..2> 00 reserved
5050 * <1> 0 BRG0 mode:0=continuous,1=single cycle
5056 if ( info->params.flags & (HDLC_FLAG_RXC_DPLL + HDLC_FLAG_TXC_DPLL) ) {
5061 /* DPLL is enabled. Use BRG1 to provide continuous reference clock */
5062 /* for DPLL. DPLL mode in HCR is dependent on the encoding used. */
5064 if ( info->bus_type == MGSL_BUS_TYPE_PCI )
5065 XtalSpeed = 11059200;
5067 XtalSpeed = 14745600;
5069 if ( info->params.flags & HDLC_FLAG_DPLL_DIV16 ) {
5073 else if ( info->params.flags & HDLC_FLAG_DPLL_DIV8 ) {
5080 /* Tc = (Xtal/Speed) - 1 */
5081 /* If twice the remainder of (Xtal/Speed) is greater than Speed */
5082 /* then rounding up gives a more precise time constant. Instead */
5083 /* of rounding up and then subtracting 1 we just don't subtract */
5084 /* the one in this case. */
5086 /*--------------------------------------------------
5087 * ejz: for DPLL mode, application should use the
5088 * same clock speed as the partner system, even
5089 * though clocking is derived from the input RxData.
5090 * In case the user uses a 0 for the clock speed,
5091 * default to 0xffffffff and don't try to divide by
5093 *--------------------------------------------------*/
5094 if ( info->params.clock_speed )
5096 Tc = (u16)((XtalSpeed/DpllDivisor)/info->params.clock_speed);
5097 if ( !((((XtalSpeed/DpllDivisor) % info->params.clock_speed) * 2)
5098 / info->params.clock_speed) )
5105 /* Write 16-bit Time Constant for BRG1 */
5106 usc_OutReg( info, TC1R, Tc );
5108 RegValue |= BIT4; /* enable BRG1 */
5110 switch ( info->params.encoding ) {
5111 case HDLC_ENCODING_NRZ:
5112 case HDLC_ENCODING_NRZB:
5113 case HDLC_ENCODING_NRZI_MARK:
5114 case HDLC_ENCODING_NRZI_SPACE: RegValue |= BIT8; break;
5115 case HDLC_ENCODING_BIPHASE_MARK:
5116 case HDLC_ENCODING_BIPHASE_SPACE: RegValue |= BIT9; break;
5117 case HDLC_ENCODING_BIPHASE_LEVEL:
5118 case HDLC_ENCODING_DIFF_BIPHASE_LEVEL: RegValue |= BIT9 + BIT8; break;
5122 usc_OutReg( info, HCR, RegValue );
5125 /* Channel Control/status Register (CCSR)
5127 * <15> X RCC FIFO Overflow status (RO)
5128 * <14> X RCC FIFO Not Empty status (RO)
5129 * <13> 0 1 = Clear RCC FIFO (WO)
5130 * <12> X DPLL Sync (RW)
5131 * <11> X DPLL 2 Missed Clocks status (RO)
5132 * <10> X DPLL 1 Missed Clock status (RO)
5133 * <9..8> 00 DPLL Resync on rising and falling edges (RW)
5134 * <7> X SDLC Loop On status (RO)
5135 * <6> X SDLC Loop Send status (RO)
5136 * <5> 1 Bypass counters for TxClk and RxClk (RW)
5137 * <4..2> 000 Last Char of SDLC frame has 8 bits (RW)
5138 * <1..0> 00 reserved
5140 * 0000 0000 0010 0000 = 0x0020
5143 usc_OutReg( info, CCSR, 0x1020 );
5146 if ( info->params.flags & HDLC_FLAG_AUTO_CTS ) {
5147 usc_OutReg( info, SICR,
5148 (u16)(usc_InReg(info,SICR) | SICR_CTS_INACTIVE) );
5152 /* enable Master Interrupt Enable bit (MIE) */
5153 usc_EnableMasterIrqBit( info );
5155 usc_ClearIrqPendingBits( info, RECEIVE_STATUS + RECEIVE_DATA +
5156 TRANSMIT_STATUS + TRANSMIT_DATA + MISC);
5158 /* arm RCC underflow interrupt */
5159 usc_OutReg(info, SICR, (u16)(usc_InReg(info,SICR) | BIT3));
5160 usc_EnableInterrupts(info, MISC);
5163 outw( 0, info->io_base ); /* clear Master Bus Enable (DCAR) */
5164 usc_DmaCmd( info, DmaCmd_ResetAllChannels ); /* disable both DMA channels */
5165 info->mbre_bit = BIT8;
5166 outw( BIT8, info->io_base ); /* set Master Bus Enable (DCAR) */
5168 if (info->bus_type == MGSL_BUS_TYPE_ISA) {
5169 /* Enable DMAEN (Port 7, Bit 14) */
5170 /* This connects the DMA request signal to the ISA bus */
5171 usc_OutReg(info, PCR, (u16)((usc_InReg(info, PCR) | BIT15) & ~BIT14));
5174 /* DMA Control Register (DCR)
5176 * <15..14> 10 Priority mode = Alternating Tx/Rx
5177 * 01 Rx has priority
5178 * 00 Tx has priority
5180 * <13> 1 Enable Priority Preempt per DCR<15..14>
5181 * (WARNING DCR<11..10> must be 00 when this is 1)
5182 * 0 Choose activate channel per DCR<11..10>
5184 * <12> 0 Little Endian for Array/List
5185 * <11..10> 00 Both Channels can use each bus grant
5186 * <9..6> 0000 reserved
5187 * <5> 0 7 CLK - Minimum Bus Re-request Interval
5188 * <4> 0 1 = drive D/C and S/D pins
5189 * <3> 1 1 = Add one wait state to all DMA cycles.
5190 * <2> 0 1 = Strobe /UAS on every transfer.
5191 * <1..0> 11 Addr incrementing only affects LS24 bits
5193 * 0110 0000 0000 1011 = 0x600b
5196 if ( info->bus_type == MGSL_BUS_TYPE_PCI ) {
5197 /* PCI adapter does not need DMA wait state */
5198 usc_OutDmaReg( info, DCR, 0xa00b );
5201 usc_OutDmaReg( info, DCR, 0x800b );
5204 /* Receive DMA mode Register (RDMR)
5206 * <15..14> 11 DMA mode = Linked List Buffer mode
5207 * <13> 1 RSBinA/L = store Rx status Block in Arrary/List entry
5208 * <12> 1 Clear count of List Entry after fetching
5209 * <11..10> 00 Address mode = Increment
5210 * <9> 1 Terminate Buffer on RxBound
5211 * <8> 0 Bus Width = 16bits
5212 * <7..0> ? status Bits (write as 0s)
5214 * 1111 0010 0000 0000 = 0xf200
5217 usc_OutDmaReg( info, RDMR, 0xf200 );
5220 /* Transmit DMA mode Register (TDMR)
5222 * <15..14> 11 DMA mode = Linked List Buffer mode
5223 * <13> 1 TCBinA/L = fetch Tx Control Block from List entry
5224 * <12> 1 Clear count of List Entry after fetching
5225 * <11..10> 00 Address mode = Increment
5226 * <9> 1 Terminate Buffer on end of frame
5227 * <8> 0 Bus Width = 16bits
5228 * <7..0> ? status Bits (Read Only so write as 0)
5230 * 1111 0010 0000 0000 = 0xf200
5233 usc_OutDmaReg( info, TDMR, 0xf200 );
5236 /* DMA Interrupt Control Register (DICR)
5238 * <15> 1 DMA Interrupt Enable
5239 * <14> 0 1 = Disable IEO from USC
5240 * <13> 0 1 = Don't provide vector during IntAck
5241 * <12> 1 1 = Include status in Vector
5242 * <10..2> 0 reserved, Must be 0s
5243 * <1> 0 1 = Rx DMA Interrupt Enabled
5244 * <0> 0 1 = Tx DMA Interrupt Enabled
5246 * 1001 0000 0000 0000 = 0x9000
5249 usc_OutDmaReg( info, DICR, 0x9000 );
5251 usc_InDmaReg( info, RDMR ); /* clear pending receive DMA IRQ bits */
5252 usc_InDmaReg( info, TDMR ); /* clear pending transmit DMA IRQ bits */
5253 usc_OutDmaReg( info, CDIR, 0x0303 ); /* clear IUS and Pending for Tx and Rx */
5255 /* Channel Control Register (CCR)
5257 * <15..14> 10 Use 32-bit Tx Control Blocks (TCBs)
5258 * <13> 0 Trigger Tx on SW Command Disabled
5259 * <12> 0 Flag Preamble Disabled
5260 * <11..10> 00 Preamble Length
5261 * <9..8> 00 Preamble Pattern
5262 * <7..6> 10 Use 32-bit Rx status Blocks (RSBs)
5263 * <5> 0 Trigger Rx on SW Command Disabled
5266 * 1000 0000 1000 0000 = 0x8080
5271 switch ( info->params.preamble_length ) {
5272 case HDLC_PREAMBLE_LENGTH_16BITS: RegValue |= BIT10; break;
5273 case HDLC_PREAMBLE_LENGTH_32BITS: RegValue |= BIT11; break;
5274 case HDLC_PREAMBLE_LENGTH_64BITS: RegValue |= BIT11 + BIT10; break;
5277 switch ( info->params.preamble ) {
5278 case HDLC_PREAMBLE_PATTERN_FLAGS: RegValue |= BIT8 + BIT12; break;
5279 case HDLC_PREAMBLE_PATTERN_ONES: RegValue |= BIT8; break;
5280 case HDLC_PREAMBLE_PATTERN_10: RegValue |= BIT9; break;
5281 case HDLC_PREAMBLE_PATTERN_01: RegValue |= BIT9 + BIT8; break;
5284 usc_OutReg( info, CCR, RegValue );
5288 * Burst/Dwell Control Register
5290 * <15..8> 0x20 Maximum number of transfers per bus grant
5291 * <7..0> 0x00 Maximum number of clock cycles per bus grant
5294 if ( info->bus_type == MGSL_BUS_TYPE_PCI ) {
5295 /* don't limit bus occupancy on PCI adapter */
5296 usc_OutDmaReg( info, BDCR, 0x0000 );
5299 usc_OutDmaReg( info, BDCR, 0x2000 );
5301 usc_stop_transmitter(info);
5302 usc_stop_receiver(info);
5304 } /* end of usc_set_sdlc_mode() */
5306 /* usc_enable_loopback()
5308 * Set the 16C32 for internal loopback mode.
5309 * The TxCLK and RxCLK signals are generated from the BRG0 and
5310 * the TxD is looped back to the RxD internally.
5312 * Arguments: info pointer to device instance data
5313 * enable 1 = enable loopback, 0 = disable
5314 * Return Value: None
5316 static void usc_enable_loopback(struct mgsl_struct *info, int enable)
5319 /* blank external TXD output */
5320 usc_OutReg(info,IOCR,usc_InReg(info,IOCR) | (BIT7+BIT6));
5322 /* Clock mode Control Register (CMCR)
5324 * <15..14> 00 counter 1 Disabled
5325 * <13..12> 00 counter 0 Disabled
5326 * <11..10> 11 BRG1 Input is TxC Pin
5327 * <9..8> 11 BRG0 Input is TxC Pin
5328 * <7..6> 01 DPLL Input is BRG1 Output
5329 * <5..3> 100 TxCLK comes from BRG0
5330 * <2..0> 100 RxCLK comes from BRG0
5332 * 0000 1111 0110 0100 = 0x0f64
5335 usc_OutReg( info, CMCR, 0x0f64 );
5337 /* Write 16-bit Time Constant for BRG0 */
5338 /* use clock speed if available, otherwise use 8 for diagnostics */
5339 if (info->params.clock_speed) {
5340 if (info->bus_type == MGSL_BUS_TYPE_PCI)
5341 usc_OutReg(info, TC0R, (u16)((11059200/info->params.clock_speed)-1));
5343 usc_OutReg(info, TC0R, (u16)((14745600/info->params.clock_speed)-1));
5345 usc_OutReg(info, TC0R, (u16)8);
5347 /* Hardware Configuration Register (HCR) Clear Bit 1, BRG0
5348 mode = Continuous Set Bit 0 to enable BRG0. */
5349 usc_OutReg( info, HCR, (u16)((usc_InReg( info, HCR ) & ~BIT1) | BIT0) );
5351 /* Input/Output Control Reg, <2..0> = 100, Drive RxC pin with BRG0 */
5352 usc_OutReg(info, IOCR, (u16)((usc_InReg(info, IOCR) & 0xfff8) | 0x0004));
5354 /* set Internal Data loopback mode */
5355 info->loopback_bits = 0x300;
5356 outw( 0x0300, info->io_base + CCAR );
5358 /* enable external TXD output */
5359 usc_OutReg(info,IOCR,usc_InReg(info,IOCR) & ~(BIT7+BIT6));
5361 /* clear Internal Data loopback mode */
5362 info->loopback_bits = 0;
5363 outw( 0,info->io_base + CCAR );
5366 } /* end of usc_enable_loopback() */
5368 /* usc_enable_aux_clock()
5370 * Enabled the AUX clock output at the specified frequency.
5374 * info pointer to device extension
5375 * data_rate data rate of clock in bits per second
5376 * A data rate of 0 disables the AUX clock.
5378 * Return Value: None
5380 static void usc_enable_aux_clock( struct mgsl_struct *info, u32 data_rate )
5386 if ( info->bus_type == MGSL_BUS_TYPE_PCI )
5387 XtalSpeed = 11059200;
5389 XtalSpeed = 14745600;
5392 /* Tc = (Xtal/Speed) - 1 */
5393 /* If twice the remainder of (Xtal/Speed) is greater than Speed */
5394 /* then rounding up gives a more precise time constant. Instead */
5395 /* of rounding up and then subtracting 1 we just don't subtract */
5396 /* the one in this case. */
5399 Tc = (u16)(XtalSpeed/data_rate);
5400 if ( !(((XtalSpeed % data_rate) * 2) / data_rate) )
5403 /* Write 16-bit Time Constant for BRG0 */
5404 usc_OutReg( info, TC0R, Tc );
5407 * Hardware Configuration Register (HCR)
5408 * Clear Bit 1, BRG0 mode = Continuous
5409 * Set Bit 0 to enable BRG0.
5412 usc_OutReg( info, HCR, (u16)((usc_InReg( info, HCR ) & ~BIT1) | BIT0) );
5414 /* Input/Output Control Reg, <2..0> = 100, Drive RxC pin with BRG0 */
5415 usc_OutReg( info, IOCR, (u16)((usc_InReg(info, IOCR) & 0xfff8) | 0x0004) );
5417 /* data rate == 0 so turn off BRG0 */
5418 usc_OutReg( info, HCR, (u16)(usc_InReg( info, HCR ) & ~BIT0) );
5421 } /* end of usc_enable_aux_clock() */
5425 * usc_process_rxoverrun_sync()
5427 * This function processes a receive overrun by resetting the
5428 * receive DMA buffers and issuing a Purge Rx FIFO command
5429 * to allow the receiver to continue receiving.
5433 * info pointer to device extension
5435 * Return Value: None
5437 static void usc_process_rxoverrun_sync( struct mgsl_struct *info )
5441 int frame_start_index;
5442 int start_of_frame_found = FALSE;
5443 int end_of_frame_found = FALSE;
5444 int reprogram_dma = FALSE;
5446 DMABUFFERENTRY *buffer_list = info->rx_buffer_list;
5449 usc_DmaCmd( info, DmaCmd_PauseRxChannel );
5450 usc_RCmd( info, RCmd_EnterHuntmode );
5451 usc_RTCmd( info, RTCmd_PurgeRxFifo );
5453 /* CurrentRxBuffer points to the 1st buffer of the next */
5454 /* possibly available receive frame. */
5456 frame_start_index = start_index = end_index = info->current_rx_buffer;
5458 /* Search for an unfinished string of buffers. This means */
5459 /* that a receive frame started (at least one buffer with */
5460 /* count set to zero) but there is no terminiting buffer */
5461 /* (status set to non-zero). */
5463 while( !buffer_list[end_index].count )
5465 /* Count field has been reset to zero by 16C32. */
5466 /* This buffer is currently in use. */
5468 if ( !start_of_frame_found )
5470 start_of_frame_found = TRUE;
5471 frame_start_index = end_index;
5472 end_of_frame_found = FALSE;
5475 if ( buffer_list[end_index].status )
5477 /* Status field has been set by 16C32. */
5478 /* This is the last buffer of a received frame. */
5480 /* We want to leave the buffers for this frame intact. */
5481 /* Move on to next possible frame. */
5483 start_of_frame_found = FALSE;
5484 end_of_frame_found = TRUE;
5487 /* advance to next buffer entry in linked list */
5489 if ( end_index == info->rx_buffer_count )
5492 if ( start_index == end_index )
5494 /* The entire list has been searched with all Counts == 0 and */
5495 /* all Status == 0. The receive buffers are */
5496 /* completely screwed, reset all receive buffers! */
5497 mgsl_reset_rx_dma_buffers( info );
5498 frame_start_index = 0;
5499 start_of_frame_found = FALSE;
5500 reprogram_dma = TRUE;
5505 if ( start_of_frame_found && !end_of_frame_found )
5507 /* There is an unfinished string of receive DMA buffers */
5508 /* as a result of the receiver overrun. */
5510 /* Reset the buffers for the unfinished frame */
5511 /* and reprogram the receive DMA controller to start */
5512 /* at the 1st buffer of unfinished frame. */
5514 start_index = frame_start_index;
5518 *((unsigned long *)&(info->rx_buffer_list[start_index++].count)) = DMABUFFERSIZE;
5520 /* Adjust index for wrap around. */
5521 if ( start_index == info->rx_buffer_count )
5524 } while( start_index != end_index );
5526 reprogram_dma = TRUE;
5529 if ( reprogram_dma )
5531 usc_UnlatchRxstatusBits(info,RXSTATUS_ALL);
5532 usc_ClearIrqPendingBits(info, RECEIVE_DATA|RECEIVE_STATUS);
5533 usc_UnlatchRxstatusBits(info, RECEIVE_DATA|RECEIVE_STATUS);
5535 usc_EnableReceiver(info,DISABLE_UNCONDITIONAL);
5537 /* This empties the receive FIFO and loads the RCC with RCLR */
5538 usc_OutReg( info, CCSR, (u16)(usc_InReg(info,CCSR) | BIT13) );
5540 /* program 16C32 with physical address of 1st DMA buffer entry */
5541 phys_addr = info->rx_buffer_list[frame_start_index].phys_entry;
5542 usc_OutDmaReg( info, NRARL, (u16)phys_addr );
5543 usc_OutDmaReg( info, NRARU, (u16)(phys_addr >> 16) );
5545 usc_UnlatchRxstatusBits( info, RXSTATUS_ALL );
5546 usc_ClearIrqPendingBits( info, RECEIVE_DATA + RECEIVE_STATUS );
5547 usc_EnableInterrupts( info, RECEIVE_STATUS );
5549 /* 1. Arm End of Buffer (EOB) Receive DMA Interrupt (BIT2 of RDIAR) */
5550 /* 2. Enable Receive DMA Interrupts (BIT1 of DICR) */
5552 usc_OutDmaReg( info, RDIAR, BIT3 + BIT2 );
5553 usc_OutDmaReg( info, DICR, (u16)(usc_InDmaReg(info,DICR) | BIT1) );
5554 usc_DmaCmd( info, DmaCmd_InitRxChannel );
5555 if ( info->params.flags & HDLC_FLAG_AUTO_DCD )
5556 usc_EnableReceiver(info,ENABLE_AUTO_DCD);
5558 usc_EnableReceiver(info,ENABLE_UNCONDITIONAL);
5562 /* This empties the receive FIFO and loads the RCC with RCLR */
5563 usc_OutReg( info, CCSR, (u16)(usc_InReg(info,CCSR) | BIT13) );
5564 usc_RTCmd( info, RTCmd_PurgeRxFifo );
5567 } /* end of usc_process_rxoverrun_sync() */
5569 /* usc_stop_receiver()
5571 * Disable USC receiver
5573 * Arguments: info pointer to device instance data
5574 * Return Value: None
5576 static void usc_stop_receiver( struct mgsl_struct *info )
5578 if (debug_level >= DEBUG_LEVEL_ISR)
5579 printk("%s(%d):usc_stop_receiver(%s)\n",
5580 __FILE__,__LINE__, info->device_name );
5582 /* Disable receive DMA channel. */
5583 /* This also disables receive DMA channel interrupts */
5584 usc_DmaCmd( info, DmaCmd_ResetRxChannel );
5586 usc_UnlatchRxstatusBits( info, RXSTATUS_ALL );
5587 usc_ClearIrqPendingBits( info, RECEIVE_DATA + RECEIVE_STATUS );
5588 usc_DisableInterrupts( info, RECEIVE_DATA + RECEIVE_STATUS );
5590 usc_EnableReceiver(info,DISABLE_UNCONDITIONAL);
5592 /* This empties the receive FIFO and loads the RCC with RCLR */
5593 usc_OutReg( info, CCSR, (u16)(usc_InReg(info,CCSR) | BIT13) );
5594 usc_RTCmd( info, RTCmd_PurgeRxFifo );
5596 info->rx_enabled = 0;
5597 info->rx_overflow = 0;
5598 info->rx_rcc_underrun = 0;
5600 } /* end of stop_receiver() */
5602 /* usc_start_receiver()
5604 * Enable the USC receiver
5606 * Arguments: info pointer to device instance data
5607 * Return Value: None
5609 static void usc_start_receiver( struct mgsl_struct *info )
5613 if (debug_level >= DEBUG_LEVEL_ISR)
5614 printk("%s(%d):usc_start_receiver(%s)\n",
5615 __FILE__,__LINE__, info->device_name );
5617 mgsl_reset_rx_dma_buffers( info );
5618 usc_stop_receiver( info );
5620 usc_OutReg( info, CCSR, (u16)(usc_InReg(info,CCSR) | BIT13) );
5621 usc_RTCmd( info, RTCmd_PurgeRxFifo );
5623 if ( info->params.mode == MGSL_MODE_HDLC ||
5624 info->params.mode == MGSL_MODE_RAW ) {
5625 /* DMA mode Transfers */
5626 /* Program the DMA controller. */
5627 /* Enable the DMA controller end of buffer interrupt. */
5629 /* program 16C32 with physical address of 1st DMA buffer entry */
5630 phys_addr = info->rx_buffer_list[0].phys_entry;
5631 usc_OutDmaReg( info, NRARL, (u16)phys_addr );
5632 usc_OutDmaReg( info, NRARU, (u16)(phys_addr >> 16) );
5634 usc_UnlatchRxstatusBits( info, RXSTATUS_ALL );
5635 usc_ClearIrqPendingBits( info, RECEIVE_DATA + RECEIVE_STATUS );
5636 usc_EnableInterrupts( info, RECEIVE_STATUS );
5638 /* 1. Arm End of Buffer (EOB) Receive DMA Interrupt (BIT2 of RDIAR) */
5639 /* 2. Enable Receive DMA Interrupts (BIT1 of DICR) */
5641 usc_OutDmaReg( info, RDIAR, BIT3 + BIT2 );
5642 usc_OutDmaReg( info, DICR, (u16)(usc_InDmaReg(info,DICR) | BIT1) );
5643 usc_DmaCmd( info, DmaCmd_InitRxChannel );
5644 if ( info->params.flags & HDLC_FLAG_AUTO_DCD )
5645 usc_EnableReceiver(info,ENABLE_AUTO_DCD);
5647 usc_EnableReceiver(info,ENABLE_UNCONDITIONAL);
5649 usc_UnlatchRxstatusBits(info, RXSTATUS_ALL);
5650 usc_ClearIrqPendingBits(info, RECEIVE_DATA + RECEIVE_STATUS);
5651 usc_EnableInterrupts(info, RECEIVE_DATA);
5653 usc_RTCmd( info, RTCmd_PurgeRxFifo );
5654 usc_RCmd( info, RCmd_EnterHuntmode );
5656 usc_EnableReceiver(info,ENABLE_UNCONDITIONAL);
5659 usc_OutReg( info, CCSR, 0x1020 );
5661 info->rx_enabled = 1;
5663 } /* end of usc_start_receiver() */
5665 /* usc_start_transmitter()
5667 * Enable the USC transmitter and send a transmit frame if
5668 * one is loaded in the DMA buffers.
5670 * Arguments: info pointer to device instance data
5671 * Return Value: None
5673 static void usc_start_transmitter( struct mgsl_struct *info )
5676 unsigned int FrameSize;
5678 if (debug_level >= DEBUG_LEVEL_ISR)
5679 printk("%s(%d):usc_start_transmitter(%s)\n",
5680 __FILE__,__LINE__, info->device_name );
5682 if ( info->xmit_cnt ) {
5684 /* If auto RTS enabled and RTS is inactive, then assert */
5685 /* RTS and set a flag indicating that the driver should */
5686 /* negate RTS when the transmission completes. */
5688 info->drop_rts_on_tx_done = 0;
5690 if ( info->params.flags & HDLC_FLAG_AUTO_RTS ) {
5691 usc_get_serial_signals( info );
5692 if ( !(info->serial_signals & SerialSignal_RTS) ) {
5693 info->serial_signals |= SerialSignal_RTS;
5694 usc_set_serial_signals( info );
5695 info->drop_rts_on_tx_done = 1;
5700 if ( info->params.mode == MGSL_MODE_ASYNC ) {
5701 if ( !info->tx_active ) {
5702 usc_UnlatchTxstatusBits(info, TXSTATUS_ALL);
5703 usc_ClearIrqPendingBits(info, TRANSMIT_STATUS + TRANSMIT_DATA);
5704 usc_EnableInterrupts(info, TRANSMIT_DATA);
5705 usc_load_txfifo(info);
5708 /* Disable transmit DMA controller while programming. */
5709 usc_DmaCmd( info, DmaCmd_ResetTxChannel );
5711 /* Transmit DMA buffer is loaded, so program USC */
5712 /* to send the frame contained in the buffers. */
5714 FrameSize = info->tx_buffer_list[info->start_tx_dma_buffer].rcc;
5716 /* if operating in Raw sync mode, reset the rcc component
5717 * of the tx dma buffer entry, otherwise, the serial controller
5718 * will send a closing sync char after this count.
5720 if ( info->params.mode == MGSL_MODE_RAW )
5721 info->tx_buffer_list[info->start_tx_dma_buffer].rcc = 0;
5723 /* Program the Transmit Character Length Register (TCLR) */
5724 /* and clear FIFO (TCC is loaded with TCLR on FIFO clear) */
5725 usc_OutReg( info, TCLR, (u16)FrameSize );
5727 usc_RTCmd( info, RTCmd_PurgeTxFifo );
5729 /* Program the address of the 1st DMA Buffer Entry in linked list */
5730 phys_addr = info->tx_buffer_list[info->start_tx_dma_buffer].phys_entry;
5731 usc_OutDmaReg( info, NTARL, (u16)phys_addr );
5732 usc_OutDmaReg( info, NTARU, (u16)(phys_addr >> 16) );
5734 usc_UnlatchTxstatusBits( info, TXSTATUS_ALL );
5735 usc_ClearIrqPendingBits( info, TRANSMIT_STATUS );
5736 usc_EnableInterrupts( info, TRANSMIT_STATUS );
5738 if ( info->params.mode == MGSL_MODE_RAW &&
5739 info->num_tx_dma_buffers > 1 ) {
5740 /* When running external sync mode, attempt to 'stream' transmit */
5741 /* by filling tx dma buffers as they become available. To do this */
5742 /* we need to enable Tx DMA EOB Status interrupts : */
5744 /* 1. Arm End of Buffer (EOB) Transmit DMA Interrupt (BIT2 of TDIAR) */
5745 /* 2. Enable Transmit DMA Interrupts (BIT0 of DICR) */
5747 usc_OutDmaReg( info, TDIAR, BIT2|BIT3 );
5748 usc_OutDmaReg( info, DICR, (u16)(usc_InDmaReg(info,DICR) | BIT0) );
5751 /* Initialize Transmit DMA Channel */
5752 usc_DmaCmd( info, DmaCmd_InitTxChannel );
5754 usc_TCmd( info, TCmd_SendFrame );
5756 info->tx_timer.expires = jiffies + msecs_to_jiffies(5000);
5757 add_timer(&info->tx_timer);
5759 info->tx_active = 1;
5762 if ( !info->tx_enabled ) {
5763 info->tx_enabled = 1;
5764 if ( info->params.flags & HDLC_FLAG_AUTO_CTS )
5765 usc_EnableTransmitter(info,ENABLE_AUTO_CTS);
5767 usc_EnableTransmitter(info,ENABLE_UNCONDITIONAL);
5770 } /* end of usc_start_transmitter() */
5772 /* usc_stop_transmitter()
5774 * Stops the transmitter and DMA
5776 * Arguments: info pointer to device isntance data
5777 * Return Value: None
5779 static void usc_stop_transmitter( struct mgsl_struct *info )
5781 if (debug_level >= DEBUG_LEVEL_ISR)
5782 printk("%s(%d):usc_stop_transmitter(%s)\n",
5783 __FILE__,__LINE__, info->device_name );
5785 del_timer(&info->tx_timer);
5787 usc_UnlatchTxstatusBits( info, TXSTATUS_ALL );
5788 usc_ClearIrqPendingBits( info, TRANSMIT_STATUS + TRANSMIT_DATA );
5789 usc_DisableInterrupts( info, TRANSMIT_STATUS + TRANSMIT_DATA );
5791 usc_EnableTransmitter(info,DISABLE_UNCONDITIONAL);
5792 usc_DmaCmd( info, DmaCmd_ResetTxChannel );
5793 usc_RTCmd( info, RTCmd_PurgeTxFifo );
5795 info->tx_enabled = 0;
5796 info->tx_active = 0;
5798 } /* end of usc_stop_transmitter() */
5800 /* usc_load_txfifo()
5802 * Fill the transmit FIFO until the FIFO is full or
5803 * there is no more data to load.
5805 * Arguments: info pointer to device extension (instance data)
5806 * Return Value: None
5808 static void usc_load_txfifo( struct mgsl_struct *info )
5813 if ( !info->xmit_cnt && !info->x_char )
5816 /* Select transmit FIFO status readback in TICR */
5817 usc_TCmd( info, TCmd_SelectTicrTxFifostatus );
5819 /* load the Transmit FIFO until FIFOs full or all data sent */
5821 while( (Fifocount = usc_InReg(info, TICR) >> 8) && info->xmit_cnt ) {
5822 /* there is more space in the transmit FIFO and */
5823 /* there is more data in transmit buffer */
5825 if ( (info->xmit_cnt > 1) && (Fifocount > 1) && !info->x_char ) {
5826 /* write a 16-bit word from transmit buffer to 16C32 */
5828 TwoBytes[0] = info->xmit_buf[info->xmit_tail++];
5829 info->xmit_tail = info->xmit_tail & (SERIAL_XMIT_SIZE-1);
5830 TwoBytes[1] = info->xmit_buf[info->xmit_tail++];
5831 info->xmit_tail = info->xmit_tail & (SERIAL_XMIT_SIZE-1);
5833 outw( *((u16 *)TwoBytes), info->io_base + DATAREG);
5835 info->xmit_cnt -= 2;
5836 info->icount.tx += 2;
5838 /* only 1 byte left to transmit or 1 FIFO slot left */
5840 outw( (inw( info->io_base + CCAR) & 0x0780) | (TDR+LSBONLY),
5841 info->io_base + CCAR );
5844 /* transmit pending high priority char */
5845 outw( info->x_char,info->io_base + CCAR );
5848 outw( info->xmit_buf[info->xmit_tail++],info->io_base + CCAR );
5849 info->xmit_tail = info->xmit_tail & (SERIAL_XMIT_SIZE-1);
5856 } /* end of usc_load_txfifo() */
5860 * Reset the adapter to a known state and prepare it for further use.
5862 * Arguments: info pointer to device instance data
5863 * Return Value: None
5865 static void usc_reset( struct mgsl_struct *info )
5867 if ( info->bus_type == MGSL_BUS_TYPE_PCI ) {
5871 /* Set BIT30 of Misc Control Register */
5872 /* (Local Control Register 0x50) to force reset of USC. */
5874 volatile u32 *MiscCtrl = (u32 *)(info->lcr_base + 0x50);
5875 u32 *LCR0BRDR = (u32 *)(info->lcr_base + 0x28);
5877 info->misc_ctrl_value |= BIT30;
5878 *MiscCtrl = info->misc_ctrl_value;
5881 * Force at least 170ns delay before clearing
5882 * reset bit. Each read from LCR takes at least
5883 * 30ns so 10 times for 300ns to be safe.
5886 readval = *MiscCtrl;
5888 info->misc_ctrl_value &= ~BIT30;
5889 *MiscCtrl = info->misc_ctrl_value;
5891 *LCR0BRDR = BUS_DESCRIPTOR(
5892 1, // Write Strobe Hold (0-3)
5893 2, // Write Strobe Delay (0-3)
5894 2, // Read Strobe Delay (0-3)
5895 0, // NWDD (Write data-data) (0-3)
5896 4, // NWAD (Write Addr-data) (0-31)
5897 0, // NXDA (Read/Write Data-Addr) (0-3)
5898 0, // NRDD (Read Data-Data) (0-3)
5899 5 // NRAD (Read Addr-Data) (0-31)
5903 outb( 0,info->io_base + 8 );
5907 info->loopback_bits = 0;
5908 info->usc_idle_mode = 0;
5911 * Program the Bus Configuration Register (BCR)
5913 * <15> 0 Don't use separate address
5914 * <14..6> 0 reserved
5915 * <5..4> 00 IAckmode = Default, don't care
5916 * <3> 1 Bus Request Totem Pole output
5917 * <2> 1 Use 16 Bit data bus
5918 * <1> 0 IRQ Totem Pole output
5919 * <0> 0 Don't Shift Right Addr
5921 * 0000 0000 0000 1100 = 0x000c
5923 * By writing to io_base + SDPIN the Wait/Ack pin is
5924 * programmed to work as a Wait pin.
5927 outw( 0x000c,info->io_base + SDPIN );
5930 outw( 0,info->io_base );
5931 outw( 0,info->io_base + CCAR );
5933 /* select little endian byte ordering */
5934 usc_RTCmd( info, RTCmd_SelectLittleEndian );
5937 /* Port Control Register (PCR)
5939 * <15..14> 11 Port 7 is Output (~DMAEN, Bit 14 : 0 = Enabled)
5940 * <13..12> 11 Port 6 is Output (~INTEN, Bit 12 : 0 = Enabled)
5941 * <11..10> 00 Port 5 is Input (No Connect, Don't Care)
5942 * <9..8> 00 Port 4 is Input (No Connect, Don't Care)
5943 * <7..6> 11 Port 3 is Output (~RTS, Bit 6 : 0 = Enabled )
5944 * <5..4> 11 Port 2 is Output (~DTR, Bit 4 : 0 = Enabled )
5945 * <3..2> 01 Port 1 is Input (Dedicated RxC)
5946 * <1..0> 01 Port 0 is Input (Dedicated TxC)
5948 * 1111 0000 1111 0101 = 0xf0f5
5951 usc_OutReg( info, PCR, 0xf0f5 );
5955 * Input/Output Control Register
5957 * <15..14> 00 CTS is active low input
5958 * <13..12> 00 DCD is active low input
5959 * <11..10> 00 TxREQ pin is input (DSR)
5960 * <9..8> 00 RxREQ pin is input (RI)
5961 * <7..6> 00 TxD is output (Transmit Data)
5962 * <5..3> 000 TxC Pin in Input (14.7456MHz Clock)
5963 * <2..0> 100 RxC is Output (drive with BRG0)
5965 * 0000 0000 0000 0100 = 0x0004
5968 usc_OutReg( info, IOCR, 0x0004 );
5970 } /* end of usc_reset() */
5972 /* usc_set_async_mode()
5974 * Program adapter for asynchronous communications.
5976 * Arguments: info pointer to device instance data
5977 * Return Value: None
5979 static void usc_set_async_mode( struct mgsl_struct *info )
5983 /* disable interrupts while programming USC */
5984 usc_DisableMasterIrqBit( info );
5986 outw( 0, info->io_base ); /* clear Master Bus Enable (DCAR) */
5987 usc_DmaCmd( info, DmaCmd_ResetAllChannels ); /* disable both DMA channels */
5989 usc_loopback_frame( info );
5991 /* Channel mode Register (CMR)
5993 * <15..14> 00 Tx Sub modes, 00 = 1 Stop Bit
5994 * <13..12> 00 00 = 16X Clock
5995 * <11..8> 0000 Transmitter mode = Asynchronous
5996 * <7..6> 00 reserved?
5997 * <5..4> 00 Rx Sub modes, 00 = 16X Clock
5998 * <3..0> 0000 Receiver mode = Asynchronous
6000 * 0000 0000 0000 0000 = 0x0
6004 if ( info->params.stop_bits != 1 )
6006 usc_OutReg( info, CMR, RegValue );
6009 /* Receiver mode Register (RMR)
6011 * <15..13> 000 encoding = None
6012 * <12..08> 00000 reserved (Sync Only)
6013 * <7..6> 00 Even parity
6014 * <5> 0 parity disabled
6015 * <4..2> 000 Receive Char Length = 8 bits
6016 * <1..0> 00 Disable Receiver
6018 * 0000 0000 0000 0000 = 0x0
6023 if ( info->params.data_bits != 8 )
6024 RegValue |= BIT4+BIT3+BIT2;
6026 if ( info->params.parity != ASYNC_PARITY_NONE ) {
6028 if ( info->params.parity != ASYNC_PARITY_ODD )
6032 usc_OutReg( info, RMR, RegValue );
6035 /* Set IRQ trigger level */
6037 usc_RCmd( info, RCmd_SelectRicrIntLevel );
6040 /* Receive Interrupt Control Register (RICR)
6042 * <15..8> ? RxFIFO IRQ Request Level
6044 * Note: For async mode the receive FIFO level must be set
6045 * to 0 to aviod the situation where the FIFO contains fewer bytes
6046 * than the trigger level and no more data is expected.
6048 * <7> 0 Exited Hunt IA (Interrupt Arm)
6049 * <6> 0 Idle Received IA
6050 * <5> 0 Break/Abort IA
6052 * <3> 0 Queued status reflects oldest byte in FIFO
6054 * <1> 0 Rx Overrun IA
6055 * <0> 0 Select TC0 value for readback
6057 * 0000 0000 0100 0000 = 0x0000 + (FIFOLEVEL in MSB)
6060 usc_OutReg( info, RICR, 0x0000 );
6062 usc_UnlatchRxstatusBits( info, RXSTATUS_ALL );
6063 usc_ClearIrqPendingBits( info, RECEIVE_STATUS );
6066 /* Transmit mode Register (TMR)
6068 * <15..13> 000 encoding = None
6069 * <12..08> 00000 reserved (Sync Only)
6070 * <7..6> 00 Transmit parity Even
6071 * <5> 0 Transmit parity Disabled
6072 * <4..2> 000 Tx Char Length = 8 bits
6073 * <1..0> 00 Disable Transmitter
6075 * 0000 0000 0000 0000 = 0x0
6080 if ( info->params.data_bits != 8 )
6081 RegValue |= BIT4+BIT3+BIT2;
6083 if ( info->params.parity != ASYNC_PARITY_NONE ) {
6085 if ( info->params.parity != ASYNC_PARITY_ODD )
6089 usc_OutReg( info, TMR, RegValue );
6091 usc_set_txidle( info );
6094 /* Set IRQ trigger level */
6096 usc_TCmd( info, TCmd_SelectTicrIntLevel );
6099 /* Transmit Interrupt Control Register (TICR)
6101 * <15..8> ? Transmit FIFO IRQ Level
6102 * <7> 0 Present IA (Interrupt Arm)
6103 * <6> 1 Idle Sent IA
6104 * <5> 0 Abort Sent IA
6105 * <4> 0 EOF/EOM Sent IA
6107 * <2> 0 1 = Wait for SW Trigger to Start Frame
6108 * <1> 0 Tx Underrun IA
6109 * <0> 0 TC0 constant on read back
6111 * 0000 0000 0100 0000 = 0x0040
6114 usc_OutReg( info, TICR, 0x1f40 );
6116 usc_UnlatchTxstatusBits( info, TXSTATUS_ALL );
6117 usc_ClearIrqPendingBits( info, TRANSMIT_STATUS );
6119 usc_enable_async_clock( info, info->params.data_rate );
6122 /* Channel Control/status Register (CCSR)
6124 * <15> X RCC FIFO Overflow status (RO)
6125 * <14> X RCC FIFO Not Empty status (RO)
6126 * <13> 0 1 = Clear RCC FIFO (WO)
6127 * <12> X DPLL in Sync status (RO)
6128 * <11> X DPLL 2 Missed Clocks status (RO)
6129 * <10> X DPLL 1 Missed Clock status (RO)
6130 * <9..8> 00 DPLL Resync on rising and falling edges (RW)
6131 * <7> X SDLC Loop On status (RO)
6132 * <6> X SDLC Loop Send status (RO)
6133 * <5> 1 Bypass counters for TxClk and RxClk (RW)
6134 * <4..2> 000 Last Char of SDLC frame has 8 bits (RW)
6135 * <1..0> 00 reserved
6137 * 0000 0000 0010 0000 = 0x0020
6140 usc_OutReg( info, CCSR, 0x0020 );
6142 usc_DisableInterrupts( info, TRANSMIT_STATUS + TRANSMIT_DATA +
6143 RECEIVE_DATA + RECEIVE_STATUS );
6145 usc_ClearIrqPendingBits( info, TRANSMIT_STATUS + TRANSMIT_DATA +
6146 RECEIVE_DATA + RECEIVE_STATUS );
6148 usc_EnableMasterIrqBit( info );
6150 if (info->bus_type == MGSL_BUS_TYPE_ISA) {
6151 /* Enable INTEN (Port 6, Bit12) */
6152 /* This connects the IRQ request signal to the ISA bus */
6153 usc_OutReg(info, PCR, (u16)((usc_InReg(info, PCR) | BIT13) & ~BIT12));
6156 } /* end of usc_set_async_mode() */
6158 /* usc_loopback_frame()
6160 * Loop back a small (2 byte) dummy SDLC frame.
6161 * Interrupts and DMA are NOT used. The purpose of this is to
6162 * clear any 'stale' status info left over from running in async mode.
6164 * The 16C32 shows the strange behaviour of marking the 1st
6165 * received SDLC frame with a CRC error even when there is no
6166 * CRC error. To get around this a small dummy from of 2 bytes
6167 * is looped back when switching from async to sync mode.
6169 * Arguments: info pointer to device instance data
6170 * Return Value: None
6172 static void usc_loopback_frame( struct mgsl_struct *info )
6175 unsigned long oldmode = info->params.mode;
6177 info->params.mode = MGSL_MODE_HDLC;
6179 usc_DisableMasterIrqBit( info );
6181 usc_set_sdlc_mode( info );
6182 usc_enable_loopback( info, 1 );
6184 /* Write 16-bit Time Constant for BRG0 */
6185 usc_OutReg( info, TC0R, 0 );
6187 /* Channel Control Register (CCR)
6189 * <15..14> 00 Don't use 32-bit Tx Control Blocks (TCBs)
6190 * <13> 0 Trigger Tx on SW Command Disabled
6191 * <12> 0 Flag Preamble Disabled
6192 * <11..10> 00 Preamble Length = 8-Bits
6193 * <9..8> 01 Preamble Pattern = flags
6194 * <7..6> 10 Don't use 32-bit Rx status Blocks (RSBs)
6195 * <5> 0 Trigger Rx on SW Command Disabled
6198 * 0000 0001 0000 0000 = 0x0100
6201 usc_OutReg( info, CCR, 0x0100 );
6203 /* SETUP RECEIVER */
6204 usc_RTCmd( info, RTCmd_PurgeRxFifo );
6205 usc_EnableReceiver(info,ENABLE_UNCONDITIONAL);
6207 /* SETUP TRANSMITTER */
6208 /* Program the Transmit Character Length Register (TCLR) */
6209 /* and clear FIFO (TCC is loaded with TCLR on FIFO clear) */
6210 usc_OutReg( info, TCLR, 2 );
6211 usc_RTCmd( info, RTCmd_PurgeTxFifo );
6213 /* unlatch Tx status bits, and start transmit channel. */
6214 usc_UnlatchTxstatusBits(info,TXSTATUS_ALL);
6215 outw(0,info->io_base + DATAREG);
6217 /* ENABLE TRANSMITTER */
6218 usc_TCmd( info, TCmd_SendFrame );
6219 usc_EnableTransmitter(info,ENABLE_UNCONDITIONAL);
6221 /* WAIT FOR RECEIVE COMPLETE */
6222 for (i=0 ; i<1000 ; i++)
6223 if (usc_InReg( info, RCSR ) & (BIT8 + BIT4 + BIT3 + BIT1))
6226 /* clear Internal Data loopback mode */
6227 usc_enable_loopback(info, 0);
6229 usc_EnableMasterIrqBit(info);
6231 info->params.mode = oldmode;
6233 } /* end of usc_loopback_frame() */
6235 /* usc_set_sync_mode() Programs the USC for SDLC communications.
6237 * Arguments: info pointer to adapter info structure
6238 * Return Value: None
6240 static void usc_set_sync_mode( struct mgsl_struct *info )
6242 usc_loopback_frame( info );
6243 usc_set_sdlc_mode( info );
6245 if (info->bus_type == MGSL_BUS_TYPE_ISA) {
6246 /* Enable INTEN (Port 6, Bit12) */
6247 /* This connects the IRQ request signal to the ISA bus */
6248 usc_OutReg(info, PCR, (u16)((usc_InReg(info, PCR) | BIT13) & ~BIT12));
6251 usc_enable_aux_clock(info, info->params.clock_speed);
6253 if (info->params.loopback)
6254 usc_enable_loopback(info,1);
6256 } /* end of mgsl_set_sync_mode() */
6258 /* usc_set_txidle() Set the HDLC idle mode for the transmitter.
6260 * Arguments: info pointer to device instance data
6261 * Return Value: None
6263 static void usc_set_txidle( struct mgsl_struct *info )
6265 u16 usc_idle_mode = IDLEMODE_FLAGS;
6267 /* Map API idle mode to USC register bits */
6269 switch( info->idle_mode ){
6270 case HDLC_TXIDLE_FLAGS: usc_idle_mode = IDLEMODE_FLAGS; break;
6271 case HDLC_TXIDLE_ALT_ZEROS_ONES: usc_idle_mode = IDLEMODE_ALT_ONE_ZERO; break;
6272 case HDLC_TXIDLE_ZEROS: usc_idle_mode = IDLEMODE_ZERO; break;
6273 case HDLC_TXIDLE_ONES: usc_idle_mode = IDLEMODE_ONE; break;
6274 case HDLC_TXIDLE_ALT_MARK_SPACE: usc_idle_mode = IDLEMODE_ALT_MARK_SPACE; break;
6275 case HDLC_TXIDLE_SPACE: usc_idle_mode = IDLEMODE_SPACE; break;
6276 case HDLC_TXIDLE_MARK: usc_idle_mode = IDLEMODE_MARK; break;
6279 info->usc_idle_mode = usc_idle_mode;
6280 //usc_OutReg(info, TCSR, usc_idle_mode);
6281 info->tcsr_value &= ~IDLEMODE_MASK; /* clear idle mode bits */
6282 info->tcsr_value += usc_idle_mode;
6283 usc_OutReg(info, TCSR, info->tcsr_value);
6286 * if SyncLink WAN adapter is running in external sync mode, the
6287 * transmitter has been set to Monosync in order to try to mimic
6288 * a true raw outbound bit stream. Monosync still sends an open/close
6289 * sync char at the start/end of a frame. Try to match those sync
6290 * patterns to the idle mode set here
6292 if ( info->params.mode == MGSL_MODE_RAW ) {
6293 unsigned char syncpat = 0;
6294 switch( info->idle_mode ) {
6295 case HDLC_TXIDLE_FLAGS:
6298 case HDLC_TXIDLE_ALT_ZEROS_ONES:
6301 case HDLC_TXIDLE_ZEROS:
6302 case HDLC_TXIDLE_SPACE:
6305 case HDLC_TXIDLE_ONES:
6306 case HDLC_TXIDLE_MARK:
6309 case HDLC_TXIDLE_ALT_MARK_SPACE:
6314 usc_SetTransmitSyncChars(info,syncpat,syncpat);
6317 } /* end of usc_set_txidle() */
6319 /* usc_get_serial_signals()
6321 * Query the adapter for the state of the V24 status (input) signals.
6323 * Arguments: info pointer to device instance data
6324 * Return Value: None
6326 static void usc_get_serial_signals( struct mgsl_struct *info )
6330 /* clear all serial signals except DTR and RTS */
6331 info->serial_signals &= SerialSignal_DTR + SerialSignal_RTS;
6333 /* Read the Misc Interrupt status Register (MISR) to get */
6334 /* the V24 status signals. */
6336 status = usc_InReg( info, MISR );
6338 /* set serial signal bits to reflect MISR */
6340 if ( status & MISCSTATUS_CTS )
6341 info->serial_signals |= SerialSignal_CTS;
6343 if ( status & MISCSTATUS_DCD )
6344 info->serial_signals |= SerialSignal_DCD;
6346 if ( status & MISCSTATUS_RI )
6347 info->serial_signals |= SerialSignal_RI;
6349 if ( status & MISCSTATUS_DSR )
6350 info->serial_signals |= SerialSignal_DSR;
6352 } /* end of usc_get_serial_signals() */
6354 /* usc_set_serial_signals()
6356 * Set the state of DTR and RTS based on contents of
6357 * serial_signals member of device extension.
6359 * Arguments: info pointer to device instance data
6360 * Return Value: None
6362 static void usc_set_serial_signals( struct mgsl_struct *info )
6365 unsigned char V24Out = info->serial_signals;
6367 /* get the current value of the Port Control Register (PCR) */
6369 Control = usc_InReg( info, PCR );
6371 if ( V24Out & SerialSignal_RTS )
6376 if ( V24Out & SerialSignal_DTR )
6381 usc_OutReg( info, PCR, Control );
6383 } /* end of usc_set_serial_signals() */
6385 /* usc_enable_async_clock()
6387 * Enable the async clock at the specified frequency.
6389 * Arguments: info pointer to device instance data
6390 * data_rate data rate of clock in bps
6391 * 0 disables the AUX clock.
6392 * Return Value: None
6394 static void usc_enable_async_clock( struct mgsl_struct *info, u32 data_rate )
6398 * Clock mode Control Register (CMCR)
6400 * <15..14> 00 counter 1 Disabled
6401 * <13..12> 00 counter 0 Disabled
6402 * <11..10> 11 BRG1 Input is TxC Pin
6403 * <9..8> 11 BRG0 Input is TxC Pin
6404 * <7..6> 01 DPLL Input is BRG1 Output
6405 * <5..3> 100 TxCLK comes from BRG0
6406 * <2..0> 100 RxCLK comes from BRG0
6408 * 0000 1111 0110 0100 = 0x0f64
6411 usc_OutReg( info, CMCR, 0x0f64 );
6415 * Write 16-bit Time Constant for BRG0
6416 * Time Constant = (ClkSpeed / data_rate) - 1
6417 * ClkSpeed = 921600 (ISA), 691200 (PCI)
6420 if ( info->bus_type == MGSL_BUS_TYPE_PCI )
6421 usc_OutReg( info, TC0R, (u16)((691200/data_rate) - 1) );
6423 usc_OutReg( info, TC0R, (u16)((921600/data_rate) - 1) );
6427 * Hardware Configuration Register (HCR)
6428 * Clear Bit 1, BRG0 mode = Continuous
6429 * Set Bit 0 to enable BRG0.
6432 usc_OutReg( info, HCR,
6433 (u16)((usc_InReg( info, HCR ) & ~BIT1) | BIT0) );
6436 /* Input/Output Control Reg, <2..0> = 100, Drive RxC pin with BRG0 */
6438 usc_OutReg( info, IOCR,
6439 (u16)((usc_InReg(info, IOCR) & 0xfff8) | 0x0004) );
6441 /* data rate == 0 so turn off BRG0 */
6442 usc_OutReg( info, HCR, (u16)(usc_InReg( info, HCR ) & ~BIT0) );
6445 } /* end of usc_enable_async_clock() */
6448 * Buffer Structures:
6450 * Normal memory access uses virtual addresses that can make discontiguous
6451 * physical memory pages appear to be contiguous in the virtual address
6452 * space (the processors memory mapping handles the conversions).
6454 * DMA transfers require physically contiguous memory. This is because
6455 * the DMA system controller and DMA bus masters deal with memory using
6456 * only physical addresses.
6458 * This causes a problem under Windows NT when large DMA buffers are
6459 * needed. Fragmentation of the nonpaged pool prevents allocations of
6460 * physically contiguous buffers larger than the PAGE_SIZE.
6462 * However the 16C32 supports Bus Master Scatter/Gather DMA which
6463 * allows DMA transfers to physically discontiguous buffers. Information
6464 * about each data transfer buffer is contained in a memory structure
6465 * called a 'buffer entry'. A list of buffer entries is maintained
6466 * to track and control the use of the data transfer buffers.
6468 * To support this strategy we will allocate sufficient PAGE_SIZE
6469 * contiguous memory buffers to allow for the total required buffer
6472 * The 16C32 accesses the list of buffer entries using Bus Master
6473 * DMA. Control information is read from the buffer entries by the
6474 * 16C32 to control data transfers. status information is written to
6475 * the buffer entries by the 16C32 to indicate the status of completed
6478 * The CPU writes control information to the buffer entries to control
6479 * the 16C32 and reads status information from the buffer entries to
6480 * determine information about received and transmitted frames.
6482 * Because the CPU and 16C32 (adapter) both need simultaneous access
6483 * to the buffer entries, the buffer entry memory is allocated with
6484 * HalAllocateCommonBuffer(). This restricts the size of the buffer
6485 * entry list to PAGE_SIZE.
6487 * The actual data buffers on the other hand will only be accessed
6488 * by the CPU or the adapter but not by both simultaneously. This allows
6489 * Scatter/Gather packet based DMA procedures for using physically
6490 * discontiguous pages.
6494 * mgsl_reset_tx_dma_buffers()
6496 * Set the count for all transmit buffers to 0 to indicate the
6497 * buffer is available for use and set the current buffer to the
6498 * first buffer. This effectively makes all buffers free and
6499 * discards any data in buffers.
6501 * Arguments: info pointer to device instance data
6502 * Return Value: None
6504 static void mgsl_reset_tx_dma_buffers( struct mgsl_struct *info )
6508 for ( i = 0; i < info->tx_buffer_count; i++ ) {
6509 *((unsigned long *)&(info->tx_buffer_list[i].count)) = 0;
6512 info->current_tx_buffer = 0;
6513 info->start_tx_dma_buffer = 0;
6514 info->tx_dma_buffers_used = 0;
6516 info->get_tx_holding_index = 0;
6517 info->put_tx_holding_index = 0;
6518 info->tx_holding_count = 0;
6520 } /* end of mgsl_reset_tx_dma_buffers() */
6523 * num_free_tx_dma_buffers()
6525 * returns the number of free tx dma buffers available
6527 * Arguments: info pointer to device instance data
6528 * Return Value: number of free tx dma buffers
6530 static int num_free_tx_dma_buffers(struct mgsl_struct *info)
6532 return info->tx_buffer_count - info->tx_dma_buffers_used;
6536 * mgsl_reset_rx_dma_buffers()
6538 * Set the count for all receive buffers to DMABUFFERSIZE
6539 * and set the current buffer to the first buffer. This effectively
6540 * makes all buffers free and discards any data in buffers.
6542 * Arguments: info pointer to device instance data
6543 * Return Value: None
6545 static void mgsl_reset_rx_dma_buffers( struct mgsl_struct *info )
6549 for ( i = 0; i < info->rx_buffer_count; i++ ) {
6550 *((unsigned long *)&(info->rx_buffer_list[i].count)) = DMABUFFERSIZE;
6551 // info->rx_buffer_list[i].count = DMABUFFERSIZE;
6552 // info->rx_buffer_list[i].status = 0;
6555 info->current_rx_buffer = 0;
6557 } /* end of mgsl_reset_rx_dma_buffers() */
6560 * mgsl_free_rx_frame_buffers()
6562 * Free the receive buffers used by a received SDLC
6563 * frame such that the buffers can be reused.
6567 * info pointer to device instance data
6568 * StartIndex index of 1st receive buffer of frame
6569 * EndIndex index of last receive buffer of frame
6571 * Return Value: None
6573 static void mgsl_free_rx_frame_buffers( struct mgsl_struct *info, unsigned int StartIndex, unsigned int EndIndex )
6576 DMABUFFERENTRY *pBufEntry;
6579 /* Starting with 1st buffer entry of the frame clear the status */
6580 /* field and set the count field to DMA Buffer Size. */
6585 pBufEntry = &(info->rx_buffer_list[Index]);
6587 if ( Index == EndIndex ) {
6588 /* This is the last buffer of the frame! */
6592 /* reset current buffer for reuse */
6593 // pBufEntry->status = 0;
6594 // pBufEntry->count = DMABUFFERSIZE;
6595 *((unsigned long *)&(pBufEntry->count)) = DMABUFFERSIZE;
6597 /* advance to next buffer entry in linked list */
6599 if ( Index == info->rx_buffer_count )
6603 /* set current buffer to next buffer after last buffer of frame */
6604 info->current_rx_buffer = Index;
6606 } /* end of free_rx_frame_buffers() */
6608 /* mgsl_get_rx_frame()
6610 * This function attempts to return a received SDLC frame from the
6611 * receive DMA buffers. Only frames received without errors are returned.
6613 * Arguments: info pointer to device extension
6614 * Return Value: 1 if frame returned, otherwise 0
6616 static int mgsl_get_rx_frame(struct mgsl_struct *info)
6618 unsigned int StartIndex, EndIndex; /* index of 1st and last buffers of Rx frame */
6619 unsigned short status;
6620 DMABUFFERENTRY *pBufEntry;
6621 unsigned int framesize = 0;
6623 unsigned long flags;
6624 struct tty_struct *tty = info->tty;
6625 int return_frame = 0;
6628 * current_rx_buffer points to the 1st buffer of the next available
6629 * receive frame. To find the last buffer of the frame look for
6630 * a non-zero status field in the buffer entries. (The status
6631 * field is set by the 16C32 after completing a receive frame.
6634 StartIndex = EndIndex = info->current_rx_buffer;
6636 while( !info->rx_buffer_list[EndIndex].status ) {
6638 * If the count field of the buffer entry is non-zero then
6639 * this buffer has not been used. (The 16C32 clears the count
6640 * field when it starts using the buffer.) If an unused buffer
6641 * is encountered then there are no frames available.
6644 if ( info->rx_buffer_list[EndIndex].count )
6647 /* advance to next buffer entry in linked list */
6649 if ( EndIndex == info->rx_buffer_count )
6652 /* if entire list searched then no frame available */
6653 if ( EndIndex == StartIndex ) {
6654 /* If this occurs then something bad happened,
6655 * all buffers have been 'used' but none mark
6656 * the end of a frame. Reset buffers and receiver.
6659 if ( info->rx_enabled ){
6660 spin_lock_irqsave(&info->irq_spinlock,flags);
6661 usc_start_receiver(info);
6662 spin_unlock_irqrestore(&info->irq_spinlock,flags);
6669 /* check status of receive frame */
6671 status = info->rx_buffer_list[EndIndex].status;
6673 if ( status & (RXSTATUS_SHORT_FRAME + RXSTATUS_OVERRUN +
6674 RXSTATUS_CRC_ERROR + RXSTATUS_ABORT) ) {
6675 if ( status & RXSTATUS_SHORT_FRAME )
6676 info->icount.rxshort++;
6677 else if ( status & RXSTATUS_ABORT )
6678 info->icount.rxabort++;
6679 else if ( status & RXSTATUS_OVERRUN )
6680 info->icount.rxover++;
6682 info->icount.rxcrc++;
6683 if ( info->params.crc_type & HDLC_CRC_RETURN_EX )
6689 struct net_device_stats *stats = hdlc_stats(info->netdev);
6691 stats->rx_frame_errors++;
6697 if ( return_frame ) {
6698 /* receive frame has no errors, get frame size.
6699 * The frame size is the starting value of the RCC (which was
6700 * set to 0xffff) minus the ending value of the RCC (decremented
6701 * once for each receive character) minus 2 for the 16-bit CRC.
6704 framesize = RCLRVALUE - info->rx_buffer_list[EndIndex].rcc;
6706 /* adjust frame size for CRC if any */
6707 if ( info->params.crc_type == HDLC_CRC_16_CCITT )
6709 else if ( info->params.crc_type == HDLC_CRC_32_CCITT )
6713 if ( debug_level >= DEBUG_LEVEL_BH )
6714 printk("%s(%d):mgsl_get_rx_frame(%s) status=%04X size=%d\n",
6715 __FILE__,__LINE__,info->device_name,status,framesize);
6717 if ( debug_level >= DEBUG_LEVEL_DATA )
6718 mgsl_trace_block(info,info->rx_buffer_list[StartIndex].virt_addr,
6719 min_t(int, framesize, DMABUFFERSIZE),0);
6722 if ( ( (info->params.crc_type & HDLC_CRC_RETURN_EX) &&
6723 ((framesize+1) > info->max_frame_size) ) ||
6724 (framesize > info->max_frame_size) )
6725 info->icount.rxlong++;
6727 /* copy dma buffer(s) to contiguous intermediate buffer */
6728 int copy_count = framesize;
6729 int index = StartIndex;
6730 unsigned char *ptmp = info->intermediate_rxbuffer;
6732 if ( !(status & RXSTATUS_CRC_ERROR))
6733 info->icount.rxok++;
6737 if ( copy_count > DMABUFFERSIZE )
6738 partial_count = DMABUFFERSIZE;
6740 partial_count = copy_count;
6742 pBufEntry = &(info->rx_buffer_list[index]);
6743 memcpy( ptmp, pBufEntry->virt_addr, partial_count );
6744 ptmp += partial_count;
6745 copy_count -= partial_count;
6747 if ( ++index == info->rx_buffer_count )
6751 if ( info->params.crc_type & HDLC_CRC_RETURN_EX ) {
6753 *ptmp = (status & RXSTATUS_CRC_ERROR ?
6757 if ( debug_level >= DEBUG_LEVEL_DATA )
6758 printk("%s(%d):mgsl_get_rx_frame(%s) rx frame status=%d\n",
6759 __FILE__,__LINE__,info->device_name,
6765 hdlcdev_rx(info,info->intermediate_rxbuffer,framesize);
6768 ldisc_receive_buf(tty, info->intermediate_rxbuffer, info->flag_buf, framesize);
6771 /* Free the buffers used by this frame. */
6772 mgsl_free_rx_frame_buffers( info, StartIndex, EndIndex );
6778 if ( info->rx_enabled && info->rx_overflow ) {
6779 /* The receiver needs to restarted because of
6780 * a receive overflow (buffer or FIFO). If the
6781 * receive buffers are now empty, then restart receiver.
6784 if ( !info->rx_buffer_list[EndIndex].status &&
6785 info->rx_buffer_list[EndIndex].count ) {
6786 spin_lock_irqsave(&info->irq_spinlock,flags);
6787 usc_start_receiver(info);
6788 spin_unlock_irqrestore(&info->irq_spinlock,flags);
6794 } /* end of mgsl_get_rx_frame() */
6796 /* mgsl_get_raw_rx_frame()
6798 * This function attempts to return a received frame from the
6799 * receive DMA buffers when running in external loop mode. In this mode,
6800 * we will return at most one DMABUFFERSIZE frame to the application.
6801 * The USC receiver is triggering off of DCD going active to start a new
6802 * frame, and DCD going inactive to terminate the frame (similar to
6803 * processing a closing flag character).
6805 * In this routine, we will return DMABUFFERSIZE "chunks" at a time.
6806 * If DCD goes inactive, the last Rx DMA Buffer will have a non-zero
6807 * status field and the RCC field will indicate the length of the
6808 * entire received frame. We take this RCC field and get the modulus
6809 * of RCC and DMABUFFERSIZE to determine if number of bytes in the
6810 * last Rx DMA buffer and return that last portion of the frame.
6812 * Arguments: info pointer to device extension
6813 * Return Value: 1 if frame returned, otherwise 0
6815 static int mgsl_get_raw_rx_frame(struct mgsl_struct *info)
6817 unsigned int CurrentIndex, NextIndex;
6818 unsigned short status;
6819 DMABUFFERENTRY *pBufEntry;
6820 unsigned int framesize = 0;
6822 unsigned long flags;
6823 struct tty_struct *tty = info->tty;
6826 * current_rx_buffer points to the 1st buffer of the next available
6827 * receive frame. The status field is set by the 16C32 after
6828 * completing a receive frame. If the status field of this buffer
6829 * is zero, either the USC is still filling this buffer or this
6830 * is one of a series of buffers making up a received frame.
6832 * If the count field of this buffer is zero, the USC is either
6833 * using this buffer or has used this buffer. Look at the count
6834 * field of the next buffer. If that next buffer's count is
6835 * non-zero, the USC is still actively using the current buffer.
6836 * Otherwise, if the next buffer's count field is zero, the
6837 * current buffer is complete and the USC is using the next
6840 CurrentIndex = NextIndex = info->current_rx_buffer;
6842 if ( NextIndex == info->rx_buffer_count )
6845 if ( info->rx_buffer_list[CurrentIndex].status != 0 ||
6846 (info->rx_buffer_list[CurrentIndex].count == 0 &&
6847 info->rx_buffer_list[NextIndex].count == 0)) {
6849 * Either the status field of this dma buffer is non-zero
6850 * (indicating the last buffer of a receive frame) or the next
6851 * buffer is marked as in use -- implying this buffer is complete
6852 * and an intermediate buffer for this received frame.
6855 status = info->rx_buffer_list[CurrentIndex].status;
6857 if ( status & (RXSTATUS_SHORT_FRAME + RXSTATUS_OVERRUN +
6858 RXSTATUS_CRC_ERROR + RXSTATUS_ABORT) ) {
6859 if ( status & RXSTATUS_SHORT_FRAME )
6860 info->icount.rxshort++;
6861 else if ( status & RXSTATUS_ABORT )
6862 info->icount.rxabort++;
6863 else if ( status & RXSTATUS_OVERRUN )
6864 info->icount.rxover++;
6866 info->icount.rxcrc++;
6870 * A receive frame is available, get frame size and status.
6872 * The frame size is the starting value of the RCC (which was
6873 * set to 0xffff) minus the ending value of the RCC (decremented
6874 * once for each receive character) minus 2 or 4 for the 16-bit
6877 * If the status field is zero, this is an intermediate buffer.
6880 * If the DMA Buffer Entry's Status field is non-zero, the
6881 * receive operation completed normally (ie: DCD dropped). The
6882 * RCC field is valid and holds the received frame size.
6883 * It is possible that the RCC field will be zero on a DMA buffer
6884 * entry with a non-zero status. This can occur if the total
6885 * frame size (number of bytes between the time DCD goes active
6886 * to the time DCD goes inactive) exceeds 65535 bytes. In this
6887 * case the 16C32 has underrun on the RCC count and appears to
6888 * stop updating this counter to let us know the actual received
6889 * frame size. If this happens (non-zero status and zero RCC),
6890 * simply return the entire RxDMA Buffer
6894 * In the event that the final RxDMA Buffer is
6895 * terminated with a non-zero status and the RCC
6896 * field is zero, we interpret this as the RCC
6897 * having underflowed (received frame > 65535 bytes).
6899 * Signal the event to the user by passing back
6900 * a status of RxStatus_CrcError returning the full
6901 * buffer and let the app figure out what data is
6904 if ( info->rx_buffer_list[CurrentIndex].rcc )
6905 framesize = RCLRVALUE - info->rx_buffer_list[CurrentIndex].rcc;
6907 framesize = DMABUFFERSIZE;
6910 framesize = DMABUFFERSIZE;
6913 if ( framesize > DMABUFFERSIZE ) {
6915 * if running in raw sync mode, ISR handler for
6916 * End Of Buffer events terminates all buffers at 4K.
6917 * If this frame size is said to be >4K, get the
6918 * actual number of bytes of the frame in this buffer.
6920 framesize = framesize % DMABUFFERSIZE;
6924 if ( debug_level >= DEBUG_LEVEL_BH )
6925 printk("%s(%d):mgsl_get_raw_rx_frame(%s) status=%04X size=%d\n",
6926 __FILE__,__LINE__,info->device_name,status,framesize);
6928 if ( debug_level >= DEBUG_LEVEL_DATA )
6929 mgsl_trace_block(info,info->rx_buffer_list[CurrentIndex].virt_addr,
6930 min_t(int, framesize, DMABUFFERSIZE),0);
6933 /* copy dma buffer(s) to contiguous intermediate buffer */
6934 /* NOTE: we never copy more than DMABUFFERSIZE bytes */
6936 pBufEntry = &(info->rx_buffer_list[CurrentIndex]);
6937 memcpy( info->intermediate_rxbuffer, pBufEntry->virt_addr, framesize);
6938 info->icount.rxok++;
6940 ldisc_receive_buf(tty, info->intermediate_rxbuffer, info->flag_buf, framesize);
6943 /* Free the buffers used by this frame. */
6944 mgsl_free_rx_frame_buffers( info, CurrentIndex, CurrentIndex );
6950 if ( info->rx_enabled && info->rx_overflow ) {
6951 /* The receiver needs to restarted because of
6952 * a receive overflow (buffer or FIFO). If the
6953 * receive buffers are now empty, then restart receiver.
6956 if ( !info->rx_buffer_list[CurrentIndex].status &&
6957 info->rx_buffer_list[CurrentIndex].count ) {
6958 spin_lock_irqsave(&info->irq_spinlock,flags);
6959 usc_start_receiver(info);
6960 spin_unlock_irqrestore(&info->irq_spinlock,flags);
6966 } /* end of mgsl_get_raw_rx_frame() */
6968 /* mgsl_load_tx_dma_buffer()
6970 * Load the transmit DMA buffer with the specified data.
6974 * info pointer to device extension
6975 * Buffer pointer to buffer containing frame to load
6976 * BufferSize size in bytes of frame in Buffer
6978 * Return Value: None
6980 static void mgsl_load_tx_dma_buffer(struct mgsl_struct *info,
6981 const char *Buffer, unsigned int BufferSize)
6983 unsigned short Copycount;
6985 DMABUFFERENTRY *pBufEntry;
6987 if ( debug_level >= DEBUG_LEVEL_DATA )
6988 mgsl_trace_block(info,Buffer, min_t(int, BufferSize, DMABUFFERSIZE), 1);
6990 if (info->params.flags & HDLC_FLAG_HDLC_LOOPMODE) {
6991 /* set CMR:13 to start transmit when
6992 * next GoAhead (abort) is received
6994 info->cmr_value |= BIT13;
6997 /* begin loading the frame in the next available tx dma
6998 * buffer, remember it's starting location for setting
6999 * up tx dma operation
7001 i = info->current_tx_buffer;
7002 info->start_tx_dma_buffer = i;
7004 /* Setup the status and RCC (Frame Size) fields of the 1st */
7005 /* buffer entry in the transmit DMA buffer list. */
7007 info->tx_buffer_list[i].status = info->cmr_value & 0xf000;
7008 info->tx_buffer_list[i].rcc = BufferSize;
7009 info->tx_buffer_list[i].count = BufferSize;
7011 /* Copy frame data from 1st source buffer to the DMA buffers. */
7012 /* The frame data may span multiple DMA buffers. */
7014 while( BufferSize ){
7015 /* Get a pointer to next DMA buffer entry. */
7016 pBufEntry = &info->tx_buffer_list[i++];
7018 if ( i == info->tx_buffer_count )
7021 /* Calculate the number of bytes that can be copied from */
7022 /* the source buffer to this DMA buffer. */
7023 if ( BufferSize > DMABUFFERSIZE )
7024 Copycount = DMABUFFERSIZE;
7026 Copycount = BufferSize;
7028 /* Actually copy data from source buffer to DMA buffer. */
7029 /* Also set the data count for this individual DMA buffer. */
7030 if ( info->bus_type == MGSL_BUS_TYPE_PCI )
7031 mgsl_load_pci_memory(pBufEntry->virt_addr, Buffer,Copycount);
7033 memcpy(pBufEntry->virt_addr, Buffer, Copycount);
7035 pBufEntry->count = Copycount;
7037 /* Advance source pointer and reduce remaining data count. */
7038 Buffer += Copycount;
7039 BufferSize -= Copycount;
7041 ++info->tx_dma_buffers_used;
7044 /* remember next available tx dma buffer */
7045 info->current_tx_buffer = i;
7047 } /* end of mgsl_load_tx_dma_buffer() */
7050 * mgsl_register_test()
7052 * Performs a register test of the 16C32.
7054 * Arguments: info pointer to device instance data
7055 * Return Value: TRUE if test passed, otherwise FALSE
7057 static BOOLEAN mgsl_register_test( struct mgsl_struct *info )
7059 static unsigned short BitPatterns[] =
7060 { 0x0000, 0xffff, 0xaaaa, 0x5555, 0x1234, 0x6969, 0x9696, 0x0f0f };
7061 static unsigned int Patterncount = sizeof(BitPatterns)/sizeof(unsigned short);
7064 unsigned long flags;
7066 spin_lock_irqsave(&info->irq_spinlock,flags);
7069 /* Verify the reset state of some registers. */
7071 if ( (usc_InReg( info, SICR ) != 0) ||
7072 (usc_InReg( info, IVR ) != 0) ||
7073 (usc_InDmaReg( info, DIVR ) != 0) ){
7078 /* Write bit patterns to various registers but do it out of */
7079 /* sync, then read back and verify values. */
7081 for ( i = 0 ; i < Patterncount ; i++ ) {
7082 usc_OutReg( info, TC0R, BitPatterns[i] );
7083 usc_OutReg( info, TC1R, BitPatterns[(i+1)%Patterncount] );
7084 usc_OutReg( info, TCLR, BitPatterns[(i+2)%Patterncount] );
7085 usc_OutReg( info, RCLR, BitPatterns[(i+3)%Patterncount] );
7086 usc_OutReg( info, RSR, BitPatterns[(i+4)%Patterncount] );
7087 usc_OutDmaReg( info, TBCR, BitPatterns[(i+5)%Patterncount] );
7089 if ( (usc_InReg( info, TC0R ) != BitPatterns[i]) ||
7090 (usc_InReg( info, TC1R ) != BitPatterns[(i+1)%Patterncount]) ||
7091 (usc_InReg( info, TCLR ) != BitPatterns[(i+2)%Patterncount]) ||
7092 (usc_InReg( info, RCLR ) != BitPatterns[(i+3)%Patterncount]) ||
7093 (usc_InReg( info, RSR ) != BitPatterns[(i+4)%Patterncount]) ||
7094 (usc_InDmaReg( info, TBCR ) != BitPatterns[(i+5)%Patterncount]) ){
7102 spin_unlock_irqrestore(&info->irq_spinlock,flags);
7106 } /* end of mgsl_register_test() */
7108 /* mgsl_irq_test() Perform interrupt test of the 16C32.
7110 * Arguments: info pointer to device instance data
7111 * Return Value: TRUE if test passed, otherwise FALSE
7113 static BOOLEAN mgsl_irq_test( struct mgsl_struct *info )
7115 unsigned long EndTime;
7116 unsigned long flags;
7118 spin_lock_irqsave(&info->irq_spinlock,flags);
7122 * Setup 16C32 to interrupt on TxC pin (14MHz clock) transition.
7123 * The ISR sets irq_occurred to 1.
7126 info->irq_occurred = FALSE;
7128 /* Enable INTEN gate for ISA adapter (Port 6, Bit12) */
7129 /* Enable INTEN (Port 6, Bit12) */
7130 /* This connects the IRQ request signal to the ISA bus */
7131 /* on the ISA adapter. This has no effect for the PCI adapter */
7132 usc_OutReg( info, PCR, (unsigned short)((usc_InReg(info, PCR) | BIT13) & ~BIT12) );
7134 usc_EnableMasterIrqBit(info);
7135 usc_EnableInterrupts(info, IO_PIN);
7136 usc_ClearIrqPendingBits(info, IO_PIN);
7138 usc_UnlatchIostatusBits(info, MISCSTATUS_TXC_LATCHED);
7139 usc_EnableStatusIrqs(info, SICR_TXC_ACTIVE + SICR_TXC_INACTIVE);
7141 spin_unlock_irqrestore(&info->irq_spinlock,flags);
7144 while( EndTime-- && !info->irq_occurred ) {
7145 msleep_interruptible(10);
7148 spin_lock_irqsave(&info->irq_spinlock,flags);
7150 spin_unlock_irqrestore(&info->irq_spinlock,flags);
7152 if ( !info->irq_occurred )
7157 } /* end of mgsl_irq_test() */
7161 * Perform a DMA test of the 16C32. A small frame is
7162 * transmitted via DMA from a transmit buffer to a receive buffer
7163 * using single buffer DMA mode.
7165 * Arguments: info pointer to device instance data
7166 * Return Value: TRUE if test passed, otherwise FALSE
7168 static BOOLEAN mgsl_dma_test( struct mgsl_struct *info )
7170 unsigned short FifoLevel;
7171 unsigned long phys_addr;
7172 unsigned int FrameSize;
7176 unsigned short status=0;
7177 unsigned long EndTime;
7178 unsigned long flags;
7179 MGSL_PARAMS tmp_params;
7181 /* save current port options */
7182 memcpy(&tmp_params,&info->params,sizeof(MGSL_PARAMS));
7183 /* load default port options */
7184 memcpy(&info->params,&default_params,sizeof(MGSL_PARAMS));
7186 #define TESTFRAMESIZE 40
7188 spin_lock_irqsave(&info->irq_spinlock,flags);
7190 /* setup 16C32 for SDLC DMA transfer mode */
7193 usc_set_sdlc_mode(info);
7194 usc_enable_loopback(info,1);
7196 /* Reprogram the RDMR so that the 16C32 does NOT clear the count
7197 * field of the buffer entry after fetching buffer address. This
7198 * way we can detect a DMA failure for a DMA read (which should be
7199 * non-destructive to system memory) before we try and write to
7200 * memory (where a failure could corrupt system memory).
7203 /* Receive DMA mode Register (RDMR)
7205 * <15..14> 11 DMA mode = Linked List Buffer mode
7206 * <13> 1 RSBinA/L = store Rx status Block in List entry
7207 * <12> 0 1 = Clear count of List Entry after fetching
7208 * <11..10> 00 Address mode = Increment
7209 * <9> 1 Terminate Buffer on RxBound
7210 * <8> 0 Bus Width = 16bits
7211 * <7..0> ? status Bits (write as 0s)
7213 * 1110 0010 0000 0000 = 0xe200
7216 usc_OutDmaReg( info, RDMR, 0xe200 );
7218 spin_unlock_irqrestore(&info->irq_spinlock,flags);
7221 /* SETUP TRANSMIT AND RECEIVE DMA BUFFERS */
7223 FrameSize = TESTFRAMESIZE;
7225 /* setup 1st transmit buffer entry: */
7226 /* with frame size and transmit control word */
7228 info->tx_buffer_list[0].count = FrameSize;
7229 info->tx_buffer_list[0].rcc = FrameSize;
7230 info->tx_buffer_list[0].status = 0x4000;
7232 /* build a transmit frame in 1st transmit DMA buffer */
7234 TmpPtr = info->tx_buffer_list[0].virt_addr;
7235 for (i = 0; i < FrameSize; i++ )
7238 /* setup 1st receive buffer entry: */
7239 /* clear status, set max receive buffer size */
7241 info->rx_buffer_list[0].status = 0;
7242 info->rx_buffer_list[0].count = FrameSize + 4;
7244 /* zero out the 1st receive buffer */
7246 memset( info->rx_buffer_list[0].virt_addr, 0, FrameSize + 4 );
7248 /* Set count field of next buffer entries to prevent */
7249 /* 16C32 from using buffers after the 1st one. */
7251 info->tx_buffer_list[1].count = 0;
7252 info->rx_buffer_list[1].count = 0;
7255 /***************************/
7256 /* Program 16C32 receiver. */
7257 /***************************/
7259 spin_lock_irqsave(&info->irq_spinlock,flags);
7261 /* setup DMA transfers */
7262 usc_RTCmd( info, RTCmd_PurgeRxFifo );
7264 /* program 16C32 receiver with physical address of 1st DMA buffer entry */
7265 phys_addr = info->rx_buffer_list[0].phys_entry;
7266 usc_OutDmaReg( info, NRARL, (unsigned short)phys_addr );
7267 usc_OutDmaReg( info, NRARU, (unsigned short)(phys_addr >> 16) );
7269 /* Clear the Rx DMA status bits (read RDMR) and start channel */
7270 usc_InDmaReg( info, RDMR );
7271 usc_DmaCmd( info, DmaCmd_InitRxChannel );
7273 /* Enable Receiver (RMR <1..0> = 10) */
7274 usc_OutReg( info, RMR, (unsigned short)((usc_InReg(info, RMR) & 0xfffc) | 0x0002) );
7276 spin_unlock_irqrestore(&info->irq_spinlock,flags);
7279 /*************************************************************/
7280 /* WAIT FOR RECEIVER TO DMA ALL PARAMETERS FROM BUFFER ENTRY */
7281 /*************************************************************/
7283 /* Wait 100ms for interrupt. */
7284 EndTime = jiffies + msecs_to_jiffies(100);
7287 if (time_after(jiffies, EndTime)) {
7292 spin_lock_irqsave(&info->irq_spinlock,flags);
7293 status = usc_InDmaReg( info, RDMR );
7294 spin_unlock_irqrestore(&info->irq_spinlock,flags);
7296 if ( !(status & BIT4) && (status & BIT5) ) {
7297 /* INITG (BIT 4) is inactive (no entry read in progress) AND */
7298 /* BUSY (BIT 5) is active (channel still active). */
7299 /* This means the buffer entry read has completed. */
7305 /******************************/
7306 /* Program 16C32 transmitter. */
7307 /******************************/
7309 spin_lock_irqsave(&info->irq_spinlock,flags);
7311 /* Program the Transmit Character Length Register (TCLR) */
7312 /* and clear FIFO (TCC is loaded with TCLR on FIFO clear) */
7314 usc_OutReg( info, TCLR, (unsigned short)info->tx_buffer_list[0].count );
7315 usc_RTCmd( info, RTCmd_PurgeTxFifo );
7317 /* Program the address of the 1st DMA Buffer Entry in linked list */
7319 phys_addr = info->tx_buffer_list[0].phys_entry;
7320 usc_OutDmaReg( info, NTARL, (unsigned short)phys_addr );
7321 usc_OutDmaReg( info, NTARU, (unsigned short)(phys_addr >> 16) );
7323 /* unlatch Tx status bits, and start transmit channel. */
7325 usc_OutReg( info, TCSR, (unsigned short)(( usc_InReg(info, TCSR) & 0x0f00) | 0xfa) );
7326 usc_DmaCmd( info, DmaCmd_InitTxChannel );
7328 /* wait for DMA controller to fill transmit FIFO */
7330 usc_TCmd( info, TCmd_SelectTicrTxFifostatus );
7332 spin_unlock_irqrestore(&info->irq_spinlock,flags);
7335 /**********************************/
7336 /* WAIT FOR TRANSMIT FIFO TO FILL */
7337 /**********************************/
7340 EndTime = jiffies + msecs_to_jiffies(100);
7343 if (time_after(jiffies, EndTime)) {
7348 spin_lock_irqsave(&info->irq_spinlock,flags);
7349 FifoLevel = usc_InReg(info, TICR) >> 8;
7350 spin_unlock_irqrestore(&info->irq_spinlock,flags);
7352 if ( FifoLevel < 16 )
7355 if ( FrameSize < 32 ) {
7356 /* This frame is smaller than the entire transmit FIFO */
7357 /* so wait for the entire frame to be loaded. */
7358 if ( FifoLevel <= (32 - FrameSize) )
7366 /* Enable 16C32 transmitter. */
7368 spin_lock_irqsave(&info->irq_spinlock,flags);
7370 /* Transmit mode Register (TMR), <1..0> = 10, Enable Transmitter */
7371 usc_TCmd( info, TCmd_SendFrame );
7372 usc_OutReg( info, TMR, (unsigned short)((usc_InReg(info, TMR) & 0xfffc) | 0x0002) );
7374 spin_unlock_irqrestore(&info->irq_spinlock,flags);
7377 /******************************/
7378 /* WAIT FOR TRANSMIT COMPLETE */
7379 /******************************/
7382 EndTime = jiffies + msecs_to_jiffies(100);
7384 /* While timer not expired wait for transmit complete */
7386 spin_lock_irqsave(&info->irq_spinlock,flags);
7387 status = usc_InReg( info, TCSR );
7388 spin_unlock_irqrestore(&info->irq_spinlock,flags);
7390 while ( !(status & (BIT6+BIT5+BIT4+BIT2+BIT1)) ) {
7391 if (time_after(jiffies, EndTime)) {
7396 spin_lock_irqsave(&info->irq_spinlock,flags);
7397 status = usc_InReg( info, TCSR );
7398 spin_unlock_irqrestore(&info->irq_spinlock,flags);
7404 /* CHECK FOR TRANSMIT ERRORS */
7405 if ( status & (BIT5 + BIT1) )
7410 /* WAIT FOR RECEIVE COMPLETE */
7413 EndTime = jiffies + msecs_to_jiffies(100);
7415 /* Wait for 16C32 to write receive status to buffer entry. */
7416 status=info->rx_buffer_list[0].status;
7417 while ( status == 0 ) {
7418 if (time_after(jiffies, EndTime)) {
7422 status=info->rx_buffer_list[0].status;
7428 /* CHECK FOR RECEIVE ERRORS */
7429 status = info->rx_buffer_list[0].status;
7431 if ( status & (BIT8 + BIT3 + BIT1) ) {
7432 /* receive error has occurred */
7435 if ( memcmp( info->tx_buffer_list[0].virt_addr ,
7436 info->rx_buffer_list[0].virt_addr, FrameSize ) ){
7442 spin_lock_irqsave(&info->irq_spinlock,flags);
7444 spin_unlock_irqrestore(&info->irq_spinlock,flags);
7446 /* restore current port options */
7447 memcpy(&info->params,&tmp_params,sizeof(MGSL_PARAMS));
7451 } /* end of mgsl_dma_test() */
7453 /* mgsl_adapter_test()
7455 * Perform the register, IRQ, and DMA tests for the 16C32.
7457 * Arguments: info pointer to device instance data
7458 * Return Value: 0 if success, otherwise -ENODEV
7460 static int mgsl_adapter_test( struct mgsl_struct *info )
7462 if ( debug_level >= DEBUG_LEVEL_INFO )
7463 printk( "%s(%d):Testing device %s\n",
7464 __FILE__,__LINE__,info->device_name );
7466 if ( !mgsl_register_test( info ) ) {
7467 info->init_error = DiagStatus_AddressFailure;
7468 printk( "%s(%d):Register test failure for device %s Addr=%04X\n",
7469 __FILE__,__LINE__,info->device_name, (unsigned short)(info->io_base) );
7473 if ( !mgsl_irq_test( info ) ) {
7474 info->init_error = DiagStatus_IrqFailure;
7475 printk( "%s(%d):Interrupt test failure for device %s IRQ=%d\n",
7476 __FILE__,__LINE__,info->device_name, (unsigned short)(info->irq_level) );
7480 if ( !mgsl_dma_test( info ) ) {
7481 info->init_error = DiagStatus_DmaFailure;
7482 printk( "%s(%d):DMA test failure for device %s DMA=%d\n",
7483 __FILE__,__LINE__,info->device_name, (unsigned short)(info->dma_level) );
7487 if ( debug_level >= DEBUG_LEVEL_INFO )
7488 printk( "%s(%d):device %s passed diagnostics\n",
7489 __FILE__,__LINE__,info->device_name );
7493 } /* end of mgsl_adapter_test() */
7495 /* mgsl_memory_test()
7497 * Test the shared memory on a PCI adapter.
7499 * Arguments: info pointer to device instance data
7500 * Return Value: TRUE if test passed, otherwise FALSE
7502 static BOOLEAN mgsl_memory_test( struct mgsl_struct *info )
7504 static unsigned long BitPatterns[] = { 0x0, 0x55555555, 0xaaaaaaaa,
7505 0x66666666, 0x99999999, 0xffffffff, 0x12345678 };
7506 unsigned long Patterncount = sizeof(BitPatterns)/sizeof(unsigned long);
7508 unsigned long TestLimit = SHARED_MEM_ADDRESS_SIZE/sizeof(unsigned long);
7509 unsigned long * TestAddr;
7511 if ( info->bus_type != MGSL_BUS_TYPE_PCI )
7514 TestAddr = (unsigned long *)info->memory_base;
7516 /* Test data lines with test pattern at one location. */
7518 for ( i = 0 ; i < Patterncount ; i++ ) {
7519 *TestAddr = BitPatterns[i];
7520 if ( *TestAddr != BitPatterns[i] )
7524 /* Test address lines with incrementing pattern over */
7525 /* entire address range. */
7527 for ( i = 0 ; i < TestLimit ; i++ ) {
7532 TestAddr = (unsigned long *)info->memory_base;
7534 for ( i = 0 ; i < TestLimit ; i++ ) {
7535 if ( *TestAddr != i * 4 )
7540 memset( info->memory_base, 0, SHARED_MEM_ADDRESS_SIZE );
7544 } /* End Of mgsl_memory_test() */
7547 /* mgsl_load_pci_memory()
7549 * Load a large block of data into the PCI shared memory.
7550 * Use this instead of memcpy() or memmove() to move data
7551 * into the PCI shared memory.
7555 * This function prevents the PCI9050 interface chip from hogging
7556 * the adapter local bus, which can starve the 16C32 by preventing
7557 * 16C32 bus master cycles.
7559 * The PCI9050 documentation says that the 9050 will always release
7560 * control of the local bus after completing the current read
7561 * or write operation.
7563 * It appears that as long as the PCI9050 write FIFO is full, the
7564 * PCI9050 treats all of the writes as a single burst transaction
7565 * and will not release the bus. This causes DMA latency problems
7566 * at high speeds when copying large data blocks to the shared
7569 * This function in effect, breaks the a large shared memory write
7570 * into multiple transations by interleaving a shared memory read
7571 * which will flush the write FIFO and 'complete' the write
7572 * transation. This allows any pending DMA request to gain control
7573 * of the local bus in a timely fasion.
7577 * TargetPtr pointer to target address in PCI shared memory
7578 * SourcePtr pointer to source buffer for data
7579 * count count in bytes of data to copy
7581 * Return Value: None
7583 static void mgsl_load_pci_memory( char* TargetPtr, const char* SourcePtr,
7584 unsigned short count )
7586 /* 16 32-bit writes @ 60ns each = 960ns max latency on local bus */
7587 #define PCI_LOAD_INTERVAL 64
7589 unsigned short Intervalcount = count / PCI_LOAD_INTERVAL;
7590 unsigned short Index;
7591 unsigned long Dummy;
7593 for ( Index = 0 ; Index < Intervalcount ; Index++ )
7595 memcpy(TargetPtr, SourcePtr, PCI_LOAD_INTERVAL);
7596 Dummy = *((volatile unsigned long *)TargetPtr);
7597 TargetPtr += PCI_LOAD_INTERVAL;
7598 SourcePtr += PCI_LOAD_INTERVAL;
7601 memcpy( TargetPtr, SourcePtr, count % PCI_LOAD_INTERVAL );
7603 } /* End Of mgsl_load_pci_memory() */
7605 static void mgsl_trace_block(struct mgsl_struct *info,const char* data, int count, int xmit)
7610 printk("%s tx data:\n",info->device_name);
7612 printk("%s rx data:\n",info->device_name);
7620 for(i=0;i<linecount;i++)
7621 printk("%02X ",(unsigned char)data[i]);
7624 for(i=0;i<linecount;i++) {
7625 if (data[i]>=040 && data[i]<=0176)
7626 printk("%c",data[i]);
7635 } /* end of mgsl_trace_block() */
7637 /* mgsl_tx_timeout()
7639 * called when HDLC frame times out
7640 * update stats and do tx completion processing
7642 * Arguments: context pointer to device instance data
7643 * Return Value: None
7645 static void mgsl_tx_timeout(unsigned long context)
7647 struct mgsl_struct *info = (struct mgsl_struct*)context;
7648 unsigned long flags;
7650 if ( debug_level >= DEBUG_LEVEL_INFO )
7651 printk( "%s(%d):mgsl_tx_timeout(%s)\n",
7652 __FILE__,__LINE__,info->device_name);
7653 if(info->tx_active &&
7654 (info->params.mode == MGSL_MODE_HDLC ||
7655 info->params.mode == MGSL_MODE_RAW) ) {
7656 info->icount.txtimeout++;
7658 spin_lock_irqsave(&info->irq_spinlock,flags);
7659 info->tx_active = 0;
7660 info->xmit_cnt = info->xmit_head = info->xmit_tail = 0;
7662 if ( info->params.flags & HDLC_FLAG_HDLC_LOOPMODE )
7663 usc_loopmode_cancel_transmit( info );
7665 spin_unlock_irqrestore(&info->irq_spinlock,flags);
7669 hdlcdev_tx_done(info);
7672 mgsl_bh_transmit(info);
7674 } /* end of mgsl_tx_timeout() */
7676 /* signal that there are no more frames to send, so that
7677 * line is 'released' by echoing RxD to TxD when current
7678 * transmission is complete (or immediately if no tx in progress).
7680 static int mgsl_loopmode_send_done( struct mgsl_struct * info )
7682 unsigned long flags;
7684 spin_lock_irqsave(&info->irq_spinlock,flags);
7685 if (info->params.flags & HDLC_FLAG_HDLC_LOOPMODE) {
7686 if (info->tx_active)
7687 info->loopmode_send_done_requested = TRUE;
7689 usc_loopmode_send_done(info);
7691 spin_unlock_irqrestore(&info->irq_spinlock,flags);
7696 /* release the line by echoing RxD to TxD
7697 * upon completion of a transmit frame
7699 static void usc_loopmode_send_done( struct mgsl_struct * info )
7701 info->loopmode_send_done_requested = FALSE;
7702 /* clear CMR:13 to 0 to start echoing RxData to TxData */
7703 info->cmr_value &= ~BIT13;
7704 usc_OutReg(info, CMR, info->cmr_value);
7707 /* abort a transmit in progress while in HDLC LoopMode
7709 static void usc_loopmode_cancel_transmit( struct mgsl_struct * info )
7711 /* reset tx dma channel and purge TxFifo */
7712 usc_RTCmd( info, RTCmd_PurgeTxFifo );
7713 usc_DmaCmd( info, DmaCmd_ResetTxChannel );
7714 usc_loopmode_send_done( info );
7717 /* for HDLC/SDLC LoopMode, setting CMR:13 after the transmitter is enabled
7718 * is an Insert Into Loop action. Upon receipt of a GoAhead sequence (RxAbort)
7719 * we must clear CMR:13 to begin repeating TxData to RxData
7721 static void usc_loopmode_insert_request( struct mgsl_struct * info )
7723 info->loopmode_insert_requested = TRUE;
7725 /* enable RxAbort irq. On next RxAbort, clear CMR:13 to
7726 * begin repeating TxData on RxData (complete insertion)
7728 usc_OutReg( info, RICR,
7729 (usc_InReg( info, RICR ) | RXSTATUS_ABORT_RECEIVED ) );
7731 /* set CMR:13 to insert into loop on next GoAhead (RxAbort) */
7732 info->cmr_value |= BIT13;
7733 usc_OutReg(info, CMR, info->cmr_value);
7736 /* return 1 if station is inserted into the loop, otherwise 0
7738 static int usc_loopmode_active( struct mgsl_struct * info)
7740 return usc_InReg( info, CCSR ) & BIT7 ? 1 : 0 ;
7746 * called by generic HDLC layer when protocol selected (PPP, frame relay, etc.)
7747 * set encoding and frame check sequence (FCS) options
7749 * dev pointer to network device structure
7750 * encoding serial encoding setting
7751 * parity FCS setting
7753 * returns 0 if success, otherwise error code
7755 static int hdlcdev_attach(struct net_device *dev, unsigned short encoding,
7756 unsigned short parity)
7758 struct mgsl_struct *info = dev_to_port(dev);
7759 unsigned char new_encoding;
7760 unsigned short new_crctype;
7762 /* return error if TTY interface open */
7768 case ENCODING_NRZ: new_encoding = HDLC_ENCODING_NRZ; break;
7769 case ENCODING_NRZI: new_encoding = HDLC_ENCODING_NRZI_SPACE; break;
7770 case ENCODING_FM_MARK: new_encoding = HDLC_ENCODING_BIPHASE_MARK; break;
7771 case ENCODING_FM_SPACE: new_encoding = HDLC_ENCODING_BIPHASE_SPACE; break;
7772 case ENCODING_MANCHESTER: new_encoding = HDLC_ENCODING_BIPHASE_LEVEL; break;
7773 default: return -EINVAL;
7778 case PARITY_NONE: new_crctype = HDLC_CRC_NONE; break;
7779 case PARITY_CRC16_PR1_CCITT: new_crctype = HDLC_CRC_16_CCITT; break;
7780 case PARITY_CRC32_PR1_CCITT: new_crctype = HDLC_CRC_32_CCITT; break;
7781 default: return -EINVAL;
7784 info->params.encoding = new_encoding;
7785 info->params.crc_type = new_crctype;;
7787 /* if network interface up, reprogram hardware */
7789 mgsl_program_hw(info);
7795 * called by generic HDLC layer to send frame
7797 * skb socket buffer containing HDLC frame
7798 * dev pointer to network device structure
7800 * returns 0 if success, otherwise error code
7802 static int hdlcdev_xmit(struct sk_buff *skb, struct net_device *dev)
7804 struct mgsl_struct *info = dev_to_port(dev);
7805 struct net_device_stats *stats = hdlc_stats(dev);
7806 unsigned long flags;
7808 if (debug_level >= DEBUG_LEVEL_INFO)
7809 printk(KERN_INFO "%s:hdlc_xmit(%s)\n",__FILE__,dev->name);
7811 /* stop sending until this frame completes */
7812 netif_stop_queue(dev);
7814 /* copy data to device buffers */
7815 info->xmit_cnt = skb->len;
7816 mgsl_load_tx_dma_buffer(info, skb->data, skb->len);
7818 /* update network statistics */
7819 stats->tx_packets++;
7820 stats->tx_bytes += skb->len;
7822 /* done with socket buffer, so free it */
7825 /* save start time for transmit timeout detection */
7826 dev->trans_start = jiffies;
7828 /* start hardware transmitter if necessary */
7829 spin_lock_irqsave(&info->irq_spinlock,flags);
7830 if (!info->tx_active)
7831 usc_start_transmitter(info);
7832 spin_unlock_irqrestore(&info->irq_spinlock,flags);
7838 * called by network layer when interface enabled
7839 * claim resources and initialize hardware
7841 * dev pointer to network device structure
7843 * returns 0 if success, otherwise error code
7845 static int hdlcdev_open(struct net_device *dev)
7847 struct mgsl_struct *info = dev_to_port(dev);
7849 unsigned long flags;
7851 if (debug_level >= DEBUG_LEVEL_INFO)
7852 printk("%s:hdlcdev_open(%s)\n",__FILE__,dev->name);
7854 /* generic HDLC layer open processing */
7855 if ((rc = hdlc_open(dev)))
7858 /* arbitrate between network and tty opens */
7859 spin_lock_irqsave(&info->netlock, flags);
7860 if (info->count != 0 || info->netcount != 0) {
7861 printk(KERN_WARNING "%s: hdlc_open returning busy\n", dev->name);
7862 spin_unlock_irqrestore(&info->netlock, flags);
7866 spin_unlock_irqrestore(&info->netlock, flags);
7868 /* claim resources and init adapter */
7869 if ((rc = startup(info)) != 0) {
7870 spin_lock_irqsave(&info->netlock, flags);
7872 spin_unlock_irqrestore(&info->netlock, flags);
7876 /* assert DTR and RTS, apply hardware settings */
7877 info->serial_signals |= SerialSignal_RTS + SerialSignal_DTR;
7878 mgsl_program_hw(info);
7880 /* enable network layer transmit */
7881 dev->trans_start = jiffies;
7882 netif_start_queue(dev);
7884 /* inform generic HDLC layer of current DCD status */
7885 spin_lock_irqsave(&info->irq_spinlock, flags);
7886 usc_get_serial_signals(info);
7887 spin_unlock_irqrestore(&info->irq_spinlock, flags);
7888 hdlc_set_carrier(info->serial_signals & SerialSignal_DCD, dev);
7894 * called by network layer when interface is disabled
7895 * shutdown hardware and release resources
7897 * dev pointer to network device structure
7899 * returns 0 if success, otherwise error code
7901 static int hdlcdev_close(struct net_device *dev)
7903 struct mgsl_struct *info = dev_to_port(dev);
7904 unsigned long flags;
7906 if (debug_level >= DEBUG_LEVEL_INFO)
7907 printk("%s:hdlcdev_close(%s)\n",__FILE__,dev->name);
7909 netif_stop_queue(dev);
7911 /* shutdown adapter and release resources */
7916 spin_lock_irqsave(&info->netlock, flags);
7918 spin_unlock_irqrestore(&info->netlock, flags);
7924 * called by network layer to process IOCTL call to network device
7926 * dev pointer to network device structure
7927 * ifr pointer to network interface request structure
7928 * cmd IOCTL command code
7930 * returns 0 if success, otherwise error code
7932 static int hdlcdev_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
7934 const size_t size = sizeof(sync_serial_settings);
7935 sync_serial_settings new_line;
7936 sync_serial_settings __user *line = ifr->ifr_settings.ifs_ifsu.sync;
7937 struct mgsl_struct *info = dev_to_port(dev);
7940 if (debug_level >= DEBUG_LEVEL_INFO)
7941 printk("%s:hdlcdev_ioctl(%s)\n",__FILE__,dev->name);
7943 /* return error if TTY interface open */
7947 if (cmd != SIOCWANDEV)
7948 return hdlc_ioctl(dev, ifr, cmd);
7950 switch(ifr->ifr_settings.type) {
7951 case IF_GET_IFACE: /* return current sync_serial_settings */
7953 ifr->ifr_settings.type = IF_IFACE_SYNC_SERIAL;
7954 if (ifr->ifr_settings.size < size) {
7955 ifr->ifr_settings.size = size; /* data size wanted */
7959 flags = info->params.flags & (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL |
7960 HDLC_FLAG_RXC_BRG | HDLC_FLAG_RXC_TXCPIN |
7961 HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL |
7962 HDLC_FLAG_TXC_BRG | HDLC_FLAG_TXC_RXCPIN);
7965 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_TXCPIN): new_line.clock_type = CLOCK_EXT; break;
7966 case (HDLC_FLAG_RXC_BRG | HDLC_FLAG_TXC_BRG): new_line.clock_type = CLOCK_INT; break;
7967 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_BRG): new_line.clock_type = CLOCK_TXINT; break;
7968 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_RXCPIN): new_line.clock_type = CLOCK_TXFROMRX; break;
7969 default: new_line.clock_type = CLOCK_DEFAULT;
7972 new_line.clock_rate = info->params.clock_speed;
7973 new_line.loopback = info->params.loopback ? 1:0;
7975 if (copy_to_user(line, &new_line, size))
7979 case IF_IFACE_SYNC_SERIAL: /* set sync_serial_settings */
7981 if(!capable(CAP_NET_ADMIN))
7983 if (copy_from_user(&new_line, line, size))
7986 switch (new_line.clock_type)
7988 case CLOCK_EXT: flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_TXCPIN; break;
7989 case CLOCK_TXFROMRX: flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_RXCPIN; break;
7990 case CLOCK_INT: flags = HDLC_FLAG_RXC_BRG | HDLC_FLAG_TXC_BRG; break;
7991 case CLOCK_TXINT: flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_BRG; break;
7992 case CLOCK_DEFAULT: flags = info->params.flags &
7993 (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL |
7994 HDLC_FLAG_RXC_BRG | HDLC_FLAG_RXC_TXCPIN |
7995 HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL |
7996 HDLC_FLAG_TXC_BRG | HDLC_FLAG_TXC_RXCPIN); break;
7997 default: return -EINVAL;
8000 if (new_line.loopback != 0 && new_line.loopback != 1)
8003 info->params.flags &= ~(HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL |
8004 HDLC_FLAG_RXC_BRG | HDLC_FLAG_RXC_TXCPIN |
8005 HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL |
8006 HDLC_FLAG_TXC_BRG | HDLC_FLAG_TXC_RXCPIN);
8007 info->params.flags |= flags;
8009 info->params.loopback = new_line.loopback;
8011 if (flags & (HDLC_FLAG_RXC_BRG | HDLC_FLAG_TXC_BRG))
8012 info->params.clock_speed = new_line.clock_rate;
8014 info->params.clock_speed = 0;
8016 /* if network interface up, reprogram hardware */
8018 mgsl_program_hw(info);
8022 return hdlc_ioctl(dev, ifr, cmd);
8027 * called by network layer when transmit timeout is detected
8029 * dev pointer to network device structure
8031 static void hdlcdev_tx_timeout(struct net_device *dev)
8033 struct mgsl_struct *info = dev_to_port(dev);
8034 struct net_device_stats *stats = hdlc_stats(dev);
8035 unsigned long flags;
8037 if (debug_level >= DEBUG_LEVEL_INFO)
8038 printk("hdlcdev_tx_timeout(%s)\n",dev->name);
8041 stats->tx_aborted_errors++;
8043 spin_lock_irqsave(&info->irq_spinlock,flags);
8044 usc_stop_transmitter(info);
8045 spin_unlock_irqrestore(&info->irq_spinlock,flags);
8047 netif_wake_queue(dev);
8051 * called by device driver when transmit completes
8052 * reenable network layer transmit if stopped
8054 * info pointer to device instance information
8056 static void hdlcdev_tx_done(struct mgsl_struct *info)
8058 if (netif_queue_stopped(info->netdev))
8059 netif_wake_queue(info->netdev);
8063 * called by device driver when frame received
8064 * pass frame to network layer
8066 * info pointer to device instance information
8067 * buf pointer to buffer contianing frame data
8068 * size count of data bytes in buf
8070 static void hdlcdev_rx(struct mgsl_struct *info, char *buf, int size)
8072 struct sk_buff *skb = dev_alloc_skb(size);
8073 struct net_device *dev = info->netdev;
8074 struct net_device_stats *stats = hdlc_stats(dev);
8076 if (debug_level >= DEBUG_LEVEL_INFO)
8077 printk("hdlcdev_rx(%s)\n",dev->name);
8080 printk(KERN_NOTICE "%s: can't alloc skb, dropping packet\n", dev->name);
8081 stats->rx_dropped++;
8085 memcpy(skb_put(skb, size),buf,size);
8087 skb->protocol = hdlc_type_trans(skb, info->netdev);
8089 stats->rx_packets++;
8090 stats->rx_bytes += size;
8094 info->netdev->last_rx = jiffies;
8098 * called by device driver when adding device instance
8099 * do generic HDLC initialization
8101 * info pointer to device instance information
8103 * returns 0 if success, otherwise error code
8105 static int hdlcdev_init(struct mgsl_struct *info)
8108 struct net_device *dev;
8111 /* allocate and initialize network and HDLC layer objects */
8113 if (!(dev = alloc_hdlcdev(info))) {
8114 printk(KERN_ERR "%s:hdlc device allocation failure\n",__FILE__);
8118 /* for network layer reporting purposes only */
8119 dev->base_addr = info->io_base;
8120 dev->irq = info->irq_level;
8121 dev->dma = info->dma_level;
8123 /* network layer callbacks and settings */
8124 dev->do_ioctl = hdlcdev_ioctl;
8125 dev->open = hdlcdev_open;
8126 dev->stop = hdlcdev_close;
8127 dev->tx_timeout = hdlcdev_tx_timeout;
8128 dev->watchdog_timeo = 10*HZ;
8129 dev->tx_queue_len = 50;
8131 /* generic HDLC layer callbacks and settings */
8132 hdlc = dev_to_hdlc(dev);
8133 hdlc->attach = hdlcdev_attach;
8134 hdlc->xmit = hdlcdev_xmit;
8136 /* register objects with HDLC layer */
8137 if ((rc = register_hdlc_device(dev))) {
8138 printk(KERN_WARNING "%s:unable to register hdlc device\n",__FILE__);
8148 * called by device driver when removing device instance
8149 * do generic HDLC cleanup
8151 * info pointer to device instance information
8153 static void hdlcdev_exit(struct mgsl_struct *info)
8155 unregister_hdlc_device(info->netdev);
8156 free_netdev(info->netdev);
8157 info->netdev = NULL;
8160 #endif /* CONFIG_HDLC */
8163 static int __devinit synclink_init_one (struct pci_dev *dev,
8164 const struct pci_device_id *ent)
8166 struct mgsl_struct *info;
8168 if (pci_enable_device(dev)) {
8169 printk("error enabling pci device %p\n", dev);
8173 if (!(info = mgsl_allocate_device())) {
8174 printk("can't allocate device instance data.\n");
8178 /* Copy user configuration info to device instance data */
8180 info->io_base = pci_resource_start(dev, 2);
8181 info->irq_level = dev->irq;
8182 info->phys_memory_base = pci_resource_start(dev, 3);
8184 /* Because veremap only works on page boundaries we must map
8185 * a larger area than is actually implemented for the LCR
8186 * memory range. We map a full page starting at the page boundary.
8188 info->phys_lcr_base = pci_resource_start(dev, 0);
8189 info->lcr_offset = info->phys_lcr_base & (PAGE_SIZE-1);
8190 info->phys_lcr_base &= ~(PAGE_SIZE-1);
8192 info->bus_type = MGSL_BUS_TYPE_PCI;
8193 info->io_addr_size = 8;
8194 info->irq_flags = SA_SHIRQ;
8196 if (dev->device == 0x0210) {
8197 /* Version 1 PCI9030 based universal PCI adapter */
8198 info->misc_ctrl_value = 0x007c4080;
8199 info->hw_version = 1;
8201 /* Version 0 PCI9050 based 5V PCI adapter
8202 * A PCI9050 bug prevents reading LCR registers if
8203 * LCR base address bit 7 is set. Maintain shadow
8204 * value so we can write to LCR misc control reg.
8206 info->misc_ctrl_value = 0x087e4546;
8207 info->hw_version = 0;
8210 mgsl_add_device(info);
8215 static void __devexit synclink_remove_one (struct pci_dev *dev)