2 * $Id: synclinkmp.c,v 4.19 2004/03/08 15:29:23 paulkf Exp $
4 * Device driver for Microgate SyncLink Multiport
5 * high speed multiprotocol serial adapter.
7 * written by Paul Fulghum for Microgate Corporation
10 * Microgate and SyncLink are trademarks of Microgate Corporation
12 * Derived from serial.c written by Theodore Ts'o and Linus Torvalds
13 * This code is released under the GNU General Public License (GPL)
15 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
16 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
18 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
19 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
20 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
21 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
23 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
24 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
25 * OF THE POSSIBILITY OF SUCH DAMAGE.
28 #define VERSION(ver,rel,seq) (((ver)<<16) | ((rel)<<8) | (seq))
30 # define BREAKPOINT() asm(" int $3");
32 # define BREAKPOINT() { }
35 #define MAX_DEVICES 12
37 #include <linux/config.h>
38 #include <linux/module.h>
39 #include <linux/errno.h>
40 #include <linux/signal.h>
41 #include <linux/sched.h>
42 #include <linux/timer.h>
43 #include <linux/interrupt.h>
44 #include <linux/pci.h>
45 #include <linux/tty.h>
46 #include <linux/tty_flip.h>
47 #include <linux/serial.h>
48 #include <linux/major.h>
49 #include <linux/string.h>
50 #include <linux/fcntl.h>
51 #include <linux/ptrace.h>
52 #include <linux/ioport.h>
54 #include <linux/slab.h>
55 #include <linux/netdevice.h>
56 #include <linux/vmalloc.h>
57 #include <linux/init.h>
58 #include <asm/serial.h>
59 #include <linux/delay.h>
60 #include <linux/ioctl.h>
62 #include <asm/system.h>
66 #include <asm/bitops.h>
67 #include <asm/types.h>
68 #include <linux/termios.h>
69 #include <linux/workqueue.h>
71 #ifdef CONFIG_SYNCLINK_SYNCPPP_MODULE
72 #define CONFIG_SYNCLINK_SYNCPPP 1
75 #ifdef CONFIG_SYNCLINK_SYNCPPP
76 #include <net/syncppp.h>
79 #define GET_USER(error,value,addr) error = get_user(value,addr)
80 #define COPY_FROM_USER(error,dest,src,size) error = copy_from_user(dest,src,size) ? -EFAULT : 0
81 #define PUT_USER(error,value,addr) error = put_user(value,addr)
82 #define COPY_TO_USER(error,dest,src,size) error = copy_to_user(dest,src,size) ? -EFAULT : 0
84 #include <asm/uaccess.h>
86 #include "linux/synclink.h"
88 static MGSL_PARAMS default_params = {
89 MGSL_MODE_HDLC, /* unsigned long mode */
90 0, /* unsigned char loopback; */
91 HDLC_FLAG_UNDERRUN_ABORT15, /* unsigned short flags; */
92 HDLC_ENCODING_NRZI_SPACE, /* unsigned char encoding; */
93 0, /* unsigned long clock_speed; */
94 0xff, /* unsigned char addr_filter; */
95 HDLC_CRC_16_CCITT, /* unsigned short crc_type; */
96 HDLC_PREAMBLE_LENGTH_8BITS, /* unsigned char preamble_length; */
97 HDLC_PREAMBLE_PATTERN_NONE, /* unsigned char preamble; */
98 9600, /* unsigned long data_rate; */
99 8, /* unsigned char data_bits; */
100 1, /* unsigned char stop_bits; */
101 ASYNC_PARITY_NONE /* unsigned char parity; */
104 /* size in bytes of DMA data buffers */
105 #define SCABUFSIZE 1024
106 #define SCA_MEM_SIZE 0x40000
107 #define SCA_BASE_SIZE 512
108 #define SCA_REG_SIZE 16
109 #define SCA_MAX_PORTS 4
110 #define SCAMAXDESC 128
112 #define BUFFERLISTSIZE 4096
114 /* SCA-I style DMA buffer descriptor */
115 typedef struct _SCADESC
117 u16 next; /* lower l6 bits of next descriptor addr */
118 u16 buf_ptr; /* lower 16 bits of buffer addr */
119 u8 buf_base; /* upper 8 bits of buffer addr */
121 u16 length; /* length of buffer */
122 u8 status; /* status of buffer */
124 } SCADESC, *PSCADESC;
126 typedef struct _SCADESC_EX
128 /* device driver bookkeeping section */
129 char *virt_addr; /* virtual address of data buffer */
130 u16 phys_entry; /* lower 16-bits of physical address of this descriptor */
131 } SCADESC_EX, *PSCADESC_EX;
133 /* The queue of BH actions to be performed */
136 #define BH_TRANSMIT 2
139 #define IO_PIN_SHUTDOWN_LIMIT 100
141 #define RELEVANT_IFLAG(iflag) (iflag & (IGNBRK|BRKINT|IGNPAR|PARMRK|INPCK))
143 struct _input_signal_events {
155 * Device instance data structure
157 typedef struct _synclinkmp_info {
158 void *if_ptr; /* General purpose pointer (used by SPPP) */
161 int count; /* count of opens */
163 unsigned short close_delay;
164 unsigned short closing_wait; /* time to wait before closing */
166 struct mgsl_icount icount;
168 struct tty_struct *tty;
170 int x_char; /* xon/xoff character */
171 int blocked_open; /* # of blocked opens */
172 u16 read_status_mask1; /* break detection (SR1 indications) */
173 u16 read_status_mask2; /* parity/framing/overun (SR2 indications) */
174 unsigned char ignore_status_mask1; /* break detection (SR1 indications) */
175 unsigned char ignore_status_mask2; /* parity/framing/overun (SR2 indications) */
176 unsigned char *tx_buf;
181 wait_queue_head_t open_wait;
182 wait_queue_head_t close_wait;
184 wait_queue_head_t status_event_wait_q;
185 wait_queue_head_t event_wait_q;
186 struct timer_list tx_timer; /* HDLC transmit timeout timer */
187 struct _synclinkmp_info *next_device; /* device list link */
188 struct timer_list status_timer; /* input signal status check timer */
190 spinlock_t lock; /* spinlock for synchronizing with ISR */
191 struct work_struct task; /* task structure for scheduling bh */
193 u32 max_frame_size; /* as set by device config */
197 int bh_running; /* Protection from multiple */
201 int dcd_chkcount; /* check counts to prevent */
202 int cts_chkcount; /* too many IRQs if a signal */
203 int dsr_chkcount; /* is floating */
206 char *buffer_list; /* virtual address of Rx & Tx buffer lists */
207 unsigned long buffer_list_phys;
209 unsigned int rx_buf_count; /* count of total allocated Rx buffers */
210 SCADESC *rx_buf_list; /* list of receive buffer entries */
211 SCADESC_EX rx_buf_list_ex[SCAMAXDESC]; /* list of receive buffer entries */
212 unsigned int current_rx_buf;
214 unsigned int tx_buf_count; /* count of total allocated Tx buffers */
215 SCADESC *tx_buf_list; /* list of transmit buffer entries */
216 SCADESC_EX tx_buf_list_ex[SCAMAXDESC]; /* list of transmit buffer entries */
217 unsigned int last_tx_buf;
219 unsigned char *tmp_rx_buf;
220 unsigned int tmp_rx_buf_count;
229 unsigned char ie0_value;
230 unsigned char ie1_value;
231 unsigned char ie2_value;
232 unsigned char ctrlreg_value;
233 unsigned char old_signals;
235 char device_name[25]; /* device instance name */
241 struct _synclinkmp_info *port_array[SCA_MAX_PORTS];
243 unsigned int bus_type; /* expansion bus type (ISA,EISA,PCI) */
245 unsigned int irq_level; /* interrupt level */
246 unsigned long irq_flags;
247 int irq_requested; /* nonzero if IRQ requested */
249 MGSL_PARAMS params; /* communications parameters */
251 unsigned char serial_signals; /* current serial signal states */
253 int irq_occurred; /* for diagnostics use */
254 unsigned int init_error; /* Initialization startup error */
257 unsigned char* memory_base; /* shared memory address (PCI only) */
258 u32 phys_memory_base;
259 int shared_mem_requested;
261 unsigned char* sca_base; /* HD64570 SCA Memory address */
264 int sca_base_requested;
266 unsigned char* lcr_base; /* local config registers (PCI only) */
269 int lcr_mem_requested;
271 unsigned char* statctrl_base; /* status/control register memory */
272 u32 phys_statctrl_base;
274 int sca_statctrl_requested;
277 char flag_buf[MAX_ASYNC_BUFFER_SIZE];
278 char char_buf[MAX_ASYNC_BUFFER_SIZE];
279 BOOLEAN drop_rts_on_tx_done;
281 struct _input_signal_events input_signal_events;
283 /* SPPP/Cisco HDLC device parts */
287 #ifdef CONFIG_SYNCLINK_SYNCPPP
288 struct ppp_device pppdev;
290 struct net_device *netdev;
291 struct net_device_stats netstats;
295 #define MGSL_MAGIC 0x5401
298 * define serial signal status change macros
300 #define MISCSTATUS_DCD_LATCHED (SerialSignal_DCD<<8) /* indicates change in DCD */
301 #define MISCSTATUS_RI_LATCHED (SerialSignal_RI<<8) /* indicates change in RI */
302 #define MISCSTATUS_CTS_LATCHED (SerialSignal_CTS<<8) /* indicates change in CTS */
303 #define MISCSTATUS_DSR_LATCHED (SerialSignal_DSR<<8) /* change in DSR */
305 /* Common Register macros */
324 /* MSCI Register macros */
354 /* Timer Register Macros */
364 /* DMA Controller Register macros */
396 /* combine with timer or DMA register address */
404 /* SCA Command Codes */
407 #define TXENABLE 0x02
408 #define TXDISABLE 0x03
409 #define TXCRCINIT 0x04
410 #define TXCRCEXCL 0x05
414 #define TXBUFCLR 0x09
416 #define RXENABLE 0x12
417 #define RXDISABLE 0x13
418 #define RXCRCINIT 0x14
419 #define RXREJECT 0x15
420 #define SEARCHMP 0x16
421 #define RXCRCEXCL 0x17
422 #define RXCRCCALC 0x18
426 /* DMA command codes */
428 #define FEICLEAR 0x02
461 #define jiffies_from_ms(a) ((((a) * HZ)/1000)+1)
464 * Global linked list of SyncLink devices
466 static SLMP_INFO *synclinkmp_device_list = NULL;
467 static int synclinkmp_adapter_count = -1;
468 static int synclinkmp_device_count = 0;
471 * Set this param to non-zero to load eax with the
472 * .text section address and breakpoint on module load.
473 * This is useful for use with gdb and add-symbol-file command.
475 static int break_on_load=0;
478 * Driver major number, defaults to zero to get auto
479 * assigned major number. May be forced as module parameter.
481 static int ttymajor=0;
484 * Array of user specified options for ISA adapters.
486 static int debug_level = 0;
487 static int maxframe[MAX_DEVICES] = {0,};
488 static int dosyncppp[MAX_DEVICES] = {0,};
490 MODULE_PARM(break_on_load,"i");
491 MODULE_PARM(ttymajor,"i");
492 MODULE_PARM(debug_level,"i");
493 MODULE_PARM(maxframe,"1-" __MODULE_STRING(MAX_DEVICES) "i");
494 MODULE_PARM(dosyncppp,"1-" __MODULE_STRING(MAX_DEVICES) "i");
496 static char *driver_name = "SyncLink MultiPort driver";
497 static char *driver_version = "$Revision: 4.19 $";
499 static int synclinkmp_init_one(struct pci_dev *dev,const struct pci_device_id *ent);
500 static void synclinkmp_remove_one(struct pci_dev *dev);
502 static struct pci_device_id synclinkmp_pci_tbl[] = {
503 { PCI_VENDOR_ID_MICROGATE, PCI_DEVICE_ID_MICROGATE_SCA, PCI_ANY_ID, PCI_ANY_ID, },
504 { 0, }, /* terminate list */
506 MODULE_DEVICE_TABLE(pci, synclinkmp_pci_tbl);
508 MODULE_LICENSE("GPL");
510 static struct pci_driver synclinkmp_pci_driver = {
511 .name = "synclinkmp",
512 .id_table = synclinkmp_pci_tbl,
513 .probe = synclinkmp_init_one,
514 .remove = __devexit_p(synclinkmp_remove_one),
518 static struct tty_driver *serial_driver;
520 /* number of characters left in xmit buffer before we ask for more */
521 #define WAKEUP_CHARS 256
524 #define MIN(a,b) ((a) < (b) ? (a) : (b))
530 static int open(struct tty_struct *tty, struct file * filp);
531 static void close(struct tty_struct *tty, struct file * filp);
532 static void hangup(struct tty_struct *tty);
533 static void set_termios(struct tty_struct *tty, struct termios *old_termios);
535 static int write(struct tty_struct *tty, int from_user, const unsigned char *buf, int count);
536 static void put_char(struct tty_struct *tty, unsigned char ch);
537 static void send_xchar(struct tty_struct *tty, char ch);
538 static void wait_until_sent(struct tty_struct *tty, int timeout);
539 static int write_room(struct tty_struct *tty);
540 static void flush_chars(struct tty_struct *tty);
541 static void flush_buffer(struct tty_struct *tty);
542 static void tx_hold(struct tty_struct *tty);
543 static void tx_release(struct tty_struct *tty);
545 static int ioctl(struct tty_struct *tty, struct file *file, unsigned int cmd, unsigned long arg);
546 static int read_proc(char *page, char **start, off_t off, int count,int *eof, void *data);
547 static int chars_in_buffer(struct tty_struct *tty);
548 static void throttle(struct tty_struct * tty);
549 static void unthrottle(struct tty_struct * tty);
550 static void set_break(struct tty_struct *tty, int break_state);
552 /* sppp support and callbacks */
554 #ifdef CONFIG_SYNCLINK_SYNCPPP
555 static void sppp_init(SLMP_INFO *info);
556 static void sppp_delete(SLMP_INFO *info);
557 static void sppp_rx_done(SLMP_INFO *info, char *buf, int size);
558 static void sppp_tx_done(SLMP_INFO *info);
560 static int sppp_cb_open(struct net_device *d);
561 static int sppp_cb_close(struct net_device *d);
562 static int sppp_cb_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd);
563 static int sppp_cb_tx(struct sk_buff *skb, struct net_device *dev);
564 static void sppp_cb_tx_timeout(struct net_device *dev);
565 static struct net_device_stats *sppp_cb_net_stats(struct net_device *dev);
570 static int get_stats(SLMP_INFO *info, struct mgsl_icount *user_icount);
571 static int get_params(SLMP_INFO *info, MGSL_PARAMS *params);
572 static int set_params(SLMP_INFO *info, MGSL_PARAMS *params);
573 static int get_txidle(SLMP_INFO *info, int*idle_mode);
574 static int set_txidle(SLMP_INFO *info, int idle_mode);
575 static int tx_enable(SLMP_INFO *info, int enable);
576 static int tx_abort(SLMP_INFO *info);
577 static int rx_enable(SLMP_INFO *info, int enable);
578 static int map_status(int signals);
579 static int modem_input_wait(SLMP_INFO *info,int arg);
580 static int wait_mgsl_event(SLMP_INFO *info, int *mask_ptr);
581 static int tiocmget(struct tty_struct *tty, struct file *file);
582 static int tiocmset(struct tty_struct *tty, struct file *file,
583 unsigned int set, unsigned int clear);
584 static void set_break(struct tty_struct *tty, int break_state);
586 static void add_device(SLMP_INFO *info);
587 static void device_init(int adapter_num, struct pci_dev *pdev);
588 static int claim_resources(SLMP_INFO *info);
589 static void release_resources(SLMP_INFO *info);
591 static int startup(SLMP_INFO *info);
592 static int block_til_ready(struct tty_struct *tty, struct file * filp,SLMP_INFO *info);
593 static void shutdown(SLMP_INFO *info);
594 static void program_hw(SLMP_INFO *info);
595 static void change_params(SLMP_INFO *info);
597 static int init_adapter(SLMP_INFO *info);
598 static int register_test(SLMP_INFO *info);
599 static int irq_test(SLMP_INFO *info);
600 static int loopback_test(SLMP_INFO *info);
601 static int adapter_test(SLMP_INFO *info);
602 static int memory_test(SLMP_INFO *info);
604 static void reset_adapter(SLMP_INFO *info);
605 static void reset_port(SLMP_INFO *info);
606 static void async_mode(SLMP_INFO *info);
607 static void hdlc_mode(SLMP_INFO *info);
609 static void rx_stop(SLMP_INFO *info);
610 static void rx_start(SLMP_INFO *info);
611 static void rx_reset_buffers(SLMP_INFO *info);
612 static void rx_free_frame_buffers(SLMP_INFO *info, unsigned int first, unsigned int last);
613 static int rx_get_frame(SLMP_INFO *info);
615 static void tx_start(SLMP_INFO *info);
616 static void tx_stop(SLMP_INFO *info);
617 static void tx_load_fifo(SLMP_INFO *info);
618 static void tx_set_idle(SLMP_INFO *info);
619 static void tx_load_dma_buffer(SLMP_INFO *info, const char *buf, unsigned int count);
621 static void get_signals(SLMP_INFO *info);
622 static void set_signals(SLMP_INFO *info);
623 static void enable_loopback(SLMP_INFO *info, int enable);
624 static void set_rate(SLMP_INFO *info, u32 data_rate);
626 static int bh_action(SLMP_INFO *info);
627 static void bh_handler(void* Context);
628 static void bh_receive(SLMP_INFO *info);
629 static void bh_transmit(SLMP_INFO *info);
630 static void bh_status(SLMP_INFO *info);
631 static void isr_timer(SLMP_INFO *info);
632 static void isr_rxint(SLMP_INFO *info);
633 static void isr_rxrdy(SLMP_INFO *info);
634 static void isr_txint(SLMP_INFO *info);
635 static void isr_txrdy(SLMP_INFO *info);
636 static void isr_rxdmaok(SLMP_INFO *info);
637 static void isr_rxdmaerror(SLMP_INFO *info);
638 static void isr_txdmaok(SLMP_INFO *info);
639 static void isr_txdmaerror(SLMP_INFO *info);
640 static void isr_io_pin(SLMP_INFO *info, u16 status);
642 static int alloc_dma_bufs(SLMP_INFO *info);
643 static void free_dma_bufs(SLMP_INFO *info);
644 static int alloc_buf_list(SLMP_INFO *info);
645 static int alloc_frame_bufs(SLMP_INFO *info, SCADESC *list, SCADESC_EX *list_ex,int count);
646 static int alloc_tmp_rx_buf(SLMP_INFO *info);
647 static void free_tmp_rx_buf(SLMP_INFO *info);
649 static void load_pci_memory(SLMP_INFO *info, char* dest, const char* src, unsigned short count);
650 static void trace_block(SLMP_INFO *info, const char* data, int count, int xmit);
651 static void tx_timeout(unsigned long context);
652 static void status_timeout(unsigned long context);
654 static unsigned char read_reg(SLMP_INFO *info, unsigned char addr);
655 static void write_reg(SLMP_INFO *info, unsigned char addr, unsigned char val);
656 static u16 read_reg16(SLMP_INFO *info, unsigned char addr);
657 static void write_reg16(SLMP_INFO *info, unsigned char addr, u16 val);
658 static unsigned char read_status_reg(SLMP_INFO * info);
659 static void write_control_reg(SLMP_INFO * info);
662 static unsigned char rx_active_fifo_level = 16; // rx request FIFO activation level in bytes
663 static unsigned char tx_active_fifo_level = 16; // tx request FIFO activation level in bytes
664 static unsigned char tx_negate_fifo_level = 32; // tx request FIFO negation level in bytes
666 static u32 misc_ctrl_value = 0x007e4040;
667 static u32 lcr1_brdr_value = 0x0080002d;
669 static u32 read_ahead_count = 8;
671 /* DPCR, DMA Priority Control
673 * 07..05 Not used, must be 0
674 * 04 BRC, bus release condition: 0=all transfers complete
675 * 1=release after 1 xfer on all channels
676 * 03 CCC, channel change condition: 0=every cycle
677 * 1=after each channel completes all xfers
678 * 02..00 PR<2..0>, priority 100=round robin
682 static unsigned char dma_priority = 0x04;
684 // Number of bytes that can be written to shared RAM
685 // in a single write operation
686 static u32 sca_pci_load_interval = 64;
689 * 1st function defined in .text section. Calling this function in
690 * init_module() followed by a breakpoint allows a remote debugger
691 * (gdb) to get the .text address for the add-symbol-file command.
692 * This allows remote debugging of dynamically loadable modules.
694 static void* synclinkmp_get_text_ptr(void);
695 static void* synclinkmp_get_text_ptr() {return synclinkmp_get_text_ptr;}
697 static inline int sanity_check(SLMP_INFO *info,
698 char *name, const char *routine)
701 static const char *badmagic =
702 "Warning: bad magic number for synclinkmp_struct (%s) in %s\n";
703 static const char *badinfo =
704 "Warning: null synclinkmp_struct for (%s) in %s\n";
707 printk(badinfo, name, routine);
710 if (info->magic != MGSL_MAGIC) {
711 printk(badmagic, name, routine);
723 /* Called when a port is opened. Init and enable port.
725 static int open(struct tty_struct *tty, struct file *filp)
732 if ((line < 0) || (line >= synclinkmp_device_count)) {
733 printk("%s(%d): open with invalid line #%d.\n",
734 __FILE__,__LINE__,line);
738 info = synclinkmp_device_list;
739 while(info && info->line != line)
740 info = info->next_device;
741 if (sanity_check(info, tty->name, "open"))
743 if ( info->init_error ) {
744 printk("%s(%d):%s device is not allocated, init error=%d\n",
745 __FILE__,__LINE__,info->device_name,info->init_error);
749 tty->driver_data = info;
752 if (debug_level >= DEBUG_LEVEL_INFO)
753 printk("%s(%d):%s open(), old ref count = %d\n",
754 __FILE__,__LINE__,tty->driver->name, info->count);
756 /* If port is closing, signal caller to try again */
757 if (tty_hung_up_p(filp) || info->flags & ASYNC_CLOSING){
758 if (info->flags & ASYNC_CLOSING)
759 interruptible_sleep_on(&info->close_wait);
760 retval = ((info->flags & ASYNC_HUP_NOTIFY) ?
761 -EAGAIN : -ERESTARTSYS);
765 info->tty->low_latency = (info->flags & ASYNC_LOW_LATENCY) ? 1 : 0;
767 spin_lock_irqsave(&info->netlock, flags);
768 if (info->netcount) {
770 spin_unlock_irqrestore(&info->netlock, flags);
774 spin_unlock_irqrestore(&info->netlock, flags);
776 if (info->count == 1) {
777 /* 1st open on this device, init hardware */
778 retval = startup(info);
783 retval = block_til_ready(tty, filp, info);
785 if (debug_level >= DEBUG_LEVEL_INFO)
786 printk("%s(%d):%s block_til_ready() returned %d\n",
787 __FILE__,__LINE__, info->device_name, retval);
791 if (debug_level >= DEBUG_LEVEL_INFO)
792 printk("%s(%d):%s open() success\n",
793 __FILE__,__LINE__, info->device_name);
799 info->tty = 0; /* tty layer will release tty struct */
807 /* Called when port is closed. Wait for remaining data to be
808 * sent. Disable port and free resources.
810 static void close(struct tty_struct *tty, struct file *filp)
812 SLMP_INFO * info = (SLMP_INFO *)tty->driver_data;
814 if (sanity_check(info, tty->name, "close"))
817 if (debug_level >= DEBUG_LEVEL_INFO)
818 printk("%s(%d):%s close() entry, count=%d\n",
819 __FILE__,__LINE__, info->device_name, info->count);
824 if (tty_hung_up_p(filp))
827 if ((tty->count == 1) && (info->count != 1)) {
829 * tty->count is 1 and the tty structure will be freed.
830 * info->count should be one in this case.
831 * if it's not, correct it so that the port is shutdown.
833 printk("%s(%d):%s close: bad refcount; tty->count is 1, "
834 "info->count is %d\n",
835 __FILE__,__LINE__, info->device_name, info->count);
841 /* if at least one open remaining, leave hardware active */
845 info->flags |= ASYNC_CLOSING;
847 /* set tty->closing to notify line discipline to
848 * only process XON/XOFF characters. Only the N_TTY
849 * discipline appears to use this (ppp does not).
853 /* wait for transmit data to clear all layers */
855 if (info->closing_wait != ASYNC_CLOSING_WAIT_NONE) {
856 if (debug_level >= DEBUG_LEVEL_INFO)
857 printk("%s(%d):%s close() calling tty_wait_until_sent\n",
858 __FILE__,__LINE__, info->device_name );
859 tty_wait_until_sent(tty, info->closing_wait);
862 if (info->flags & ASYNC_INITIALIZED)
863 wait_until_sent(tty, info->timeout);
865 if (tty->driver->flush_buffer)
866 tty->driver->flush_buffer(tty);
868 if (tty->ldisc.flush_buffer)
869 tty->ldisc.flush_buffer(tty);
876 if (info->blocked_open) {
877 if (info->close_delay) {
878 set_current_state(TASK_INTERRUPTIBLE);
879 schedule_timeout(info->close_delay);
881 wake_up_interruptible(&info->open_wait);
884 info->flags &= ~(ASYNC_NORMAL_ACTIVE|ASYNC_CLOSING);
886 wake_up_interruptible(&info->close_wait);
889 if (debug_level >= DEBUG_LEVEL_INFO)
890 printk("%s(%d):%s close() exit, count=%d\n", __FILE__,__LINE__,
891 tty->driver->name, info->count);
894 /* Called by tty_hangup() when a hangup is signaled.
895 * This is the same as closing all open descriptors for the port.
897 static void hangup(struct tty_struct *tty)
899 SLMP_INFO *info = (SLMP_INFO *)tty->driver_data;
901 if (debug_level >= DEBUG_LEVEL_INFO)
902 printk("%s(%d):%s hangup()\n",
903 __FILE__,__LINE__, info->device_name );
905 if (sanity_check(info, tty->name, "hangup"))
912 info->flags &= ~ASYNC_NORMAL_ACTIVE;
915 wake_up_interruptible(&info->open_wait);
918 /* Set new termios settings
920 static void set_termios(struct tty_struct *tty, struct termios *old_termios)
922 SLMP_INFO *info = (SLMP_INFO *)tty->driver_data;
925 if (debug_level >= DEBUG_LEVEL_INFO)
926 printk("%s(%d):%s set_termios()\n", __FILE__,__LINE__,
929 /* just return if nothing has changed */
930 if ((tty->termios->c_cflag == old_termios->c_cflag)
931 && (RELEVANT_IFLAG(tty->termios->c_iflag)
932 == RELEVANT_IFLAG(old_termios->c_iflag)))
937 /* Handle transition to B0 status */
938 if (old_termios->c_cflag & CBAUD &&
939 !(tty->termios->c_cflag & CBAUD)) {
940 info->serial_signals &= ~(SerialSignal_RTS + SerialSignal_DTR);
941 spin_lock_irqsave(&info->lock,flags);
943 spin_unlock_irqrestore(&info->lock,flags);
946 /* Handle transition away from B0 status */
947 if (!(old_termios->c_cflag & CBAUD) &&
948 tty->termios->c_cflag & CBAUD) {
949 info->serial_signals |= SerialSignal_DTR;
950 if (!(tty->termios->c_cflag & CRTSCTS) ||
951 !test_bit(TTY_THROTTLED, &tty->flags)) {
952 info->serial_signals |= SerialSignal_RTS;
954 spin_lock_irqsave(&info->lock,flags);
956 spin_unlock_irqrestore(&info->lock,flags);
959 /* Handle turning off CRTSCTS */
960 if (old_termios->c_cflag & CRTSCTS &&
961 !(tty->termios->c_cflag & CRTSCTS)) {
967 /* Send a block of data
971 * tty pointer to tty information structure
972 * from_user flag: 1 = from user process
973 * buf pointer to buffer containing send data
974 * count size of send data in bytes
976 * Return Value: number of characters written
978 static int write(struct tty_struct *tty, int from_user,
979 const unsigned char *buf, int count)
982 SLMP_INFO *info = (SLMP_INFO *)tty->driver_data;
985 if (debug_level >= DEBUG_LEVEL_INFO)
986 printk("%s(%d):%s write() count=%d\n",
987 __FILE__,__LINE__,info->device_name,count);
989 if (sanity_check(info, tty->name, "write"))
992 if (!tty || !info->tx_buf)
995 if (info->params.mode == MGSL_MODE_HDLC) {
996 if (count > info->max_frame_size) {
1000 if (info->tx_active)
1002 if (info->tx_count) {
1003 /* send accumulated data from send_char() calls */
1004 /* as frame and wait before accepting more data. */
1005 tx_load_dma_buffer(info, info->tx_buf, info->tx_count);
1009 ret = info->tx_count = count;
1010 tx_load_dma_buffer(info, buf, count);
1017 MIN(info->max_frame_size - info->tx_count - 1,
1018 info->max_frame_size - info->tx_put));
1023 COPY_FROM_USER(err, info->tx_buf + info->tx_put, buf, c);
1030 memcpy(info->tx_buf + info->tx_put, buf, c);
1032 spin_lock_irqsave(&info->lock,flags);
1034 if (info->tx_put >= info->max_frame_size)
1035 info->tx_put -= info->max_frame_size;
1036 info->tx_count += c;
1037 spin_unlock_irqrestore(&info->lock,flags);
1044 if (info->params.mode == MGSL_MODE_HDLC) {
1046 ret = info->tx_count = 0;
1049 tx_load_dma_buffer(info, info->tx_buf, info->tx_count);
1052 if (info->tx_count && !tty->stopped && !tty->hw_stopped) {
1053 spin_lock_irqsave(&info->lock,flags);
1054 if (!info->tx_active)
1056 spin_unlock_irqrestore(&info->lock,flags);
1060 if (debug_level >= DEBUG_LEVEL_INFO)
1061 printk( "%s(%d):%s write() returning=%d\n",
1062 __FILE__,__LINE__,info->device_name,ret);
1066 /* Add a character to the transmit buffer.
1068 static void put_char(struct tty_struct *tty, unsigned char ch)
1070 SLMP_INFO *info = (SLMP_INFO *)tty->driver_data;
1071 unsigned long flags;
1073 if ( debug_level >= DEBUG_LEVEL_INFO ) {
1074 printk( "%s(%d):%s put_char(%d)\n",
1075 __FILE__,__LINE__,info->device_name,ch);
1078 if (sanity_check(info, tty->name, "put_char"))
1081 if (!tty || !info->tx_buf)
1084 spin_lock_irqsave(&info->lock,flags);
1086 if ( (info->params.mode != MGSL_MODE_HDLC) ||
1087 !info->tx_active ) {
1089 if (info->tx_count < info->max_frame_size - 1) {
1090 info->tx_buf[info->tx_put++] = ch;
1091 if (info->tx_put >= info->max_frame_size)
1092 info->tx_put -= info->max_frame_size;
1097 spin_unlock_irqrestore(&info->lock,flags);
1100 /* Send a high-priority XON/XOFF character
1102 static void send_xchar(struct tty_struct *tty, char ch)
1104 SLMP_INFO *info = (SLMP_INFO *)tty->driver_data;
1105 unsigned long flags;
1107 if (debug_level >= DEBUG_LEVEL_INFO)
1108 printk("%s(%d):%s send_xchar(%d)\n",
1109 __FILE__,__LINE__, info->device_name, ch );
1111 if (sanity_check(info, tty->name, "send_xchar"))
1116 /* Make sure transmit interrupts are on */
1117 spin_lock_irqsave(&info->lock,flags);
1118 if (!info->tx_enabled)
1120 spin_unlock_irqrestore(&info->lock,flags);
1124 /* Wait until the transmitter is empty.
1126 static void wait_until_sent(struct tty_struct *tty, int timeout)
1128 SLMP_INFO * info = (SLMP_INFO *)tty->driver_data;
1129 unsigned long orig_jiffies, char_time;
1134 if (debug_level >= DEBUG_LEVEL_INFO)
1135 printk("%s(%d):%s wait_until_sent() entry\n",
1136 __FILE__,__LINE__, info->device_name );
1138 if (sanity_check(info, tty->name, "wait_until_sent"))
1141 if (!(info->flags & ASYNC_INITIALIZED))
1144 orig_jiffies = jiffies;
1146 /* Set check interval to 1/5 of estimated time to
1147 * send a character, and make it at least 1. The check
1148 * interval should also be less than the timeout.
1149 * Note: use tight timings here to satisfy the NIST-PCTS.
1152 if ( info->params.data_rate ) {
1153 char_time = info->timeout/(32 * 5);
1160 char_time = MIN(char_time, timeout);
1162 if ( info->params.mode == MGSL_MODE_HDLC ) {
1163 while (info->tx_active) {
1164 set_current_state(TASK_INTERRUPTIBLE);
1165 schedule_timeout(char_time);
1166 if (signal_pending(current))
1168 if (timeout && time_after(jiffies, orig_jiffies + timeout))
1172 //TODO: determine if there is something similar to USC16C32
1173 // TXSTATUS_ALL_SENT status
1174 while ( info->tx_active && info->tx_enabled) {
1175 set_current_state(TASK_INTERRUPTIBLE);
1176 schedule_timeout(char_time);
1177 if (signal_pending(current))
1179 if (timeout && time_after(jiffies, orig_jiffies + timeout))
1185 if (debug_level >= DEBUG_LEVEL_INFO)
1186 printk("%s(%d):%s wait_until_sent() exit\n",
1187 __FILE__,__LINE__, info->device_name );
1190 /* Return the count of free bytes in transmit buffer
1192 static int write_room(struct tty_struct *tty)
1194 SLMP_INFO *info = (SLMP_INFO *)tty->driver_data;
1197 if (sanity_check(info, tty->name, "write_room"))
1200 if (info->params.mode == MGSL_MODE_HDLC) {
1201 ret = (info->tx_active) ? 0 : HDLC_MAX_FRAME_SIZE;
1203 ret = info->max_frame_size - info->tx_count - 1;
1208 if (debug_level >= DEBUG_LEVEL_INFO)
1209 printk("%s(%d):%s write_room()=%d\n",
1210 __FILE__, __LINE__, info->device_name, ret);
1215 /* enable transmitter and send remaining buffered characters
1217 static void flush_chars(struct tty_struct *tty)
1219 SLMP_INFO *info = (SLMP_INFO *)tty->driver_data;
1220 unsigned long flags;
1222 if ( debug_level >= DEBUG_LEVEL_INFO )
1223 printk( "%s(%d):%s flush_chars() entry tx_count=%d\n",
1224 __FILE__,__LINE__,info->device_name,info->tx_count);
1226 if (sanity_check(info, tty->name, "flush_chars"))
1229 if (info->tx_count <= 0 || tty->stopped || tty->hw_stopped ||
1233 if ( debug_level >= DEBUG_LEVEL_INFO )
1234 printk( "%s(%d):%s flush_chars() entry, starting transmitter\n",
1235 __FILE__,__LINE__,info->device_name );
1237 spin_lock_irqsave(&info->lock,flags);
1239 if (!info->tx_active) {
1240 if ( (info->params.mode == MGSL_MODE_HDLC) &&
1242 /* operating in synchronous (frame oriented) mode */
1243 /* copy data from circular tx_buf to */
1244 /* transmit DMA buffer. */
1245 tx_load_dma_buffer(info,
1246 info->tx_buf,info->tx_count);
1251 spin_unlock_irqrestore(&info->lock,flags);
1254 /* Discard all data in the send buffer
1256 static void flush_buffer(struct tty_struct *tty)
1258 SLMP_INFO *info = (SLMP_INFO *)tty->driver_data;
1259 unsigned long flags;
1261 if (debug_level >= DEBUG_LEVEL_INFO)
1262 printk("%s(%d):%s flush_buffer() entry\n",
1263 __FILE__,__LINE__, info->device_name );
1265 if (sanity_check(info, tty->name, "flush_buffer"))
1268 spin_lock_irqsave(&info->lock,flags);
1269 info->tx_count = info->tx_put = info->tx_get = 0;
1270 del_timer(&info->tx_timer);
1271 spin_unlock_irqrestore(&info->lock,flags);
1273 wake_up_interruptible(&tty->write_wait);
1274 if ((tty->flags & (1 << TTY_DO_WRITE_WAKEUP)) &&
1275 tty->ldisc.write_wakeup)
1276 (tty->ldisc.write_wakeup)(tty);
1279 /* throttle (stop) transmitter
1281 static void tx_hold(struct tty_struct *tty)
1283 SLMP_INFO *info = (SLMP_INFO *)tty->driver_data;
1284 unsigned long flags;
1286 if (sanity_check(info, tty->name, "tx_hold"))
1289 if ( debug_level >= DEBUG_LEVEL_INFO )
1290 printk("%s(%d):%s tx_hold()\n",
1291 __FILE__,__LINE__,info->device_name);
1293 spin_lock_irqsave(&info->lock,flags);
1294 if (info->tx_enabled)
1296 spin_unlock_irqrestore(&info->lock,flags);
1299 /* release (start) transmitter
1301 static void tx_release(struct tty_struct *tty)
1303 SLMP_INFO *info = (SLMP_INFO *)tty->driver_data;
1304 unsigned long flags;
1306 if (sanity_check(info, tty->name, "tx_release"))
1309 if ( debug_level >= DEBUG_LEVEL_INFO )
1310 printk("%s(%d):%s tx_release()\n",
1311 __FILE__,__LINE__,info->device_name);
1313 spin_lock_irqsave(&info->lock,flags);
1314 if (!info->tx_enabled)
1316 spin_unlock_irqrestore(&info->lock,flags);
1319 /* Service an IOCTL request
1323 * tty pointer to tty instance data
1324 * file pointer to associated file object for device
1325 * cmd IOCTL command code
1326 * arg command argument/context
1328 * Return Value: 0 if success, otherwise error code
1330 static int ioctl(struct tty_struct *tty, struct file *file,
1331 unsigned int cmd, unsigned long arg)
1333 SLMP_INFO *info = (SLMP_INFO *)tty->driver_data;
1335 struct mgsl_icount cnow; /* kernel counter temps */
1336 struct serial_icounter_struct *p_cuser; /* user space */
1337 unsigned long flags;
1339 if (debug_level >= DEBUG_LEVEL_INFO)
1340 printk("%s(%d):%s ioctl() cmd=%08X\n", __FILE__,__LINE__,
1341 info->device_name, cmd );
1343 if (sanity_check(info, tty->name, "ioctl"))
1346 if ((cmd != TIOCGSERIAL) && (cmd != TIOCSSERIAL) &&
1347 (cmd != TIOCMIWAIT) && (cmd != TIOCGICOUNT)) {
1348 if (tty->flags & (1 << TTY_IO_ERROR))
1353 case MGSL_IOCGPARAMS:
1354 return get_params(info,(MGSL_PARAMS *)arg);
1355 case MGSL_IOCSPARAMS:
1356 return set_params(info,(MGSL_PARAMS *)arg);
1357 case MGSL_IOCGTXIDLE:
1358 return get_txidle(info,(int*)arg);
1359 case MGSL_IOCSTXIDLE:
1360 return set_txidle(info,(int)arg);
1361 case MGSL_IOCTXENABLE:
1362 return tx_enable(info,(int)arg);
1363 case MGSL_IOCRXENABLE:
1364 return rx_enable(info,(int)arg);
1365 case MGSL_IOCTXABORT:
1366 return tx_abort(info);
1367 case MGSL_IOCGSTATS:
1368 return get_stats(info,(struct mgsl_icount*)arg);
1369 case MGSL_IOCWAITEVENT:
1370 return wait_mgsl_event(info,(int*)arg);
1371 case MGSL_IOCLOOPTXDONE:
1372 return 0; // TODO: Not supported, need to document
1373 /* Wait for modem input (DCD,RI,DSR,CTS) change
1374 * as specified by mask in arg (TIOCM_RNG/DSR/CD/CTS)
1377 return modem_input_wait(info,(int)arg);
1380 * Get counter of input serial line interrupts (DCD,RI,DSR,CTS)
1381 * Return: write counters to the user passed counter struct
1382 * NB: both 1->0 and 0->1 transitions are counted except for
1383 * RI where only 0->1 is counted.
1386 spin_lock_irqsave(&info->lock,flags);
1387 cnow = info->icount;
1388 spin_unlock_irqrestore(&info->lock,flags);
1389 p_cuser = (struct serial_icounter_struct *) arg;
1390 PUT_USER(error,cnow.cts, &p_cuser->cts);
1391 if (error) return error;
1392 PUT_USER(error,cnow.dsr, &p_cuser->dsr);
1393 if (error) return error;
1394 PUT_USER(error,cnow.rng, &p_cuser->rng);
1395 if (error) return error;
1396 PUT_USER(error,cnow.dcd, &p_cuser->dcd);
1397 if (error) return error;
1398 PUT_USER(error,cnow.rx, &p_cuser->rx);
1399 if (error) return error;
1400 PUT_USER(error,cnow.tx, &p_cuser->tx);
1401 if (error) return error;
1402 PUT_USER(error,cnow.frame, &p_cuser->frame);
1403 if (error) return error;
1404 PUT_USER(error,cnow.overrun, &p_cuser->overrun);
1405 if (error) return error;
1406 PUT_USER(error,cnow.parity, &p_cuser->parity);
1407 if (error) return error;
1408 PUT_USER(error,cnow.brk, &p_cuser->brk);
1409 if (error) return error;
1410 PUT_USER(error,cnow.buf_overrun, &p_cuser->buf_overrun);
1411 if (error) return error;
1414 return -ENOIOCTLCMD;
1420 * /proc fs routines....
1423 static inline int line_info(char *buf, SLMP_INFO *info)
1427 unsigned long flags;
1429 ret = sprintf(buf, "%s: SCABase=%08x Mem=%08X StatusControl=%08x LCR=%08X\n"
1430 "\tIRQ=%d MaxFrameSize=%u\n",
1432 info->phys_sca_base,
1433 info->phys_memory_base,
1434 info->phys_statctrl_base,
1435 info->phys_lcr_base,
1437 info->max_frame_size );
1439 /* output current serial signal states */
1440 spin_lock_irqsave(&info->lock,flags);
1442 spin_unlock_irqrestore(&info->lock,flags);
1446 if (info->serial_signals & SerialSignal_RTS)
1447 strcat(stat_buf, "|RTS");
1448 if (info->serial_signals & SerialSignal_CTS)
1449 strcat(stat_buf, "|CTS");
1450 if (info->serial_signals & SerialSignal_DTR)
1451 strcat(stat_buf, "|DTR");
1452 if (info->serial_signals & SerialSignal_DSR)
1453 strcat(stat_buf, "|DSR");
1454 if (info->serial_signals & SerialSignal_DCD)
1455 strcat(stat_buf, "|CD");
1456 if (info->serial_signals & SerialSignal_RI)
1457 strcat(stat_buf, "|RI");
1459 if (info->params.mode == MGSL_MODE_HDLC) {
1460 ret += sprintf(buf+ret, "\tHDLC txok:%d rxok:%d",
1461 info->icount.txok, info->icount.rxok);
1462 if (info->icount.txunder)
1463 ret += sprintf(buf+ret, " txunder:%d", info->icount.txunder);
1464 if (info->icount.txabort)
1465 ret += sprintf(buf+ret, " txabort:%d", info->icount.txabort);
1466 if (info->icount.rxshort)
1467 ret += sprintf(buf+ret, " rxshort:%d", info->icount.rxshort);
1468 if (info->icount.rxlong)
1469 ret += sprintf(buf+ret, " rxlong:%d", info->icount.rxlong);
1470 if (info->icount.rxover)
1471 ret += sprintf(buf+ret, " rxover:%d", info->icount.rxover);
1472 if (info->icount.rxcrc)
1473 ret += sprintf(buf+ret, " rxlong:%d", info->icount.rxcrc);
1475 ret += sprintf(buf+ret, "\tASYNC tx:%d rx:%d",
1476 info->icount.tx, info->icount.rx);
1477 if (info->icount.frame)
1478 ret += sprintf(buf+ret, " fe:%d", info->icount.frame);
1479 if (info->icount.parity)
1480 ret += sprintf(buf+ret, " pe:%d", info->icount.parity);
1481 if (info->icount.brk)
1482 ret += sprintf(buf+ret, " brk:%d", info->icount.brk);
1483 if (info->icount.overrun)
1484 ret += sprintf(buf+ret, " oe:%d", info->icount.overrun);
1487 /* Append serial signal status to end */
1488 ret += sprintf(buf+ret, " %s\n", stat_buf+1);
1490 ret += sprintf(buf+ret, "\ttxactive=%d bh_req=%d bh_run=%d pending_bh=%x\n",
1491 info->tx_active,info->bh_requested,info->bh_running,
1497 /* Called to print information about devices
1499 int read_proc(char *page, char **start, off_t off, int count,
1500 int *eof, void *data)
1506 len += sprintf(page, "synclinkmp driver:%s\n", driver_version);
1508 info = synclinkmp_device_list;
1510 l = line_info(page + len, info);
1512 if (len+begin > off+count)
1514 if (len+begin < off) {
1518 info = info->next_device;
1523 if (off >= len+begin)
1525 *start = page + (off-begin);
1526 return ((count < begin+len-off) ? count : begin+len-off);
1529 /* Return the count of bytes in transmit buffer
1531 static int chars_in_buffer(struct tty_struct *tty)
1533 SLMP_INFO *info = (SLMP_INFO *)tty->driver_data;
1535 if (sanity_check(info, tty->name, "chars_in_buffer"))
1538 if (debug_level >= DEBUG_LEVEL_INFO)
1539 printk("%s(%d):%s chars_in_buffer()=%d\n",
1540 __FILE__, __LINE__, info->device_name, info->tx_count);
1542 return info->tx_count;
1545 /* Signal remote device to throttle send data (our receive data)
1547 static void throttle(struct tty_struct * tty)
1549 SLMP_INFO *info = (SLMP_INFO *)tty->driver_data;
1550 unsigned long flags;
1552 if (debug_level >= DEBUG_LEVEL_INFO)
1553 printk("%s(%d):%s throttle() entry\n",
1554 __FILE__,__LINE__, info->device_name );
1556 if (sanity_check(info, tty->name, "throttle"))
1560 send_xchar(tty, STOP_CHAR(tty));
1562 if (tty->termios->c_cflag & CRTSCTS) {
1563 spin_lock_irqsave(&info->lock,flags);
1564 info->serial_signals &= ~SerialSignal_RTS;
1566 spin_unlock_irqrestore(&info->lock,flags);
1570 /* Signal remote device to stop throttling send data (our receive data)
1572 static void unthrottle(struct tty_struct * tty)
1574 SLMP_INFO *info = (SLMP_INFO *)tty->driver_data;
1575 unsigned long flags;
1577 if (debug_level >= DEBUG_LEVEL_INFO)
1578 printk("%s(%d):%s unthrottle() entry\n",
1579 __FILE__,__LINE__, info->device_name );
1581 if (sanity_check(info, tty->name, "unthrottle"))
1588 send_xchar(tty, START_CHAR(tty));
1591 if (tty->termios->c_cflag & CRTSCTS) {
1592 spin_lock_irqsave(&info->lock,flags);
1593 info->serial_signals |= SerialSignal_RTS;
1595 spin_unlock_irqrestore(&info->lock,flags);
1599 /* set or clear transmit break condition
1600 * break_state -1=set break condition, 0=clear
1602 static void set_break(struct tty_struct *tty, int break_state)
1604 unsigned char RegValue;
1605 SLMP_INFO * info = (SLMP_INFO *)tty->driver_data;
1606 unsigned long flags;
1608 if (debug_level >= DEBUG_LEVEL_INFO)
1609 printk("%s(%d):%s set_break(%d)\n",
1610 __FILE__,__LINE__, info->device_name, break_state);
1612 if (sanity_check(info, tty->name, "set_break"))
1615 spin_lock_irqsave(&info->lock,flags);
1616 RegValue = read_reg(info, CTL);
1617 if (break_state == -1)
1621 write_reg(info, CTL, RegValue);
1622 spin_unlock_irqrestore(&info->lock,flags);
1625 #ifdef CONFIG_SYNCLINK_SYNCPPP
1627 /* syncppp support and callbacks */
1629 static void cb_setup(struct net_device *dev)
1631 dev->open = sppp_cb_open;
1632 dev->stop = sppp_cb_close;
1633 dev->hard_start_xmit = sppp_cb_tx;
1634 dev->do_ioctl = sppp_cb_ioctl;
1635 dev->get_stats = sppp_cb_net_stats;
1636 dev->tx_timeout = sppp_cb_tx_timeout;
1637 dev->watchdog_timeo = 10*HZ;
1640 static void sppp_init(SLMP_INFO *info)
1642 struct net_device *d;
1644 sprintf(info->netname,"mgslm%dp%d",info->adapter_num,info->port_num);
1646 d = alloc_netdev(0, info->netname, cb_setup);
1648 printk(KERN_WARNING "%s: alloc_netdev failed.\n",
1653 info->if_ptr = &info->pppdev;
1654 info->netdev = info->pppdev.dev = d;
1656 d->irq = info->irq_level;
1659 sppp_attach(&info->pppdev);
1662 if (register_netdev(d)) {
1663 printk(KERN_WARNING "%s: register_netdev failed.\n", d->name);
1664 sppp_detach(info->netdev);
1665 info->netdev = NULL;
1666 info->pppdev.dev = NULL;
1671 if (debug_level >= DEBUG_LEVEL_INFO)
1672 printk("sppp_init(%s)\n",info->netname);
1675 static void sppp_delete(SLMP_INFO *info)
1677 if (debug_level >= DEBUG_LEVEL_INFO)
1678 printk("sppp_delete(%s)\n",info->netname);
1679 unregister_netdev(info->netdev);
1680 sppp_detach(info->netdev);
1681 free_netdev(info->netdev);
1682 info->netdev = NULL;
1683 info->pppdev.dev = NULL;
1686 static int sppp_cb_open(struct net_device *d)
1688 SLMP_INFO *info = d->priv;
1690 unsigned long flags;
1692 if (debug_level >= DEBUG_LEVEL_INFO)
1693 printk("sppp_cb_open(%s)\n",info->netname);
1695 spin_lock_irqsave(&info->netlock, flags);
1696 if (info->count != 0 || info->netcount != 0) {
1697 printk(KERN_WARNING "%s: sppp_cb_open returning busy\n", info->netname);
1698 spin_unlock_irqrestore(&info->netlock, flags);
1702 spin_unlock_irqrestore(&info->netlock, flags);
1704 /* claim resources and init adapter */
1705 if ((err = startup(info)) != 0)
1708 /* allow syncppp module to do open processing */
1709 if ((err = sppp_open(d)) != 0) {
1714 info->serial_signals |= SerialSignal_RTS + SerialSignal_DTR;
1717 d->trans_start = jiffies;
1718 netif_start_queue(d);
1722 spin_lock_irqsave(&info->netlock, flags);
1724 spin_unlock_irqrestore(&info->netlock, flags);
1728 static void sppp_cb_tx_timeout(struct net_device *dev)
1730 SLMP_INFO *info = dev->priv;
1731 unsigned long flags;
1733 if (debug_level >= DEBUG_LEVEL_INFO)
1734 printk("sppp_tx_timeout(%s)\n",info->netname);
1736 info->netstats.tx_errors++;
1737 info->netstats.tx_aborted_errors++;
1739 spin_lock_irqsave(&info->lock,flags);
1741 spin_unlock_irqrestore(&info->lock,flags);
1743 netif_wake_queue(dev);
1746 static int sppp_cb_tx(struct sk_buff *skb, struct net_device *dev)
1748 SLMP_INFO *info = dev->priv;
1749 unsigned long flags;
1751 if (debug_level >= DEBUG_LEVEL_INFO)
1752 printk("sppp_tx(%s)\n",info->netname);
1754 netif_stop_queue(dev);
1756 info->tx_count = skb->len;
1757 tx_load_dma_buffer(info, skb->data, skb->len);
1758 info->netstats.tx_packets++;
1759 info->netstats.tx_bytes += skb->len;
1762 dev->trans_start = jiffies;
1764 spin_lock_irqsave(&info->lock,flags);
1765 if (!info->tx_active)
1767 spin_unlock_irqrestore(&info->lock,flags);
1772 static int sppp_cb_close(struct net_device *d)
1774 SLMP_INFO *info = d->priv;
1775 unsigned long flags;
1777 if (debug_level >= DEBUG_LEVEL_INFO)
1778 printk("sppp_cb_close(%s)\n",info->netname);
1780 /* shutdown adapter and release resources */
1783 /* allow syncppp to do close processing */
1785 netif_stop_queue(d);
1787 spin_lock_irqsave(&info->netlock, flags);
1789 spin_unlock_irqrestore(&info->netlock, flags);
1793 static void sppp_rx_done(SLMP_INFO *info, char *buf, int size)
1795 struct sk_buff *skb = dev_alloc_skb(size);
1796 if (debug_level >= DEBUG_LEVEL_INFO)
1797 printk("sppp_rx_done(%s)\n",info->netname);
1799 printk(KERN_NOTICE "%s: can't alloc skb, dropping packet\n",
1801 info->netstats.rx_dropped++;
1805 memcpy(skb_put(skb, size),buf,size);
1807 skb->protocol = htons(ETH_P_WAN_PPP);
1808 skb->dev = info->netdev;
1809 skb->mac.raw = skb->data;
1810 info->netstats.rx_packets++;
1811 info->netstats.rx_bytes += size;
1813 info->netdev->trans_start = jiffies;
1816 static void sppp_tx_done(SLMP_INFO *info)
1818 if (netif_queue_stopped(info->netdev))
1819 netif_wake_queue(info->netdev);
1822 static struct net_device_stats *sppp_cb_net_stats(struct net_device *dev)
1824 SLMP_INFO *info = dev->priv;
1825 if (debug_level >= DEBUG_LEVEL_INFO)
1826 printk("net_stats(%s)\n",info->netname);
1827 return &info->netstats;
1830 static int sppp_cb_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1832 SLMP_INFO *info = dev->priv;
1833 if (debug_level >= DEBUG_LEVEL_INFO)
1834 printk("%s(%d):ioctl %s cmd=%08X\n", __FILE__,__LINE__,
1835 info->netname, cmd );
1836 return sppp_do_ioctl(dev, ifr, cmd);
1839 #endif /* ifdef CONFIG_SYNCLINK_SYNCPPP */
1842 /* Return next bottom half action to perform.
1843 * Return Value: BH action code or 0 if nothing to do.
1845 int bh_action(SLMP_INFO *info)
1847 unsigned long flags;
1850 spin_lock_irqsave(&info->lock,flags);
1852 if (info->pending_bh & BH_RECEIVE) {
1853 info->pending_bh &= ~BH_RECEIVE;
1855 } else if (info->pending_bh & BH_TRANSMIT) {
1856 info->pending_bh &= ~BH_TRANSMIT;
1858 } else if (info->pending_bh & BH_STATUS) {
1859 info->pending_bh &= ~BH_STATUS;
1864 /* Mark BH routine as complete */
1865 info->bh_running = 0;
1866 info->bh_requested = 0;
1869 spin_unlock_irqrestore(&info->lock,flags);
1874 /* Perform bottom half processing of work items queued by ISR.
1876 void bh_handler(void* Context)
1878 SLMP_INFO *info = (SLMP_INFO*)Context;
1884 if ( debug_level >= DEBUG_LEVEL_BH )
1885 printk( "%s(%d):%s bh_handler() entry\n",
1886 __FILE__,__LINE__,info->device_name);
1888 info->bh_running = 1;
1890 while((action = bh_action(info)) != 0) {
1892 /* Process work item */
1893 if ( debug_level >= DEBUG_LEVEL_BH )
1894 printk( "%s(%d):%s bh_handler() work item action=%d\n",
1895 __FILE__,__LINE__,info->device_name, action);
1909 /* unknown work item ID */
1910 printk("%s(%d):%s Unknown work item ID=%08X!\n",
1911 __FILE__,__LINE__,info->device_name,action);
1916 if ( debug_level >= DEBUG_LEVEL_BH )
1917 printk( "%s(%d):%s bh_handler() exit\n",
1918 __FILE__,__LINE__,info->device_name);
1921 void bh_receive(SLMP_INFO *info)
1923 if ( debug_level >= DEBUG_LEVEL_BH )
1924 printk( "%s(%d):%s bh_receive()\n",
1925 __FILE__,__LINE__,info->device_name);
1927 while( rx_get_frame(info) );
1930 void bh_transmit(SLMP_INFO *info)
1932 struct tty_struct *tty = info->tty;
1934 if ( debug_level >= DEBUG_LEVEL_BH )
1935 printk( "%s(%d):%s bh_transmit() entry\n",
1936 __FILE__,__LINE__,info->device_name);
1939 if ((tty->flags & (1 << TTY_DO_WRITE_WAKEUP)) &&
1940 tty->ldisc.write_wakeup) {
1941 if ( debug_level >= DEBUG_LEVEL_BH )
1942 printk( "%s(%d):%s calling ldisc.write_wakeup\n",
1943 __FILE__,__LINE__,info->device_name);
1944 (tty->ldisc.write_wakeup)(tty);
1946 wake_up_interruptible(&tty->write_wait);
1950 void bh_status(SLMP_INFO *info)
1952 if ( debug_level >= DEBUG_LEVEL_BH )
1953 printk( "%s(%d):%s bh_status() entry\n",
1954 __FILE__,__LINE__,info->device_name);
1956 info->ri_chkcount = 0;
1957 info->dsr_chkcount = 0;
1958 info->dcd_chkcount = 0;
1959 info->cts_chkcount = 0;
1962 void isr_timer(SLMP_INFO * info)
1964 unsigned char timer = (info->port_num & 1) ? TIMER2 : TIMER0;
1966 /* IER2<7..4> = timer<3..0> interrupt enables (0=disabled) */
1967 write_reg(info, IER2, 0);
1969 /* TMCS, Timer Control/Status Register
1971 * 07 CMF, Compare match flag (read only) 1=match
1972 * 06 ECMI, CMF Interrupt Enable: 0=disabled
1973 * 05 Reserved, must be 0
1974 * 04 TME, Timer Enable
1975 * 03..00 Reserved, must be 0
1979 write_reg(info, (unsigned char)(timer + TMCS), 0);
1981 info->irq_occurred = TRUE;
1983 if ( debug_level >= DEBUG_LEVEL_ISR )
1984 printk("%s(%d):%s isr_timer()\n",
1985 __FILE__,__LINE__,info->device_name);
1988 void isr_rxint(SLMP_INFO * info)
1990 struct tty_struct *tty = info->tty;
1991 struct mgsl_icount *icount = &info->icount;
1992 unsigned char status = read_reg(info, SR1);
1993 unsigned char status2 = read_reg(info, SR2);
1995 /* clear status bits */
1996 if ( status & (FLGD + IDLD + CDCD + BRKD) )
1997 write_reg(info, SR1,
1998 (unsigned char)(status & (FLGD + IDLD + CDCD + BRKD)));
2000 if ( status2 & OVRN )
2001 write_reg(info, SR2, (unsigned char)(status2 & OVRN));
2003 if ( debug_level >= DEBUG_LEVEL_ISR )
2004 printk("%s(%d):%s isr_rxint status=%02X %02x\n",
2005 __FILE__,__LINE__,info->device_name,status,status2);
2007 if (info->params.mode == MGSL_MODE_ASYNC) {
2008 if (status & BRKD) {
2011 /* process break detection if tty control
2012 * is not set to ignore it
2015 if (!(status & info->ignore_status_mask1)) {
2016 if (info->read_status_mask1 & BRKD) {
2017 *tty->flip.flag_buf_ptr = TTY_BREAK;
2018 if (info->flags & ASYNC_SAK)
2026 if (status & (FLGD|IDLD)) {
2028 info->icount.exithunt++;
2029 else if (status & IDLD)
2030 info->icount.rxidle++;
2031 wake_up_interruptible(&info->event_wait_q);
2035 if (status & CDCD) {
2036 /* simulate a common modem status change interrupt
2039 get_signals( info );
2041 MISCSTATUS_DCD_LATCHED|(info->serial_signals&SerialSignal_DCD));
2046 * handle async rx data interrupts
2048 void isr_rxrdy(SLMP_INFO * info)
2051 unsigned char DataByte;
2052 struct tty_struct *tty = info->tty;
2053 struct mgsl_icount *icount = &info->icount;
2055 if ( debug_level >= DEBUG_LEVEL_ISR )
2056 printk("%s(%d):%s isr_rxrdy\n",
2057 __FILE__,__LINE__,info->device_name);
2059 while((status = read_reg(info,CST0)) & BIT0)
2061 DataByte = read_reg(info,TRB);
2064 if (tty->flip.count >= TTY_FLIPBUF_SIZE)
2067 *tty->flip.char_buf_ptr = DataByte;
2068 *tty->flip.flag_buf_ptr = 0;
2073 if ( status & (PE + FRME + OVRN) ) {
2074 printk("%s(%d):%s rxerr=%04X\n",
2075 __FILE__,__LINE__,info->device_name,status);
2077 /* update error statistics */
2080 else if (status & FRME)
2082 else if (status & OVRN)
2085 /* discard char if tty control flags say so */
2086 if (status & info->ignore_status_mask2)
2089 status &= info->read_status_mask2;
2093 *tty->flip.flag_buf_ptr = TTY_PARITY;
2094 else if (status & FRME)
2095 *tty->flip.flag_buf_ptr = TTY_FRAME;
2096 if (status & OVRN) {
2097 /* Overrun is special, since it's
2098 * reported immediately, and doesn't
2099 * affect the current character
2101 if (tty->flip.count < TTY_FLIPBUF_SIZE) {
2103 tty->flip.flag_buf_ptr++;
2104 tty->flip.char_buf_ptr++;
2105 *tty->flip.flag_buf_ptr = TTY_OVERRUN;
2109 } /* end of if (error) */
2112 tty->flip.flag_buf_ptr++;
2113 tty->flip.char_buf_ptr++;
2118 if ( debug_level >= DEBUG_LEVEL_ISR ) {
2119 printk("%s(%d):%s isr_rxrdy() flip count=%d\n",
2120 __FILE__,__LINE__,info->device_name,
2121 tty ? tty->flip.count : 0);
2122 printk("%s(%d):%s rx=%d brk=%d parity=%d frame=%d overrun=%d\n",
2123 __FILE__,__LINE__,info->device_name,
2124 icount->rx,icount->brk,icount->parity,
2125 icount->frame,icount->overrun);
2128 if ( tty && tty->flip.count )
2129 tty_flip_buffer_push(tty);
2132 void isr_txeom(SLMP_INFO * info, unsigned char status)
2134 if ( debug_level >= DEBUG_LEVEL_ISR )
2135 printk("%s(%d):%s isr_txeom status=%02x\n",
2136 __FILE__,__LINE__,info->device_name,status);
2138 /* disable and clear MSCI interrupts */
2139 info->ie1_value &= ~(IDLE + UDRN);
2140 write_reg(info, IE1, info->ie1_value);
2141 write_reg(info, SR1, (unsigned char)(UDRN + IDLE));
2143 write_reg(info, TXDMA + DIR, 0x00); /* disable Tx DMA IRQs */
2144 write_reg(info, TXDMA + DSR, 0xc0); /* clear IRQs and disable DMA */
2145 write_reg(info, TXDMA + DCMD, SWABORT); /* reset/init DMA channel */
2147 if ( info->tx_active ) {
2148 if (info->params.mode != MGSL_MODE_ASYNC) {
2150 info->icount.txunder++;
2151 else if (status & IDLE)
2152 info->icount.txok++;
2155 info->tx_active = 0;
2156 info->tx_count = info->tx_put = info->tx_get = 0;
2158 del_timer(&info->tx_timer);
2160 if (info->params.mode != MGSL_MODE_ASYNC && info->drop_rts_on_tx_done ) {
2161 info->serial_signals &= ~SerialSignal_RTS;
2162 info->drop_rts_on_tx_done = 0;
2166 #ifdef CONFIG_SYNCLINK_SYNCPPP
2172 if (info->tty && (info->tty->stopped || info->tty->hw_stopped)) {
2176 info->pending_bh |= BH_TRANSMIT;
2183 * handle tx status interrupts
2185 void isr_txint(SLMP_INFO * info)
2187 unsigned char status = read_reg(info, SR1);
2189 /* clear status bits */
2190 write_reg(info, SR1, (unsigned char)(status & (UDRN + IDLE + CCTS)));
2192 if ( debug_level >= DEBUG_LEVEL_ISR )
2193 printk("%s(%d):%s isr_txint status=%02x\n",
2194 __FILE__,__LINE__,info->device_name,status);
2196 if (status & (UDRN + IDLE))
2197 isr_txeom(info, status);
2199 if (status & CCTS) {
2200 /* simulate a common modem status change interrupt
2203 get_signals( info );
2205 MISCSTATUS_CTS_LATCHED|(info->serial_signals&SerialSignal_CTS));
2211 * handle async tx data interrupts
2213 void isr_txrdy(SLMP_INFO * info)
2215 if ( debug_level >= DEBUG_LEVEL_ISR )
2216 printk("%s(%d):%s isr_txrdy() tx_count=%d\n",
2217 __FILE__,__LINE__,info->device_name,info->tx_count);
2219 if (info->tty && (info->tty->stopped || info->tty->hw_stopped)) {
2224 if ( info->tx_count )
2225 tx_load_fifo( info );
2227 info->tx_active = 0;
2228 info->ie0_value &= ~TXRDYE;
2229 write_reg(info, IE0, info->ie0_value);
2232 if (info->tx_count < WAKEUP_CHARS)
2233 info->pending_bh |= BH_TRANSMIT;
2236 void isr_rxdmaok(SLMP_INFO * info)
2238 /* BIT7 = EOT (end of transfer)
2239 * BIT6 = EOM (end of message/frame)
2241 unsigned char status = read_reg(info,RXDMA + DSR) & 0xc0;
2243 /* clear IRQ (BIT0 must be 1 to prevent clearing DE bit) */
2244 write_reg(info, RXDMA + DSR, (unsigned char)(status | 1));
2246 if ( debug_level >= DEBUG_LEVEL_ISR )
2247 printk("%s(%d):%s isr_rxdmaok(), status=%02x\n",
2248 __FILE__,__LINE__,info->device_name,status);
2250 info->pending_bh |= BH_RECEIVE;
2253 void isr_rxdmaerror(SLMP_INFO * info)
2255 /* BIT5 = BOF (buffer overflow)
2256 * BIT4 = COF (counter overflow)
2258 unsigned char status = read_reg(info,RXDMA + DSR) & 0x30;
2260 /* clear IRQ (BIT0 must be 1 to prevent clearing DE bit) */
2261 write_reg(info, RXDMA + DSR, (unsigned char)(status | 1));
2263 if ( debug_level >= DEBUG_LEVEL_ISR )
2264 printk("%s(%d):%s isr_rxdmaerror(), status=%02x\n",
2265 __FILE__,__LINE__,info->device_name,status);
2267 info->rx_overflow = TRUE;
2268 info->pending_bh |= BH_RECEIVE;
2271 void isr_txdmaok(SLMP_INFO * info)
2273 /* BIT7 = EOT (end of transfer, used for async mode)
2274 * BIT6 = EOM (end of message/frame, used for sync mode)
2276 * We don't look at DMA status because only EOT is enabled
2277 * and we always clear and disable all tx DMA IRQs.
2279 // unsigned char dma_status = read_reg(info,TXDMA + DSR) & 0xc0;
2280 unsigned char status_reg1 = read_reg(info, SR1);
2282 write_reg(info, TXDMA + DIR, 0x00); /* disable Tx DMA IRQs */
2283 write_reg(info, TXDMA + DSR, 0xc0); /* clear IRQs and disable DMA */
2284 write_reg(info, TXDMA + DCMD, SWABORT); /* reset/init DMA channel */
2286 if ( debug_level >= DEBUG_LEVEL_ISR )
2287 printk("%s(%d):%s isr_txdmaok(), status=%02x\n",
2288 __FILE__,__LINE__,info->device_name,status_reg1);
2290 /* If transmitter already idle, do end of frame processing,
2291 * otherwise enable interrupt for tx IDLE.
2293 if (status_reg1 & IDLE)
2294 isr_txeom(info, IDLE);
2296 /* disable and clear underrun IRQ, enable IDLE interrupt */
2297 info->ie1_value |= IDLE;
2298 info->ie1_value &= ~UDRN;
2299 write_reg(info, IE1, info->ie1_value);
2301 write_reg(info, SR1, UDRN);
2305 void isr_txdmaerror(SLMP_INFO * info)
2307 /* BIT5 = BOF (buffer overflow)
2308 * BIT4 = COF (counter overflow)
2310 unsigned char status = read_reg(info,TXDMA + DSR) & 0x30;
2312 /* clear IRQ (BIT0 must be 1 to prevent clearing DE bit) */
2313 write_reg(info, TXDMA + DSR, (unsigned char)(status | 1));
2315 if ( debug_level >= DEBUG_LEVEL_ISR )
2316 printk("%s(%d):%s isr_txdmaerror(), status=%02x\n",
2317 __FILE__,__LINE__,info->device_name,status);
2320 /* handle input serial signal changes
2322 void isr_io_pin( SLMP_INFO *info, u16 status )
2324 struct mgsl_icount *icount;
2326 if ( debug_level >= DEBUG_LEVEL_ISR )
2327 printk("%s(%d):isr_io_pin status=%04X\n",
2328 __FILE__,__LINE__,status);
2330 if (status & (MISCSTATUS_CTS_LATCHED | MISCSTATUS_DCD_LATCHED |
2331 MISCSTATUS_DSR_LATCHED | MISCSTATUS_RI_LATCHED) ) {
2332 icount = &info->icount;
2333 /* update input line counters */
2334 if (status & MISCSTATUS_RI_LATCHED) {
2336 if ( status & SerialSignal_RI )
2337 info->input_signal_events.ri_up++;
2339 info->input_signal_events.ri_down++;
2341 if (status & MISCSTATUS_DSR_LATCHED) {
2343 if ( status & SerialSignal_DSR )
2344 info->input_signal_events.dsr_up++;
2346 info->input_signal_events.dsr_down++;
2348 if (status & MISCSTATUS_DCD_LATCHED) {
2349 if ((info->dcd_chkcount)++ >= IO_PIN_SHUTDOWN_LIMIT) {
2350 info->ie1_value &= ~CDCD;
2351 write_reg(info, IE1, info->ie1_value);
2354 if (status & SerialSignal_DCD) {
2355 info->input_signal_events.dcd_up++;
2356 #ifdef CONFIG_SYNCLINK_SYNCPPP
2358 sppp_reopen(info->netdev);
2361 info->input_signal_events.dcd_down++;
2363 if (status & MISCSTATUS_CTS_LATCHED)
2365 if ((info->cts_chkcount)++ >= IO_PIN_SHUTDOWN_LIMIT) {
2366 info->ie1_value &= ~CCTS;
2367 write_reg(info, IE1, info->ie1_value);
2370 if ( status & SerialSignal_CTS )
2371 info->input_signal_events.cts_up++;
2373 info->input_signal_events.cts_down++;
2375 wake_up_interruptible(&info->status_event_wait_q);
2376 wake_up_interruptible(&info->event_wait_q);
2378 if ( (info->flags & ASYNC_CHECK_CD) &&
2379 (status & MISCSTATUS_DCD_LATCHED) ) {
2380 if ( debug_level >= DEBUG_LEVEL_ISR )
2381 printk("%s CD now %s...", info->device_name,
2382 (status & SerialSignal_DCD) ? "on" : "off");
2383 if (status & SerialSignal_DCD)
2384 wake_up_interruptible(&info->open_wait);
2386 if ( debug_level >= DEBUG_LEVEL_ISR )
2387 printk("doing serial hangup...");
2389 tty_hangup(info->tty);
2393 if ( (info->flags & ASYNC_CTS_FLOW) &&
2394 (status & MISCSTATUS_CTS_LATCHED) ) {
2396 if (info->tty->hw_stopped) {
2397 if (status & SerialSignal_CTS) {
2398 if ( debug_level >= DEBUG_LEVEL_ISR )
2399 printk("CTS tx start...");
2400 info->tty->hw_stopped = 0;
2402 info->pending_bh |= BH_TRANSMIT;
2406 if (!(status & SerialSignal_CTS)) {
2407 if ( debug_level >= DEBUG_LEVEL_ISR )
2408 printk("CTS tx stop...");
2409 info->tty->hw_stopped = 1;
2417 info->pending_bh |= BH_STATUS;
2420 /* Interrupt service routine entry point.
2423 * irq interrupt number that caused interrupt
2424 * dev_id device ID supplied during interrupt registration
2425 * regs interrupted processor context
2427 static irqreturn_t synclinkmp_interrupt(int irq, void *dev_id,
2428 struct pt_regs *regs)
2431 unsigned char status, status0, status1=0;
2432 unsigned char dmastatus, dmastatus0, dmastatus1=0;
2433 unsigned char timerstatus0, timerstatus1=0;
2434 unsigned char shift;
2438 if ( debug_level >= DEBUG_LEVEL_ISR )
2439 printk("%s(%d): synclinkmp_interrupt(%d)entry.\n",
2440 __FILE__,__LINE__,irq);
2442 info = (SLMP_INFO *)dev_id;
2446 spin_lock(&info->lock);
2450 /* get status for SCA0 (ports 0-1) */
2451 tmp = read_reg16(info, ISR0); /* get ISR0 and ISR1 in one read */
2452 status0 = (unsigned char)tmp;
2453 dmastatus0 = (unsigned char)(tmp>>8);
2454 timerstatus0 = read_reg(info, ISR2);
2456 if ( debug_level >= DEBUG_LEVEL_ISR )
2457 printk("%s(%d):%s status0=%02x, dmastatus0=%02x, timerstatus0=%02x\n",
2458 __FILE__,__LINE__,info->device_name,
2459 status0,dmastatus0,timerstatus0);
2461 if (info->port_count == 4) {
2462 /* get status for SCA1 (ports 2-3) */
2463 tmp = read_reg16(info->port_array[2], ISR0);
2464 status1 = (unsigned char)tmp;
2465 dmastatus1 = (unsigned char)(tmp>>8);
2466 timerstatus1 = read_reg(info->port_array[2], ISR2);
2468 if ( debug_level >= DEBUG_LEVEL_ISR )
2469 printk("%s(%d):%s status1=%02x, dmastatus1=%02x, timerstatus1=%02x\n",
2470 __FILE__,__LINE__,info->device_name,
2471 status1,dmastatus1,timerstatus1);
2474 if (!status0 && !dmastatus0 && !timerstatus0 &&
2475 !status1 && !dmastatus1 && !timerstatus1)
2478 for(i=0; i < info->port_count ; i++) {
2479 if (info->port_array[i] == NULL)
2483 dmastatus = dmastatus0;
2486 dmastatus = dmastatus1;
2489 shift = i & 1 ? 4 :0;
2491 if (status & BIT0 << shift)
2492 isr_rxrdy(info->port_array[i]);
2493 if (status & BIT1 << shift)
2494 isr_txrdy(info->port_array[i]);
2495 if (status & BIT2 << shift)
2496 isr_rxint(info->port_array[i]);
2497 if (status & BIT3 << shift)
2498 isr_txint(info->port_array[i]);
2500 if (dmastatus & BIT0 << shift)
2501 isr_rxdmaerror(info->port_array[i]);
2502 if (dmastatus & BIT1 << shift)
2503 isr_rxdmaok(info->port_array[i]);
2504 if (dmastatus & BIT2 << shift)
2505 isr_txdmaerror(info->port_array[i]);
2506 if (dmastatus & BIT3 << shift)
2507 isr_txdmaok(info->port_array[i]);
2510 if (timerstatus0 & (BIT5 | BIT4))
2511 isr_timer(info->port_array[0]);
2512 if (timerstatus0 & (BIT7 | BIT6))
2513 isr_timer(info->port_array[1]);
2514 if (timerstatus1 & (BIT5 | BIT4))
2515 isr_timer(info->port_array[2]);
2516 if (timerstatus1 & (BIT7 | BIT6))
2517 isr_timer(info->port_array[3]);
2520 for(i=0; i < info->port_count ; i++) {
2521 SLMP_INFO * port = info->port_array[i];
2523 /* Request bottom half processing if there's something
2524 * for it to do and the bh is not already running.
2526 * Note: startup adapter diags require interrupts.
2527 * do not request bottom half processing if the
2528 * device is not open in a normal mode.
2530 if ( port && (port->count || port->netcount) &&
2531 port->pending_bh && !port->bh_running &&
2532 !port->bh_requested ) {
2533 if ( debug_level >= DEBUG_LEVEL_ISR )
2534 printk("%s(%d):%s queueing bh task.\n",
2535 __FILE__,__LINE__,port->device_name);
2536 schedule_work(&port->task);
2537 port->bh_requested = 1;
2541 spin_unlock(&info->lock);
2543 if ( debug_level >= DEBUG_LEVEL_ISR )
2544 printk("%s(%d):synclinkmp_interrupt(%d)exit.\n",
2545 __FILE__,__LINE__,irq);
2549 /* Initialize and start device.
2551 static int startup(SLMP_INFO * info)
2553 if ( debug_level >= DEBUG_LEVEL_INFO )
2554 printk("%s(%d):%s tx_releaseup()\n",__FILE__,__LINE__,info->device_name);
2556 if (info->flags & ASYNC_INITIALIZED)
2559 if (!info->tx_buf) {
2560 info->tx_buf = (unsigned char *)kmalloc(info->max_frame_size, GFP_KERNEL);
2561 if (!info->tx_buf) {
2562 printk(KERN_ERR"%s(%d):%s can't allocate transmit buffer\n",
2563 __FILE__,__LINE__,info->device_name);
2568 info->pending_bh = 0;
2570 /* program hardware for current parameters */
2573 change_params(info);
2575 info->status_timer.expires = jiffies + jiffies_from_ms(10);
2576 add_timer(&info->status_timer);
2579 clear_bit(TTY_IO_ERROR, &info->tty->flags);
2581 info->flags |= ASYNC_INITIALIZED;
2586 /* Called by close() and hangup() to shutdown hardware
2588 static void shutdown(SLMP_INFO * info)
2590 unsigned long flags;
2592 if (!(info->flags & ASYNC_INITIALIZED))
2595 if (debug_level >= DEBUG_LEVEL_INFO)
2596 printk("%s(%d):%s synclinkmp_shutdown()\n",
2597 __FILE__,__LINE__, info->device_name );
2599 /* clear status wait queue because status changes */
2600 /* can't happen after shutting down the hardware */
2601 wake_up_interruptible(&info->status_event_wait_q);
2602 wake_up_interruptible(&info->event_wait_q);
2604 del_timer(&info->tx_timer);
2605 del_timer(&info->status_timer);
2608 kfree(info->tx_buf);
2612 spin_lock_irqsave(&info->lock,flags);
2616 if (!info->tty || info->tty->termios->c_cflag & HUPCL) {
2617 info->serial_signals &= ~(SerialSignal_DTR + SerialSignal_RTS);
2621 spin_unlock_irqrestore(&info->lock,flags);
2624 set_bit(TTY_IO_ERROR, &info->tty->flags);
2626 info->flags &= ~ASYNC_INITIALIZED;
2629 static void program_hw(SLMP_INFO *info)
2631 unsigned long flags;
2633 spin_lock_irqsave(&info->lock,flags);
2638 info->tx_count = info->tx_put = info->tx_get = 0;
2640 if (info->params.mode == MGSL_MODE_HDLC || info->netcount)
2647 info->dcd_chkcount = 0;
2648 info->cts_chkcount = 0;
2649 info->ri_chkcount = 0;
2650 info->dsr_chkcount = 0;
2652 info->ie1_value |= (CDCD|CCTS);
2653 write_reg(info, IE1, info->ie1_value);
2657 if (info->netcount || (info->tty && info->tty->termios->c_cflag & CREAD) )
2660 spin_unlock_irqrestore(&info->lock,flags);
2663 /* Reconfigure adapter based on new parameters
2665 static void change_params(SLMP_INFO *info)
2670 if (!info->tty || !info->tty->termios)
2673 if (debug_level >= DEBUG_LEVEL_INFO)
2674 printk("%s(%d):%s change_params()\n",
2675 __FILE__,__LINE__, info->device_name );
2677 cflag = info->tty->termios->c_cflag;
2679 /* if B0 rate (hangup) specified then negate DTR and RTS */
2680 /* otherwise assert DTR and RTS */
2682 info->serial_signals |= SerialSignal_RTS + SerialSignal_DTR;
2684 info->serial_signals &= ~(SerialSignal_RTS + SerialSignal_DTR);
2686 /* byte size and parity */
2688 switch (cflag & CSIZE) {
2689 case CS5: info->params.data_bits = 5; break;
2690 case CS6: info->params.data_bits = 6; break;
2691 case CS7: info->params.data_bits = 7; break;
2692 case CS8: info->params.data_bits = 8; break;
2693 /* Never happens, but GCC is too dumb to figure it out */
2694 default: info->params.data_bits = 7; break;
2698 info->params.stop_bits = 2;
2700 info->params.stop_bits = 1;
2702 info->params.parity = ASYNC_PARITY_NONE;
2703 if (cflag & PARENB) {
2705 info->params.parity = ASYNC_PARITY_ODD;
2707 info->params.parity = ASYNC_PARITY_EVEN;
2710 info->params.parity = ASYNC_PARITY_SPACE;
2714 /* calculate number of jiffies to transmit a full
2715 * FIFO (32 bytes) at specified data rate
2717 bits_per_char = info->params.data_bits +
2718 info->params.stop_bits + 1;
2720 /* if port data rate is set to 460800 or less then
2721 * allow tty settings to override, otherwise keep the
2722 * current data rate.
2724 if (info->params.data_rate <= 460800) {
2725 info->params.data_rate = tty_get_baud_rate(info->tty);
2728 if ( info->params.data_rate ) {
2729 info->timeout = (32*HZ*bits_per_char) /
2730 info->params.data_rate;
2732 info->timeout += HZ/50; /* Add .02 seconds of slop */
2734 if (cflag & CRTSCTS)
2735 info->flags |= ASYNC_CTS_FLOW;
2737 info->flags &= ~ASYNC_CTS_FLOW;
2740 info->flags &= ~ASYNC_CHECK_CD;
2742 info->flags |= ASYNC_CHECK_CD;
2744 /* process tty input control flags */
2746 info->read_status_mask2 = OVRN;
2747 if (I_INPCK(info->tty))
2748 info->read_status_mask2 |= PE | FRME;
2749 if (I_BRKINT(info->tty) || I_PARMRK(info->tty))
2750 info->read_status_mask1 |= BRKD;
2751 if (I_IGNPAR(info->tty))
2752 info->ignore_status_mask2 |= PE | FRME;
2753 if (I_IGNBRK(info->tty)) {
2754 info->ignore_status_mask1 |= BRKD;
2755 /* If ignoring parity and break indicators, ignore
2756 * overruns too. (For real raw support).
2758 if (I_IGNPAR(info->tty))
2759 info->ignore_status_mask2 |= OVRN;
2765 static int get_stats(SLMP_INFO * info, struct mgsl_icount *user_icount)
2769 if (debug_level >= DEBUG_LEVEL_INFO)
2770 printk("%s(%d):%s get_params()\n",
2771 __FILE__,__LINE__, info->device_name);
2773 COPY_TO_USER(err,user_icount, &info->icount, sizeof(struct mgsl_icount));
2775 if ( debug_level >= DEBUG_LEVEL_INFO )
2776 printk( "%s(%d):%s get_stats() user buffer copy failed\n",
2777 __FILE__,__LINE__,info->device_name);
2784 static int get_params(SLMP_INFO * info, MGSL_PARAMS *user_params)
2787 if (debug_level >= DEBUG_LEVEL_INFO)
2788 printk("%s(%d):%s get_params()\n",
2789 __FILE__,__LINE__, info->device_name);
2791 COPY_TO_USER(err,user_params, &info->params, sizeof(MGSL_PARAMS));
2793 if ( debug_level >= DEBUG_LEVEL_INFO )
2794 printk( "%s(%d):%s get_params() user buffer copy failed\n",
2795 __FILE__,__LINE__,info->device_name);
2802 static int set_params(SLMP_INFO * info, MGSL_PARAMS *new_params)
2804 unsigned long flags;
2805 MGSL_PARAMS tmp_params;
2808 if (debug_level >= DEBUG_LEVEL_INFO)
2809 printk("%s(%d):%s set_params\n",
2810 __FILE__,__LINE__,info->device_name );
2811 COPY_FROM_USER(err,&tmp_params, new_params, sizeof(MGSL_PARAMS));
2813 if ( debug_level >= DEBUG_LEVEL_INFO )
2814 printk( "%s(%d):%s set_params() user buffer copy failed\n",
2815 __FILE__,__LINE__,info->device_name);
2819 spin_lock_irqsave(&info->lock,flags);
2820 memcpy(&info->params,&tmp_params,sizeof(MGSL_PARAMS));
2821 spin_unlock_irqrestore(&info->lock,flags);
2823 change_params(info);
2828 static int get_txidle(SLMP_INFO * info, int*idle_mode)
2832 if (debug_level >= DEBUG_LEVEL_INFO)
2833 printk("%s(%d):%s get_txidle()=%d\n",
2834 __FILE__,__LINE__, info->device_name, info->idle_mode);
2836 COPY_TO_USER(err,idle_mode, &info->idle_mode, sizeof(int));
2838 if ( debug_level >= DEBUG_LEVEL_INFO )
2839 printk( "%s(%d):%s get_txidle() user buffer copy failed\n",
2840 __FILE__,__LINE__,info->device_name);
2847 static int set_txidle(SLMP_INFO * info, int idle_mode)
2849 unsigned long flags;
2851 if (debug_level >= DEBUG_LEVEL_INFO)
2852 printk("%s(%d):%s set_txidle(%d)\n",
2853 __FILE__,__LINE__,info->device_name, idle_mode );
2855 spin_lock_irqsave(&info->lock,flags);
2856 info->idle_mode = idle_mode;
2857 tx_set_idle( info );
2858 spin_unlock_irqrestore(&info->lock,flags);
2862 static int tx_enable(SLMP_INFO * info, int enable)
2864 unsigned long flags;
2866 if (debug_level >= DEBUG_LEVEL_INFO)
2867 printk("%s(%d):%s tx_enable(%d)\n",
2868 __FILE__,__LINE__,info->device_name, enable);
2870 spin_lock_irqsave(&info->lock,flags);
2872 if ( !info->tx_enabled ) {
2876 if ( info->tx_enabled )
2879 spin_unlock_irqrestore(&info->lock,flags);
2883 /* abort send HDLC frame
2885 static int tx_abort(SLMP_INFO * info)
2887 unsigned long flags;
2889 if (debug_level >= DEBUG_LEVEL_INFO)
2890 printk("%s(%d):%s tx_abort()\n",
2891 __FILE__,__LINE__,info->device_name);
2893 spin_lock_irqsave(&info->lock,flags);
2894 if ( info->tx_active && info->params.mode == MGSL_MODE_HDLC ) {
2895 info->ie1_value &= ~UDRN;
2896 info->ie1_value |= IDLE;
2897 write_reg(info, IE1, info->ie1_value); /* disable tx status interrupts */
2898 write_reg(info, SR1, (unsigned char)(IDLE + UDRN)); /* clear pending */
2900 write_reg(info, TXDMA + DSR, 0); /* disable DMA channel */
2901 write_reg(info, TXDMA + DCMD, SWABORT); /* reset/init DMA channel */
2903 write_reg(info, CMD, TXABORT);
2905 spin_unlock_irqrestore(&info->lock,flags);
2909 static int rx_enable(SLMP_INFO * info, int enable)
2911 unsigned long flags;
2913 if (debug_level >= DEBUG_LEVEL_INFO)
2914 printk("%s(%d):%s rx_enable(%d)\n",
2915 __FILE__,__LINE__,info->device_name,enable);
2917 spin_lock_irqsave(&info->lock,flags);
2919 if ( !info->rx_enabled )
2922 if ( info->rx_enabled )
2925 spin_unlock_irqrestore(&info->lock,flags);
2929 static int map_status(int signals)
2931 /* Map status bits to API event bits */
2933 return ((signals & SerialSignal_DSR) ? MgslEvent_DsrActive : MgslEvent_DsrInactive) +
2934 ((signals & SerialSignal_CTS) ? MgslEvent_CtsActive : MgslEvent_CtsInactive) +
2935 ((signals & SerialSignal_DCD) ? MgslEvent_DcdActive : MgslEvent_DcdInactive) +
2936 ((signals & SerialSignal_RI) ? MgslEvent_RiActive : MgslEvent_RiInactive);
2939 /* wait for specified event to occur
2941 static int wait_mgsl_event(SLMP_INFO * info, int * mask_ptr)
2943 unsigned long flags;
2946 struct mgsl_icount cprev, cnow;
2949 struct _input_signal_events oldsigs, newsigs;
2950 DECLARE_WAITQUEUE(wait, current);
2952 COPY_FROM_USER(rc,&mask, mask_ptr, sizeof(int));
2957 if (debug_level >= DEBUG_LEVEL_INFO)
2958 printk("%s(%d):%s wait_mgsl_event(%d)\n",
2959 __FILE__,__LINE__,info->device_name,mask);
2961 spin_lock_irqsave(&info->lock,flags);
2963 /* return immediately if state matches requested events */
2965 s = map_status(info->serial_signals);
2968 ( ((s & SerialSignal_DSR) ? MgslEvent_DsrActive:MgslEvent_DsrInactive) +
2969 ((s & SerialSignal_DCD) ? MgslEvent_DcdActive:MgslEvent_DcdInactive) +
2970 ((s & SerialSignal_CTS) ? MgslEvent_CtsActive:MgslEvent_CtsInactive) +
2971 ((s & SerialSignal_RI) ? MgslEvent_RiActive :MgslEvent_RiInactive) );
2973 spin_unlock_irqrestore(&info->lock,flags);
2977 /* save current irq counts */
2978 cprev = info->icount;
2979 oldsigs = info->input_signal_events;
2981 /* enable hunt and idle irqs if needed */
2982 if (mask & (MgslEvent_ExitHuntMode+MgslEvent_IdleReceived)) {
2983 unsigned char oldval = info->ie1_value;
2984 unsigned char newval = oldval +
2985 (mask & MgslEvent_ExitHuntMode ? FLGD:0) +
2986 (mask & MgslEvent_IdleReceived ? IDLE:0);
2987 if ( oldval != newval ) {
2988 info->ie1_value = newval;
2989 write_reg(info, IE1, info->ie1_value);
2993 set_current_state(TASK_INTERRUPTIBLE);
2994 add_wait_queue(&info->event_wait_q, &wait);
2996 spin_unlock_irqrestore(&info->lock,flags);
3000 if (signal_pending(current)) {
3005 /* get current irq counts */
3006 spin_lock_irqsave(&info->lock,flags);
3007 cnow = info->icount;
3008 newsigs = info->input_signal_events;
3009 set_current_state(TASK_INTERRUPTIBLE);
3010 spin_unlock_irqrestore(&info->lock,flags);
3012 /* if no change, wait aborted for some reason */
3013 if (newsigs.dsr_up == oldsigs.dsr_up &&
3014 newsigs.dsr_down == oldsigs.dsr_down &&
3015 newsigs.dcd_up == oldsigs.dcd_up &&
3016 newsigs.dcd_down == oldsigs.dcd_down &&
3017 newsigs.cts_up == oldsigs.cts_up &&
3018 newsigs.cts_down == oldsigs.cts_down &&
3019 newsigs.ri_up == oldsigs.ri_up &&
3020 newsigs.ri_down == oldsigs.ri_down &&
3021 cnow.exithunt == cprev.exithunt &&
3022 cnow.rxidle == cprev.rxidle) {
3028 ( (newsigs.dsr_up != oldsigs.dsr_up ? MgslEvent_DsrActive:0) +
3029 (newsigs.dsr_down != oldsigs.dsr_down ? MgslEvent_DsrInactive:0) +
3030 (newsigs.dcd_up != oldsigs.dcd_up ? MgslEvent_DcdActive:0) +
3031 (newsigs.dcd_down != oldsigs.dcd_down ? MgslEvent_DcdInactive:0) +
3032 (newsigs.cts_up != oldsigs.cts_up ? MgslEvent_CtsActive:0) +
3033 (newsigs.cts_down != oldsigs.cts_down ? MgslEvent_CtsInactive:0) +
3034 (newsigs.ri_up != oldsigs.ri_up ? MgslEvent_RiActive:0) +
3035 (newsigs.ri_down != oldsigs.ri_down ? MgslEvent_RiInactive:0) +
3036 (cnow.exithunt != cprev.exithunt ? MgslEvent_ExitHuntMode:0) +
3037 (cnow.rxidle != cprev.rxidle ? MgslEvent_IdleReceived:0) );
3045 remove_wait_queue(&info->event_wait_q, &wait);
3046 set_current_state(TASK_RUNNING);
3049 if (mask & (MgslEvent_ExitHuntMode + MgslEvent_IdleReceived)) {
3050 spin_lock_irqsave(&info->lock,flags);
3051 if (!waitqueue_active(&info->event_wait_q)) {
3052 /* disable enable exit hunt mode/idle rcvd IRQs */
3053 info->ie1_value &= ~(FLGD|IDLE);
3054 write_reg(info, IE1, info->ie1_value);
3056 spin_unlock_irqrestore(&info->lock,flags);
3060 PUT_USER(rc, events, mask_ptr);
3065 static int modem_input_wait(SLMP_INFO *info,int arg)
3067 unsigned long flags;
3069 struct mgsl_icount cprev, cnow;
3070 DECLARE_WAITQUEUE(wait, current);
3072 /* save current irq counts */
3073 spin_lock_irqsave(&info->lock,flags);
3074 cprev = info->icount;
3075 add_wait_queue(&info->status_event_wait_q, &wait);
3076 set_current_state(TASK_INTERRUPTIBLE);
3077 spin_unlock_irqrestore(&info->lock,flags);
3081 if (signal_pending(current)) {
3086 /* get new irq counts */
3087 spin_lock_irqsave(&info->lock,flags);
3088 cnow = info->icount;
3089 set_current_state(TASK_INTERRUPTIBLE);
3090 spin_unlock_irqrestore(&info->lock,flags);
3092 /* if no change, wait aborted for some reason */
3093 if (cnow.rng == cprev.rng && cnow.dsr == cprev.dsr &&
3094 cnow.dcd == cprev.dcd && cnow.cts == cprev.cts) {
3099 /* check for change in caller specified modem input */
3100 if ((arg & TIOCM_RNG && cnow.rng != cprev.rng) ||
3101 (arg & TIOCM_DSR && cnow.dsr != cprev.dsr) ||
3102 (arg & TIOCM_CD && cnow.dcd != cprev.dcd) ||
3103 (arg & TIOCM_CTS && cnow.cts != cprev.cts)) {
3110 remove_wait_queue(&info->status_event_wait_q, &wait);
3111 set_current_state(TASK_RUNNING);
3115 /* return the state of the serial control and status signals
3117 static int tiocmget(struct tty_struct *tty, struct file *file)
3119 SLMP_INFO *info = (SLMP_INFO *)tty->driver_data;
3120 unsigned int result;
3121 unsigned long flags;
3123 spin_lock_irqsave(&info->lock,flags);
3125 spin_unlock_irqrestore(&info->lock,flags);
3127 result = ((info->serial_signals & SerialSignal_RTS) ? TIOCM_RTS:0) +
3128 ((info->serial_signals & SerialSignal_DTR) ? TIOCM_DTR:0) +
3129 ((info->serial_signals & SerialSignal_DCD) ? TIOCM_CAR:0) +
3130 ((info->serial_signals & SerialSignal_RI) ? TIOCM_RNG:0) +
3131 ((info->serial_signals & SerialSignal_DSR) ? TIOCM_DSR:0) +
3132 ((info->serial_signals & SerialSignal_CTS) ? TIOCM_CTS:0);
3134 if (debug_level >= DEBUG_LEVEL_INFO)
3135 printk("%s(%d):%s tiocmget() value=%08X\n",
3136 __FILE__,__LINE__, info->device_name, result );
3140 /* set modem control signals (DTR/RTS)
3142 static int tiocmset(struct tty_struct *tty, struct file *file,
3143 unsigned int set, unsigned int clear)
3145 SLMP_INFO *info = (SLMP_INFO *)tty->driver_data;
3146 unsigned long flags;
3148 if (debug_level >= DEBUG_LEVEL_INFO)
3149 printk("%s(%d):%s tiocmset(%x,%x)\n",
3150 __FILE__,__LINE__,info->device_name, set, clear);
3152 if (set & TIOCM_RTS)
3153 info->serial_signals |= SerialSignal_RTS;
3154 if (set & TIOCM_DTR)
3155 info->serial_signals |= SerialSignal_DTR;
3156 if (clear & TIOCM_RTS)
3157 info->serial_signals &= ~SerialSignal_RTS;
3158 if (clear & TIOCM_DTR)
3159 info->serial_signals &= ~SerialSignal_DTR;
3161 spin_lock_irqsave(&info->lock,flags);
3163 spin_unlock_irqrestore(&info->lock,flags);
3170 /* Block the current process until the specified port is ready to open.
3172 static int block_til_ready(struct tty_struct *tty, struct file *filp,
3175 DECLARE_WAITQUEUE(wait, current);
3177 int do_clocal = 0, extra_count = 0;
3178 unsigned long flags;
3180 if (debug_level >= DEBUG_LEVEL_INFO)
3181 printk("%s(%d):%s block_til_ready()\n",
3182 __FILE__,__LINE__, tty->driver->name );
3184 if (filp->f_flags & O_NONBLOCK || tty->flags & (1 << TTY_IO_ERROR)){
3185 /* nonblock mode is set or port is not enabled */
3186 /* just verify that callout device is not active */
3187 info->flags |= ASYNC_NORMAL_ACTIVE;
3191 if (tty->termios->c_cflag & CLOCAL)
3194 /* Wait for carrier detect and the line to become
3195 * free (i.e., not in use by the callout). While we are in
3196 * this loop, info->count is dropped by one, so that
3197 * close() knows when to free things. We restore it upon
3198 * exit, either normal or abnormal.
3202 add_wait_queue(&info->open_wait, &wait);
3204 if (debug_level >= DEBUG_LEVEL_INFO)
3205 printk("%s(%d):%s block_til_ready() before block, count=%d\n",
3206 __FILE__,__LINE__, tty->driver->name, info->count );
3208 spin_lock_irqsave(&info->lock, flags);
3209 if (!tty_hung_up_p(filp)) {
3213 spin_unlock_irqrestore(&info->lock, flags);
3214 info->blocked_open++;
3217 if ((tty->termios->c_cflag & CBAUD)) {
3218 spin_lock_irqsave(&info->lock,flags);
3219 info->serial_signals |= SerialSignal_RTS + SerialSignal_DTR;
3221 spin_unlock_irqrestore(&info->lock,flags);
3224 set_current_state(TASK_INTERRUPTIBLE);
3226 if (tty_hung_up_p(filp) || !(info->flags & ASYNC_INITIALIZED)){
3227 retval = (info->flags & ASYNC_HUP_NOTIFY) ?
3228 -EAGAIN : -ERESTARTSYS;
3232 spin_lock_irqsave(&info->lock,flags);
3234 spin_unlock_irqrestore(&info->lock,flags);
3236 if (!(info->flags & ASYNC_CLOSING) &&
3237 (do_clocal || (info->serial_signals & SerialSignal_DCD)) ) {
3241 if (signal_pending(current)) {
3242 retval = -ERESTARTSYS;
3246 if (debug_level >= DEBUG_LEVEL_INFO)
3247 printk("%s(%d):%s block_til_ready() count=%d\n",
3248 __FILE__,__LINE__, tty->driver->name, info->count );
3253 set_current_state(TASK_RUNNING);
3254 remove_wait_queue(&info->open_wait, &wait);
3258 info->blocked_open--;
3260 if (debug_level >= DEBUG_LEVEL_INFO)
3261 printk("%s(%d):%s block_til_ready() after, count=%d\n",
3262 __FILE__,__LINE__, tty->driver->name, info->count );
3265 info->flags |= ASYNC_NORMAL_ACTIVE;
3270 int alloc_dma_bufs(SLMP_INFO *info)
3272 unsigned short BuffersPerFrame;
3273 unsigned short BufferCount;
3275 // Force allocation to start at 64K boundary for each port.
3276 // This is necessary because *all* buffer descriptors for a port
3277 // *must* be in the same 64K block. All descriptors on a port
3278 // share a common 'base' address (upper 8 bits of 24 bits) programmed
3279 // into the CBP register.
3280 info->port_array[0]->last_mem_alloc = (SCA_MEM_SIZE/4) * info->port_num;
3282 /* Calculate the number of DMA buffers necessary to hold the */
3283 /* largest allowable frame size. Note: If the max frame size is */
3284 /* not an even multiple of the DMA buffer size then we need to */
3285 /* round the buffer count per frame up one. */
3287 BuffersPerFrame = (unsigned short)(info->max_frame_size/SCABUFSIZE);
3288 if ( info->max_frame_size % SCABUFSIZE )
3291 /* calculate total number of data buffers (SCABUFSIZE) possible
3292 * in one ports memory (SCA_MEM_SIZE/4) after allocating memory
3293 * for the descriptor list (BUFFERLISTSIZE).
3295 BufferCount = (SCA_MEM_SIZE/4 - BUFFERLISTSIZE)/SCABUFSIZE;
3297 /* limit number of buffers to maximum amount of descriptors */
3298 if (BufferCount > BUFFERLISTSIZE/sizeof(SCADESC))
3299 BufferCount = BUFFERLISTSIZE/sizeof(SCADESC);
3301 /* use enough buffers to transmit one max size frame */
3302 info->tx_buf_count = BuffersPerFrame + 1;
3304 /* never use more than half the available buffers for transmit */
3305 if (info->tx_buf_count > (BufferCount/2))
3306 info->tx_buf_count = BufferCount/2;
3308 if (info->tx_buf_count > SCAMAXDESC)
3309 info->tx_buf_count = SCAMAXDESC;
3311 /* use remaining buffers for receive */
3312 info->rx_buf_count = BufferCount - info->tx_buf_count;
3314 if (info->rx_buf_count > SCAMAXDESC)
3315 info->rx_buf_count = SCAMAXDESC;
3317 if ( debug_level >= DEBUG_LEVEL_INFO )
3318 printk("%s(%d):%s Allocating %d TX and %d RX DMA buffers.\n",
3319 __FILE__,__LINE__, info->device_name,
3320 info->tx_buf_count,info->rx_buf_count);
3322 if ( alloc_buf_list( info ) < 0 ||
3323 alloc_frame_bufs(info,
3325 info->rx_buf_list_ex,
3326 info->rx_buf_count) < 0 ||
3327 alloc_frame_bufs(info,
3329 info->tx_buf_list_ex,
3330 info->tx_buf_count) < 0 ||
3331 alloc_tmp_rx_buf(info) < 0 ) {
3332 printk("%s(%d):%s Can't allocate DMA buffer memory\n",
3333 __FILE__,__LINE__, info->device_name);
3337 rx_reset_buffers( info );
3342 /* Allocate DMA buffers for the transmit and receive descriptor lists.
3344 int alloc_buf_list(SLMP_INFO *info)
3348 /* build list in adapter shared memory */
3349 info->buffer_list = info->memory_base + info->port_array[0]->last_mem_alloc;
3350 info->buffer_list_phys = info->port_array[0]->last_mem_alloc;
3351 info->port_array[0]->last_mem_alloc += BUFFERLISTSIZE;
3353 memset(info->buffer_list, 0, BUFFERLISTSIZE);
3355 /* Save virtual address pointers to the receive and */
3356 /* transmit buffer lists. (Receive 1st). These pointers will */
3357 /* be used by the processor to access the lists. */
3358 info->rx_buf_list = (SCADESC *)info->buffer_list;
3360 info->tx_buf_list = (SCADESC *)info->buffer_list;
3361 info->tx_buf_list += info->rx_buf_count;
3363 /* Build links for circular buffer entry lists (tx and rx)
3365 * Note: links are physical addresses read by the SCA device
3366 * to determine the next buffer entry to use.
3369 for ( i = 0; i < info->rx_buf_count; i++ ) {
3370 /* calculate and store physical address of this buffer entry */
3371 info->rx_buf_list_ex[i].phys_entry =
3372 info->buffer_list_phys + (i * sizeof(SCABUFSIZE));
3374 /* calculate and store physical address of */
3375 /* next entry in cirular list of entries */
3376 info->rx_buf_list[i].next = info->buffer_list_phys;
3377 if ( i < info->rx_buf_count - 1 )
3378 info->rx_buf_list[i].next += (i + 1) * sizeof(SCADESC);
3380 info->rx_buf_list[i].length = SCABUFSIZE;
3383 for ( i = 0; i < info->tx_buf_count; i++ ) {
3384 /* calculate and store physical address of this buffer entry */
3385 info->tx_buf_list_ex[i].phys_entry = info->buffer_list_phys +
3386 ((info->rx_buf_count + i) * sizeof(SCADESC));
3388 /* calculate and store physical address of */
3389 /* next entry in cirular list of entries */
3391 info->tx_buf_list[i].next = info->buffer_list_phys +
3392 info->rx_buf_count * sizeof(SCADESC);
3394 if ( i < info->tx_buf_count - 1 )
3395 info->tx_buf_list[i].next += (i + 1) * sizeof(SCADESC);
3401 /* Allocate the frame DMA buffers used by the specified buffer list.
3403 int alloc_frame_bufs(SLMP_INFO *info, SCADESC *buf_list,SCADESC_EX *buf_list_ex,int count)
3406 unsigned long phys_addr;
3408 for ( i = 0; i < count; i++ ) {
3409 buf_list_ex[i].virt_addr = info->memory_base + info->port_array[0]->last_mem_alloc;
3410 phys_addr = info->port_array[0]->last_mem_alloc;
3411 info->port_array[0]->last_mem_alloc += SCABUFSIZE;
3413 buf_list[i].buf_ptr = (unsigned short)phys_addr;
3414 buf_list[i].buf_base = (unsigned char)(phys_addr >> 16);
3420 void free_dma_bufs(SLMP_INFO *info)
3422 info->buffer_list = NULL;
3423 info->rx_buf_list = NULL;
3424 info->tx_buf_list = NULL;
3427 /* allocate buffer large enough to hold max_frame_size.
3428 * This buffer is used to pass an assembled frame to the line discipline.
3430 int alloc_tmp_rx_buf(SLMP_INFO *info)
3432 info->tmp_rx_buf = kmalloc(info->max_frame_size, GFP_KERNEL);
3433 if (info->tmp_rx_buf == NULL)
3438 void free_tmp_rx_buf(SLMP_INFO *info)
3440 if (info->tmp_rx_buf)
3441 kfree(info->tmp_rx_buf);
3442 info->tmp_rx_buf = NULL;
3445 int claim_resources(SLMP_INFO *info)
3447 if (request_mem_region(info->phys_memory_base,0x40000,"synclinkmp") == NULL) {
3448 printk( "%s(%d):%s mem addr conflict, Addr=%08X\n",
3449 __FILE__,__LINE__,info->device_name, info->phys_memory_base);
3453 info->shared_mem_requested = 1;
3455 if (request_mem_region(info->phys_lcr_base + info->lcr_offset,128,"synclinkmp") == NULL) {
3456 printk( "%s(%d):%s lcr mem addr conflict, Addr=%08X\n",
3457 __FILE__,__LINE__,info->device_name, info->phys_lcr_base);
3461 info->lcr_mem_requested = 1;
3463 if (request_mem_region(info->phys_sca_base + info->sca_offset,512,"synclinkmp") == NULL) {
3464 printk( "%s(%d):%s sca mem addr conflict, Addr=%08X\n",
3465 __FILE__,__LINE__,info->device_name, info->phys_sca_base);
3469 info->sca_base_requested = 1;
3471 if (request_mem_region(info->phys_statctrl_base + info->statctrl_offset,16,"synclinkmp") == NULL) {
3472 printk( "%s(%d):%s stat/ctrl mem addr conflict, Addr=%08X\n",
3473 __FILE__,__LINE__,info->device_name, info->phys_statctrl_base);
3477 info->sca_statctrl_requested = 1;
3479 info->memory_base = ioremap(info->phys_memory_base,SCA_MEM_SIZE);
3480 if (!info->memory_base) {
3481 printk( "%s(%d):%s Cant map shared memory, MemAddr=%08X\n",
3482 __FILE__,__LINE__,info->device_name, info->phys_memory_base );
3486 if ( !memory_test(info) ) {
3487 printk( "%s(%d):Shared Memory Test failed for device %s MemAddr=%08X\n",
3488 __FILE__,__LINE__,info->device_name, info->phys_memory_base );
3492 info->lcr_base = ioremap(info->phys_lcr_base,PAGE_SIZE) + info->lcr_offset;
3493 if (!info->lcr_base) {
3494 printk( "%s(%d):%s Cant map LCR memory, MemAddr=%08X\n",
3495 __FILE__,__LINE__,info->device_name, info->phys_lcr_base );
3499 info->sca_base = ioremap(info->phys_sca_base,PAGE_SIZE) + info->sca_offset;
3500 if (!info->sca_base) {
3501 printk( "%s(%d):%s Cant map SCA memory, MemAddr=%08X\n",
3502 __FILE__,__LINE__,info->device_name, info->phys_sca_base );
3506 info->statctrl_base = ioremap(info->phys_statctrl_base,PAGE_SIZE) + info->statctrl_offset;
3507 if (!info->statctrl_base) {
3508 printk( "%s(%d):%s Cant map SCA Status/Control memory, MemAddr=%08X\n",
3509 __FILE__,__LINE__,info->device_name, info->phys_statctrl_base );
3516 release_resources( info );
3520 void release_resources(SLMP_INFO *info)
3522 if ( debug_level >= DEBUG_LEVEL_INFO )
3523 printk( "%s(%d):%s release_resources() entry\n",
3524 __FILE__,__LINE__,info->device_name );
3526 if ( info->irq_requested ) {
3527 free_irq(info->irq_level, info);
3528 info->irq_requested = 0;
3531 if ( info->shared_mem_requested ) {
3532 release_mem_region(info->phys_memory_base,0x40000);
3533 info->shared_mem_requested = 0;
3535 if ( info->lcr_mem_requested ) {
3536 release_mem_region(info->phys_lcr_base + info->lcr_offset,128);
3537 info->lcr_mem_requested = 0;
3539 if ( info->sca_base_requested ) {
3540 release_mem_region(info->phys_sca_base + info->sca_offset,512);
3541 info->sca_base_requested = 0;
3543 if ( info->sca_statctrl_requested ) {
3544 release_mem_region(info->phys_statctrl_base + info->statctrl_offset,16);
3545 info->sca_statctrl_requested = 0;
3548 if (info->memory_base){
3549 iounmap(info->memory_base);
3550 info->memory_base = 0;
3553 if (info->sca_base) {
3554 iounmap(info->sca_base - info->sca_offset);
3558 if (info->statctrl_base) {
3559 iounmap(info->statctrl_base - info->statctrl_offset);
3560 info->statctrl_base=0;
3563 if (info->lcr_base){
3564 iounmap(info->lcr_base - info->lcr_offset);
3568 if ( debug_level >= DEBUG_LEVEL_INFO )
3569 printk( "%s(%d):%s release_resources() exit\n",
3570 __FILE__,__LINE__,info->device_name );
3573 /* Add the specified device instance data structure to the
3574 * global linked list of devices and increment the device count.
3576 void add_device(SLMP_INFO *info)
3578 info->next_device = NULL;
3579 info->line = synclinkmp_device_count;
3580 sprintf(info->device_name,"ttySLM%dp%d",info->adapter_num,info->port_num);
3582 if (info->line < MAX_DEVICES) {
3583 if (maxframe[info->line])
3584 info->max_frame_size = maxframe[info->line];
3585 info->dosyncppp = dosyncppp[info->line];
3588 synclinkmp_device_count++;
3590 if ( !synclinkmp_device_list )
3591 synclinkmp_device_list = info;
3593 SLMP_INFO *current_dev = synclinkmp_device_list;
3594 while( current_dev->next_device )
3595 current_dev = current_dev->next_device;
3596 current_dev->next_device = info;
3599 if ( info->max_frame_size < 4096 )
3600 info->max_frame_size = 4096;
3601 else if ( info->max_frame_size > 65535 )
3602 info->max_frame_size = 65535;
3604 printk( "SyncLink MultiPort %s: "
3605 "Mem=(%08x %08X %08x %08X) IRQ=%d MaxFrameSize=%u\n",
3607 info->phys_sca_base,
3608 info->phys_memory_base,
3609 info->phys_statctrl_base,
3610 info->phys_lcr_base,
3612 info->max_frame_size );
3614 #ifdef CONFIG_SYNCLINK_SYNCPPP
3615 if (info->dosyncppp)
3620 /* Allocate and initialize a device instance structure
3622 * Return Value: pointer to SLMP_INFO if success, otherwise NULL
3624 SLMP_INFO *alloc_dev(int adapter_num, int port_num, struct pci_dev *pdev)
3628 info = (SLMP_INFO *)kmalloc(sizeof(SLMP_INFO),
3632 printk("%s(%d) Error can't allocate device instance data for adapter %d, port %d\n",
3633 __FILE__,__LINE__, adapter_num, port_num);
3635 memset(info, 0, sizeof(SLMP_INFO));
3636 info->magic = MGSL_MAGIC;
3637 INIT_WORK(&info->task, bh_handler, info);
3638 info->max_frame_size = 4096;
3639 info->close_delay = 5*HZ/10;
3640 info->closing_wait = 30*HZ;
3641 init_waitqueue_head(&info->open_wait);
3642 init_waitqueue_head(&info->close_wait);
3643 init_waitqueue_head(&info->status_event_wait_q);
3644 init_waitqueue_head(&info->event_wait_q);
3645 spin_lock_init(&info->netlock);
3646 memcpy(&info->params,&default_params,sizeof(MGSL_PARAMS));
3647 info->idle_mode = HDLC_TXIDLE_FLAGS;
3648 info->adapter_num = adapter_num;
3649 info->port_num = port_num;
3651 /* Copy configuration info to device instance data */
3652 info->irq_level = pdev->irq;
3653 info->phys_lcr_base = pci_resource_start(pdev,0);
3654 info->phys_sca_base = pci_resource_start(pdev,2);
3655 info->phys_memory_base = pci_resource_start(pdev,3);
3656 info->phys_statctrl_base = pci_resource_start(pdev,4);
3658 /* Because veremap only works on page boundaries we must map
3659 * a larger area than is actually implemented for the LCR
3660 * memory range. We map a full page starting at the page boundary.
3662 info->lcr_offset = info->phys_lcr_base & (PAGE_SIZE-1);
3663 info->phys_lcr_base &= ~(PAGE_SIZE-1);
3665 info->sca_offset = info->phys_sca_base & (PAGE_SIZE-1);
3666 info->phys_sca_base &= ~(PAGE_SIZE-1);
3668 info->statctrl_offset = info->phys_statctrl_base & (PAGE_SIZE-1);
3669 info->phys_statctrl_base &= ~(PAGE_SIZE-1);
3671 info->bus_type = MGSL_BUS_TYPE_PCI;
3672 info->irq_flags = SA_SHIRQ;
3674 init_timer(&info->tx_timer);
3675 info->tx_timer.data = (unsigned long)info;
3676 info->tx_timer.function = tx_timeout;
3678 init_timer(&info->status_timer);
3679 info->status_timer.data = (unsigned long)info;
3680 info->status_timer.function = status_timeout;
3682 /* Store the PCI9050 misc control register value because a flaw
3683 * in the PCI9050 prevents LCR registers from being read if
3684 * BIOS assigns an LCR base address with bit 7 set.
3686 * Only the misc control register is accessed for which only
3687 * write access is needed, so set an initial value and change
3688 * bits to the device instance data as we write the value
3689 * to the actual misc control register.
3691 info->misc_ctrl_value = 0x087e4546;
3693 /* initial port state is unknown - if startup errors
3694 * occur, init_error will be set to indicate the
3695 * problem. Once the port is fully initialized,
3696 * this value will be set to 0 to indicate the
3697 * port is available.
3699 info->init_error = -1;
3705 void device_init(int adapter_num, struct pci_dev *pdev)
3707 SLMP_INFO *port_array[SCA_MAX_PORTS];
3710 /* allocate device instances for up to SCA_MAX_PORTS devices */
3711 for ( port = 0; port < SCA_MAX_PORTS; ++port ) {
3712 port_array[port] = alloc_dev(adapter_num,port,pdev);
3713 if( port_array[port] == NULL ) {
3714 for ( --port; port >= 0; --port )
3715 kfree(port_array[port]);
3720 /* give copy of port_array to all ports and add to device list */
3721 for ( port = 0; port < SCA_MAX_PORTS; ++port ) {
3722 memcpy(port_array[port]->port_array,port_array,sizeof(port_array));
3723 add_device( port_array[port] );
3724 spin_lock_init(&port_array[port]->lock);
3727 /* Allocate and claim adapter resources */
3728 if ( !claim_resources(port_array[0]) ) {
3730 alloc_dma_bufs(port_array[0]);
3732 /* copy resource information from first port to others */
3733 for ( port = 1; port < SCA_MAX_PORTS; ++port ) {
3734 port_array[port]->lock = port_array[0]->lock;
3735 port_array[port]->irq_level = port_array[0]->irq_level;
3736 port_array[port]->memory_base = port_array[0]->memory_base;
3737 port_array[port]->sca_base = port_array[0]->sca_base;
3738 port_array[port]->statctrl_base = port_array[0]->statctrl_base;
3739 port_array[port]->lcr_base = port_array[0]->lcr_base;
3740 alloc_dma_bufs(port_array[port]);
3743 if ( request_irq(port_array[0]->irq_level,
3744 synclinkmp_interrupt,
3745 port_array[0]->irq_flags,
3746 port_array[0]->device_name,
3747 port_array[0]) < 0 ) {
3748 printk( "%s(%d):%s Cant request interrupt, IRQ=%d\n",
3750 port_array[0]->device_name,
3751 port_array[0]->irq_level );
3754 port_array[0]->irq_requested = 1;
3755 adapter_test(port_array[0]);
3760 static struct tty_operations ops = {
3764 .put_char = put_char,
3765 .flush_chars = flush_chars,
3766 .write_room = write_room,
3767 .chars_in_buffer = chars_in_buffer,
3768 .flush_buffer = flush_buffer,
3770 .throttle = throttle,
3771 .unthrottle = unthrottle,
3772 .send_xchar = send_xchar,
3773 .break_ctl = set_break,
3774 .wait_until_sent = wait_until_sent,
3775 .read_proc = read_proc,
3776 .set_termios = set_termios,
3778 .start = tx_release,
3780 .tiocmget = tiocmget,
3781 .tiocmset = tiocmset,
3784 /* Driver initialization entry point.
3787 static int __init synclinkmp_init(void)
3789 if (break_on_load) {
3790 synclinkmp_get_text_ptr();
3794 printk("%s %s\n", driver_name, driver_version);
3796 synclinkmp_adapter_count = -1;
3797 pci_register_driver(&synclinkmp_pci_driver);
3799 if ( !synclinkmp_device_list ) {
3800 printk("%s(%d):No SyncLink devices found.\n",__FILE__,__LINE__);
3804 serial_driver = alloc_tty_driver(synclinkmp_device_count);
3808 /* Initialize the tty_driver structure */
3810 serial_driver->owner = THIS_MODULE;
3811 serial_driver->driver_name = "synclinkmp";
3812 serial_driver->name = "ttySLM";
3813 serial_driver->major = ttymajor;
3814 serial_driver->minor_start = 64;
3815 serial_driver->type = TTY_DRIVER_TYPE_SERIAL;
3816 serial_driver->subtype = SERIAL_TYPE_NORMAL;
3817 serial_driver->init_termios = tty_std_termios;
3818 serial_driver->init_termios.c_cflag =
3819 B9600 | CS8 | CREAD | HUPCL | CLOCAL;
3820 serial_driver->flags = TTY_DRIVER_REAL_RAW;
3821 tty_set_operations(serial_driver, &ops);
3822 if (tty_register_driver(serial_driver) < 0)
3823 printk("%s(%d):Couldn't register serial driver\n",
3826 printk("%s %s, tty major#%d\n",
3827 driver_name, driver_version,
3828 serial_driver->major);
3833 static void __exit synclinkmp_exit(void)
3835 unsigned long flags;
3840 printk("Unloading %s %s\n", driver_name, driver_version);
3842 if ((rc = tty_unregister_driver(serial_driver)))
3843 printk("%s(%d) failed to unregister tty driver err=%d\n",
3844 __FILE__,__LINE__,rc);
3845 put_tty_driver(serial_driver);
3847 info = synclinkmp_device_list;
3849 #ifdef CONFIG_SYNCLINK_SYNCPPP
3850 if (info->dosyncppp)
3854 if ( info->port_num == 0 ) {
3855 if ( info->irq_requested ) {
3856 free_irq(info->irq_level, info);
3857 info->irq_requested = 0;
3860 info = info->next_device;
3863 /* port 0 of each adapter originally claimed
3864 * all resources, release those now
3866 info = synclinkmp_device_list;
3868 free_dma_bufs(info);
3869 free_tmp_rx_buf(info);
3870 if ( info->port_num == 0 ) {
3871 spin_lock_irqsave(&info->lock,flags);
3872 reset_adapter(info);
3873 write_reg(info, LPR, 1); /* set low power mode */
3874 spin_unlock_irqrestore(&info->lock,flags);
3875 release_resources(info);
3878 info = info->next_device;
3882 pci_unregister_driver(&synclinkmp_pci_driver);
3885 module_init(synclinkmp_init);
3886 module_exit(synclinkmp_exit);
3888 /* Set the port for internal loopback mode.
3889 * The TxCLK and RxCLK signals are generated from the BRG and
3890 * the TxD is looped back to the RxD internally.
3892 void enable_loopback(SLMP_INFO *info, int enable)
3895 /* MD2 (Mode Register 2)
3896 * 01..00 CNCT<1..0> Channel Connection 11=Local Loopback
3898 write_reg(info, MD2, (unsigned char)(read_reg(info, MD2) | (BIT1 + BIT0)));
3900 /* degate external TxC clock source */
3901 info->port_array[0]->ctrlreg_value |= (BIT0 << (info->port_num * 2));
3902 write_control_reg(info);
3904 /* RXS/TXS (Rx/Tx clock source)
3905 * 07 Reserved, must be 0
3906 * 06..04 Clock Source, 100=BRG
3907 * 03..00 Clock Divisor, 0000=1
3909 write_reg(info, RXS, 0x40);
3910 write_reg(info, TXS, 0x40);
3913 /* MD2 (Mode Register 2)
3914 * 01..00 CNCT<1..0> Channel connection, 0=normal
3916 write_reg(info, MD2, (unsigned char)(read_reg(info, MD2) & ~(BIT1 + BIT0)));
3918 /* RXS/TXS (Rx/Tx clock source)
3919 * 07 Reserved, must be 0
3920 * 06..04 Clock Source, 000=RxC/TxC Pin
3921 * 03..00 Clock Divisor, 0000=1
3923 write_reg(info, RXS, 0x00);
3924 write_reg(info, TXS, 0x00);
3927 /* set LinkSpeed if available, otherwise default to 2Mbps */
3928 if (info->params.clock_speed)
3929 set_rate(info, info->params.clock_speed);
3931 set_rate(info, 3686400);
3934 /* Set the baud rate register to the desired speed
3936 * data_rate data rate of clock in bits per second
3937 * A data rate of 0 disables the AUX clock.
3939 void set_rate( SLMP_INFO *info, u32 data_rate )
3942 unsigned char BRValue;
3945 /* fBRG = fCLK/(TMC * 2^BR)
3947 if (data_rate != 0) {
3948 Divisor = 14745600/data_rate;
3955 if (TMCValue != 1 && TMCValue != 2) {
3956 /* BRValue of 0 provides 50/50 duty cycle *only* when
3957 * TMCValue is 1 or 2. BRValue of 1 to 9 always provides
3964 /* while TMCValue is too big for TMC register, divide
3965 * by 2 and increment BR exponent.
3967 for(; TMCValue > 256 && BRValue < 10; BRValue++)
3970 write_reg(info, TXS,
3971 (unsigned char)((read_reg(info, TXS) & 0xf0) | BRValue));
3972 write_reg(info, RXS,
3973 (unsigned char)((read_reg(info, RXS) & 0xf0) | BRValue));
3974 write_reg(info, TMC, (unsigned char)TMCValue);
3977 write_reg(info, TXS,0);
3978 write_reg(info, RXS,0);
3979 write_reg(info, TMC, 0);
3985 void rx_stop(SLMP_INFO *info)
3987 if (debug_level >= DEBUG_LEVEL_ISR)
3988 printk("%s(%d):%s rx_stop()\n",
3989 __FILE__,__LINE__, info->device_name );
3991 write_reg(info, CMD, RXRESET);
3993 info->ie0_value &= ~RXRDYE;
3994 write_reg(info, IE0, info->ie0_value); /* disable Rx data interrupts */
3996 write_reg(info, RXDMA + DSR, 0); /* disable Rx DMA */
3997 write_reg(info, RXDMA + DCMD, SWABORT); /* reset/init Rx DMA */
3998 write_reg(info, RXDMA + DIR, 0); /* disable Rx DMA interrupts */
4000 info->rx_enabled = 0;
4001 info->rx_overflow = 0;
4004 /* enable the receiver
4006 void rx_start(SLMP_INFO *info)
4010 if (debug_level >= DEBUG_LEVEL_ISR)
4011 printk("%s(%d):%s rx_start()\n",
4012 __FILE__,__LINE__, info->device_name );
4014 write_reg(info, CMD, RXRESET);
4016 if ( info->params.mode == MGSL_MODE_HDLC ) {
4017 /* HDLC, disabe IRQ on rxdata */
4018 info->ie0_value &= ~RXRDYE;
4019 write_reg(info, IE0, info->ie0_value);
4021 /* Reset all Rx DMA buffers and program rx dma */
4022 write_reg(info, RXDMA + DSR, 0); /* disable Rx DMA */
4023 write_reg(info, RXDMA + DCMD, SWABORT); /* reset/init Rx DMA */
4025 for (i = 0; i < info->rx_buf_count; i++) {
4026 info->rx_buf_list[i].status = 0xff;
4028 // throttle to 4 shared memory writes at a time to prevent
4029 // hogging local bus (keep latency time for DMA requests low).
4031 read_status_reg(info);
4033 info->current_rx_buf = 0;
4035 /* set current/1st descriptor address */
4036 write_reg16(info, RXDMA + CDA,
4037 info->rx_buf_list_ex[0].phys_entry);
4039 /* set new last rx descriptor address */
4040 write_reg16(info, RXDMA + EDA,
4041 info->rx_buf_list_ex[info->rx_buf_count - 1].phys_entry);
4043 /* set buffer length (shared by all rx dma data buffers) */
4044 write_reg16(info, RXDMA + BFL, SCABUFSIZE);
4046 write_reg(info, RXDMA + DIR, 0x60); /* enable Rx DMA interrupts (EOM/BOF) */
4047 write_reg(info, RXDMA + DSR, 0xf2); /* clear Rx DMA IRQs, enable Rx DMA */
4049 /* async, enable IRQ on rxdata */
4050 info->ie0_value |= RXRDYE;
4051 write_reg(info, IE0, info->ie0_value);
4054 write_reg(info, CMD, RXENABLE);
4056 info->rx_overflow = FALSE;
4057 info->rx_enabled = 1;
4060 /* Enable the transmitter and send a transmit frame if
4061 * one is loaded in the DMA buffers.
4063 void tx_start(SLMP_INFO *info)
4065 if (debug_level >= DEBUG_LEVEL_ISR)
4066 printk("%s(%d):%s tx_start() tx_count=%d\n",
4067 __FILE__,__LINE__, info->device_name,info->tx_count );
4069 if (!info->tx_enabled ) {
4070 write_reg(info, CMD, TXRESET);
4071 write_reg(info, CMD, TXENABLE);
4072 info->tx_enabled = TRUE;
4075 if ( info->tx_count ) {
4077 /* If auto RTS enabled and RTS is inactive, then assert */
4078 /* RTS and set a flag indicating that the driver should */
4079 /* negate RTS when the transmission completes. */
4081 info->drop_rts_on_tx_done = 0;
4083 if (info->params.mode != MGSL_MODE_ASYNC) {
4085 if ( info->params.flags & HDLC_FLAG_AUTO_RTS ) {
4086 get_signals( info );
4087 if ( !(info->serial_signals & SerialSignal_RTS) ) {
4088 info->serial_signals |= SerialSignal_RTS;
4089 set_signals( info );
4090 info->drop_rts_on_tx_done = 1;
4094 write_reg(info, TXDMA + DSR, 0); /* disable DMA channel */
4095 write_reg(info, TXDMA + DCMD, SWABORT); /* reset/init DMA channel */
4097 /* set TX CDA (current descriptor address) */
4098 write_reg16(info, TXDMA + CDA,
4099 info->tx_buf_list_ex[0].phys_entry);
4101 /* set TX EDA (last descriptor address) */
4102 write_reg16(info, TXDMA + EDA,
4103 info->tx_buf_list_ex[info->last_tx_buf].phys_entry);
4105 /* clear IDLE and UDRN status bit */
4106 info->ie1_value &= ~(IDLE + UDRN);
4107 if (info->params.mode != MGSL_MODE_ASYNC)
4108 info->ie1_value |= UDRN; /* HDLC, IRQ on underrun */
4109 write_reg(info, IE1, info->ie1_value); /* enable MSCI interrupts */
4110 write_reg(info, SR1, (unsigned char)(IDLE + UDRN));
4112 write_reg(info, TXDMA + DIR, 0x40); /* enable Tx DMA interrupts (EOM) */
4113 write_reg(info, TXDMA + DSR, 0xf2); /* clear Tx DMA IRQs, enable Tx DMA */
4115 info->tx_timer.expires = jiffies + jiffies_from_ms(5000);
4116 add_timer(&info->tx_timer);
4120 /* async, enable IRQ on txdata */
4121 info->ie0_value |= TXRDYE;
4122 write_reg(info, IE0, info->ie0_value);
4125 info->tx_active = 1;
4129 /* stop the transmitter and DMA
4131 void tx_stop( SLMP_INFO *info )
4133 if (debug_level >= DEBUG_LEVEL_ISR)
4134 printk("%s(%d):%s tx_stop()\n",
4135 __FILE__,__LINE__, info->device_name );
4137 del_timer(&info->tx_timer);
4139 write_reg(info, TXDMA + DSR, 0); /* disable DMA channel */
4140 write_reg(info, TXDMA + DCMD, SWABORT); /* reset/init DMA channel */
4142 write_reg(info, CMD, TXRESET);
4144 info->ie1_value &= ~(UDRN + IDLE);
4145 write_reg(info, IE1, info->ie1_value); /* disable tx status interrupts */
4146 write_reg(info, SR1, (unsigned char)(IDLE + UDRN)); /* clear pending */
4148 info->ie0_value &= ~TXRDYE;
4149 write_reg(info, IE0, info->ie0_value); /* disable tx data interrupts */
4151 info->tx_enabled = 0;
4152 info->tx_active = 0;
4155 /* Fill the transmit FIFO until the FIFO is full or
4156 * there is no more data to load.
4158 void tx_load_fifo(SLMP_INFO *info)
4162 /* do nothing is now tx data available and no XON/XOFF pending */
4164 if ( !info->tx_count && !info->x_char )
4167 /* load the Transmit FIFO until FIFOs full or all data sent */
4169 while( info->tx_count && (read_reg(info,SR0) & BIT1) ) {
4171 /* there is more space in the transmit FIFO and */
4172 /* there is more data in transmit buffer */
4174 if ( (info->tx_count > 1) && !info->x_char ) {
4176 TwoBytes[0] = info->tx_buf[info->tx_get++];
4177 if (info->tx_get >= info->max_frame_size)
4178 info->tx_get -= info->max_frame_size;
4179 TwoBytes[1] = info->tx_buf[info->tx_get++];
4180 if (info->tx_get >= info->max_frame_size)
4181 info->tx_get -= info->max_frame_size;
4183 write_reg16(info, TRB, *((u16 *)TwoBytes));
4185 info->tx_count -= 2;
4186 info->icount.tx += 2;
4188 /* only 1 byte left to transmit or 1 FIFO slot left */
4191 /* transmit pending high priority char */
4192 write_reg(info, TRB, info->x_char);
4195 write_reg(info, TRB, info->tx_buf[info->tx_get++]);
4196 if (info->tx_get >= info->max_frame_size)
4197 info->tx_get -= info->max_frame_size;
4205 /* Reset a port to a known state
4207 void reset_port(SLMP_INFO *info)
4209 if (info->sca_base) {
4214 info->serial_signals &= ~(SerialSignal_DTR + SerialSignal_RTS);
4217 /* disable all port interrupts */
4218 info->ie0_value = 0;
4219 info->ie1_value = 0;
4220 info->ie2_value = 0;
4221 write_reg(info, IE0, info->ie0_value);
4222 write_reg(info, IE1, info->ie1_value);
4223 write_reg(info, IE2, info->ie2_value);
4225 write_reg(info, CMD, CHRESET);
4229 /* Reset all the ports to a known state.
4231 void reset_adapter(SLMP_INFO *info)
4235 for ( i=0; i < SCA_MAX_PORTS; ++i) {
4236 if (info->port_array[i])
4237 reset_port(info->port_array[i]);
4241 /* Program port for asynchronous communications.
4243 void async_mode(SLMP_INFO *info)
4246 unsigned char RegValue;
4251 /* MD0, Mode Register 0
4253 * 07..05 PRCTL<2..0>, Protocol Mode, 000=async
4254 * 04 AUTO, Auto-enable (RTS/CTS/DCD)
4255 * 03 Reserved, must be 0
4256 * 02 CRCCC, CRC Calculation, 0=disabled
4257 * 01..00 STOP<1..0> Stop bits (00=1,10=2)
4262 if (info->params.stop_bits != 1)
4264 write_reg(info, MD0, RegValue);
4266 /* MD1, Mode Register 1
4268 * 07..06 BRATE<1..0>, bit rate, 00=1/1 01=1/16 10=1/32 11=1/64
4269 * 05..04 TXCHR<1..0>, tx char size, 00=8 bits,01=7,10=6,11=5
4270 * 03..02 RXCHR<1..0>, rx char size
4271 * 01..00 PMPM<1..0>, Parity mode, 00=none 10=even 11=odd
4276 switch (info->params.data_bits) {
4277 case 7: RegValue |= BIT4 + BIT2; break;
4278 case 6: RegValue |= BIT5 + BIT3; break;
4279 case 5: RegValue |= BIT5 + BIT4 + BIT3 + BIT2; break;
4281 if (info->params.parity != ASYNC_PARITY_NONE) {
4283 if (info->params.parity == ASYNC_PARITY_ODD)
4286 write_reg(info, MD1, RegValue);
4288 /* MD2, Mode Register 2
4290 * 07..02 Reserved, must be 0
4291 * 01..00 CNCT<1..0> Channel connection, 0=normal
4296 write_reg(info, MD2, RegValue);
4298 /* RXS, Receive clock source
4300 * 07 Reserved, must be 0
4301 * 06..04 RXCS<2..0>, clock source, 000=RxC Pin, 100=BRG, 110=DPLL
4302 * 03..00 RXBR<3..0>, rate divisor, 0000=1
4305 write_reg(info, RXS, RegValue);
4307 /* TXS, Transmit clock source
4309 * 07 Reserved, must be 0
4310 * 06..04 RXCS<2..0>, clock source, 000=TxC Pin, 100=BRG, 110=Receive Clock
4311 * 03..00 RXBR<3..0>, rate divisor, 0000=1
4314 write_reg(info, TXS, RegValue);
4318 * 6,4,2,0 CLKSEL<3..0>, 0 = TcCLK in, 1 = Auxclk out
4320 info->port_array[0]->ctrlreg_value |= (BIT0 << (info->port_num * 2));
4321 write_control_reg(info);
4325 /* RRC Receive Ready Control 0
4327 * 07..05 Reserved, must be 0
4328 * 04..00 RRC<4..0> Rx FIFO trigger active 0x00 = 1 byte
4330 write_reg(info, TRC0, 0x00);
4332 /* TRC0 Transmit Ready Control 0
4334 * 07..05 Reserved, must be 0
4335 * 04..00 TRC<4..0> Tx FIFO trigger active 0x10 = 16 bytes
4337 write_reg(info, TRC0, 0x10);
4339 /* TRC1 Transmit Ready Control 1
4341 * 07..05 Reserved, must be 0
4342 * 04..00 TRC<4..0> Tx FIFO trigger inactive 0x1e = 31 bytes (full-1)
4344 write_reg(info, TRC1, 0x1e);
4346 /* CTL, MSCI control register
4348 * 07..06 Reserved, set to 0
4349 * 05 UDRNC, underrun control, 0=abort 1=CRC+flag (HDLC/BSC)
4350 * 04 IDLC, idle control, 0=mark 1=idle register
4351 * 03 BRK, break, 0=off 1 =on (async)
4352 * 02 SYNCLD, sync char load enable (BSC) 1=enabled
4353 * 01 GOP, go active on poll (LOOP mode) 1=enabled
4354 * 00 RTS, RTS output control, 0=active 1=inactive
4359 if (!(info->serial_signals & SerialSignal_RTS))
4361 write_reg(info, CTL, RegValue);
4363 /* enable status interrupts */
4364 info->ie0_value |= TXINTE + RXINTE;
4365 write_reg(info, IE0, info->ie0_value);
4367 /* enable break detect interrupt */
4368 info->ie1_value = BRKD;
4369 write_reg(info, IE1, info->ie1_value);
4371 /* enable rx overrun interrupt */
4372 info->ie2_value = OVRN;
4373 write_reg(info, IE2, info->ie2_value);
4375 set_rate( info, info->params.data_rate * 16 );
4377 if (info->params.loopback)
4378 enable_loopback(info,1);
4381 /* Program the SCA for HDLC communications.
4383 void hdlc_mode(SLMP_INFO *info)
4385 unsigned char RegValue;
4388 // Can't use DPLL because SCA outputs recovered clock on RxC when
4389 // DPLL mode selected. This causes output contention with RxC receiver.
4390 // Use of DPLL would require external hardware to disable RxC receiver
4391 // when DPLL mode selected.
4392 info->params.flags &= ~(HDLC_FLAG_TXC_DPLL + HDLC_FLAG_RXC_DPLL);
4394 /* disable DMA interrupts */
4395 write_reg(info, TXDMA + DIR, 0);
4396 write_reg(info, RXDMA + DIR, 0);
4398 /* MD0, Mode Register 0
4400 * 07..05 PRCTL<2..0>, Protocol Mode, 100=HDLC
4401 * 04 AUTO, Auto-enable (RTS/CTS/DCD)
4402 * 03 Reserved, must be 0
4403 * 02 CRCCC, CRC Calculation, 1=enabled
4404 * 01 CRC1, CRC selection, 0=CRC-16,1=CRC-CCITT-16
4405 * 00 CRC0, CRC initial value, 1 = all 1s
4410 if (info->params.flags & HDLC_FLAG_AUTO_CTS)
4412 if (info->params.flags & HDLC_FLAG_AUTO_DCD)
4414 if (info->params.crc_type == HDLC_CRC_16_CCITT)
4415 RegValue |= BIT2 + BIT1;
4416 write_reg(info, MD0, RegValue);
4418 /* MD1, Mode Register 1
4420 * 07..06 ADDRS<1..0>, Address detect, 00=no addr check
4421 * 05..04 TXCHR<1..0>, tx char size, 00=8 bits
4422 * 03..02 RXCHR<1..0>, rx char size, 00=8 bits
4423 * 01..00 PMPM<1..0>, Parity mode, 00=no parity
4428 write_reg(info, MD1, RegValue);
4430 /* MD2, Mode Register 2
4432 * 07 NRZFM, 0=NRZ, 1=FM
4433 * 06..05 CODE<1..0> Encoding, 00=NRZ
4434 * 04..03 DRATE<1..0> DPLL Divisor, 00=8
4435 * 02 Reserved, must be 0
4436 * 01..00 CNCT<1..0> Channel connection, 0=normal
4441 switch(info->params.encoding) {
4442 case HDLC_ENCODING_NRZI: RegValue |= BIT5; break;
4443 case HDLC_ENCODING_BIPHASE_MARK: RegValue |= BIT7 + BIT5; break; /* aka FM1 */
4444 case HDLC_ENCODING_BIPHASE_SPACE: RegValue |= BIT7 + BIT6; break; /* aka FM0 */
4445 case HDLC_ENCODING_BIPHASE_LEVEL: RegValue |= BIT7; break; /* aka Manchester */
4447 case HDLC_ENCODING_NRZB: /* not supported */
4448 case HDLC_ENCODING_NRZI_MARK: /* not supported */
4449 case HDLC_ENCODING_DIFF_BIPHASE_LEVEL: /* not supported */
4452 if ( info->params.flags & HDLC_FLAG_DPLL_DIV16 ) {
4455 } else if ( info->params.flags & HDLC_FLAG_DPLL_DIV8 ) {
4461 write_reg(info, MD2, RegValue);
4464 /* RXS, Receive clock source
4466 * 07 Reserved, must be 0
4467 * 06..04 RXCS<2..0>, clock source, 000=RxC Pin, 100=BRG, 110=DPLL
4468 * 03..00 RXBR<3..0>, rate divisor, 0000=1
4471 if (info->params.flags & HDLC_FLAG_RXC_BRG)
4473 if (info->params.flags & HDLC_FLAG_RXC_DPLL)
4474 RegValue |= BIT6 + BIT5;
4475 write_reg(info, RXS, RegValue);
4477 /* TXS, Transmit clock source
4479 * 07 Reserved, must be 0
4480 * 06..04 RXCS<2..0>, clock source, 000=TxC Pin, 100=BRG, 110=Receive Clock
4481 * 03..00 RXBR<3..0>, rate divisor, 0000=1
4484 if (info->params.flags & HDLC_FLAG_TXC_BRG)
4486 if (info->params.flags & HDLC_FLAG_TXC_DPLL)
4487 RegValue |= BIT6 + BIT5;
4488 write_reg(info, TXS, RegValue);
4490 if (info->params.flags & HDLC_FLAG_RXC_DPLL)
4491 set_rate(info, info->params.clock_speed * DpllDivisor);
4493 set_rate(info, info->params.clock_speed);
4495 /* GPDATA (General Purpose I/O Data Register)
4497 * 6,4,2,0 CLKSEL<3..0>, 0 = TcCLK in, 1 = Auxclk out
4499 if (info->params.flags & HDLC_FLAG_TXC_BRG)
4500 info->port_array[0]->ctrlreg_value |= (BIT0 << (info->port_num * 2));
4502 info->port_array[0]->ctrlreg_value &= ~(BIT0 << (info->port_num * 2));
4503 write_control_reg(info);
4505 /* RRC Receive Ready Control 0
4507 * 07..05 Reserved, must be 0
4508 * 04..00 RRC<4..0> Rx FIFO trigger active
4510 write_reg(info, RRC, rx_active_fifo_level);
4512 /* TRC0 Transmit Ready Control 0
4514 * 07..05 Reserved, must be 0
4515 * 04..00 TRC<4..0> Tx FIFO trigger active
4517 write_reg(info, TRC0, tx_active_fifo_level);
4519 /* TRC1 Transmit Ready Control 1
4521 * 07..05 Reserved, must be 0
4522 * 04..00 TRC<4..0> Tx FIFO trigger inactive 0x1f = 32 bytes (full)
4524 write_reg(info, TRC1, (unsigned char)(tx_negate_fifo_level - 1));
4526 /* DMR, DMA Mode Register
4528 * 07..05 Reserved, must be 0
4529 * 04 TMOD, Transfer Mode: 1=chained-block
4530 * 03 Reserved, must be 0
4531 * 02 NF, Number of Frames: 1=multi-frame
4532 * 01 CNTE, Frame End IRQ Counter enable: 0=disabled
4533 * 00 Reserved, must be 0
4537 write_reg(info, TXDMA + DMR, 0x14);
4538 write_reg(info, RXDMA + DMR, 0x14);
4540 /* Set chain pointer base (upper 8 bits of 24 bit addr) */
4541 write_reg(info, RXDMA + CPB,
4542 (unsigned char)(info->buffer_list_phys >> 16));
4544 /* Set chain pointer base (upper 8 bits of 24 bit addr) */
4545 write_reg(info, TXDMA + CPB,
4546 (unsigned char)(info->buffer_list_phys >> 16));
4548 /* enable status interrupts. other code enables/disables
4549 * the individual sources for these two interrupt classes.
4551 info->ie0_value |= TXINTE + RXINTE;
4552 write_reg(info, IE0, info->ie0_value);
4554 /* CTL, MSCI control register
4556 * 07..06 Reserved, set to 0
4557 * 05 UDRNC, underrun control, 0=abort 1=CRC+flag (HDLC/BSC)
4558 * 04 IDLC, idle control, 0=mark 1=idle register
4559 * 03 BRK, break, 0=off 1 =on (async)
4560 * 02 SYNCLD, sync char load enable (BSC) 1=enabled
4561 * 01 GOP, go active on poll (LOOP mode) 1=enabled
4562 * 00 RTS, RTS output control, 0=active 1=inactive
4567 if (!(info->serial_signals & SerialSignal_RTS))
4569 write_reg(info, CTL, RegValue);
4571 /* preamble not supported ! */
4577 set_rate(info, info->params.clock_speed);
4579 if (info->params.loopback)
4580 enable_loopback(info,1);
4583 /* Set the transmit HDLC idle mode
4585 void tx_set_idle(SLMP_INFO *info)
4587 unsigned char RegValue = 0xff;
4589 /* Map API idle mode to SCA register bits */
4590 switch(info->idle_mode) {
4591 case HDLC_TXIDLE_FLAGS: RegValue = 0x7e; break;
4592 case HDLC_TXIDLE_ALT_ZEROS_ONES: RegValue = 0xaa; break;
4593 case HDLC_TXIDLE_ZEROS: RegValue = 0x00; break;
4594 case HDLC_TXIDLE_ONES: RegValue = 0xff; break;
4595 case HDLC_TXIDLE_ALT_MARK_SPACE: RegValue = 0xaa; break;
4596 case HDLC_TXIDLE_SPACE: RegValue = 0x00; break;
4597 case HDLC_TXIDLE_MARK: RegValue = 0xff; break;
4600 write_reg(info, IDL, RegValue);
4603 /* Query the adapter for the state of the V24 status (input) signals.
4605 void get_signals(SLMP_INFO *info)
4607 u16 status = read_reg(info, SR3);
4608 u16 gpstatus = read_status_reg(info);
4611 /* clear all serial signals except DTR and RTS */
4612 info->serial_signals &= SerialSignal_DTR + SerialSignal_RTS;
4614 /* set serial signal bits to reflect MISR */
4616 if (!(status & BIT3))
4617 info->serial_signals |= SerialSignal_CTS;
4619 if ( !(status & BIT2))
4620 info->serial_signals |= SerialSignal_DCD;
4622 testbit = BIT1 << (info->port_num * 2); // Port 0..3 RI is GPDATA<1,3,5,7>
4623 if (!(gpstatus & testbit))
4624 info->serial_signals |= SerialSignal_RI;
4626 testbit = BIT0 << (info->port_num * 2); // Port 0..3 DSR is GPDATA<0,2,4,6>
4627 if (!(gpstatus & testbit))
4628 info->serial_signals |= SerialSignal_DSR;
4631 /* Set the state of DTR and RTS based on contents of
4632 * serial_signals member of device context.
4634 void set_signals(SLMP_INFO *info)
4636 unsigned char RegValue;
4639 RegValue = read_reg(info, CTL);
4640 if (info->serial_signals & SerialSignal_RTS)
4644 write_reg(info, CTL, RegValue);
4646 // Port 0..3 DTR is ctrl reg <1,3,5,7>
4647 EnableBit = BIT1 << (info->port_num*2);
4648 if (info->serial_signals & SerialSignal_DTR)
4649 info->port_array[0]->ctrlreg_value &= ~EnableBit;
4651 info->port_array[0]->ctrlreg_value |= EnableBit;
4652 write_control_reg(info);
4655 /*******************/
4656 /* DMA Buffer Code */
4657 /*******************/
4659 /* Set the count for all receive buffers to SCABUFSIZE
4660 * and set the current buffer to the first buffer. This effectively
4661 * makes all buffers free and discards any data in buffers.
4663 void rx_reset_buffers(SLMP_INFO *info)
4665 rx_free_frame_buffers(info, 0, info->rx_buf_count - 1);
4668 /* Free the buffers used by a received frame
4670 * info pointer to device instance data
4671 * first index of 1st receive buffer of frame
4672 * last index of last receive buffer of frame
4674 void rx_free_frame_buffers(SLMP_INFO *info, unsigned int first, unsigned int last)
4679 /* reset current buffer for reuse */
4680 info->rx_buf_list[first].status = 0xff;
4682 if (first == last) {
4684 /* set new last rx descriptor address */
4685 write_reg16(info, RXDMA + EDA, info->rx_buf_list_ex[first].phys_entry);
4689 if (first == info->rx_buf_count)
4693 /* set current buffer to next buffer after last buffer of frame */
4694 info->current_rx_buf = first;
4697 /* Return a received frame from the receive DMA buffers.
4698 * Only frames received without errors are returned.
4700 * Return Value: 1 if frame returned, otherwise 0
4702 int rx_get_frame(SLMP_INFO *info)
4704 unsigned int StartIndex, EndIndex; /* index of 1st and last buffers of Rx frame */
4705 unsigned short status;
4706 unsigned int framesize = 0;
4708 unsigned long flags;
4709 struct tty_struct *tty = info->tty;
4710 unsigned char addr_field = 0xff;
4712 SCADESC_EX *desc_ex;
4715 /* assume no frame returned, set zero length */
4720 * current_rx_buf points to the 1st buffer of the next available
4721 * receive frame. To find the last buffer of the frame look for
4722 * a non-zero status field in the buffer entries. (The status
4723 * field is set by the 16C32 after completing a receive frame.
4725 StartIndex = EndIndex = info->current_rx_buf;
4728 desc = &info->rx_buf_list[EndIndex];
4729 desc_ex = &info->rx_buf_list_ex[EndIndex];
4731 if (desc->status == 0xff)
4732 goto Cleanup; /* current desc still in use, no frames available */
4734 if (framesize == 0 && info->params.addr_filter != 0xff)
4735 addr_field = desc_ex->virt_addr[0];
4737 framesize += desc->length;
4739 /* Status != 0 means last buffer of frame */
4744 if (EndIndex == info->rx_buf_count)
4747 if (EndIndex == info->current_rx_buf) {
4748 /* all buffers have been 'used' but none mark */
4749 /* the end of a frame. Reset buffers and receiver. */
4750 if ( info->rx_enabled ){
4751 spin_lock_irqsave(&info->lock,flags);
4753 spin_unlock_irqrestore(&info->lock,flags);
4760 /* check status of receive frame */
4762 /* frame status is byte stored after frame data
4764 * 7 EOM (end of msg), 1 = last buffer of frame
4765 * 6 Short Frame, 1 = short frame
4766 * 5 Abort, 1 = frame aborted
4767 * 4 Residue, 1 = last byte is partial
4768 * 3 Overrun, 1 = overrun occurred during frame reception
4769 * 2 CRC, 1 = CRC error detected
4772 status = desc->status;
4774 /* ignore CRC bit if not using CRC (bit is undefined) */
4775 /* Note:CRC is not save to data buffer */
4776 if (info->params.crc_type == HDLC_CRC_NONE)
4779 if (framesize == 0 ||
4780 (addr_field != 0xff && addr_field != info->params.addr_filter)) {
4781 /* discard 0 byte frames, this seems to occur sometime
4782 * when remote is idling flags.
4784 rx_free_frame_buffers(info, StartIndex, EndIndex);
4791 if (status & (BIT6+BIT5+BIT3+BIT2)) {
4792 /* received frame has errors,
4793 * update counts and mark frame size as 0
4796 info->icount.rxshort++;
4797 else if (status & BIT5)
4798 info->icount.rxabort++;
4799 else if (status & BIT3)
4800 info->icount.rxover++;
4802 info->icount.rxcrc++;
4806 #ifdef CONFIG_SYNCLINK_SYNCPPP
4807 info->netstats.rx_errors++;
4808 info->netstats.rx_frame_errors++;
4812 if ( debug_level >= DEBUG_LEVEL_BH )
4813 printk("%s(%d):%s rx_get_frame() status=%04X size=%d\n",
4814 __FILE__,__LINE__,info->device_name,status,framesize);
4816 if ( debug_level >= DEBUG_LEVEL_DATA )
4817 trace_block(info,info->rx_buf_list_ex[StartIndex].virt_addr,
4818 MIN(framesize,SCABUFSIZE),0);
4821 if (framesize > info->max_frame_size)
4822 info->icount.rxlong++;
4824 /* copy dma buffer(s) to contiguous intermediate buffer */
4825 int copy_count = framesize;
4826 int index = StartIndex;
4827 unsigned char *ptmp = info->tmp_rx_buf;
4828 info->tmp_rx_buf_count = framesize;
4830 info->icount.rxok++;
4833 int partial_count = MIN(copy_count,SCABUFSIZE);
4835 info->rx_buf_list_ex[index].virt_addr,
4837 ptmp += partial_count;
4838 copy_count -= partial_count;
4840 if ( ++index == info->rx_buf_count )
4844 #ifdef CONFIG_SYNCLINK_SYNCPPP
4845 if (info->netcount) {
4846 /* pass frame to syncppp device */
4847 sppp_rx_done(info,info->tmp_rx_buf,framesize);
4852 if ( tty && tty->ldisc.receive_buf ) {
4853 /* Call the line discipline receive callback directly. */
4854 tty->ldisc.receive_buf(tty,
4862 /* Free the buffers used by this frame. */
4863 rx_free_frame_buffers( info, StartIndex, EndIndex );
4868 if ( info->rx_enabled && info->rx_overflow ) {
4869 /* Receiver is enabled, but needs to restarted due to
4870 * rx buffer overflow. If buffers are empty, restart receiver.
4872 if (info->rx_buf_list[EndIndex].status == 0xff) {
4873 spin_lock_irqsave(&info->lock,flags);
4875 spin_unlock_irqrestore(&info->lock,flags);
4882 /* load the transmit DMA buffer with data
4884 void tx_load_dma_buffer(SLMP_INFO *info, const char *buf, unsigned int count)
4886 unsigned short copy_count;
4889 SCADESC_EX *desc_ex;
4891 if ( debug_level >= DEBUG_LEVEL_DATA )
4892 trace_block(info,buf, MIN(count,SCABUFSIZE), 1);
4894 /* Copy source buffer to one or more DMA buffers, starting with
4895 * the first transmit dma buffer.
4899 copy_count = MIN(count,SCABUFSIZE);
4901 desc = &info->tx_buf_list[i];
4902 desc_ex = &info->tx_buf_list_ex[i];
4904 load_pci_memory(info, desc_ex->virt_addr,buf,copy_count);
4906 desc->length = copy_count;
4910 count -= copy_count;
4916 if (i >= info->tx_buf_count)
4920 info->tx_buf_list[i].status = 0x81; /* set EOM and EOT status */
4921 info->last_tx_buf = ++i;
4924 int register_test(SLMP_INFO *info)
4926 static unsigned char testval[] = {0x00, 0xff, 0xaa, 0x55, 0x69, 0x96};
4927 static unsigned int count = sizeof(testval)/sizeof(unsigned char);
4930 unsigned long flags;
4932 spin_lock_irqsave(&info->lock,flags);
4935 /* assume failure */
4936 info->init_error = DiagStatus_AddressFailure;
4938 /* Write bit patterns to various registers but do it out of */
4939 /* sync, then read back and verify values. */
4941 for (i = 0 ; i < count ; i++) {
4942 write_reg(info, TMC, testval[i]);
4943 write_reg(info, IDL, testval[(i+1)%count]);
4944 write_reg(info, SA0, testval[(i+2)%count]);
4945 write_reg(info, SA1, testval[(i+3)%count]);
4947 if ( (read_reg(info, TMC) != testval[i]) ||
4948 (read_reg(info, IDL) != testval[(i+1)%count]) ||
4949 (read_reg(info, SA0) != testval[(i+2)%count]) ||
4950 (read_reg(info, SA1) != testval[(i+3)%count]) )
4958 spin_unlock_irqrestore(&info->lock,flags);
4963 int irq_test(SLMP_INFO *info)
4965 unsigned long timeout;
4966 unsigned long flags;
4968 unsigned char timer = (info->port_num & 1) ? TIMER2 : TIMER0;
4970 spin_lock_irqsave(&info->lock,flags);
4973 /* assume failure */
4974 info->init_error = DiagStatus_IrqFailure;
4975 info->irq_occurred = FALSE;
4977 /* setup timer0 on SCA0 to interrupt */
4979 /* IER2<7..4> = timer<3..0> interrupt enables (1=enabled) */
4980 write_reg(info, IER2, (unsigned char)((info->port_num & 1) ? BIT6 : BIT4));
4982 write_reg(info, (unsigned char)(timer + TEPR), 0); /* timer expand prescale */
4983 write_reg16(info, (unsigned char)(timer + TCONR), 1); /* timer constant */
4986 /* TMCS, Timer Control/Status Register
4988 * 07 CMF, Compare match flag (read only) 1=match
4989 * 06 ECMI, CMF Interrupt Enable: 1=enabled
4990 * 05 Reserved, must be 0
4991 * 04 TME, Timer Enable
4992 * 03..00 Reserved, must be 0
4996 write_reg(info, (unsigned char)(timer + TMCS), 0x50);
4998 spin_unlock_irqrestore(&info->lock,flags);
5001 while( timeout-- && !info->irq_occurred ) {
5002 set_current_state(TASK_INTERRUPTIBLE);
5003 schedule_timeout(jiffies_from_ms(10));
5006 spin_lock_irqsave(&info->lock,flags);
5008 spin_unlock_irqrestore(&info->lock,flags);
5010 return info->irq_occurred;
5013 /* initialize individual SCA device (2 ports)
5015 int sca_init(SLMP_INFO *info)
5017 /* set wait controller to single mem partition (low), no wait states */
5018 write_reg(info, PABR0, 0); /* wait controller addr boundary 0 */
5019 write_reg(info, PABR1, 0); /* wait controller addr boundary 1 */
5020 write_reg(info, WCRL, 0); /* wait controller low range */
5021 write_reg(info, WCRM, 0); /* wait controller mid range */
5022 write_reg(info, WCRH, 0); /* wait controller high range */
5024 /* DPCR, DMA Priority Control
5026 * 07..05 Not used, must be 0
5027 * 04 BRC, bus release condition: 0=all transfers complete
5028 * 03 CCC, channel change condition: 0=every cycle
5029 * 02..00 PR<2..0>, priority 100=round robin
5033 write_reg(info, DPCR, dma_priority);
5035 /* DMA Master Enable, BIT7: 1=enable all channels */
5036 write_reg(info, DMER, 0x80);
5038 /* enable all interrupt classes */
5039 write_reg(info, IER0, 0xff); /* TxRDY,RxRDY,TxINT,RxINT (ports 0-1) */
5040 write_reg(info, IER1, 0xff); /* DMIB,DMIA (channels 0-3) */
5041 write_reg(info, IER2, 0xf0); /* TIRQ (timers 0-3) */
5043 /* ITCR, interrupt control register
5044 * 07 IPC, interrupt priority, 0=MSCI->DMA
5045 * 06..05 IAK<1..0>, Acknowledge cycle, 00=non-ack cycle
5046 * 04 VOS, Vector Output, 0=unmodified vector
5047 * 03..00 Reserved, must be 0
5049 write_reg(info, ITCR, 0);
5054 /* initialize adapter hardware
5056 int init_adapter(SLMP_INFO *info)
5060 /* Set BIT30 of Local Control Reg 0x50 to reset SCA */
5061 volatile u32 *MiscCtrl = (u32 *)(info->lcr_base + 0x50);
5064 info->misc_ctrl_value |= BIT30;
5065 *MiscCtrl = info->misc_ctrl_value;
5068 * Force at least 170ns delay before clearing
5069 * reset bit. Each read from LCR takes at least
5070 * 30ns so 10 times for 300ns to be safe.
5073 readval = *MiscCtrl;
5075 info->misc_ctrl_value &= ~BIT30;
5076 *MiscCtrl = info->misc_ctrl_value;
5078 /* init control reg (all DTRs off, all clksel=input) */
5079 info->ctrlreg_value = 0xaa;
5080 write_control_reg(info);
5083 volatile u32 *LCR1BRDR = (u32 *)(info->lcr_base + 0x2c);
5084 lcr1_brdr_value &= ~(BIT5 + BIT4 + BIT3);
5086 switch(read_ahead_count)
5089 lcr1_brdr_value |= BIT5 + BIT4 + BIT3;
5092 lcr1_brdr_value |= BIT5 + BIT4;
5095 lcr1_brdr_value |= BIT5 + BIT3;
5098 lcr1_brdr_value |= BIT5;
5102 *LCR1BRDR = lcr1_brdr_value;
5103 *MiscCtrl = misc_ctrl_value;
5106 sca_init(info->port_array[0]);
5107 sca_init(info->port_array[2]);
5112 /* Loopback an HDLC frame to test the hardware
5113 * interrupt and DMA functions.
5115 int loopback_test(SLMP_INFO *info)
5117 #define TESTFRAMESIZE 20
5119 unsigned long timeout;
5120 u16 count = TESTFRAMESIZE;
5121 unsigned char buf[TESTFRAMESIZE];
5123 unsigned long flags;
5125 struct tty_struct *oldtty = info->tty;
5126 u32 speed = info->params.clock_speed;
5128 info->params.clock_speed = 3686400;
5131 /* assume failure */
5132 info->init_error = DiagStatus_DmaFailure;
5134 /* build and send transmit frame */
5135 for (count = 0; count < TESTFRAMESIZE;++count)
5136 buf[count] = (unsigned char)count;
5138 memset(info->tmp_rx_buf,0,TESTFRAMESIZE);
5140 /* program hardware for HDLC and enabled receiver */
5141 spin_lock_irqsave(&info->lock,flags);
5143 enable_loopback(info,1);
5145 info->tx_count = count;
5146 tx_load_dma_buffer(info,buf,count);
5148 spin_unlock_irqrestore(&info->lock,flags);
5150 /* wait for receive complete */
5151 /* Set a timeout for waiting for interrupt. */
5152 for ( timeout = 100; timeout; --timeout ) {
5153 set_current_state(TASK_INTERRUPTIBLE);
5154 schedule_timeout(jiffies_from_ms(10));
5156 if (rx_get_frame(info)) {
5162 /* verify received frame length and contents */
5164 ( info->tmp_rx_buf_count != count ||
5165 memcmp(buf, info->tmp_rx_buf,count))) {
5169 spin_lock_irqsave(&info->lock,flags);
5170 reset_adapter(info);
5171 spin_unlock_irqrestore(&info->lock,flags);
5173 info->params.clock_speed = speed;
5179 /* Perform diagnostics on hardware
5181 int adapter_test( SLMP_INFO *info )
5183 unsigned long flags;
5184 if ( debug_level >= DEBUG_LEVEL_INFO )
5185 printk( "%s(%d):Testing device %s\n",
5186 __FILE__,__LINE__,info->device_name );
5188 spin_lock_irqsave(&info->lock,flags);
5190 spin_unlock_irqrestore(&info->lock,flags);
5192 info->port_array[0]->port_count = 0;
5194 if ( register_test(info->port_array[0]) &&
5195 register_test(info->port_array[1])) {
5197 info->port_array[0]->port_count = 2;
5199 if ( register_test(info->port_array[2]) &&
5200 register_test(info->port_array[3]) )
5201 info->port_array[0]->port_count += 2;
5204 printk( "%s(%d):Register test failure for device %s Addr=%08lX\n",
5205 __FILE__,__LINE__,info->device_name, (unsigned long)(info->phys_sca_base));
5209 if ( !irq_test(info->port_array[0]) ||
5210 !irq_test(info->port_array[1]) ||
5211 (info->port_count == 4 && !irq_test(info->port_array[2])) ||
5212 (info->port_count == 4 && !irq_test(info->port_array[3]))) {
5213 printk( "%s(%d):Interrupt test failure for device %s IRQ=%d\n",
5214 __FILE__,__LINE__,info->device_name, (unsigned short)(info->irq_level) );
5218 if (!loopback_test(info->port_array[0]) ||
5219 !loopback_test(info->port_array[1]) ||
5220 (info->port_count == 4 && !loopback_test(info->port_array[2])) ||
5221 (info->port_count == 4 && !loopback_test(info->port_array[3]))) {
5222 printk( "%s(%d):DMA test failure for device %s\n",
5223 __FILE__,__LINE__,info->device_name);
5227 if ( debug_level >= DEBUG_LEVEL_INFO )
5228 printk( "%s(%d):device %s passed diagnostics\n",
5229 __FILE__,__LINE__,info->device_name );
5231 info->port_array[0]->init_error = 0;
5232 info->port_array[1]->init_error = 0;
5233 if ( info->port_count > 2 ) {
5234 info->port_array[2]->init_error = 0;
5235 info->port_array[3]->init_error = 0;
5241 /* Test the shared memory on a PCI adapter.
5243 int memory_test(SLMP_INFO *info)
5245 static unsigned long testval[] = { 0x0, 0x55555555, 0xaaaaaaaa,
5246 0x66666666, 0x99999999, 0xffffffff, 0x12345678 };
5247 unsigned long count = sizeof(testval)/sizeof(unsigned long);
5249 unsigned long limit = SCA_MEM_SIZE/sizeof(unsigned long);
5250 unsigned long * addr = (unsigned long *)info->memory_base;
5252 /* Test data lines with test pattern at one location. */
5254 for ( i = 0 ; i < count ; i++ ) {
5256 if ( *addr != testval[i] )
5260 /* Test address lines with incrementing pattern over */
5261 /* entire address range. */
5263 for ( i = 0 ; i < limit ; i++ ) {
5268 addr = (unsigned long *)info->memory_base;
5270 for ( i = 0 ; i < limit ; i++ ) {
5271 if ( *addr != i * 4 )
5276 memset( info->memory_base, 0, SCA_MEM_SIZE );
5280 /* Load data into PCI adapter shared memory.
5282 * The PCI9050 releases control of the local bus
5283 * after completing the current read or write operation.
5285 * While the PCI9050 write FIFO not empty, the
5286 * PCI9050 treats all of the writes as a single transaction
5287 * and does not release the bus. This causes DMA latency problems
5288 * at high speeds when copying large data blocks to the shared memory.
5290 * This function breaks a write into multiple transations by
5291 * interleaving a read which flushes the write FIFO and 'completes'
5292 * the write transation. This allows any pending DMA request to gain control
5293 * of the local bus in a timely fasion.
5295 void load_pci_memory(SLMP_INFO *info, char* dest, const char* src, unsigned short count)
5297 /* A load interval of 16 allows for 4 32-bit writes at */
5298 /* 136ns each for a maximum latency of 542ns on the local bus.*/
5300 unsigned short interval = count / sca_pci_load_interval;
5303 for ( i = 0 ; i < interval ; i++ )
5305 memcpy(dest, src, sca_pci_load_interval);
5306 read_status_reg(info);
5307 dest += sca_pci_load_interval;
5308 src += sca_pci_load_interval;
5311 memcpy(dest, src, count % sca_pci_load_interval);
5314 void trace_block(SLMP_INFO *info,const char* data, int count, int xmit)
5319 printk("%s tx data:\n",info->device_name);
5321 printk("%s rx data:\n",info->device_name);
5329 for(i=0;i<linecount;i++)
5330 printk("%02X ",(unsigned char)data[i]);
5333 for(i=0;i<linecount;i++) {
5334 if (data[i]>=040 && data[i]<=0176)
5335 printk("%c",data[i]);
5344 } /* end of trace_block() */
5346 /* called when HDLC frame times out
5347 * update stats and do tx completion processing
5349 void tx_timeout(unsigned long context)
5351 SLMP_INFO *info = (SLMP_INFO*)context;
5352 unsigned long flags;
5354 if ( debug_level >= DEBUG_LEVEL_INFO )
5355 printk( "%s(%d):%s tx_timeout()\n",
5356 __FILE__,__LINE__,info->device_name);
5357 if(info->tx_active && info->params.mode == MGSL_MODE_HDLC) {
5358 info->icount.txtimeout++;
5360 spin_lock_irqsave(&info->lock,flags);
5361 info->tx_active = 0;
5362 info->tx_count = info->tx_put = info->tx_get = 0;
5364 spin_unlock_irqrestore(&info->lock,flags);
5366 #ifdef CONFIG_SYNCLINK_SYNCPPP
5374 /* called to periodically check the DSR/RI modem signal input status
5376 void status_timeout(unsigned long context)
5379 SLMP_INFO *info = (SLMP_INFO*)context;
5380 unsigned long flags;
5381 unsigned char delta;
5384 spin_lock_irqsave(&info->lock,flags);
5386 spin_unlock_irqrestore(&info->lock,flags);
5388 /* check for DSR/RI state change */
5390 delta = info->old_signals ^ info->serial_signals;
5391 info->old_signals = info->serial_signals;
5393 if (delta & SerialSignal_DSR)
5394 status |= MISCSTATUS_DSR_LATCHED|(info->serial_signals&SerialSignal_DSR);
5396 if (delta & SerialSignal_RI)
5397 status |= MISCSTATUS_RI_LATCHED|(info->serial_signals&SerialSignal_RI);
5399 if (delta & SerialSignal_DCD)
5400 status |= MISCSTATUS_DCD_LATCHED|(info->serial_signals&SerialSignal_DCD);
5402 if (delta & SerialSignal_CTS)
5403 status |= MISCSTATUS_CTS_LATCHED|(info->serial_signals&SerialSignal_CTS);
5406 isr_io_pin(info,status);
5408 info->status_timer.data = (unsigned long)info;
5409 info->status_timer.function = status_timeout;
5410 info->status_timer.expires = jiffies + jiffies_from_ms(10);
5411 add_timer(&info->status_timer);
5415 /* Register Access Routines -
5416 * All registers are memory mapped
5418 #define CALC_REGADDR() \
5419 unsigned char * RegAddr = (unsigned char*)(info->sca_base + Addr); \
5420 if (info->port_num > 1) \
5421 RegAddr += 256; /* port 0-1 SCA0, 2-3 SCA1 */ \
5422 if ( info->port_num & 1) { \
5424 RegAddr += 0x40; /* DMA access */ \
5425 else if (Addr > 0x1f && Addr < 0x60) \
5426 RegAddr += 0x20; /* MSCI access */ \
5430 unsigned char read_reg(SLMP_INFO * info, unsigned char Addr)
5435 void write_reg(SLMP_INFO * info, unsigned char Addr, unsigned char Value)
5441 u16 read_reg16(SLMP_INFO * info, unsigned char Addr)
5444 return *((u16 *)RegAddr);
5447 void write_reg16(SLMP_INFO * info, unsigned char Addr, u16 Value)
5450 *((u16 *)RegAddr) = Value;
5453 unsigned char read_status_reg(SLMP_INFO * info)
5455 unsigned char *RegAddr = (unsigned char *)info->statctrl_base;
5459 void write_control_reg(SLMP_INFO * info)
5461 unsigned char *RegAddr = (unsigned char *)info->statctrl_base;
5462 *RegAddr = info->port_array[0]->ctrlreg_value;
5466 static int __devinit synclinkmp_init_one (struct pci_dev *dev,
5467 const struct pci_device_id *ent)
5469 if (pci_enable_device(dev)) {
5470 printk("error enabling pci device %p\n", dev);
5473 device_init( ++synclinkmp_adapter_count, dev );
5477 static void __devexit synclinkmp_remove_one (struct pci_dev *dev)