drivers/char/synclinkmp.c

   1 /*
   2  * $Id: synclinkmp.c,v 4.22 2004/06/03 14:50:10 paulkf Exp $
   3  *
   4  * Device driver for Microgate SyncLink Multiport
   5  * high speed multiprotocol serial adapter.
   6  *
   7  * written by Paul Fulghum for Microgate Corporation
   8  * paulkf@microgate.com
   9  *
  10  * Microgate and SyncLink are trademarks of Microgate Corporation
  11  *
  12  * Derived from serial.c written by Theodore Ts'o and Linus Torvalds
  13  * This code is released under the GNU General Public License (GPL)
  14  *
  15  * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
  16  * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
  17  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  18  * DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
  19  * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  20  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
  21  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  22  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
  23  * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  24  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
  25  * OF THE POSSIBILITY OF SUCH DAMAGE.
  26  */
  27
  28 #define VERSION(ver,rel,seq) (((ver)<<16) | ((rel)<<8) | (seq))
  29 #if defined(__i386__)
  30 #  define BREAKPOINT() asm("   int $3");
  31 #else
  32 #  define BREAKPOINT() { }
  33 #endif
  34
  35 #define MAX_DEVICES 12
  36
  37 #include <linux/config.h>
  38 #include <linux/module.h>
  39 #include <linux/errno.h>
  40 #include <linux/signal.h>
  41 #include <linux/sched.h>
  42 #include <linux/timer.h>
  43 #include <linux/interrupt.h>
  44 #include <linux/pci.h>
  45 #include <linux/tty.h>
  46 #include <linux/tty_flip.h>
  47 #include <linux/serial.h>
  48 #include <linux/major.h>
  49 #include <linux/string.h>
  50 #include <linux/fcntl.h>
  51 #include <linux/ptrace.h>
  52 #include <linux/ioport.h>
  53 #include <linux/mm.h>
  54 #include <linux/slab.h>
  55 #include <linux/netdevice.h>
  56 #include <linux/vmalloc.h>
  57 #include <linux/init.h>
  58 #include <asm/serial.h>
  59 #include <linux/delay.h>
  60 #include <linux/ioctl.h>
  61
  62 #include <asm/system.h>
  63 #include <asm/io.h>
  64 #include <asm/irq.h>
  65 #include <asm/dma.h>
  66 #include <asm/bitops.h>
  67 #include <asm/types.h>
  68 #include <linux/termios.h>
  69 #include <linux/workqueue.h>
  70
  71 #ifdef CONFIG_SYNCLINK_SYNCPPP_MODULE
  72 #define CONFIG_SYNCLINK_SYNCPPP 1
  73 #endif
  74
  75 #ifdef CONFIG_SYNCLINK_SYNCPPP
  76 #include <net/syncppp.h>
  77 #endif
  78
  79 #define GET_USER(error,value,addr) error = get_user(value,addr)
  80 #define COPY_FROM_USER(error,dest,src,size) error = copy_from_user(dest,src,size) ? -EFAULT : 0
  81 #define PUT_USER(error,value,addr) error = put_user(value,addr)
  82 #define COPY_TO_USER(error,dest,src,size) error = copy_to_user(dest,src,size) ? -EFAULT : 0
  83
  84 #include <asm/uaccess.h>
  85
  86 #include "linux/synclink.h"
  87
  88 static MGSL_PARAMS default_params = {
  89         MGSL_MODE_HDLC,                 /* unsigned long mode */
  90         0,                              /* unsigned char loopback; */
  91         HDLC_FLAG_UNDERRUN_ABORT15,     /* unsigned short flags; */
  92         HDLC_ENCODING_NRZI_SPACE,       /* unsigned char encoding; */
  93         0,                              /* unsigned long clock_speed; */
  94         0xff,                           /* unsigned char addr_filter; */
  95         HDLC_CRC_16_CCITT,              /* unsigned short crc_type; */
  96         HDLC_PREAMBLE_LENGTH_8BITS,     /* unsigned char preamble_length; */
  97         HDLC_PREAMBLE_PATTERN_NONE,     /* unsigned char preamble; */
  98         9600,                           /* unsigned long data_rate; */
  99         8,                              /* unsigned char data_bits; */
 100         1,                              /* unsigned char stop_bits; */
 101         ASYNC_PARITY_NONE               /* unsigned char parity; */
 102 };
 103
 104 /* size in bytes of DMA data buffers */
 105 #define SCABUFSIZE      1024
 106 #define SCA_MEM_SIZE    0x40000
 107 #define SCA_BASE_SIZE   512
 108 #define SCA_REG_SIZE    16
 109 #define SCA_MAX_PORTS   4
 110 #define SCAMAXDESC      128
 111
 112 #define BUFFERLISTSIZE  4096
 113
 114 /* SCA-I style DMA buffer descriptor */
 115 typedef struct _SCADESC
 116 {
 117         u16     next;           /* lower l6 bits of next descriptor addr */
 118         u16     buf_ptr;        /* lower 16 bits of buffer addr */
 119         u8      buf_base;       /* upper 8 bits of buffer addr */
 120         u8      pad1;
 121         u16     length;         /* length of buffer */
 122         u8      status;         /* status of buffer */
 123         u8      pad2;
 124 } SCADESC, *PSCADESC;
 125
 126 typedef struct _SCADESC_EX
 127 {
 128         /* device driver bookkeeping section */
 129         char    *virt_addr;     /* virtual address of data buffer */
 130         u16     phys_entry;     /* lower 16-bits of physical address of this descriptor */
 131 } SCADESC_EX, *PSCADESC_EX;
 132
 133 /* The queue of BH actions to be performed */
 134
 135 #define BH_RECEIVE  1
 136 #define BH_TRANSMIT 2
 137 #define BH_STATUS   4
 138
 139 #define IO_PIN_SHUTDOWN_LIMIT 100
 140
 141 #define RELEVANT_IFLAG(iflag) (iflag & (IGNBRK|BRKINT|IGNPAR|PARMRK|INPCK))
 142
 143 struct  _input_signal_events {
 144         int     ri_up;
 145         int     ri_down;
 146         int     dsr_up;
 147         int     dsr_down;
 148         int     dcd_up;
 149         int     dcd_down;
 150         int     cts_up;
 151         int     cts_down;
 152 };
 153
 154 /*
 155  * Device instance data structure
 156  */
 157 typedef struct _synclinkmp_info {
 158         void *if_ptr;                           /* General purpose pointer (used by SPPP) */
 159         int                     magic;
 160         int                     flags;
 161         int                     count;          /* count of opens */
 162         int                     line;
 163         unsigned short          close_delay;
 164         unsigned short          closing_wait;   /* time to wait before closing */
 165
 166         struct mgsl_icount      icount;
 167
 168         struct tty_struct       *tty;
 169         int                     timeout;
 170         int                     x_char;         /* xon/xoff character */
 171         int                     blocked_open;   /* # of blocked opens */
 172         u16                     read_status_mask1;  /* break detection (SR1 indications) */
 173         u16                     read_status_mask2;  /* parity/framing/overun (SR2 indications) */
 174         unsigned char           ignore_status_mask1;  /* break detection (SR1 indications) */
 175         unsigned char           ignore_status_mask2;  /* parity/framing/overun (SR2 indications) */
 176         unsigned char           *tx_buf;
 177         int                     tx_put;
 178         int                     tx_get;
 179         int                     tx_count;
 180
 181         wait_queue_head_t       open_wait;
 182         wait_queue_head_t       close_wait;
 183
 184         wait_queue_head_t       status_event_wait_q;
 185         wait_queue_head_t       event_wait_q;
 186         struct timer_list       tx_timer;       /* HDLC transmit timeout timer */
 187         struct _synclinkmp_info *next_device;   /* device list link */
 188         struct timer_list       status_timer;   /* input signal status check timer */
 189
 190         spinlock_t lock;                /* spinlock for synchronizing with ISR */
 191         struct work_struct task;                        /* task structure for scheduling bh */
 192
 193         u32 max_frame_size;                     /* as set by device config */
 194
 195         u32 pending_bh;
 196
 197         int bh_running;                         /* Protection from multiple */
 198         int isr_overflow;
 199         int bh_requested;
 200
 201         int dcd_chkcount;                       /* check counts to prevent */
 202         int cts_chkcount;                       /* too many IRQs if a signal */
 203         int dsr_chkcount;                       /* is floating */
 204         int ri_chkcount;
 205
 206         char *buffer_list;                      /* virtual address of Rx & Tx buffer lists */
 207         unsigned long buffer_list_phys;
 208
 209         unsigned int rx_buf_count;              /* count of total allocated Rx buffers */
 210         SCADESC *rx_buf_list;                   /* list of receive buffer entries */
 211         SCADESC_EX rx_buf_list_ex[SCAMAXDESC]; /* list of receive buffer entries */
 212         unsigned int current_rx_buf;
 213
 214         unsigned int tx_buf_count;              /* count of total allocated Tx buffers */
 215         SCADESC *tx_buf_list;           /* list of transmit buffer entries */
 216         SCADESC_EX tx_buf_list_ex[SCAMAXDESC]; /* list of transmit buffer entries */
 217         unsigned int last_tx_buf;
 218
 219         unsigned char *tmp_rx_buf;
 220         unsigned int tmp_rx_buf_count;
 221
 222         int rx_enabled;
 223         int rx_overflow;
 224
 225         int tx_enabled;
 226         int tx_active;
 227         u32 idle_mode;
 228
 229         unsigned char ie0_value;
 230         unsigned char ie1_value;
 231         unsigned char ie2_value;
 232         unsigned char ctrlreg_value;
 233         unsigned char old_signals;
 234
 235         char device_name[25];                   /* device instance name */
 236
 237         int port_count;
 238         int adapter_num;
 239         int port_num;
 240
 241         struct _synclinkmp_info *port_array[SCA_MAX_PORTS];
 242
 243         unsigned int bus_type;                  /* expansion bus type (ISA,EISA,PCI) */
 244
 245         unsigned int irq_level;                 /* interrupt level */
 246         unsigned long irq_flags;
 247         int irq_requested;                      /* nonzero if IRQ requested */
 248
 249         MGSL_PARAMS params;                     /* communications parameters */
 250
 251         unsigned char serial_signals;           /* current serial signal states */
 252
 253         int irq_occurred;                       /* for diagnostics use */
 254         unsigned int init_error;                /* Initialization startup error */
 255
 256         u32 last_mem_alloc;
 257         unsigned char* memory_base;             /* shared memory address (PCI only) */
 258         u32 phys_memory_base;
 259         int shared_mem_requested;
 260
 261         unsigned char* sca_base;                /* HD64570 SCA Memory address */
 262         u32 phys_sca_base;
 263         u32 sca_offset;
 264         int sca_base_requested;
 265
 266         unsigned char* lcr_base;                /* local config registers (PCI only) */
 267         u32 phys_lcr_base;
 268         u32 lcr_offset;
 269         int lcr_mem_requested;
 270
 271         unsigned char* statctrl_base;           /* status/control register memory */
 272         u32 phys_statctrl_base;
 273         u32 statctrl_offset;
 274         int sca_statctrl_requested;
 275
 276         u32 misc_ctrl_value;
 277         char flag_buf[MAX_ASYNC_BUFFER_SIZE];
 278         char char_buf[MAX_ASYNC_BUFFER_SIZE];
 279         BOOLEAN drop_rts_on_tx_done;
 280
 281         struct  _input_signal_events    input_signal_events;
 282
 283         /* SPPP/Cisco HDLC device parts */
 284         int netcount;
 285         int dosyncppp;
 286         spinlock_t netlock;
 287 #ifdef CONFIG_SYNCLINK_SYNCPPP
 288         struct ppp_device pppdev;
 289         char netname[10];
 290         struct net_device *netdev;
 291         struct net_device_stats netstats;
 292 #endif
 293 } SLMP_INFO;
 294
 295 #define MGSL_MAGIC 0x5401
 296
 297 /*
 298  * define serial signal status change macros
 299  */
 300 #define MISCSTATUS_DCD_LATCHED  (SerialSignal_DCD<<8)   /* indicates change in DCD */
 301 #define MISCSTATUS_RI_LATCHED   (SerialSignal_RI<<8)    /* indicates change in RI */
 302 #define MISCSTATUS_CTS_LATCHED  (SerialSignal_CTS<<8)   /* indicates change in CTS */
 303 #define MISCSTATUS_DSR_LATCHED  (SerialSignal_DSR<<8)   /* change in DSR */
 304
 305 /* Common Register macros */
 306 #define LPR     0x00
 307 #define PABR0   0x02
 308 #define PABR1   0x03
 309 #define WCRL    0x04
 310 #define WCRM    0x05
 311 #define WCRH    0x06
 312 #define DPCR    0x08
 313 #define DMER    0x09
 314 #define ISR0    0x10
 315 #define ISR1    0x11
 316 #define ISR2    0x12
 317 #define IER0    0x14
 318 #define IER1    0x15
 319 #define IER2    0x16
 320 #define ITCR    0x18
 321 #define INTVR   0x1a
 322 #define IMVR    0x1c
 323
 324 /* MSCI Register macros */
 325 #define TRB     0x20
 326 #define TRBL    0x20
 327 #define TRBH    0x21
 328 #define SR0     0x22
 329 #define SR1     0x23
 330 #define SR2     0x24
 331 #define SR3     0x25
 332 #define FST     0x26
 333 #define IE0     0x28
 334 #define IE1     0x29
 335 #define IE2     0x2a
 336 #define FIE     0x2b
 337 #define CMD     0x2c
 338 #define MD0     0x2e
 339 #define MD1     0x2f
 340 #define MD2     0x30
 341 #define CTL     0x31
 342 #define SA0     0x32
 343 #define SA1     0x33
 344 #define IDL     0x34
 345 #define TMC     0x35
 346 #define RXS     0x36
 347 #define TXS     0x37
 348 #define TRC0    0x38
 349 #define TRC1    0x39
 350 #define RRC     0x3a
 351 #define CST0    0x3c
 352 #define CST1    0x3d
 353
 354 /* Timer Register Macros */
 355 #define TCNT    0x60
 356 #define TCNTL   0x60
 357 #define TCNTH   0x61
 358 #define TCONR   0x62
 359 #define TCONRL  0x62
 360 #define TCONRH  0x63
 361 #define TMCS    0x64
 362 #define TEPR    0x65
 363
 364 /*
 365  *  FIXME: DAR here clashed with asm-ppc/reg.h and asm-sh/.../dma.h
 366  */
 367 #undef DAR
 368 /* DMA Controller Register macros */
 369 #define DAR     0x80
 370 #define DARL    0x80
 371 #define DARH    0x81
 372 #define DARB    0x82
 373 #define BAR     0x80
 374 #define BARL    0x80
 375 #define BARH    0x81
 376 #define BARB    0x82
 377 #define SAR     0x84
 378 #define SARL    0x84
 379 #define SARH    0x85
 380 #define SARB    0x86
 381 #define CPB     0x86
 382 #define CDA     0x88
 383 #define CDAL    0x88
 384 #define CDAH    0x89
 385 #define EDA     0x8a
 386 #define EDAL    0x8a
 387 #define EDAH    0x8b
 388 #define BFL     0x8c
 389 #define BFLL    0x8c
 390 #define BFLH    0x8d
 391 #define BCR     0x8e
 392 #define BCRL    0x8e
 393 #define BCRH    0x8f
 394 #define DSR     0x90
 395 #define DMR     0x91
 396 #define FCT     0x93
 397 #define DIR     0x94
 398 #define DCMD    0x95
 399
 400 /* combine with timer or DMA register address */
 401 #define TIMER0  0x00
 402 #define TIMER1  0x08
 403 #define TIMER2  0x10
 404 #define TIMER3  0x18
 405 #define RXDMA   0x00
 406 #define TXDMA   0x20
 407
 408 /* SCA Command Codes */
 409 #define NOOP            0x00
 410 #define TXRESET         0x01
 411 #define TXENABLE        0x02
 412 #define TXDISABLE       0x03
 413 #define TXCRCINIT       0x04
 414 #define TXCRCEXCL       0x05
 415 #define TXEOM           0x06
 416 #define TXABORT         0x07
 417 #define MPON            0x08
 418 #define TXBUFCLR        0x09
 419 #define RXRESET         0x11
 420 #define RXENABLE        0x12
 421 #define RXDISABLE       0x13
 422 #define RXCRCINIT       0x14
 423 #define RXREJECT        0x15
 424 #define SEARCHMP        0x16
 425 #define RXCRCEXCL       0x17
 426 #define RXCRCCALC       0x18
 427 #define CHRESET         0x21
 428 #define HUNT            0x31
 429
 430 /* DMA command codes */
 431 #define SWABORT         0x01
 432 #define FEICLEAR        0x02
 433
 434 /* IE0 */
 435 #define TXINTE          BIT7
 436 #define RXINTE          BIT6
 437 #define TXRDYE          BIT1
 438 #define RXRDYE          BIT0
 439
 440 /* IE1 & SR1 */
 441 #define UDRN    BIT7
 442 #define IDLE    BIT6
 443 #define SYNCD   BIT4
 444 #define FLGD    BIT4
 445 #define CCTS    BIT3
 446 #define CDCD    BIT2
 447 #define BRKD    BIT1
 448 #define ABTD    BIT1
 449 #define GAPD    BIT1
 450 #define BRKE    BIT0
 451 #define IDLD    BIT0
 452
 453 /* IE2 & SR2 */
 454 #define EOM     BIT7
 455 #define PMP     BIT6
 456 #define SHRT    BIT6
 457 #define PE      BIT5
 458 #define ABT     BIT5
 459 #define FRME    BIT4
 460 #define RBIT    BIT4
 461 #define OVRN    BIT3
 462 #define CRCE    BIT2
 463
 464
 465 #define jiffies_from_ms(a) ((((a) * HZ)/1000)+1)
 466
 467 /*
 468  * Global linked list of SyncLink devices
 469  */
 470 static SLMP_INFO *synclinkmp_device_list = NULL;
 471 static int synclinkmp_adapter_count = -1;
 472 static int synclinkmp_device_count = 0;
 473
 474 /*
 475  * Set this param to non-zero to load eax with the
 476  * .text section address and breakpoint on module load.
 477  * This is useful for use with gdb and add-symbol-file command.
 478  */
 479 static int break_on_load=0;
 480
 481 /*
 482  * Driver major number, defaults to zero to get auto
 483  * assigned major number. May be forced as module parameter.
 484  */
 485 static int ttymajor=0;
 486
 487 /*
 488  * Array of user specified options for ISA adapters.
 489  */
 490 static int debug_level = 0;
 491 static int maxframe[MAX_DEVICES] = {0,};
 492 static int dosyncppp[MAX_DEVICES] = {0,};
 493
 494 MODULE_PARM(break_on_load,"i");
 495 MODULE_PARM(ttymajor,"i");
 496 MODULE_PARM(debug_level,"i");
 497 MODULE_PARM(maxframe,"1-" __MODULE_STRING(MAX_DEVICES) "i");
 498 MODULE_PARM(dosyncppp,"1-" __MODULE_STRING(MAX_DEVICES) "i");
 499
 500 static char *driver_name = "SyncLink MultiPort driver";
 501 static char *driver_version = "$Revision: 4.22 $";
 502
 503 static int synclinkmp_init_one(struct pci_dev *dev,const struct pci_device_id *ent);
 504 static void synclinkmp_remove_one(struct pci_dev *dev);
 505
 506 static struct pci_device_id synclinkmp_pci_tbl[] = {
 507         { PCI_VENDOR_ID_MICROGATE, PCI_DEVICE_ID_MICROGATE_SCA, PCI_ANY_ID, PCI_ANY_ID, },
 508         { 0, }, /* terminate list */
 509 };
 510 MODULE_DEVICE_TABLE(pci, synclinkmp_pci_tbl);
 511
 512 MODULE_LICENSE("GPL");
 513
 514 static struct pci_driver synclinkmp_pci_driver = {
 515         .name           = "synclinkmp",
 516         .id_table       = synclinkmp_pci_tbl,
 517         .probe          = synclinkmp_init_one,
 518         .remove         = __devexit_p(synclinkmp_remove_one),
 519 };
 520
 521
 522 static struct tty_driver *serial_driver;
 523
 524 /* number of characters left in xmit buffer before we ask for more */
 525 #define WAKEUP_CHARS 256
 526
 527 #ifndef MIN
 528 #define MIN(a,b) ((a) < (b) ? (a) : (b))
 529 #endif
 530
 531
 532 /* tty callbacks */
 533
 534 static int  open(struct tty_struct *tty, struct file * filp);
 535 static void close(struct tty_struct *tty, struct file * filp);
 536 static void hangup(struct tty_struct *tty);
 537 static void set_termios(struct tty_struct *tty, struct termios *old_termios);
 538
 539 static int  write(struct tty_struct *tty, int from_user, const unsigned char *buf, int count);
 540 static void put_char(struct tty_struct *tty, unsigned char ch);
 541 static void send_xchar(struct tty_struct *tty, char ch);
 542 static void wait_until_sent(struct tty_struct *tty, int timeout);
 543 static int  write_room(struct tty_struct *tty);
 544 static void flush_chars(struct tty_struct *tty);
 545 static void flush_buffer(struct tty_struct *tty);
 546 static void tx_hold(struct tty_struct *tty);
 547 static void tx_release(struct tty_struct *tty);
 548
 549 static int  ioctl(struct tty_struct *tty, struct file *file, unsigned int cmd, unsigned long arg);
 550 static int  read_proc(char *page, char **start, off_t off, int count,int *eof, void *data);
 551 static int  chars_in_buffer(struct tty_struct *tty);
 552 static void throttle(struct tty_struct * tty);
 553 static void unthrottle(struct tty_struct * tty);
 554 static void set_break(struct tty_struct *tty, int break_state);
 555
 556 /* sppp support and callbacks */
 557
 558 #ifdef CONFIG_SYNCLINK_SYNCPPP
 559 static void sppp_init(SLMP_INFO *info);
 560 static void sppp_delete(SLMP_INFO *info);
 561 static void sppp_rx_done(SLMP_INFO *info, char *buf, int size);
 562 static void sppp_tx_done(SLMP_INFO *info);
 563
 564 static int  sppp_cb_open(struct net_device *d);
 565 static int  sppp_cb_close(struct net_device *d);
 566 static int  sppp_cb_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd);
 567 static int  sppp_cb_tx(struct sk_buff *skb, struct net_device *dev);
 568 static void sppp_cb_tx_timeout(struct net_device *dev);
 569 static struct net_device_stats *sppp_cb_net_stats(struct net_device *dev);
 570 #endif
 571
 572 /* ioctl handlers */
 573
 574 static int  get_stats(SLMP_INFO *info, struct mgsl_icount __user *user_icount);
 575 static int  get_params(SLMP_INFO *info, MGSL_PARAMS __user *params);
 576 static int  set_params(SLMP_INFO *info, MGSL_PARAMS __user *params);
 577 static int  get_txidle(SLMP_INFO *info, int __user *idle_mode);
 578 static int  set_txidle(SLMP_INFO *info, int idle_mode);
 579 static int  tx_enable(SLMP_INFO *info, int enable);
 580 static int  tx_abort(SLMP_INFO *info);
 581 static int  rx_enable(SLMP_INFO *info, int enable);
 582 static int  map_status(int signals);
 583 static int  modem_input_wait(SLMP_INFO *info,int arg);
 584 static int  wait_mgsl_event(SLMP_INFO *info, int __user *mask_ptr);
 585 static int  tiocmget(struct tty_struct *tty, struct file *file);
 586 static int  tiocmset(struct tty_struct *tty, struct file *file,
 587                      unsigned int set, unsigned int clear);
 588 static void set_break(struct tty_struct *tty, int break_state);
 589
 590 static void add_device(SLMP_INFO *info);
 591 static void device_init(int adapter_num, struct pci_dev *pdev);
 592 static int  claim_resources(SLMP_INFO *info);
 593 static void release_resources(SLMP_INFO *info);
 594
 595 static int  startup(SLMP_INFO *info);
 596 static int  block_til_ready(struct tty_struct *tty, struct file * filp,SLMP_INFO *info);
 597 static void shutdown(SLMP_INFO *info);
 598 static void program_hw(SLMP_INFO *info);
 599 static void change_params(SLMP_INFO *info);
 600
 601 static int  init_adapter(SLMP_INFO *info);
 602 static int  register_test(SLMP_INFO *info);
 603 static int  irq_test(SLMP_INFO *info);
 604 static int  loopback_test(SLMP_INFO *info);
 605 static int  adapter_test(SLMP_INFO *info);
 606 static int  memory_test(SLMP_INFO *info);
 607
 608 static void reset_adapter(SLMP_INFO *info);
 609 static void reset_port(SLMP_INFO *info);
 610 static void async_mode(SLMP_INFO *info);
 611 static void hdlc_mode(SLMP_INFO *info);
 612
 613 static void rx_stop(SLMP_INFO *info);
 614 static void rx_start(SLMP_INFO *info);
 615 static void rx_reset_buffers(SLMP_INFO *info);
 616 static void rx_free_frame_buffers(SLMP_INFO *info, unsigned int first, unsigned int last);
 617 static int  rx_get_frame(SLMP_INFO *info);
 618
 619 static void tx_start(SLMP_INFO *info);
 620 static void tx_stop(SLMP_INFO *info);
 621 static void tx_load_fifo(SLMP_INFO *info);
 622 static void tx_set_idle(SLMP_INFO *info);
 623 static void tx_load_dma_buffer(SLMP_INFO *info, const char *buf, unsigned int count);
 624
 625 static void get_signals(SLMP_INFO *info);
 626 static void set_signals(SLMP_INFO *info);
 627 static void enable_loopback(SLMP_INFO *info, int enable);
 628 static void set_rate(SLMP_INFO *info, u32 data_rate);
 629
 630 static int  bh_action(SLMP_INFO *info);
 631 static void bh_handler(void* Context);
 632 static void bh_receive(SLMP_INFO *info);
 633 static void bh_transmit(SLMP_INFO *info);
 634 static void bh_status(SLMP_INFO *info);
 635 static void isr_timer(SLMP_INFO *info);
 636 static void isr_rxint(SLMP_INFO *info);
 637 static void isr_rxrdy(SLMP_INFO *info);
 638 static void isr_txint(SLMP_INFO *info);
 639 static void isr_txrdy(SLMP_INFO *info);
 640 static void isr_rxdmaok(SLMP_INFO *info);
 641 static void isr_rxdmaerror(SLMP_INFO *info);
 642 static void isr_txdmaok(SLMP_INFO *info);
 643 static void isr_txdmaerror(SLMP_INFO *info);
 644 static void isr_io_pin(SLMP_INFO *info, u16 status);
 645
 646 static int  alloc_dma_bufs(SLMP_INFO *info);
 647 static void free_dma_bufs(SLMP_INFO *info);
 648 static int  alloc_buf_list(SLMP_INFO *info);
 649 static int  alloc_frame_bufs(SLMP_INFO *info, SCADESC *list, SCADESC_EX *list_ex,int count);
 650 static int  alloc_tmp_rx_buf(SLMP_INFO *info);
 651 static void free_tmp_rx_buf(SLMP_INFO *info);
 652
 653 static void load_pci_memory(SLMP_INFO *info, char* dest, const char* src, unsigned short count);
 654 static void trace_block(SLMP_INFO *info, const char* data, int count, int xmit);
 655 static void tx_timeout(unsigned long context);
 656 static void status_timeout(unsigned long context);
 657
 658 static unsigned char read_reg(SLMP_INFO *info, unsigned char addr);
 659 static void write_reg(SLMP_INFO *info, unsigned char addr, unsigned char val);
 660 static u16 read_reg16(SLMP_INFO *info, unsigned char addr);
 661 static void write_reg16(SLMP_INFO *info, unsigned char addr, u16 val);
 662 static unsigned char read_status_reg(SLMP_INFO * info);
 663 static void write_control_reg(SLMP_INFO * info);
 664
 665
 666 static unsigned char rx_active_fifo_level = 16; // rx request FIFO activation level in bytes
 667 static unsigned char tx_active_fifo_level = 16; // tx request FIFO activation level in bytes
 668 static unsigned char tx_negate_fifo_level = 32; // tx request FIFO negation level in bytes
 669
 670 static u32 misc_ctrl_value = 0x007e4040;
 671 static u32 lcr1_brdr_value = 0x0080002d;
 672
 673 static u32 read_ahead_count = 8;
 674
 675 /* DPCR, DMA Priority Control
 676  *
 677  * 07..05  Not used, must be 0
 678  * 04      BRC, bus release condition: 0=all transfers complete
 679  *              1=release after 1 xfer on all channels
 680  * 03      CCC, channel change condition: 0=every cycle
 681  *              1=after each channel completes all xfers
 682  * 02..00  PR<2..0>, priority 100=round robin
 683  *
 684  * 00000100 = 0x00
 685  */
 686 static unsigned char dma_priority = 0x04;
 687
 688 // Number of bytes that can be written to shared RAM
 689 // in a single write operation
 690 static u32 sca_pci_load_interval = 64;
 691
 692 /*
 693  * 1st function defined in .text section. Calling this function in
 694  * init_module() followed by a breakpoint allows a remote debugger
 695  * (gdb) to get the .text address for the add-symbol-file command.
 696  * This allows remote debugging of dynamically loadable modules.
 697  */
 698 static void* synclinkmp_get_text_ptr(void);
 699 static void* synclinkmp_get_text_ptr(void) {return synclinkmp_get_text_ptr;}
 700
 701 static inline int sanity_check(SLMP_INFO *info,
 702                                char *name, const char *routine)
 703 {
 704 #ifdef SANITY_CHECK
 705         static const char *badmagic =
 706                 "Warning: bad magic number for synclinkmp_struct (%s) in %s\n";
 707         static const char *badinfo =
 708                 "Warning: null synclinkmp_struct for (%s) in %s\n";
 709
 710         if (!info) {
 711                 printk(badinfo, name, routine);
 712                 return 1;
 713         }
 714         if (info->magic != MGSL_MAGIC) {
 715                 printk(badmagic, name, routine);
 716                 return 1;
 717         }
 718 #else
 719         if (!info)
 720                 return 1;
 721 #endif
 722         return 0;
 723 }
 724
 725 /* tty callbacks */
 726
 727 /* Called when a port is opened.  Init and enable port.
 728  */
 729 static int open(struct tty_struct *tty, struct file *filp)
 730 {
 731         SLMP_INFO *info;
 732         int retval, line;
 733         unsigned long flags;
 734
 735         line = tty->index;
 736         if ((line < 0) || (line >= synclinkmp_device_count)) {
 737                 printk("%s(%d): open with invalid line #%d.\n",
 738                         __FILE__,__LINE__,line);
 739                 return -ENODEV;
 740         }
 741
 742         info = synclinkmp_device_list;
 743         while(info && info->line != line)
 744                 info = info->next_device;
 745         if (sanity_check(info, tty->name, "open"))
 746                 return -ENODEV;
 747         if ( info->init_error ) {
 748                 printk("%s(%d):%s device is not allocated, init error=%d\n",
 749                         __FILE__,__LINE__,info->device_name,info->init_error);
 750                 return -ENODEV;
 751         }
 752
 753         tty->driver_data = info;
 754         info->tty = tty;
 755
 756         if (debug_level >= DEBUG_LEVEL_INFO)
 757                 printk("%s(%d):%s open(), old ref count = %d\n",
 758                          __FILE__,__LINE__,tty->driver->name, info->count);
 759
 760         /* If port is closing, signal caller to try again */
 761         if (tty_hung_up_p(filp) || info->flags & ASYNC_CLOSING){
 762                 if (info->flags & ASYNC_CLOSING)
 763                         interruptible_sleep_on(&info->close_wait);
 764                 retval = ((info->flags & ASYNC_HUP_NOTIFY) ?
 765                         -EAGAIN : -ERESTARTSYS);
 766                 goto cleanup;
 767         }
 768
 769         info->tty->low_latency = (info->flags & ASYNC_LOW_LATENCY) ? 1 : 0;
 770
 771         spin_lock_irqsave(&info->netlock, flags);
 772         if (info->netcount) {
 773                 retval = -EBUSY;
 774                 spin_unlock_irqrestore(&info->netlock, flags);
 775                 goto cleanup;
 776         }
 777         info->count++;
 778         spin_unlock_irqrestore(&info->netlock, flags);
 779
 780         if (info->count == 1) {
 781                 /* 1st open on this device, init hardware */
 782                 retval = startup(info);
 783                 if (retval < 0)
 784                         goto cleanup;
 785         }
 786
 787         retval = block_til_ready(tty, filp, info);
 788         if (retval) {
 789                 if (debug_level >= DEBUG_LEVEL_INFO)
 790                         printk("%s(%d):%s block_til_ready() returned %d\n",
 791                                  __FILE__,__LINE__, info->device_name, retval);
 792                 goto cleanup;
 793         }
 794
 795         if (debug_level >= DEBUG_LEVEL_INFO)
 796                 printk("%s(%d):%s open() success\n",
 797                          __FILE__,__LINE__, info->device_name);
 798         retval = 0;
 799
 800 cleanup:
 801         if (retval) {
 802                 if (tty->count == 1)
 803                         info->tty = NULL;/* tty layer will release tty struct */
 804                 if(info->count)
 805                         info->count--;
 806         }
 807
 808         return retval;
 809 }
 810
 811 /* Called when port is closed. Wait for remaining data to be
 812  * sent. Disable port and free resources.
 813  */
 814 static void close(struct tty_struct *tty, struct file *filp)
 815 {
 816         SLMP_INFO * info = (SLMP_INFO *)tty->driver_data;
 817
 818         if (sanity_check(info, tty->name, "close"))
 819                 return;
 820
 821         if (debug_level >= DEBUG_LEVEL_INFO)
 822                 printk("%s(%d):%s close() entry, count=%d\n",
 823                          __FILE__,__LINE__, info->device_name, info->count);
 824
 825         if (!info->count)
 826                 return;
 827
 828         if (tty_hung_up_p(filp))
 829                 goto cleanup;
 830
 831         if ((tty->count == 1) && (info->count != 1)) {
 832                 /*
 833                  * tty->count is 1 and the tty structure will be freed.
 834                  * info->count should be one in this case.
 835                  * if it's not, correct it so that the port is shutdown.
 836                  */
 837                 printk("%s(%d):%s close: bad refcount; tty->count is 1, "
 838                        "info->count is %d\n",
 839                          __FILE__,__LINE__, info->device_name, info->count);
 840                 info->count = 1;
 841         }
 842
 843         info->count--;
 844
 845         /* if at least one open remaining, leave hardware active */
 846         if (info->count)
 847                 goto cleanup;
 848
 849         info->flags |= ASYNC_CLOSING;
 850
 851         /* set tty->closing to notify line discipline to
 852          * only process XON/XOFF characters. Only the N_TTY
 853          * discipline appears to use this (ppp does not).
 854          */
 855         tty->closing = 1;
 856
 857         /* wait for transmit data to clear all layers */
 858
 859         if (info->closing_wait != ASYNC_CLOSING_WAIT_NONE) {
 860                 if (debug_level >= DEBUG_LEVEL_INFO)
 861                         printk("%s(%d):%s close() calling tty_wait_until_sent\n",
 862                                  __FILE__,__LINE__, info->device_name );
 863                 tty_wait_until_sent(tty, info->closing_wait);
 864         }
 865
 866         if (info->flags & ASYNC_INITIALIZED)
 867                 wait_until_sent(tty, info->timeout);
 868
 869         if (tty->driver->flush_buffer)
 870                 tty->driver->flush_buffer(tty);
 871
 872         if (tty->ldisc.flush_buffer)
 873                 tty->ldisc.flush_buffer(tty);
 874
 875         shutdown(info);
 876
 877         tty->closing = 0;
 878         info->tty = NULL;
 879
 880         if (info->blocked_open) {
 881                 if (info->close_delay) {
 882                         set_current_state(TASK_INTERRUPTIBLE);
 883                         schedule_timeout(info->close_delay);
 884                 }
 885                 wake_up_interruptible(&info->open_wait);
 886         }
 887
 888         info->flags &= ~(ASYNC_NORMAL_ACTIVE|ASYNC_CLOSING);
 889
 890         wake_up_interruptible(&info->close_wait);
 891
 892 cleanup:
 893         if (debug_level >= DEBUG_LEVEL_INFO)
 894                 printk("%s(%d):%s close() exit, count=%d\n", __FILE__,__LINE__,
 895                         tty->driver->name, info->count);
 896 }
 897
 898 /* Called by tty_hangup() when a hangup is signaled.
 899  * This is the same as closing all open descriptors for the port.
 900  */
 901 static void hangup(struct tty_struct *tty)
 902 {
 903         SLMP_INFO *info = (SLMP_INFO *)tty->driver_data;
 904
 905         if (debug_level >= DEBUG_LEVEL_INFO)
 906                 printk("%s(%d):%s hangup()\n",
 907                          __FILE__,__LINE__, info->device_name );
 908
 909         if (sanity_check(info, tty->name, "hangup"))
 910                 return;
 911
 912         flush_buffer(tty);
 913         shutdown(info);
 914
 915         info->count = 0;
 916         info->flags &= ~ASYNC_NORMAL_ACTIVE;
 917         info->tty = NULL;
 918
 919         wake_up_interruptible(&info->open_wait);
 920 }
 921
 922 /* Set new termios settings
 923  */
 924 static void set_termios(struct tty_struct *tty, struct termios *old_termios)
 925 {
 926         SLMP_INFO *info = (SLMP_INFO *)tty->driver_data;
 927         unsigned long flags;
 928
 929         if (debug_level >= DEBUG_LEVEL_INFO)
 930                 printk("%s(%d):%s set_termios()\n", __FILE__,__LINE__,
 931                         tty->driver->name );
 932
 933         /* just return if nothing has changed */
 934         if ((tty->termios->c_cflag == old_termios->c_cflag)
 935             && (RELEVANT_IFLAG(tty->termios->c_iflag)
 936                 == RELEVANT_IFLAG(old_termios->c_iflag)))
 937           return;
 938
 939         change_params(info);
 940
 941         /* Handle transition to B0 status */
 942         if (old_termios->c_cflag & CBAUD &&
 943             !(tty->termios->c_cflag & CBAUD)) {
 944                 info->serial_signals &= ~(SerialSignal_RTS + SerialSignal_DTR);
 945                 spin_lock_irqsave(&info->lock,flags);
 946                 set_signals(info);
 947                 spin_unlock_irqrestore(&info->lock,flags);
 948         }
 949
 950         /* Handle transition away from B0 status */
 951         if (!(old_termios->c_cflag & CBAUD) &&
 952             tty->termios->c_cflag & CBAUD) {
 953                 info->serial_signals |= SerialSignal_DTR;
 954                 if (!(tty->termios->c_cflag & CRTSCTS) ||
 955                     !test_bit(TTY_THROTTLED, &tty->flags)) {
 956                         info->serial_signals |= SerialSignal_RTS;
 957                 }
 958                 spin_lock_irqsave(&info->lock,flags);
 959                 set_signals(info);
 960                 spin_unlock_irqrestore(&info->lock,flags);
 961         }
 962
 963         /* Handle turning off CRTSCTS */
 964         if (old_termios->c_cflag & CRTSCTS &&
 965             !(tty->termios->c_cflag & CRTSCTS)) {
 966                 tty->hw_stopped = 0;
 967                 tx_release(tty);
 968         }
 969 }
 970
 971 /* Send a block of data
 972  *
 973  * Arguments:
 974  *
 975  *      tty             pointer to tty information structure
 976  *      from_user       flag: 1 = from user process
 977  *      buf             pointer to buffer containing send data
 978  *      count           size of send data in bytes
 979  *
 980  * Return Value:        number of characters written
 981  */
 982 static int write(struct tty_struct *tty, int from_user,
 983                  const unsigned char *buf, int count)
 984 {
 985         int     c, ret = 0, err;
 986         SLMP_INFO *info = (SLMP_INFO *)tty->driver_data;
 987         unsigned long flags;
 988
 989         if (debug_level >= DEBUG_LEVEL_INFO)
 990                 printk("%s(%d):%s write() count=%d\n",
 991                        __FILE__,__LINE__,info->device_name,count);
 992
 993         if (sanity_check(info, tty->name, "write"))
 994                 goto cleanup;
 995
 996         if (!tty || !info->tx_buf)
 997                 goto cleanup;
 998
 999         if (info->params.mode == MGSL_MODE_HDLC) {
1000                 if (count > info->max_frame_size) {
1001                         ret = -EIO;
1002                         goto cleanup;
1003                 }
1004                 if (info->tx_active)
1005                         goto cleanup;
1006                 if (info->tx_count) {
1007                         /* send accumulated data from send_char() calls */
1008                         /* as frame and wait before accepting more data. */
1009                         tx_load_dma_buffer(info, info->tx_buf, info->tx_count);
1010                         goto start;
1011                 }
1012                 if (!from_user) {
1013                         ret = info->tx_count = count;
1014                         tx_load_dma_buffer(info, buf, count);
1015                         goto start;
1016                 }
1017         }
1018
1019         for (;;) {
1020                 c = MIN(count,
1021                         MIN(info->max_frame_size - info->tx_count - 1,
1022                             info->max_frame_size - info->tx_put));
1023                 if (c <= 0)
1024                         break;
1025
1026                 if (from_user) {
1027                         COPY_FROM_USER(err, info->tx_buf + info->tx_put, buf, c);
1028                         if (err) {
1029                                 if (!ret)
1030                                         ret = -EFAULT;
1031                                 break;
1032                         }
1033                 } else
1034                         memcpy(info->tx_buf + info->tx_put, buf, c);
1035
1036                 spin_lock_irqsave(&info->lock,flags);
1037                 info->tx_put += c;
1038                 if (info->tx_put >= info->max_frame_size)
1039                         info->tx_put -= info->max_frame_size;
1040                 info->tx_count += c;
1041                 spin_unlock_irqrestore(&info->lock,flags);
1042
1043                 buf += c;
1044                 count -= c;
1045                 ret += c;
1046         }
1047
1048         if (info->params.mode == MGSL_MODE_HDLC) {
1049                 if (count) {
1050                         ret = info->tx_count = 0;
1051                         goto cleanup;
1052                 }
1053                 tx_load_dma_buffer(info, info->tx_buf, info->tx_count);
1054         }
1055 start:
1056         if (info->tx_count && !tty->stopped && !tty->hw_stopped) {
1057                 spin_lock_irqsave(&info->lock,flags);
1058                 if (!info->tx_active)
1059                         tx_start(info);
1060                 spin_unlock_irqrestore(&info->lock,flags);
1061         }
1062
1063 cleanup:
1064         if (debug_level >= DEBUG_LEVEL_INFO)
1065                 printk( "%s(%d):%s write() returning=%d\n",
1066                         __FILE__,__LINE__,info->device_name,ret);
1067         return ret;
1068 }
1069
1070 /* Add a character to the transmit buffer.
1071  */
1072 static void put_char(struct tty_struct *tty, unsigned char ch)
1073 {
1074         SLMP_INFO *info = (SLMP_INFO *)tty->driver_data;
1075         unsigned long flags;
1076
1077         if ( debug_level >= DEBUG_LEVEL_INFO ) {
1078                 printk( "%s(%d):%s put_char(%d)\n",
1079                         __FILE__,__LINE__,info->device_name,ch);
1080         }
1081
1082         if (sanity_check(info, tty->name, "put_char"))
1083                 return;
1084
1085         if (!tty || !info->tx_buf)
1086                 return;
1087
1088         spin_lock_irqsave(&info->lock,flags);
1089
1090         if ( (info->params.mode != MGSL_MODE_HDLC) ||
1091              !info->tx_active ) {
1092
1093                 if (info->tx_count < info->max_frame_size - 1) {
1094                         info->tx_buf[info->tx_put++] = ch;
1095                         if (info->tx_put >= info->max_frame_size)
1096                                 info->tx_put -= info->max_frame_size;
1097                         info->tx_count++;
1098                 }
1099         }
1100
1101         spin_unlock_irqrestore(&info->lock,flags);
1102 }
1103
1104 /* Send a high-priority XON/XOFF character
1105  */
1106 static void send_xchar(struct tty_struct *tty, char ch)
1107 {
1108         SLMP_INFO *info = (SLMP_INFO *)tty->driver_data;
1109         unsigned long flags;
1110
1111         if (debug_level >= DEBUG_LEVEL_INFO)
1112                 printk("%s(%d):%s send_xchar(%d)\n",
1113                          __FILE__,__LINE__, info->device_name, ch );
1114
1115         if (sanity_check(info, tty->name, "send_xchar"))
1116                 return;
1117
1118         info->x_char = ch;
1119         if (ch) {
1120                 /* Make sure transmit interrupts are on */
1121                 spin_lock_irqsave(&info->lock,flags);
1122                 if (!info->tx_enabled)
1123                         tx_start(info);
1124                 spin_unlock_irqrestore(&info->lock,flags);
1125         }
1126 }
1127
1128 /* Wait until the transmitter is empty.
1129  */
1130 static void wait_until_sent(struct tty_struct *tty, int timeout)
1131 {
1132         SLMP_INFO * info = (SLMP_INFO *)tty->driver_data;
1133         unsigned long orig_jiffies, char_time;
1134
1135         if (!info )
1136                 return;
1137
1138         if (debug_level >= DEBUG_LEVEL_INFO)
1139                 printk("%s(%d):%s wait_until_sent() entry\n",
1140                          __FILE__,__LINE__, info->device_name );
1141
1142         if (sanity_check(info, tty->name, "wait_until_sent"))
1143                 return;
1144
1145         if (!(info->flags & ASYNC_INITIALIZED))
1146                 goto exit;
1147
1148         orig_jiffies = jiffies;
1149
1150         /* Set check interval to 1/5 of estimated time to
1151          * send a character, and make it at least 1. The check
1152          * interval should also be less than the timeout.
1153          * Note: use tight timings here to satisfy the NIST-PCTS.
1154          */
1155
1156         if ( info->params.data_rate ) {
1157                 char_time = info->timeout/(32 * 5);
1158                 if (!char_time)
1159                         char_time++;
1160         } else
1161                 char_time = 1;
1162
1163         if (timeout)
1164                 char_time = MIN(char_time, timeout);
1165
1166         if ( info->params.mode == MGSL_MODE_HDLC ) {
1167                 while (info->tx_active) {
1168                         set_current_state(TASK_INTERRUPTIBLE);
1169                         schedule_timeout(char_time);
1170                         if (signal_pending(current))
1171                                 break;
1172                         if (timeout && time_after(jiffies, orig_jiffies + timeout))
1173                                 break;
1174                 }
1175         } else {
1176                 //TODO: determine if there is something similar to USC16C32
1177                 //      TXSTATUS_ALL_SENT status
1178                 while ( info->tx_active && info->tx_enabled) {
1179                         set_current_state(TASK_INTERRUPTIBLE);
1180                         schedule_timeout(char_time);
1181                         if (signal_pending(current))
1182                                 break;
1183                         if (timeout && time_after(jiffies, orig_jiffies + timeout))
1184                                 break;
1185                 }
1186         }
1187
1188 exit:
1189         if (debug_level >= DEBUG_LEVEL_INFO)
1190                 printk("%s(%d):%s wait_until_sent() exit\n",
1191                          __FILE__,__LINE__, info->device_name );
1192 }
1193
1194 /* Return the count of free bytes in transmit buffer
1195  */
1196 static int write_room(struct tty_struct *tty)
1197 {
1198         SLMP_INFO *info = (SLMP_INFO *)tty->driver_data;
1199         int ret;
1200
1201         if (sanity_check(info, tty->name, "write_room"))
1202                 return 0;
1203
1204         if (info->params.mode == MGSL_MODE_HDLC) {
1205                 ret = (info->tx_active) ? 0 : HDLC_MAX_FRAME_SIZE;
1206         } else {
1207                 ret = info->max_frame_size - info->tx_count - 1;
1208                 if (ret < 0)
1209                         ret = 0;
1210         }
1211
1212         if (debug_level >= DEBUG_LEVEL_INFO)
1213                 printk("%s(%d):%s write_room()=%d\n",
1214                        __FILE__, __LINE__, info->device_name, ret);
1215
1216         return ret;
1217 }
1218
1219 /* enable transmitter and send remaining buffered characters
1220  */
1221 static void flush_chars(struct tty_struct *tty)
1222 {
1223         SLMP_INFO *info = (SLMP_INFO *)tty->driver_data;
1224         unsigned long flags;
1225
1226         if ( debug_level >= DEBUG_LEVEL_INFO )
1227                 printk( "%s(%d):%s flush_chars() entry tx_count=%d\n",
1228                         __FILE__,__LINE__,info->device_name,info->tx_count);
1229
1230         if (sanity_check(info, tty->name, "flush_chars"))
1231                 return;
1232
1233         if (info->tx_count <= 0 || tty->stopped || tty->hw_stopped ||
1234             !info->tx_buf)
1235                 return;
1236
1237         if ( debug_level >= DEBUG_LEVEL_INFO )
1238                 printk( "%s(%d):%s flush_chars() entry, starting transmitter\n",
1239                         __FILE__,__LINE__,info->device_name );
1240
1241         spin_lock_irqsave(&info->lock,flags);
1242
1243         if (!info->tx_active) {
1244                 if ( (info->params.mode == MGSL_MODE_HDLC) &&
1245                         info->tx_count ) {
1246                         /* operating in synchronous (frame oriented) mode */
1247                         /* copy data from circular tx_buf to */
1248                         /* transmit DMA buffer. */
1249                         tx_load_dma_buffer(info,
1250                                  info->tx_buf,info->tx_count);
1251                 }
1252                 tx_start(info);
1253         }
1254
1255         spin_unlock_irqrestore(&info->lock,flags);
1256 }
1257
1258 /* Discard all data in the send buffer
1259  */
1260 static void flush_buffer(struct tty_struct *tty)
1261 {
1262         SLMP_INFO *info = (SLMP_INFO *)tty->driver_data;
1263         unsigned long flags;
1264
1265         if (debug_level >= DEBUG_LEVEL_INFO)
1266                 printk("%s(%d):%s flush_buffer() entry\n",
1267                          __FILE__,__LINE__, info->device_name );
1268
1269         if (sanity_check(info, tty->name, "flush_buffer"))
1270                 return;
1271
1272         spin_lock_irqsave(&info->lock,flags);
1273         info->tx_count = info->tx_put = info->tx_get = 0;
1274         del_timer(&info->tx_timer);
1275         spin_unlock_irqrestore(&info->lock,flags);
1276
1277         wake_up_interruptible(&tty->write_wait);
1278         if ((tty->flags & (1 << TTY_DO_WRITE_WAKEUP)) &&
1279             tty->ldisc.write_wakeup)
1280                 (tty->ldisc.write_wakeup)(tty);
1281 }
1282
1283 /* throttle (stop) transmitter
1284  */
1285 static void tx_hold(struct tty_struct *tty)
1286 {
1287         SLMP_INFO *info = (SLMP_INFO *)tty->driver_data;
1288         unsigned long flags;
1289
1290         if (sanity_check(info, tty->name, "tx_hold"))
1291                 return;
1292
1293         if ( debug_level >= DEBUG_LEVEL_INFO )
1294                 printk("%s(%d):%s tx_hold()\n",
1295                         __FILE__,__LINE__,info->device_name);
1296
1297         spin_lock_irqsave(&info->lock,flags);
1298         if (info->tx_enabled)
1299                 tx_stop(info);
1300         spin_unlock_irqrestore(&info->lock,flags);
1301 }
1302
1303 /* release (start) transmitter
1304  */
1305 static void tx_release(struct tty_struct *tty)
1306 {
1307         SLMP_INFO *info = (SLMP_INFO *)tty->driver_data;
1308         unsigned long flags;
1309
1310         if (sanity_check(info, tty->name, "tx_release"))
1311                 return;
1312
1313         if ( debug_level >= DEBUG_LEVEL_INFO )
1314                 printk("%s(%d):%s tx_release()\n",
1315                         __FILE__,__LINE__,info->device_name);
1316
1317         spin_lock_irqsave(&info->lock,flags);
1318         if (!info->tx_enabled)
1319                 tx_start(info);
1320         spin_unlock_irqrestore(&info->lock,flags);
1321 }
1322
1323 /* Service an IOCTL request
1324  *
1325  * Arguments:
1326  *
1327  *      tty     pointer to tty instance data
1328  *      file    pointer to associated file object for device
1329  *      cmd     IOCTL command code
1330  *      arg     command argument/context
1331  *
1332  * Return Value:        0 if success, otherwise error code
1333  */
1334 static int ioctl(struct tty_struct *tty, struct file *file,
1335                  unsigned int cmd, unsigned long arg)
1336 {
1337         SLMP_INFO *info = (SLMP_INFO *)tty->driver_data;
1338         int error;
1339         struct mgsl_icount cnow;        /* kernel counter temps */
1340         struct serial_icounter_struct __user *p_cuser;  /* user space */
1341         unsigned long flags;
1342         void __user *argp = (void __user *)arg;
1343
1344         if (debug_level >= DEBUG_LEVEL_INFO)
1345                 printk("%s(%d):%s ioctl() cmd=%08X\n", __FILE__,__LINE__,
1346                         info->device_name, cmd );
1347
1348         if (sanity_check(info, tty->name, "ioctl"))
1349                 return -ENODEV;
1350
1351         if ((cmd != TIOCGSERIAL) && (cmd != TIOCSSERIAL) &&
1352             (cmd != TIOCMIWAIT) && (cmd != TIOCGICOUNT)) {
1353                 if (tty->flags & (1 << TTY_IO_ERROR))
1354                     return -EIO;
1355         }
1356
1357         switch (cmd) {
1358         case MGSL_IOCGPARAMS:
1359                 return get_params(info, argp);
1360         case MGSL_IOCSPARAMS:
1361                 return set_params(info, argp);
1362         case MGSL_IOCGTXIDLE:
1363                 return get_txidle(info, argp);
1364         case MGSL_IOCSTXIDLE:
1365                 return set_txidle(info, (int)arg);
1366         case MGSL_IOCTXENABLE:
1367                 return tx_enable(info, (int)arg);
1368         case MGSL_IOCRXENABLE:
1369                 return rx_enable(info, (int)arg);
1370         case MGSL_IOCTXABORT:
1371                 return tx_abort(info);
1372         case MGSL_IOCGSTATS:
1373                 return get_stats(info, argp);
1374         case MGSL_IOCWAITEVENT:
1375                 return wait_mgsl_event(info, argp);
1376         case MGSL_IOCLOOPTXDONE:
1377                 return 0; // TODO: Not supported, need to document
1378                 /* Wait for modem input (DCD,RI,DSR,CTS) change
1379                  * as specified by mask in arg (TIOCM_RNG/DSR/CD/CTS)
1380                  */
1381         case TIOCMIWAIT:
1382                 return modem_input_wait(info,(int)arg);
1383
1384                 /*
1385                  * Get counter of input serial line interrupts (DCD,RI,DSR,CTS)
1386                  * Return: write counters to the user passed counter struct
1387                  * NB: both 1->0 and 0->1 transitions are counted except for
1388                  *     RI where only 0->1 is counted.
1389                  */
1390         case TIOCGICOUNT:
1391                 spin_lock_irqsave(&info->lock,flags);
1392                 cnow = info->icount;
1393                 spin_unlock_irqrestore(&info->lock,flags);
1394                 p_cuser = argp;
1395                 PUT_USER(error,cnow.cts, &p_cuser->cts);
1396                 if (error) return error;
1397                 PUT_USER(error,cnow.dsr, &p_cuser->dsr);
1398                 if (error) return error;
1399                 PUT_USER(error,cnow.rng, &p_cuser->rng);
1400                 if (error) return error;
1401                 PUT_USER(error,cnow.dcd, &p_cuser->dcd);
1402                 if (error) return error;
1403                 PUT_USER(error,cnow.rx, &p_cuser->rx);
1404                 if (error) return error;
1405                 PUT_USER(error,cnow.tx, &p_cuser->tx);
1406                 if (error) return error;
1407                 PUT_USER(error,cnow.frame, &p_cuser->frame);
1408                 if (error) return error;
1409                 PUT_USER(error,cnow.overrun, &p_cuser->overrun);
1410                 if (error) return error;
1411                 PUT_USER(error,cnow.parity, &p_cuser->parity);
1412                 if (error) return error;
1413                 PUT_USER(error,cnow.brk, &p_cuser->brk);
1414                 if (error) return error;
1415                 PUT_USER(error,cnow.buf_overrun, &p_cuser->buf_overrun);
1416                 if (error) return error;
1417                 return 0;
1418         default:
1419                 return -ENOIOCTLCMD;
1420         }
1421         return 0;
1422 }
1423
1424 /*
1425  * /proc fs routines....
1426  */
1427
1428 static inline int line_info(char *buf, SLMP_INFO *info)
1429 {
1430         char    stat_buf[30];
1431         int     ret;
1432         unsigned long flags;
1433
1434         ret = sprintf(buf, "%s: SCABase=%08x Mem=%08X StatusControl=%08x LCR=%08X\n"
1435                        "\tIRQ=%d MaxFrameSize=%u\n",
1436                 info->device_name,
1437                 info->phys_sca_base,
1438                 info->phys_memory_base,
1439                 info->phys_statctrl_base,
1440                 info->phys_lcr_base,
1441                 info->irq_level,
1442                 info->max_frame_size );
1443
1444         /* output current serial signal states */
1445         spin_lock_irqsave(&info->lock,flags);
1446         get_signals(info);
1447         spin_unlock_irqrestore(&info->lock,flags);
1448
1449         stat_buf[0] = 0;
1450         stat_buf[1] = 0;
1451         if (info->serial_signals & SerialSignal_RTS)
1452                 strcat(stat_buf, "|RTS");
1453         if (info->serial_signals & SerialSignal_CTS)
1454                 strcat(stat_buf, "|CTS");
1455         if (info->serial_signals & SerialSignal_DTR)
1456                 strcat(stat_buf, "|DTR");
1457         if (info->serial_signals & SerialSignal_DSR)
1458                 strcat(stat_buf, "|DSR");
1459         if (info->serial_signals & SerialSignal_DCD)
1460                 strcat(stat_buf, "|CD");
1461         if (info->serial_signals & SerialSignal_RI)
1462                 strcat(stat_buf, "|RI");
1463
1464         if (info->params.mode == MGSL_MODE_HDLC) {
1465                 ret += sprintf(buf+ret, "\tHDLC txok:%d rxok:%d",
1466                               info->icount.txok, info->icount.rxok);
1467                 if (info->icount.txunder)
1468                         ret += sprintf(buf+ret, " txunder:%d", info->icount.txunder);
1469                 if (info->icount.txabort)
1470                         ret += sprintf(buf+ret, " txabort:%d", info->icount.txabort);
1471                 if (info->icount.rxshort)
1472                         ret += sprintf(buf+ret, " rxshort:%d", info->icount.rxshort);
1473                 if (info->icount.rxlong)
1474                         ret += sprintf(buf+ret, " rxlong:%d", info->icount.rxlong);
1475                 if (info->icount.rxover)
1476                         ret += sprintf(buf+ret, " rxover:%d", info->icount.rxover);
1477                 if (info->icount.rxcrc)
1478                         ret += sprintf(buf+ret, " rxlong:%d", info->icount.rxcrc);
1479         } else {
1480                 ret += sprintf(buf+ret, "\tASYNC tx:%d rx:%d",
1481                               info->icount.tx, info->icount.rx);
1482                 if (info->icount.frame)
1483                         ret += sprintf(buf+ret, " fe:%d", info->icount.frame);
1484                 if (info->icount.parity)
1485                         ret += sprintf(buf+ret, " pe:%d", info->icount.parity);
1486                 if (info->icount.brk)
1487                         ret += sprintf(buf+ret, " brk:%d", info->icount.brk);
1488                 if (info->icount.overrun)
1489                         ret += sprintf(buf+ret, " oe:%d", info->icount.overrun);
1490         }
1491
1492         /* Append serial signal status to end */
1493         ret += sprintf(buf+ret, " %s\n", stat_buf+1);
1494
1495         ret += sprintf(buf+ret, "\ttxactive=%d bh_req=%d bh_run=%d pending_bh=%x\n",
1496          info->tx_active,info->bh_requested,info->bh_running,
1497          info->pending_bh);
1498
1499         return ret;
1500 }
1501
1502 /* Called to print information about devices
1503  */
1504 int read_proc(char *page, char **start, off_t off, int count,
1505               int *eof, void *data)
1506 {
1507         int len = 0, l;
1508         off_t   begin = 0;
1509         SLMP_INFO *info;
1510
1511         len += sprintf(page, "synclinkmp driver:%s\n", driver_version);
1512
1513         info = synclinkmp_device_list;
1514         while( info ) {
1515                 l = line_info(page + len, info);
1516                 len += l;
1517                 if (len+begin > off+count)
1518                         goto done;
1519                 if (len+begin < off) {
1520                         begin += len;
1521                         len = 0;
1522                 }
1523                 info = info->next_device;
1524         }
1525
1526         *eof = 1;
1527 done:
1528         if (off >= len+begin)
1529                 return 0;
1530         *start = page + (off-begin);
1531         return ((count < begin+len-off) ? count : begin+len-off);
1532 }
1533
1534 /* Return the count of bytes in transmit buffer
1535  */
1536 static int chars_in_buffer(struct tty_struct *tty)
1537 {
1538         SLMP_INFO *info = (SLMP_INFO *)tty->driver_data;
1539
1540         if (sanity_check(info, tty->name, "chars_in_buffer"))
1541                 return 0;
1542
1543         if (debug_level >= DEBUG_LEVEL_INFO)
1544                 printk("%s(%d):%s chars_in_buffer()=%d\n",
1545                        __FILE__, __LINE__, info->device_name, info->tx_count);
1546
1547         return info->tx_count;
1548 }
1549
1550 /* Signal remote device to throttle send data (our receive data)
1551  */
1552 static void throttle(struct tty_struct * tty)
1553 {
1554         SLMP_INFO *info = (SLMP_INFO *)tty->driver_data;
1555         unsigned long flags;
1556
1557         if (debug_level >= DEBUG_LEVEL_INFO)
1558                 printk("%s(%d):%s throttle() entry\n",
1559                          __FILE__,__LINE__, info->device_name );
1560
1561         if (sanity_check(info, tty->name, "throttle"))
1562                 return;
1563
1564         if (I_IXOFF(tty))
1565                 send_xchar(tty, STOP_CHAR(tty));
1566
1567         if (tty->termios->c_cflag & CRTSCTS) {
1568                 spin_lock_irqsave(&info->lock,flags);
1569                 info->serial_signals &= ~SerialSignal_RTS;
1570                 set_signals(info);
1571                 spin_unlock_irqrestore(&info->lock,flags);
1572         }
1573 }
1574
1575 /* Signal remote device to stop throttling send data (our receive data)
1576  */
1577 static void unthrottle(struct tty_struct * tty)
1578 {
1579         SLMP_INFO *info = (SLMP_INFO *)tty->driver_data;
1580         unsigned long flags;
1581
1582         if (debug_level >= DEBUG_LEVEL_INFO)
1583                 printk("%s(%d):%s unthrottle() entry\n",
1584                          __FILE__,__LINE__, info->device_name );
1585
1586         if (sanity_check(info, tty->name, "unthrottle"))
1587                 return;
1588
1589         if (I_IXOFF(tty)) {
1590                 if (info->x_char)
1591                         info->x_char = 0;
1592                 else
1593                         send_xchar(tty, START_CHAR(tty));
1594         }
1595
1596         if (tty->termios->c_cflag & CRTSCTS) {
1597                 spin_lock_irqsave(&info->lock,flags);
1598                 info->serial_signals |= SerialSignal_RTS;
1599                 set_signals(info);
1600                 spin_unlock_irqrestore(&info->lock,flags);
1601         }
1602 }
1603
1604 /* set or clear transmit break condition
1605  * break_state  -1=set break condition, 0=clear
1606  */
1607 static void set_break(struct tty_struct *tty, int break_state)
1608 {
1609         unsigned char RegValue;
1610         SLMP_INFO * info = (SLMP_INFO *)tty->driver_data;
1611         unsigned long flags;
1612
1613         if (debug_level >= DEBUG_LEVEL_INFO)
1614                 printk("%s(%d):%s set_break(%d)\n",
1615                          __FILE__,__LINE__, info->device_name, break_state);
1616
1617         if (sanity_check(info, tty->name, "set_break"))
1618                 return;
1619
1620         spin_lock_irqsave(&info->lock,flags);
1621         RegValue = read_reg(info, CTL);
1622         if (break_state == -1)
1623                 RegValue |= BIT3;
1624         else
1625                 RegValue &= ~BIT3;
1626         write_reg(info, CTL, RegValue);
1627         spin_unlock_irqrestore(&info->lock,flags);
1628 }
1629
1630 #ifdef CONFIG_SYNCLINK_SYNCPPP
1631
1632 /* syncppp support and callbacks */
1633
1634 static void cb_setup(struct net_device *dev)
1635 {
1636         dev->open = sppp_cb_open;
1637         dev->stop = sppp_cb_close;
1638         dev->hard_start_xmit = sppp_cb_tx;
1639         dev->do_ioctl = sppp_cb_ioctl;
1640         dev->get_stats = sppp_cb_net_stats;
1641         dev->tx_timeout = sppp_cb_tx_timeout;
1642         dev->watchdog_timeo = 10*HZ;
1643 }
1644
1645 static void sppp_init(SLMP_INFO *info)
1646 {
1647         struct net_device *d;
1648
1649         sprintf(info->netname,"mgslm%dp%d",info->adapter_num,info->port_num);
1650
1651         d = alloc_netdev(0, info->netname, cb_setup);
1652         if (!d) {
1653                 printk(KERN_WARNING "%s: alloc_netdev failed.\n",
1654                                                 info->netname);
1655                 return;
1656         }
1657
1658         info->if_ptr = &info->pppdev;
1659         info->netdev = info->pppdev.dev = d;
1660
1661         d->irq = info->irq_level;
1662         d->priv = info;
1663
1664         sppp_attach(&info->pppdev);
1665         cb_setup(d);
1666
1667         if (register_netdev(d)) {
1668                 printk(KERN_WARNING "%s: register_netdev failed.\n", d->name);
1669                 sppp_detach(info->netdev);
1670                 info->netdev = NULL;
1671                 info->pppdev.dev = NULL;
1672                 free_netdev(d);
1673                 return;
1674         }
1675
1676         if (debug_level >= DEBUG_LEVEL_INFO)
1677                 printk("sppp_init(%s)\n",info->netname);
1678 }
1679
1680 static void sppp_delete(SLMP_INFO *info)
1681 {
1682         if (debug_level >= DEBUG_LEVEL_INFO)
1683                 printk("sppp_delete(%s)\n",info->netname);
1684         unregister_netdev(info->netdev);
1685         sppp_detach(info->netdev);
1686         free_netdev(info->netdev);
1687         info->netdev = NULL;
1688         info->pppdev.dev = NULL;
1689 }
1690
1691 static int sppp_cb_open(struct net_device *d)
1692 {
1693         SLMP_INFO *info = d->priv;
1694         int err;
1695         unsigned long flags;
1696
1697         if (debug_level >= DEBUG_LEVEL_INFO)
1698                 printk("sppp_cb_open(%s)\n",info->netname);
1699
1700         spin_lock_irqsave(&info->netlock, flags);
1701         if (info->count != 0 || info->netcount != 0) {
1702                 printk(KERN_WARNING "%s: sppp_cb_open returning busy\n", info->netname);
1703                 spin_unlock_irqrestore(&info->netlock, flags);
1704                 return -EBUSY;
1705         }
1706         info->netcount=1;
1707         spin_unlock_irqrestore(&info->netlock, flags);
1708
1709         /* claim resources and init adapter */
1710         if ((err = startup(info)) != 0)
1711                 goto open_fail;
1712
1713         /* allow syncppp module to do open processing */
1714         if ((err = sppp_open(d)) != 0) {
1715                 shutdown(info);
1716                 goto open_fail;
1717         }
1718
1719         info->serial_signals |= SerialSignal_RTS + SerialSignal_DTR;
1720         program_hw(info);
1721
1722         d->trans_start = jiffies;
1723         netif_start_queue(d);
1724         return 0;
1725
1726 open_fail:
1727         spin_lock_irqsave(&info->netlock, flags);
1728         info->netcount=0;
1729         spin_unlock_irqrestore(&info->netlock, flags);
1730         return err;
1731 }
1732
1733 static void sppp_cb_tx_timeout(struct net_device *dev)
1734 {
1735         SLMP_INFO *info = dev->priv;
1736         unsigned long flags;
1737
1738         if (debug_level >= DEBUG_LEVEL_INFO)
1739                 printk("sppp_tx_timeout(%s)\n",info->netname);
1740
1741         info->netstats.tx_errors++;
1742         info->netstats.tx_aborted_errors++;
1743
1744         spin_lock_irqsave(&info->lock,flags);
1745         tx_stop(info);
1746         spin_unlock_irqrestore(&info->lock,flags);
1747
1748         netif_wake_queue(dev);
1749 }
1750
1751 static int sppp_cb_tx(struct sk_buff *skb, struct net_device *dev)
1752 {
1753         SLMP_INFO *info = dev->priv;
1754         unsigned long flags;
1755
1756         if (debug_level >= DEBUG_LEVEL_INFO)
1757                 printk("sppp_tx(%s)\n",info->netname);
1758
1759         netif_stop_queue(dev);
1760
1761         info->tx_count = skb->len;
1762         tx_load_dma_buffer(info, skb->data, skb->len);
1763         info->netstats.tx_packets++;
1764         info->netstats.tx_bytes += skb->len;
1765         dev_kfree_skb(skb);
1766
1767         dev->trans_start = jiffies;
1768
1769         spin_lock_irqsave(&info->lock,flags);
1770         if (!info->tx_active)
1771                 tx_start(info);
1772         spin_unlock_irqrestore(&info->lock,flags);
1773
1774         return 0;
1775 }
1776
1777 static int sppp_cb_close(struct net_device *d)
1778 {
1779         SLMP_INFO *info = d->priv;
1780         unsigned long flags;
1781
1782         if (debug_level >= DEBUG_LEVEL_INFO)
1783                 printk("sppp_cb_close(%s)\n",info->netname);
1784
1785         /* shutdown adapter and release resources */
1786         shutdown(info);
1787
1788         /* allow syncppp to do close processing */
1789         sppp_close(d);
1790         netif_stop_queue(d);
1791
1792         spin_lock_irqsave(&info->netlock, flags);
1793         info->netcount=0;
1794         spin_unlock_irqrestore(&info->netlock, flags);
1795         return 0;
1796 }
1797
1798 static void sppp_rx_done(SLMP_INFO *info, char *buf, int size)
1799 {
1800         struct sk_buff *skb = dev_alloc_skb(size);
1801         if (debug_level >= DEBUG_LEVEL_INFO)
1802                 printk("sppp_rx_done(%s)\n",info->netname);
1803         if (skb == NULL) {
1804                 printk(KERN_NOTICE "%s: can't alloc skb, dropping packet\n",
1805                         info->netname);
1806                 info->netstats.rx_dropped++;
1807                 return;
1808         }
1809
1810         memcpy(skb_put(skb, size),buf,size);
1811
1812         skb->protocol = htons(ETH_P_WAN_PPP);
1813         skb->dev = info->netdev;
1814         skb->mac.raw = skb->data;
1815         info->netstats.rx_packets++;
1816         info->netstats.rx_bytes += size;
1817         netif_rx(skb);
1818         info->netdev->trans_start = jiffies;
1819 }
1820
1821 static void sppp_tx_done(SLMP_INFO *info)
1822 {
1823         if (netif_queue_stopped(info->netdev))
1824             netif_wake_queue(info->netdev);
1825 }
1826
1827 static struct net_device_stats *sppp_cb_net_stats(struct net_device *dev)
1828 {
1829         SLMP_INFO *info = dev->priv;
1830         if (debug_level >= DEBUG_LEVEL_INFO)
1831                 printk("net_stats(%s)\n",info->netname);
1832         return &info->netstats;
1833 }
1834
1835 static int sppp_cb_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1836 {
1837         SLMP_INFO *info = dev->priv;
1838         if (debug_level >= DEBUG_LEVEL_INFO)
1839                 printk("%s(%d):ioctl %s cmd=%08X\n", __FILE__,__LINE__,
1840                         info->netname, cmd );
1841         return sppp_do_ioctl(dev, ifr, cmd);
1842 }
1843
1844 #endif /* ifdef CONFIG_SYNCLINK_SYNCPPP */
1845
1846
1847 /* Return next bottom half action to perform.
1848  * Return Value:        BH action code or 0 if nothing to do.
1849  */
1850 int bh_action(SLMP_INFO *info)
1851 {
1852         unsigned long flags;
1853         int rc = 0;
1854
1855         spin_lock_irqsave(&info->lock,flags);
1856
1857         if (info->pending_bh & BH_RECEIVE) {
1858                 info->pending_bh &= ~BH_RECEIVE;
1859                 rc = BH_RECEIVE;
1860         } else if (info->pending_bh & BH_TRANSMIT) {
1861                 info->pending_bh &= ~BH_TRANSMIT;
1862                 rc = BH_TRANSMIT;
1863         } else if (info->pending_bh & BH_STATUS) {
1864                 info->pending_bh &= ~BH_STATUS;
1865                 rc = BH_STATUS;
1866         }
1867
1868         if (!rc) {
1869                 /* Mark BH routine as complete */
1870                 info->bh_running   = 0;
1871                 info->bh_requested = 0;
1872         }
1873
1874         spin_unlock_irqrestore(&info->lock,flags);
1875
1876         return rc;
1877 }
1878
1879 /* Perform bottom half processing of work items queued by ISR.
1880  */
1881 void bh_handler(void* Context)
1882 {
1883         SLMP_INFO *info = (SLMP_INFO*)Context;
1884         int action;
1885
1886         if (!info)
1887                 return;
1888
1889         if ( debug_level >= DEBUG_LEVEL_BH )
1890                 printk( "%s(%d):%s bh_handler() entry\n",
1891                         __FILE__,__LINE__,info->device_name);
1892
1893         info->bh_running = 1;
1894
1895         while((action = bh_action(info)) != 0) {
1896
1897                 /* Process work item */
1898                 if ( debug_level >= DEBUG_LEVEL_BH )
1899                         printk( "%s(%d):%s bh_handler() work item action=%d\n",
1900                                 __FILE__,__LINE__,info->device_name, action);
1901
1902                 switch (action) {
1903
1904                 case BH_RECEIVE:
1905                         bh_receive(info);
1906                         break;
1907                 case BH_TRANSMIT:
1908                         bh_transmit(info);
1909                         break;
1910                 case BH_STATUS:
1911                         bh_status(info);
1912                         break;
1913                 default:
1914                         /* unknown work item ID */
1915                         printk("%s(%d):%s Unknown work item ID=%08X!\n",
1916                                 __FILE__,__LINE__,info->device_name,action);
1917                         break;
1918                 }
1919         }
1920
1921         if ( debug_level >= DEBUG_LEVEL_BH )
1922                 printk( "%s(%d):%s bh_handler() exit\n",
1923                         __FILE__,__LINE__,info->device_name);
1924 }
1925
1926 void bh_receive(SLMP_INFO *info)
1927 {
1928         if ( debug_level >= DEBUG_LEVEL_BH )
1929                 printk( "%s(%d):%s bh_receive()\n",
1930                         __FILE__,__LINE__,info->device_name);
1931
1932         while( rx_get_frame(info) );
1933 }
1934
1935 void bh_transmit(SLMP_INFO *info)
1936 {
1937         struct tty_struct *tty = info->tty;
1938
1939         if ( debug_level >= DEBUG_LEVEL_BH )
1940                 printk( "%s(%d):%s bh_transmit() entry\n",
1941                         __FILE__,__LINE__,info->device_name);
1942
1943         if (tty) {
1944                 if ((tty->flags & (1 << TTY_DO_WRITE_WAKEUP)) &&
1945                     tty->ldisc.write_wakeup) {
1946                         if ( debug_level >= DEBUG_LEVEL_BH )
1947                                 printk( "%s(%d):%s calling ldisc.write_wakeup\n",
1948                                         __FILE__,__LINE__,info->device_name);
1949                         (tty->ldisc.write_wakeup)(tty);
1950                 }
1951                 wake_up_interruptible(&tty->write_wait);
1952         }
1953 }
1954
1955 void bh_status(SLMP_INFO *info)
1956 {
1957         if ( debug_level >= DEBUG_LEVEL_BH )
1958                 printk( "%s(%d):%s bh_status() entry\n",
1959                         __FILE__,__LINE__,info->device_name);
1960
1961         info->ri_chkcount = 0;
1962         info->dsr_chkcount = 0;
1963         info->dcd_chkcount = 0;
1964         info->cts_chkcount = 0;
1965 }
1966
1967 void isr_timer(SLMP_INFO * info)
1968 {
1969         unsigned char timer = (info->port_num & 1) ? TIMER2 : TIMER0;
1970
1971         /* IER2<7..4> = timer<3..0> interrupt enables (0=disabled) */
1972         write_reg(info, IER2, 0);
1973
1974         /* TMCS, Timer Control/Status Register
1975          *
1976          * 07      CMF, Compare match flag (read only) 1=match
1977          * 06      ECMI, CMF Interrupt Enable: 0=disabled
1978          * 05      Reserved, must be 0
1979          * 04      TME, Timer Enable
1980          * 03..00  Reserved, must be 0
1981          *
1982          * 0000 0000
1983          */
1984         write_reg(info, (unsigned char)(timer + TMCS), 0);
1985
1986         info->irq_occurred = TRUE;
1987
1988         if ( debug_level >= DEBUG_LEVEL_ISR )
1989                 printk("%s(%d):%s isr_timer()\n",
1990                         __FILE__,__LINE__,info->device_name);
1991 }
1992
1993 void isr_rxint(SLMP_INFO * info)
1994 {
1995         struct tty_struct *tty = info->tty;
1996         struct  mgsl_icount *icount = &info->icount;
1997         unsigned char status = read_reg(info, SR1);
1998         unsigned char status2 = read_reg(info, SR2);
1999
2000         /* clear status bits */
2001         if ( status & (FLGD + IDLD + CDCD + BRKD) )
2002                 write_reg(info, SR1,
2003                                 (unsigned char)(status & (FLGD + IDLD + CDCD + BRKD)));
2004
2005         if ( status2 & OVRN )
2006                 write_reg(info, SR2, (unsigned char)(status2 & OVRN));
2007
2008         if ( debug_level >= DEBUG_LEVEL_ISR )
2009                 printk("%s(%d):%s isr_rxint status=%02X %02x\n",
2010                         __FILE__,__LINE__,info->device_name,status,status2);
2011
2012         if (info->params.mode == MGSL_MODE_ASYNC) {
2013                 if (status & BRKD) {
2014                         icount->brk++;
2015
2016                         /* process break detection if tty control
2017                          * is not set to ignore it
2018                          */
2019                         if ( tty ) {
2020                                 if (!(status & info->ignore_status_mask1)) {
2021                                         if (info->read_status_mask1 & BRKD) {
2022                                                 *tty->flip.flag_buf_ptr = TTY_BREAK;
2023                                                 if (info->flags & ASYNC_SAK)
2024                                                         do_SAK(tty);
2025                                         }
2026                                 }
2027                         }
2028                 }
2029         }
2030         else {
2031                 if (status & (FLGD|IDLD)) {
2032                         if (status & FLGD)
2033                                 info->icount.exithunt++;
2034                         else if (status & IDLD)
2035                                 info->icount.rxidle++;
2036                         wake_up_interruptible(&info->event_wait_q);
2037                 }
2038         }
2039
2040         if (status & CDCD) {
2041                 /* simulate a common modem status change interrupt
2042                  * for our handler
2043                  */
2044                 get_signals( info );
2045                 isr_io_pin(info,
2046                         MISCSTATUS_DCD_LATCHED|(info->serial_signals&SerialSignal_DCD));
2047         }
2048 }
2049
2050 /*
2051  * handle async rx data interrupts
2052  */
2053 void isr_rxrdy(SLMP_INFO * info)
2054 {
2055         u16 status;
2056         unsigned char DataByte;
2057         struct tty_struct *tty = info->tty;
2058         struct  mgsl_icount *icount = &info->icount;
2059
2060         if ( debug_level >= DEBUG_LEVEL_ISR )
2061                 printk("%s(%d):%s isr_rxrdy\n",
2062                         __FILE__,__LINE__,info->device_name);
2063
2064         while((status = read_reg(info,CST0)) & BIT0)
2065         {
2066                 DataByte = read_reg(info,TRB);
2067
2068                 if ( tty ) {
2069                         if (tty->flip.count >= TTY_FLIPBUF_SIZE)
2070                                 continue;
2071
2072                         *tty->flip.char_buf_ptr = DataByte;
2073                         *tty->flip.flag_buf_ptr = 0;
2074                 }
2075
2076                 icount->rx++;
2077
2078                 if ( status & (PE + FRME + OVRN) ) {
2079                         printk("%s(%d):%s rxerr=%04X\n",
2080                                 __FILE__,__LINE__,info->device_name,status);
2081
2082                         /* update error statistics */
2083                         if (status & PE)
2084                                 icount->parity++;
2085                         else if (status & FRME)
2086                                 icount->frame++;
2087                         else if (status & OVRN)
2088                                 icount->overrun++;
2089
2090                         /* discard char if tty control flags say so */
2091                         if (status & info->ignore_status_mask2)
2092                                 continue;
2093
2094                         status &= info->read_status_mask2;
2095
2096                         if ( tty ) {
2097                                 if (status & PE)
2098                                         *tty->flip.flag_buf_ptr = TTY_PARITY;
2099                                 else if (status & FRME)
2100                                         *tty->flip.flag_buf_ptr = TTY_FRAME;
2101                                 if (status & OVRN) {
2102                                         /* Overrun is special, since it's
2103                                          * reported immediately, and doesn't
2104                                          * affect the current character
2105                                          */
2106                                         if (tty->flip.count < TTY_FLIPBUF_SIZE) {
2107                                                 tty->flip.count++;
2108                                                 tty->flip.flag_buf_ptr++;
2109                                                 tty->flip.char_buf_ptr++;
2110                                                 *tty->flip.flag_buf_ptr = TTY_OVERRUN;
2111                                         }
2112                                 }
2113                         }
2114                 }       /* end of if (error) */
2115
2116                 if ( tty ) {
2117                         tty->flip.flag_buf_ptr++;
2118                         tty->flip.char_buf_ptr++;
2119                         tty->flip.count++;
2120                 }
2121         }
2122
2123         if ( debug_level >= DEBUG_LEVEL_ISR ) {
2124                 printk("%s(%d):%s isr_rxrdy() flip count=%d\n",
2125                         __FILE__,__LINE__,info->device_name,
2126                         tty ? tty->flip.count : 0);
2127                 printk("%s(%d):%s rx=%d brk=%d parity=%d frame=%d overrun=%d\n",
2128                         __FILE__,__LINE__,info->device_name,
2129                         icount->rx,icount->brk,icount->parity,
2130                         icount->frame,icount->overrun);
2131         }
2132
2133         if ( tty && tty->flip.count )
2134                 tty_flip_buffer_push(tty);
2135 }
2136
2137 void isr_txeom(SLMP_INFO * info, unsigned char status)
2138 {
2139         if ( debug_level >= DEBUG_LEVEL_ISR )
2140                 printk("%s(%d):%s isr_txeom status=%02x\n",
2141                         __FILE__,__LINE__,info->device_name,status);
2142
2143         /* disable and clear MSCI interrupts */
2144         info->ie1_value &= ~(IDLE + UDRN);
2145         write_reg(info, IE1, info->ie1_value);
2146         write_reg(info, SR1, (unsigned char)(UDRN + IDLE));
2147
2148         write_reg(info, TXDMA + DIR, 0x00); /* disable Tx DMA IRQs */
2149         write_reg(info, TXDMA + DSR, 0xc0); /* clear IRQs and disable DMA */
2150         write_reg(info, TXDMA + DCMD, SWABORT); /* reset/init DMA channel */
2151
2152         if ( info->tx_active ) {
2153                 if (info->params.mode != MGSL_MODE_ASYNC) {
2154                         if (status & UDRN)
2155                                 info->icount.txunder++;
2156                         else if (status & IDLE)
2157                                 info->icount.txok++;
2158                 }
2159
2160                 info->tx_active = 0;
2161                 info->tx_count = info->tx_put = info->tx_get = 0;
2162
2163                 del_timer(&info->tx_timer);
2164
2165                 if (info->params.mode != MGSL_MODE_ASYNC && info->drop_rts_on_tx_done ) {
2166                         info->serial_signals &= ~SerialSignal_RTS;
2167                         info->drop_rts_on_tx_done = 0;
2168                         set_signals(info);
2169                 }
2170
2171 #ifdef CONFIG_SYNCLINK_SYNCPPP
2172                 if (info->netcount)
2173                         sppp_tx_done(info);
2174                 else
2175 #endif
2176                 {
2177                         if (info->tty && (info->tty->stopped || info->tty->hw_stopped)) {
2178                                 tx_stop(info);
2179                                 return;
2180                         }
2181                         info->pending_bh |= BH_TRANSMIT;
2182                 }
2183         }
2184 }
2185
2186
2187 /*
2188  * handle tx status interrupts
2189  */
2190 void isr_txint(SLMP_INFO * info)
2191 {
2192         unsigned char status = read_reg(info, SR1);
2193
2194         /* clear status bits */
2195         write_reg(info, SR1, (unsigned char)(status & (UDRN + IDLE + CCTS)));
2196
2197         if ( debug_level >= DEBUG_LEVEL_ISR )
2198                 printk("%s(%d):%s isr_txint status=%02x\n",
2199                         __FILE__,__LINE__,info->device_name,status);
2200
2201         if (status & (UDRN + IDLE))
2202                 isr_txeom(info, status);
2203
2204         if (status & CCTS) {
2205                 /* simulate a common modem status change interrupt
2206                  * for our handler
2207                  */
2208                 get_signals( info );
2209                 isr_io_pin(info,
2210                         MISCSTATUS_CTS_LATCHED|(info->serial_signals&SerialSignal_CTS));
2211
2212         }
2213 }
2214
2215 /*
2216  * handle async tx data interrupts
2217  */
2218 void isr_txrdy(SLMP_INFO * info)
2219 {
2220         if ( debug_level >= DEBUG_LEVEL_ISR )
2221                 printk("%s(%d):%s isr_txrdy() tx_count=%d\n",
2222                         __FILE__,__LINE__,info->device_name,info->tx_count);
2223
2224         if (info->tty && (info->tty->stopped || info->tty->hw_stopped)) {
2225                 tx_stop(info);
2226                 return;
2227         }
2228
2229         if ( info->tx_count )
2230                 tx_load_fifo( info );
2231         else {
2232                 info->tx_active = 0;
2233                 info->ie0_value &= ~TXRDYE;
2234                 write_reg(info, IE0, info->ie0_value);
2235         }
2236
2237         if (info->tx_count < WAKEUP_CHARS)
2238                 info->pending_bh |= BH_TRANSMIT;
2239 }
2240
2241 void isr_rxdmaok(SLMP_INFO * info)
2242 {
2243         /* BIT7 = EOT (end of transfer)
2244          * BIT6 = EOM (end of message/frame)
2245          */
2246         unsigned char status = read_reg(info,RXDMA + DSR) & 0xc0;
2247
2248         /* clear IRQ (BIT0 must be 1 to prevent clearing DE bit) */
2249         write_reg(info, RXDMA + DSR, (unsigned char)(status | 1));
2250
2251         if ( debug_level >= DEBUG_LEVEL_ISR )
2252                 printk("%s(%d):%s isr_rxdmaok(), status=%02x\n",
2253                         __FILE__,__LINE__,info->device_name,status);
2254
2255         info->pending_bh |= BH_RECEIVE;
2256 }
2257
2258 void isr_rxdmaerror(SLMP_INFO * info)
2259 {
2260         /* BIT5 = BOF (buffer overflow)
2261          * BIT4 = COF (counter overflow)
2262          */
2263         unsigned char status = read_reg(info,RXDMA + DSR) & 0x30;
2264
2265         /* clear IRQ (BIT0 must be 1 to prevent clearing DE bit) */
2266         write_reg(info, RXDMA + DSR, (unsigned char)(status | 1));
2267
2268         if ( debug_level >= DEBUG_LEVEL_ISR )
2269                 printk("%s(%d):%s isr_rxdmaerror(), status=%02x\n",
2270                         __FILE__,__LINE__,info->device_name,status);
2271
2272         info->rx_overflow = TRUE;
2273         info->pending_bh |= BH_RECEIVE;
2274 }
2275
2276 void isr_txdmaok(SLMP_INFO * info)
2277 {
2278         /* BIT7 = EOT (end of transfer, used for async mode)
2279          * BIT6 = EOM (end of message/frame, used for sync mode)
2280          *
2281          * We don't look at DMA status because only EOT is enabled
2282          * and we always clear and disable all tx DMA IRQs.
2283          */
2284 //      unsigned char dma_status = read_reg(info,TXDMA + DSR) & 0xc0;
2285         unsigned char status_reg1 = read_reg(info, SR1);
2286
2287         write_reg(info, TXDMA + DIR, 0x00);     /* disable Tx DMA IRQs */
2288         write_reg(info, TXDMA + DSR, 0xc0); /* clear IRQs and disable DMA */
2289         write_reg(info, TXDMA + DCMD, SWABORT); /* reset/init DMA channel */
2290
2291         if ( debug_level >= DEBUG_LEVEL_ISR )
2292                 printk("%s(%d):%s isr_txdmaok(), status=%02x\n",
2293                         __FILE__,__LINE__,info->device_name,status_reg1);
2294
2295         /* If transmitter already idle, do end of frame processing,
2296          * otherwise enable interrupt for tx IDLE.
2297          */
2298         if (status_reg1 & IDLE)
2299                 isr_txeom(info, IDLE);
2300         else {
2301                 /* disable and clear underrun IRQ, enable IDLE interrupt */
2302                 info->ie1_value |= IDLE;
2303                 info->ie1_value &= ~UDRN;
2304                 write_reg(info, IE1, info->ie1_value);
2305
2306                 write_reg(info, SR1, UDRN);
2307         }
2308 }
2309
2310 void isr_txdmaerror(SLMP_INFO * info)
2311 {
2312         /* BIT5 = BOF (buffer overflow)
2313          * BIT4 = COF (counter overflow)
2314          */
2315         unsigned char status = read_reg(info,TXDMA + DSR) & 0x30;
2316
2317         /* clear IRQ (BIT0 must be 1 to prevent clearing DE bit) */
2318         write_reg(info, TXDMA + DSR, (unsigned char)(status | 1));
2319
2320         if ( debug_level >= DEBUG_LEVEL_ISR )
2321                 printk("%s(%d):%s isr_txdmaerror(), status=%02x\n",
2322                         __FILE__,__LINE__,info->device_name,status);
2323 }
2324
2325 /* handle input serial signal changes
2326  */
2327 void isr_io_pin( SLMP_INFO *info, u16 status )
2328 {
2329         struct  mgsl_icount *icount;
2330
2331         if ( debug_level >= DEBUG_LEVEL_ISR )
2332                 printk("%s(%d):isr_io_pin status=%04X\n",
2333                         __FILE__,__LINE__,status);
2334
2335         if (status & (MISCSTATUS_CTS_LATCHED | MISCSTATUS_DCD_LATCHED |
2336                       MISCSTATUS_DSR_LATCHED | MISCSTATUS_RI_LATCHED) ) {
2337                 icount = &info->icount;
2338                 /* update input line counters */
2339                 if (status & MISCSTATUS_RI_LATCHED) {
2340                         icount->rng++;
2341                         if ( status & SerialSignal_RI )
2342                                 info->input_signal_events.ri_up++;
2343                         else
2344                                 info->input_signal_events.ri_down++;
2345                 }
2346                 if (status & MISCSTATUS_DSR_LATCHED) {
2347                         icount->dsr++;
2348                         if ( status & SerialSignal_DSR )
2349                                 info->input_signal_events.dsr_up++;
2350                         else
2351                                 info->input_signal_events.dsr_down++;
2352                 }
2353                 if (status & MISCSTATUS_DCD_LATCHED) {
2354                         if ((info->dcd_chkcount)++ >= IO_PIN_SHUTDOWN_LIMIT) {
2355                                 info->ie1_value &= ~CDCD;
2356                                 write_reg(info, IE1, info->ie1_value);
2357                         }
2358                         icount->dcd++;
2359                         if (status & SerialSignal_DCD) {
2360                                 info->input_signal_events.dcd_up++;
2361 #ifdef CONFIG_SYNCLINK_SYNCPPP
2362                                 if (info->netcount)
2363                                         sppp_reopen(info->netdev);
2364 #endif
2365                         } else
2366                                 info->input_signal_events.dcd_down++;
2367                 }
2368                 if (status & MISCSTATUS_CTS_LATCHED)
2369                 {
2370                         if ((info->cts_chkcount)++ >= IO_PIN_SHUTDOWN_LIMIT) {
2371                                 info->ie1_value &= ~CCTS;
2372                                 write_reg(info, IE1, info->ie1_value);
2373                         }
2374                         icount->cts++;
2375                         if ( status & SerialSignal_CTS )
2376                                 info->input_signal_events.cts_up++;
2377                         else
2378                                 info->input_signal_events.cts_down++;
2379                 }
2380                 wake_up_interruptible(&info->status_event_wait_q);
2381                 wake_up_interruptible(&info->event_wait_q);
2382
2383                 if ( (info->flags & ASYNC_CHECK_CD) &&
2384                      (status & MISCSTATUS_DCD_LATCHED) ) {
2385                         if ( debug_level >= DEBUG_LEVEL_ISR )
2386                                 printk("%s CD now %s...", info->device_name,
2387                                        (status & SerialSignal_DCD) ? "on" : "off");
2388                         if (status & SerialSignal_DCD)
2389                                 wake_up_interruptible(&info->open_wait);
2390                         else {
2391                                 if ( debug_level >= DEBUG_LEVEL_ISR )
2392                                         printk("doing serial hangup...");
2393                                 if (info->tty)
2394                                         tty_hangup(info->tty);
2395                         }
2396                 }
2397
2398                 if ( (info->flags & ASYNC_CTS_FLOW) &&
2399                      (status & MISCSTATUS_CTS_LATCHED) ) {
2400                         if ( info->tty ) {
2401                                 if (info->tty->hw_stopped) {
2402                                         if (status & SerialSignal_CTS) {
2403                                                 if ( debug_level >= DEBUG_LEVEL_ISR )
2404                                                         printk("CTS tx start...");
2405                                                 info->tty->hw_stopped = 0;
2406                                                 tx_start(info);
2407                                                 info->pending_bh |= BH_TRANSMIT;
2408                                                 return;
2409                                         }
2410                                 } else {
2411                                         if (!(status & SerialSignal_CTS)) {
2412                                                 if ( debug_level >= DEBUG_LEVEL_ISR )
2413                                                         printk("CTS tx stop...");
2414                                                 info->tty->hw_stopped = 1;
2415                                                 tx_stop(info);
2416                                         }
2417                                 }
2418                         }
2419                 }
2420         }
2421
2422         info->pending_bh |= BH_STATUS;
2423 }
2424
2425 /* Interrupt service routine entry point.
2426  *
2427  * Arguments:
2428  *      irq             interrupt number that caused interrupt
2429  *      dev_id          device ID supplied during interrupt registration
2430  *      regs            interrupted processor context
2431  */
2432 static irqreturn_t synclinkmp_interrupt(int irq, void *dev_id,
2433                                         struct pt_regs *regs)
2434 {
2435         SLMP_INFO * info;
2436         unsigned char status, status0, status1=0;
2437         unsigned char dmastatus, dmastatus0, dmastatus1=0;
2438         unsigned char timerstatus0, timerstatus1=0;
2439         unsigned char shift;
2440         unsigned int i;
2441         unsigned short tmp;
2442
2443         if ( debug_level >= DEBUG_LEVEL_ISR )
2444                 printk("%s(%d): synclinkmp_interrupt(%d)entry.\n",
2445                         __FILE__,__LINE__,irq);
2446
2447         info = (SLMP_INFO *)dev_id;
2448         if (!info)
2449                 return IRQ_NONE;
2450
2451         spin_lock(&info->lock);
2452
2453         for(;;) {
2454
2455                 /* get status for SCA0 (ports 0-1) */
2456                 tmp = read_reg16(info, ISR0);   /* get ISR0 and ISR1 in one read */
2457                 status0 = (unsigned char)tmp;
2458                 dmastatus0 = (unsigned char)(tmp>>8);
2459                 timerstatus0 = read_reg(info, ISR2);
2460
2461                 if ( debug_level >= DEBUG_LEVEL_ISR )
2462                         printk("%s(%d):%s status0=%02x, dmastatus0=%02x, timerstatus0=%02x\n",
2463                                 __FILE__,__LINE__,info->device_name,
2464                                 status0,dmastatus0,timerstatus0);
2465
2466                 if (info->port_count == 4) {
2467                         /* get status for SCA1 (ports 2-3) */
2468                         tmp = read_reg16(info->port_array[2], ISR0);
2469                         status1 = (unsigned char)tmp;
2470                         dmastatus1 = (unsigned char)(tmp>>8);
2471                         timerstatus1 = read_reg(info->port_array[2], ISR2);
2472
2473                         if ( debug_level >= DEBUG_LEVEL_ISR )
2474                                 printk("%s(%d):%s status1=%02x, dmastatus1=%02x, timerstatus1=%02x\n",
2475                                         __FILE__,__LINE__,info->device_name,
2476                                         status1,dmastatus1,timerstatus1);
2477                 }
2478
2479                 if (!status0 && !dmastatus0 && !timerstatus0 &&
2480                          !status1 && !dmastatus1 && !timerstatus1)
2481                         break;
2482
2483                 for(i=0; i < info->port_count ; i++) {
2484                         if (info->port_array[i] == NULL)
2485                                 continue;
2486                         if (i < 2) {
2487                                 status = status0;
2488                                 dmastatus = dmastatus0;
2489                         } else {
2490                                 status = status1;
2491                                 dmastatus = dmastatus1;
2492                         }
2493
2494                         shift = i & 1 ? 4 :0;
2495
2496                         if (status & BIT0 << shift)
2497                                 isr_rxrdy(info->port_array[i]);
2498                         if (status & BIT1 << shift)
2499                                 isr_txrdy(info->port_array[i]);
2500                         if (status & BIT2 << shift)
2501                                 isr_rxint(info->port_array[i]);
2502                         if (status & BIT3 << shift)
2503                                 isr_txint(info->port_array[i]);
2504
2505                         if (dmastatus & BIT0 << shift)
2506                                 isr_rxdmaerror(info->port_array[i]);
2507                         if (dmastatus & BIT1 << shift)
2508                                 isr_rxdmaok(info->port_array[i]);
2509                         if (dmastatus & BIT2 << shift)
2510                                 isr_txdmaerror(info->port_array[i]);
2511                         if (dmastatus & BIT3 << shift)
2512                                 isr_txdmaok(info->port_array[i]);
2513                 }
2514
2515                 if (timerstatus0 & (BIT5 | BIT4))
2516                         isr_timer(info->port_array[0]);
2517                 if (timerstatus0 & (BIT7 | BIT6))
2518                         isr_timer(info->port_array[1]);
2519                 if (timerstatus1 & (BIT5 | BIT4))
2520                         isr_timer(info->port_array[2]);
2521                 if (timerstatus1 & (BIT7 | BIT6))
2522                         isr_timer(info->port_array[3]);
2523         }
2524
2525         for(i=0; i < info->port_count ; i++) {
2526                 SLMP_INFO * port = info->port_array[i];
2527
2528                 /* Request bottom half processing if there's something
2529                  * for it to do and the bh is not already running.
2530                  *
2531                  * Note: startup adapter diags require interrupts.
2532                  * do not request bottom half processing if the
2533                  * device is not open in a normal mode.
2534                  */
2535                 if ( port && (port->count || port->netcount) &&
2536                      port->pending_bh && !port->bh_running &&
2537                      !port->bh_requested ) {
2538                         if ( debug_level >= DEBUG_LEVEL_ISR )
2539                                 printk("%s(%d):%s queueing bh task.\n",
2540                                         __FILE__,__LINE__,port->device_name);
2541                         schedule_work(&port->task);
2542                         port->bh_requested = 1;
2543                 }
2544         }
2545
2546         spin_unlock(&info->lock);
2547
2548         if ( debug_level >= DEBUG_LEVEL_ISR )
2549                 printk("%s(%d):synclinkmp_interrupt(%d)exit.\n",
2550                         __FILE__,__LINE__,irq);
2551         return IRQ_HANDLED;
2552 }
2553
2554 /* Initialize and start device.
2555  */
2556 static int startup(SLMP_INFO * info)
2557 {
2558         if ( debug_level >= DEBUG_LEVEL_INFO )
2559                 printk("%s(%d):%s tx_releaseup()\n",__FILE__,__LINE__,info->device_name);
2560
2561         if (info->flags & ASYNC_INITIALIZED)
2562                 return 0;
2563
2564         if (!info->tx_buf) {
2565                 info->tx_buf = (unsigned char *)kmalloc(info->max_frame_size, GFP_KERNEL);
2566                 if (!info->tx_buf) {
2567                         printk(KERN_ERR"%s(%d):%s can't allocate transmit buffer\n",
2568                                 __FILE__,__LINE__,info->device_name);
2569                         return -ENOMEM;
2570                 }
2571         }
2572
2573         info->pending_bh = 0;
2574
2575         /* program hardware for current parameters */
2576         reset_port(info);
2577
2578         change_params(info);
2579
2580         info->status_timer.expires = jiffies + jiffies_from_ms(10);
2581         add_timer(&info->status_timer);
2582
2583         if (info->tty)
2584                 clear_bit(TTY_IO_ERROR, &info->tty->flags);
2585
2586         info->flags |= ASYNC_INITIALIZED;
2587
2588         return 0;
2589 }
2590
2591 /* Called by close() and hangup() to shutdown hardware
2592  */
2593 static void shutdown(SLMP_INFO * info)
2594 {
2595         unsigned long flags;
2596
2597         if (!(info->flags & ASYNC_INITIALIZED))
2598                 return;
2599
2600         if (debug_level >= DEBUG_LEVEL_INFO)
2601                 printk("%s(%d):%s synclinkmp_shutdown()\n",
2602                          __FILE__,__LINE__, info->device_name );
2603
2604         /* clear status wait queue because status changes */
2605         /* can't happen after shutting down the hardware */
2606         wake_up_interruptible(&info->status_event_wait_q);
2607         wake_up_interruptible(&info->event_wait_q);
2608
2609         del_timer(&info->tx_timer);
2610         del_timer(&info->status_timer);
2611
2612         if (info->tx_buf) {
2613                 kfree(info->tx_buf);
2614                 info->tx_buf = NULL;
2615         }
2616
2617         spin_lock_irqsave(&info->lock,flags);
2618
2619         reset_port(info);
2620
2621         if (!info->tty || info->tty->termios->c_cflag & HUPCL) {
2622                 info->serial_signals &= ~(SerialSignal_DTR + SerialSignal_RTS);
2623                 set_signals(info);
2624         }
2625
2626         spin_unlock_irqrestore(&info->lock,flags);
2627
2628         if (info->tty)
2629                 set_bit(TTY_IO_ERROR, &info->tty->flags);
2630
2631         info->flags &= ~ASYNC_INITIALIZED;
2632 }
2633
2634 static void program_hw(SLMP_INFO *info)
2635 {
2636         unsigned long flags;
2637
2638         spin_lock_irqsave(&info->lock,flags);
2639
2640         rx_stop(info);
2641         tx_stop(info);
2642
2643         info->tx_count = info->tx_put = info->tx_get = 0;
2644
2645         if (info->params.mode == MGSL_MODE_HDLC || info->netcount)
2646                 hdlc_mode(info);
2647         else
2648                 async_mode(info);
2649
2650         set_signals(info);
2651
2652         info->dcd_chkcount = 0;
2653         info->cts_chkcount = 0;
2654         info->ri_chkcount = 0;
2655         info->dsr_chkcount = 0;
2656
2657         info->ie1_value |= (CDCD|CCTS);
2658         write_reg(info, IE1, info->ie1_value);
2659
2660         get_signals(info);
2661
2662         if (info->netcount || (info->tty && info->tty->termios->c_cflag & CREAD) )
2663                 rx_start(info);
2664
2665         spin_unlock_irqrestore(&info->lock,flags);
2666 }
2667
2668 /* Reconfigure adapter based on new parameters
2669  */
2670 static void change_params(SLMP_INFO *info)
2671 {
2672         unsigned cflag;
2673         int bits_per_char;
2674
2675         if (!info->tty || !info->tty->termios)
2676                 return;
2677
2678         if (debug_level >= DEBUG_LEVEL_INFO)
2679                 printk("%s(%d):%s change_params()\n",
2680                          __FILE__,__LINE__, info->device_name );
2681
2682         cflag = info->tty->termios->c_cflag;
2683
2684         /* if B0 rate (hangup) specified then negate DTR and RTS */
2685         /* otherwise assert DTR and RTS */
2686         if (cflag & CBAUD)
2687                 info->serial_signals |= SerialSignal_RTS + SerialSignal_DTR;
2688         else
2689                 info->serial_signals &= ~(SerialSignal_RTS + SerialSignal_DTR);
2690
2691         /* byte size and parity */
2692
2693         switch (cflag & CSIZE) {
2694               case CS5: info->params.data_bits = 5; break;
2695               case CS6: info->params.data_bits = 6; break;
2696               case CS7: info->params.data_bits = 7; break;
2697               case CS8: info->params.data_bits = 8; break;
2698               /* Never happens, but GCC is too dumb to figure it out */
2699               default:  info->params.data_bits = 7; break;
2700               }
2701
2702         if (cflag & CSTOPB)
2703                 info->params.stop_bits = 2;
2704         else
2705                 info->params.stop_bits = 1;
2706
2707         info->params.parity = ASYNC_PARITY_NONE;
2708         if (cflag & PARENB) {
2709                 if (cflag & PARODD)
2710                         info->params.parity = ASYNC_PARITY_ODD;
2711                 else
2712                         info->params.parity = ASYNC_PARITY_EVEN;
2713 #ifdef CMSPAR
2714                 if (cflag & CMSPAR)
2715                         info->params.parity = ASYNC_PARITY_SPACE;
2716 #endif
2717         }
2718
2719         /* calculate number of jiffies to transmit a full
2720          * FIFO (32 bytes) at specified data rate
2721          */
2722         bits_per_char = info->params.data_bits +
2723                         info->params.stop_bits + 1;
2724
2725         /* if port data rate is set to 460800 or less then
2726          * allow tty settings to override, otherwise keep the
2727          * current data rate.
2728          */
2729         if (info->params.data_rate <= 460800) {
2730                 info->params.data_rate = tty_get_baud_rate(info->tty);
2731         }
2732
2733         if ( info->params.data_rate ) {
2734                 info->timeout = (32*HZ*bits_per_char) /
2735                                 info->params.data_rate;
2736         }
2737         info->timeout += HZ/50;         /* Add .02 seconds of slop */
2738
2739         if (cflag & CRTSCTS)
2740                 info->flags |= ASYNC_CTS_FLOW;
2741         else
2742                 info->flags &= ~ASYNC_CTS_FLOW;
2743
2744         if (cflag & CLOCAL)
2745                 info->flags &= ~ASYNC_CHECK_CD;
2746         else
2747                 info->flags |= ASYNC_CHECK_CD;
2748
2749         /* process tty input control flags */
2750
2751         info->read_status_mask2 = OVRN;
2752         if (I_INPCK(info->tty))
2753                 info->read_status_mask2 |= PE | FRME;
2754         if (I_BRKINT(info->tty) || I_PARMRK(info->tty))
2755                 info->read_status_mask1 |= BRKD;
2756         if (I_IGNPAR(info->tty))
2757                 info->ignore_status_mask2 |= PE | FRME;
2758         if (I_IGNBRK(info->tty)) {
2759                 info->ignore_status_mask1 |= BRKD;
2760                 /* If ignoring parity and break indicators, ignore
2761                  * overruns too.  (For real raw support).
2762                  */
2763                 if (I_IGNPAR(info->tty))
2764                         info->ignore_status_mask2 |= OVRN;
2765         }
2766
2767         program_hw(info);
2768 }
2769
2770 static int get_stats(SLMP_INFO * info, struct mgsl_icount __user *user_icount)
2771 {
2772         int err;
2773
2774         if (debug_level >= DEBUG_LEVEL_INFO)
2775                 printk("%s(%d):%s get_params()\n",
2776                          __FILE__,__LINE__, info->device_name);
2777
2778         COPY_TO_USER(err,user_icount, &info->icount, sizeof(struct mgsl_icount));
2779         if (err) {
2780                 if ( debug_level >= DEBUG_LEVEL_INFO )
2781                         printk( "%s(%d):%s get_stats() user buffer copy failed\n",
2782                                 __FILE__,__LINE__,info->device_name);
2783                 return -EFAULT;
2784         }
2785
2786         return 0;
2787 }
2788
2789 static int get_params(SLMP_INFO * info, MGSL_PARAMS __user *user_params)
2790 {
2791         int err;
2792         if (debug_level >= DEBUG_LEVEL_INFO)
2793                 printk("%s(%d):%s get_params()\n",
2794                          __FILE__,__LINE__, info->device_name);
2795
2796         COPY_TO_USER(err,user_params, &info->params, sizeof(MGSL_PARAMS));
2797         if (err) {
2798                 if ( debug_level >= DEBUG_LEVEL_INFO )
2799                         printk( "%s(%d):%s get_params() user buffer copy failed\n",
2800                                 __FILE__,__LINE__,info->device_name);
2801                 return -EFAULT;
2802         }
2803
2804         return 0;
2805 }
2806
2807 static int set_params(SLMP_INFO * info, MGSL_PARAMS __user *new_params)
2808 {
2809         unsigned long flags;
2810         MGSL_PARAMS tmp_params;
2811         int err;
2812
2813         if (debug_level >= DEBUG_LEVEL_INFO)
2814                 printk("%s(%d):%s set_params\n",
2815                         __FILE__,__LINE__,info->device_name );
2816         COPY_FROM_USER(err,&tmp_params, new_params, sizeof(MGSL_PARAMS));
2817         if (err) {
2818                 if ( debug_level >= DEBUG_LEVEL_INFO )
2819                         printk( "%s(%d):%s set_params() user buffer copy failed\n",
2820                                 __FILE__,__LINE__,info->device_name);
2821                 return -EFAULT;
2822         }
2823
2824         spin_lock_irqsave(&info->lock,flags);
2825         memcpy(&info->params,&tmp_params,sizeof(MGSL_PARAMS));
2826         spin_unlock_irqrestore(&info->lock,flags);
2827
2828         change_params(info);
2829
2830         return 0;
2831 }
2832
2833 static int get_txidle(SLMP_INFO * info, int __user *idle_mode)
2834 {
2835         int err;
2836
2837         if (debug_level >= DEBUG_LEVEL_INFO)
2838                 printk("%s(%d):%s get_txidle()=%d\n",
2839                          __FILE__,__LINE__, info->device_name, info->idle_mode);
2840
2841         COPY_TO_USER(err,idle_mode, &info->idle_mode, sizeof(int));
2842         if (err) {
2843                 if ( debug_level >= DEBUG_LEVEL_INFO )
2844                         printk( "%s(%d):%s get_txidle() user buffer copy failed\n",
2845                                 __FILE__,__LINE__,info->device_name);
2846                 return -EFAULT;
2847         }
2848
2849         return 0;
2850 }
2851
2852 static int set_txidle(SLMP_INFO * info, int idle_mode)
2853 {
2854         unsigned long flags;
2855
2856         if (debug_level >= DEBUG_LEVEL_INFO)
2857                 printk("%s(%d):%s set_txidle(%d)\n",
2858                         __FILE__,__LINE__,info->device_name, idle_mode );
2859
2860         spin_lock_irqsave(&info->lock,flags);
2861         info->idle_mode = idle_mode;
2862         tx_set_idle( info );
2863         spin_unlock_irqrestore(&info->lock,flags);
2864         return 0;
2865 }
2866
2867 static int tx_enable(SLMP_INFO * info, int enable)
2868 {
2869         unsigned long flags;
2870
2871         if (debug_level >= DEBUG_LEVEL_INFO)
2872                 printk("%s(%d):%s tx_enable(%d)\n",
2873                         __FILE__,__LINE__,info->device_name, enable);
2874
2875         spin_lock_irqsave(&info->lock,flags);
2876         if ( enable ) {
2877                 if ( !info->tx_enabled ) {
2878                         tx_start(info);
2879                 }
2880         } else {
2881                 if ( info->tx_enabled )
2882                         tx_stop(info);
2883         }
2884         spin_unlock_irqrestore(&info->lock,flags);
2885         return 0;
2886 }
2887
2888 /* abort send HDLC frame
2889  */
2890 static int tx_abort(SLMP_INFO * info)
2891 {
2892         unsigned long flags;
2893
2894         if (debug_level >= DEBUG_LEVEL_INFO)
2895                 printk("%s(%d):%s tx_abort()\n",
2896                         __FILE__,__LINE__,info->device_name);
2897
2898         spin_lock_irqsave(&info->lock,flags);
2899         if ( info->tx_active && info->params.mode == MGSL_MODE_HDLC ) {
2900                 info->ie1_value &= ~UDRN;
2901                 info->ie1_value |= IDLE;
2902                 write_reg(info, IE1, info->ie1_value);  /* disable tx status interrupts */
2903                 write_reg(info, SR1, (unsigned char)(IDLE + UDRN));     /* clear pending */
2904
2905                 write_reg(info, TXDMA + DSR, 0);                /* disable DMA channel */
2906                 write_reg(info, TXDMA + DCMD, SWABORT); /* reset/init DMA channel */
2907
2908                 write_reg(info, CMD, TXABORT);
2909         }
2910         spin_unlock_irqrestore(&info->lock,flags);
2911         return 0;
2912 }
2913
2914 static int rx_enable(SLMP_INFO * info, int enable)
2915 {
2916         unsigned long flags;
2917
2918         if (debug_level >= DEBUG_LEVEL_INFO)
2919                 printk("%s(%d):%s rx_enable(%d)\n",
2920                         __FILE__,__LINE__,info->device_name,enable);
2921
2922         spin_lock_irqsave(&info->lock,flags);
2923         if ( enable ) {
2924                 if ( !info->rx_enabled )
2925                         rx_start(info);
2926         } else {
2927                 if ( info->rx_enabled )
2928                         rx_stop(info);
2929         }
2930         spin_unlock_irqrestore(&info->lock,flags);
2931         return 0;
2932 }
2933
2934 static int map_status(int signals)
2935 {
2936         /* Map status bits to API event bits */
2937
2938         return ((signals & SerialSignal_DSR) ? MgslEvent_DsrActive : MgslEvent_DsrInactive) +
2939                ((signals & SerialSignal_CTS) ? MgslEvent_CtsActive : MgslEvent_CtsInactive) +
2940                ((signals & SerialSignal_DCD) ? MgslEvent_DcdActive : MgslEvent_DcdInactive) +
2941                ((signals & SerialSignal_RI)  ? MgslEvent_RiActive : MgslEvent_RiInactive);
2942 }
2943
2944 /* wait for specified event to occur
2945  */
2946 static int wait_mgsl_event(SLMP_INFO * info, int __user *mask_ptr)
2947 {
2948         unsigned long flags;
2949         int s;
2950         int rc=0;
2951         struct mgsl_icount cprev, cnow;
2952         int events;
2953         int mask;
2954         struct  _input_signal_events oldsigs, newsigs;
2955         DECLARE_WAITQUEUE(wait, current);
2956
2957         COPY_FROM_USER(rc,&mask, mask_ptr, sizeof(int));
2958         if (rc) {
2959                 return  -EFAULT;
2960         }
2961
2962         if (debug_level >= DEBUG_LEVEL_INFO)
2963                 printk("%s(%d):%s wait_mgsl_event(%d)\n",
2964                         __FILE__,__LINE__,info->device_name,mask);
2965
2966         spin_lock_irqsave(&info->lock,flags);
2967
2968         /* return immediately if state matches requested events */
2969         get_signals(info);
2970         s = map_status(info->serial_signals);
2971
2972         events = mask &
2973                 ( ((s & SerialSignal_DSR) ? MgslEvent_DsrActive:MgslEvent_DsrInactive) +
2974                   ((s & SerialSignal_DCD) ? MgslEvent_DcdActive:MgslEvent_DcdInactive) +
2975                   ((s & SerialSignal_CTS) ? MgslEvent_CtsActive:MgslEvent_CtsInactive) +
2976                   ((s & SerialSignal_RI)  ? MgslEvent_RiActive :MgslEvent_RiInactive) );
2977         if (events) {
2978                 spin_unlock_irqrestore(&info->lock,flags);
2979                 goto exit;
2980         }
2981
2982         /* save current irq counts */
2983         cprev = info->icount;
2984         oldsigs = info->input_signal_events;
2985
2986         /* enable hunt and idle irqs if needed */
2987         if (mask & (MgslEvent_ExitHuntMode+MgslEvent_IdleReceived)) {
2988                 unsigned char oldval = info->ie1_value;
2989                 unsigned char newval = oldval +
2990                          (mask & MgslEvent_ExitHuntMode ? FLGD:0) +
2991                          (mask & MgslEvent_IdleReceived ? IDLE:0);
2992                 if ( oldval != newval ) {
2993                         info->ie1_value = newval;
2994                         write_reg(info, IE1, info->ie1_value);
2995                 }
2996         }
2997
2998         set_current_state(TASK_INTERRUPTIBLE);
2999         add_wait_queue(&info->event_wait_q, &wait);
3000
3001         spin_unlock_irqrestore(&info->lock,flags);
3002
3003         for(;;) {
3004                 schedule();
3005                 if (signal_pending(current)) {
3006                         rc = -ERESTARTSYS;
3007                         break;
3008                 }
3009
3010                 /* get current irq counts */
3011                 spin_lock_irqsave(&info->lock,flags);
3012                 cnow = info->icount;
3013                 newsigs = info->input_signal_events;
3014                 set_current_state(TASK_INTERRUPTIBLE);
3015                 spin_unlock_irqrestore(&info->lock,flags);
3016
3017                 /* if no change, wait aborted for some reason */
3018                 if (newsigs.dsr_up   == oldsigs.dsr_up   &&
3019                     newsigs.dsr_down == oldsigs.dsr_down &&
3020                     newsigs.dcd_up   == oldsigs.dcd_up   &&
3021                     newsigs.dcd_down == oldsigs.dcd_down &&
3022                     newsigs.cts_up   == oldsigs.cts_up   &&
3023                     newsigs.cts_down == oldsigs.cts_down &&
3024                     newsigs.ri_up    == oldsigs.ri_up    &&
3025                     newsigs.ri_down  == oldsigs.ri_down  &&
3026                     cnow.exithunt    == cprev.exithunt   &&
3027                     cnow.rxidle      == cprev.rxidle) {
3028                         rc = -EIO;
3029                         break;
3030                 }
3031
3032                 events = mask &
3033                         ( (newsigs.dsr_up   != oldsigs.dsr_up   ? MgslEvent_DsrActive:0)   +
3034                           (newsigs.dsr_down != oldsigs.dsr_down ? MgslEvent_DsrInactive:0) +
3035                           (newsigs.dcd_up   != oldsigs.dcd_up   ? MgslEvent_DcdActive:0)   +
3036                           (newsigs.dcd_down != oldsigs.dcd_down ? MgslEvent_DcdInactive:0) +
3037                           (newsigs.cts_up   != oldsigs.cts_up   ? MgslEvent_CtsActive:0)   +
3038                           (newsigs.cts_down != oldsigs.cts_down ? MgslEvent_CtsInactive:0) +
3039                           (newsigs.ri_up    != oldsigs.ri_up    ? MgslEvent_RiActive:0)    +
3040                           (newsigs.ri_down  != oldsigs.ri_down  ? MgslEvent_RiInactive:0)  +
3041                           (cnow.exithunt    != cprev.exithunt   ? MgslEvent_ExitHuntMode:0) +
3042                           (cnow.rxidle      != cprev.rxidle     ? MgslEvent_IdleReceived:0) );
3043                 if (events)
3044                         break;
3045
3046                 cprev = cnow;
3047                 oldsigs = newsigs;
3048         }
3049
3050         remove_wait_queue(&info->event_wait_q, &wait);
3051         set_current_state(TASK_RUNNING);
3052
3053
3054         if (mask & (MgslEvent_ExitHuntMode + MgslEvent_IdleReceived)) {
3055                 spin_lock_irqsave(&info->lock,flags);
3056                 if (!waitqueue_active(&info->event_wait_q)) {
3057                         /* disable enable exit hunt mode/idle rcvd IRQs */
3058                         info->ie1_value &= ~(FLGD|IDLE);
3059                         write_reg(info, IE1, info->ie1_value);
3060                 }
3061                 spin_unlock_irqrestore(&info->lock,flags);
3062         }
3063 exit:
3064         if ( rc == 0 )
3065                 PUT_USER(rc, events, mask_ptr);
3066
3067         return rc;
3068 }
3069
3070 static int modem_input_wait(SLMP_INFO *info,int arg)
3071 {
3072         unsigned long flags;
3073         int rc;
3074         struct mgsl_icount cprev, cnow;
3075         DECLARE_WAITQUEUE(wait, current);
3076
3077         /* save current irq counts */
3078         spin_lock_irqsave(&info->lock,flags);
3079         cprev = info->icount;
3080         add_wait_queue(&info->status_event_wait_q, &wait);
3081         set_current_state(TASK_INTERRUPTIBLE);
3082         spin_unlock_irqrestore(&info->lock,flags);
3083
3084         for(;;) {
3085                 schedule();
3086                 if (signal_pending(current)) {
3087                         rc = -ERESTARTSYS;
3088                         break;
3089                 }
3090
3091                 /* get new irq counts */
3092                 spin_lock_irqsave(&info->lock,flags);
3093                 cnow = info->icount;
3094                 set_current_state(TASK_INTERRUPTIBLE);
3095                 spin_unlock_irqrestore(&info->lock,flags);
3096
3097                 /* if no change, wait aborted for some reason */
3098                 if (cnow.rng == cprev.rng && cnow.dsr == cprev.dsr &&
3099                     cnow.dcd == cprev.dcd && cnow.cts == cprev.cts) {
3100                         rc = -EIO;
3101                         break;
3102                 }
3103
3104                 /* check for change in caller specified modem input */
3105                 if ((arg & TIOCM_RNG && cnow.rng != cprev.rng) ||
3106                     (arg & TIOCM_DSR && cnow.dsr != cprev.dsr) ||
3107                     (arg & TIOCM_CD  && cnow.dcd != cprev.dcd) ||
3108                     (arg & TIOCM_CTS && cnow.cts != cprev.cts)) {
3109                         rc = 0;
3110                         break;
3111                 }
3112
3113                 cprev = cnow;
3114         }
3115         remove_wait_queue(&info->status_event_wait_q, &wait);
3116         set_current_state(TASK_RUNNING);
3117         return rc;
3118 }
3119
3120 /* return the state of the serial control and status signals
3121  */
3122 static int tiocmget(struct tty_struct *tty, struct file *file)
3123 {
3124         SLMP_INFO *info = (SLMP_INFO *)tty->driver_data;
3125         unsigned int result;
3126         unsigned long flags;
3127
3128         spin_lock_irqsave(&info->lock,flags);
3129         get_signals(info);
3130         spin_unlock_irqrestore(&info->lock,flags);
3131
3132         result = ((info->serial_signals & SerialSignal_RTS) ? TIOCM_RTS:0) +
3133                 ((info->serial_signals & SerialSignal_DTR) ? TIOCM_DTR:0) +
3134                 ((info->serial_signals & SerialSignal_DCD) ? TIOCM_CAR:0) +
3135                 ((info->serial_signals & SerialSignal_RI)  ? TIOCM_RNG:0) +
3136                 ((info->serial_signals & SerialSignal_DSR) ? TIOCM_DSR:0) +
3137                 ((info->serial_signals & SerialSignal_CTS) ? TIOCM_CTS:0);
3138
3139         if (debug_level >= DEBUG_LEVEL_INFO)
3140                 printk("%s(%d):%s tiocmget() value=%08X\n",
3141                          __FILE__,__LINE__, info->device_name, result );
3142         return result;
3143 }
3144
3145 /* set modem control signals (DTR/RTS)
3146  */
3147 static int tiocmset(struct tty_struct *tty, struct file *file,
3148                     unsigned int set, unsigned int clear)
3149 {
3150         SLMP_INFO *info = (SLMP_INFO *)tty->driver_data;
3151         unsigned long flags;
3152
3153         if (debug_level >= DEBUG_LEVEL_INFO)
3154                 printk("%s(%d):%s tiocmset(%x,%x)\n",
3155                         __FILE__,__LINE__,info->device_name, set, clear);
3156
3157         if (set & TIOCM_RTS)
3158                 info->serial_signals |= SerialSignal_RTS;
3159         if (set & TIOCM_DTR)
3160                 info->serial_signals |= SerialSignal_DTR;
3161         if (clear & TIOCM_RTS)
3162                 info->serial_signals &= ~SerialSignal_RTS;
3163         if (clear & TIOCM_DTR)
3164                 info->serial_signals &= ~SerialSignal_DTR;
3165
3166         spin_lock_irqsave(&info->lock,flags);
3167         set_signals(info);
3168         spin_unlock_irqrestore(&info->lock,flags);
3169
3170         return 0;
3171 }
3172
3173
3174
3175 /* Block the current process until the specified port is ready to open.
3176  */
3177 static int block_til_ready(struct tty_struct *tty, struct file *filp,
3178                            SLMP_INFO *info)
3179 {
3180         DECLARE_WAITQUEUE(wait, current);
3181         int             retval;
3182         int             do_clocal = 0, extra_count = 0;
3183         unsigned long   flags;
3184
3185         if (debug_level >= DEBUG_LEVEL_INFO)
3186                 printk("%s(%d):%s block_til_ready()\n",
3187                          __FILE__,__LINE__, tty->driver->name );
3188
3189         if (filp->f_flags & O_NONBLOCK || tty->flags & (1 << TTY_IO_ERROR)){
3190                 /* nonblock mode is set or port is not enabled */
3191                 /* just verify that callout device is not active */
3192                 info->flags |= ASYNC_NORMAL_ACTIVE;
3193                 return 0;
3194         }
3195
3196         if (tty->termios->c_cflag & CLOCAL)
3197                 do_clocal = 1;
3198
3199         /* Wait for carrier detect and the line to become
3200          * free (i.e., not in use by the callout).  While we are in
3201          * this loop, info->count is dropped by one, so that
3202          * close() knows when to free things.  We restore it upon
3203          * exit, either normal or abnormal.
3204          */
3205
3206         retval = 0;
3207         add_wait_queue(&info->open_wait, &wait);
3208
3209         if (debug_level >= DEBUG_LEVEL_INFO)
3210                 printk("%s(%d):%s block_til_ready() before block, count=%d\n",
3211                          __FILE__,__LINE__, tty->driver->name, info->count );
3212
3213         spin_lock_irqsave(&info->lock, flags);
3214         if (!tty_hung_up_p(filp)) {
3215                 extra_count = 1;
3216                 info->count--;
3217         }
3218         spin_unlock_irqrestore(&info->lock, flags);
3219         info->blocked_open++;
3220
3221         while (1) {
3222                 if ((tty->termios->c_cflag & CBAUD)) {
3223                         spin_lock_irqsave(&info->lock,flags);
3224                         info->serial_signals |= SerialSignal_RTS + SerialSignal_DTR;
3225                         set_signals(info);
3226                         spin_unlock_irqrestore(&info->lock,flags);
3227                 }
3228
3229                 set_current_state(TASK_INTERRUPTIBLE);
3230
3231                 if (tty_hung_up_p(filp) || !(info->flags & ASYNC_INITIALIZED)){
3232                         retval = (info->flags & ASYNC_HUP_NOTIFY) ?
3233                                         -EAGAIN : -ERESTARTSYS;
3234                         break;
3235                 }
3236
3237                 spin_lock_irqsave(&info->lock,flags);
3238                 get_signals(info);
3239                 spin_unlock_irqrestore(&info->lock,flags);
3240
3241                 if (!(info->flags & ASYNC_CLOSING) &&
3242                     (do_clocal || (info->serial_signals & SerialSignal_DCD)) ) {
3243                         break;
3244                 }
3245
3246                 if (signal_pending(current)) {
3247                         retval = -ERESTARTSYS;
3248                         break;
3249                 }
3250
3251                 if (debug_level >= DEBUG_LEVEL_INFO)
3252                         printk("%s(%d):%s block_til_ready() count=%d\n",
3253                                  __FILE__,__LINE__, tty->driver->name, info->count );
3254
3255                 schedule();
3256         }
3257
3258         set_current_state(TASK_RUNNING);
3259         remove_wait_queue(&info->open_wait, &wait);
3260
3261         if (extra_count)
3262                 info->count++;
3263         info->blocked_open--;
3264
3265         if (debug_level >= DEBUG_LEVEL_INFO)
3266                 printk("%s(%d):%s block_til_ready() after, count=%d\n",
3267                          __FILE__,__LINE__, tty->driver->name, info->count );
3268
3269         if (!retval)
3270                 info->flags |= ASYNC_NORMAL_ACTIVE;
3271
3272         return retval;
3273 }
3274
3275 int alloc_dma_bufs(SLMP_INFO *info)
3276 {
3277         unsigned short BuffersPerFrame;
3278         unsigned short BufferCount;
3279
3280         // Force allocation to start at 64K boundary for each port.
3281         // This is necessary because *all* buffer descriptors for a port
3282         // *must* be in the same 64K block. All descriptors on a port
3283         // share a common 'base' address (upper 8 bits of 24 bits) programmed
3284         // into the CBP register.
3285         info->port_array[0]->last_mem_alloc = (SCA_MEM_SIZE/4) * info->port_num;
3286
3287         /* Calculate the number of DMA buffers necessary to hold the */
3288         /* largest allowable frame size. Note: If the max frame size is */
3289         /* not an even multiple of the DMA buffer size then we need to */
3290         /* round the buffer count per frame up one. */
3291
3292         BuffersPerFrame = (unsigned short)(info->max_frame_size/SCABUFSIZE);
3293         if ( info->max_frame_size % SCABUFSIZE )
3294                 BuffersPerFrame++;
3295
3296         /* calculate total number of data buffers (SCABUFSIZE) possible
3297          * in one ports memory (SCA_MEM_SIZE/4) after allocating memory
3298          * for the descriptor list (BUFFERLISTSIZE).
3299          */
3300         BufferCount = (SCA_MEM_SIZE/4 - BUFFERLISTSIZE)/SCABUFSIZE;
3301
3302         /* limit number of buffers to maximum amount of descriptors */
3303         if (BufferCount > BUFFERLISTSIZE/sizeof(SCADESC))
3304                 BufferCount = BUFFERLISTSIZE/sizeof(SCADESC);
3305
3306         /* use enough buffers to transmit one max size frame */
3307         info->tx_buf_count = BuffersPerFrame + 1;
3308
3309         /* never use more than half the available buffers for transmit */
3310         if (info->tx_buf_count > (BufferCount/2))
3311                 info->tx_buf_count = BufferCount/2;
3312
3313         if (info->tx_buf_count > SCAMAXDESC)
3314                 info->tx_buf_count = SCAMAXDESC;
3315
3316         /* use remaining buffers for receive */
3317         info->rx_buf_count = BufferCount - info->tx_buf_count;
3318
3319         if (info->rx_buf_count > SCAMAXDESC)
3320                 info->rx_buf_count = SCAMAXDESC;
3321
3322         if ( debug_level >= DEBUG_LEVEL_INFO )
3323                 printk("%s(%d):%s Allocating %d TX and %d RX DMA buffers.\n",
3324                         __FILE__,__LINE__, info->device_name,
3325                         info->tx_buf_count,info->rx_buf_count);
3326
3327         if ( alloc_buf_list( info ) < 0 ||
3328                 alloc_frame_bufs(info,
3329                                         info->rx_buf_list,
3330                                         info->rx_buf_list_ex,
3331                                         info->rx_buf_count) < 0 ||
3332                 alloc_frame_bufs(info,
3333                                         info->tx_buf_list,
3334                                         info->tx_buf_list_ex,
3335                                         info->tx_buf_count) < 0 ||
3336                 alloc_tmp_rx_buf(info) < 0 ) {
3337                 printk("%s(%d):%s Can't allocate DMA buffer memory\n",
3338                         __FILE__,__LINE__, info->device_name);
3339                 return -ENOMEM;
3340         }
3341
3342         rx_reset_buffers( info );
3343
3344         return 0;
3345 }
3346
3347 /* Allocate DMA buffers for the transmit and receive descriptor lists.
3348  */
3349 int alloc_buf_list(SLMP_INFO *info)
3350 {
3351         unsigned int i;
3352
3353         /* build list in adapter shared memory */
3354         info->buffer_list = info->memory_base + info->port_array[0]->last_mem_alloc;
3355         info->buffer_list_phys = info->port_array[0]->last_mem_alloc;
3356         info->port_array[0]->last_mem_alloc += BUFFERLISTSIZE;
3357
3358         memset(info->buffer_list, 0, BUFFERLISTSIZE);
3359
3360         /* Save virtual address pointers to the receive and */
3361         /* transmit buffer lists. (Receive 1st). These pointers will */
3362         /* be used by the processor to access the lists. */
3363         info->rx_buf_list = (SCADESC *)info->buffer_list;
3364
3365         info->tx_buf_list = (SCADESC *)info->buffer_list;
3366         info->tx_buf_list += info->rx_buf_count;
3367
3368         /* Build links for circular buffer entry lists (tx and rx)
3369          *
3370          * Note: links are physical addresses read by the SCA device
3371          * to determine the next buffer entry to use.
3372          */
3373
3374         for ( i = 0; i < info->rx_buf_count; i++ ) {
3375                 /* calculate and store physical address of this buffer entry */
3376                 info->rx_buf_list_ex[i].phys_entry =
3377                         info->buffer_list_phys + (i * sizeof(SCABUFSIZE));
3378
3379                 /* calculate and store physical address of */
3380                 /* next entry in cirular list of entries */
3381                 info->rx_buf_list[i].next = info->buffer_list_phys;
3382                 if ( i < info->rx_buf_count - 1 )
3383                         info->rx_buf_list[i].next += (i + 1) * sizeof(SCADESC);
3384
3385                 info->rx_buf_list[i].length = SCABUFSIZE;
3386         }
3387
3388         for ( i = 0; i < info->tx_buf_count; i++ ) {
3389                 /* calculate and store physical address of this buffer entry */
3390                 info->tx_buf_list_ex[i].phys_entry = info->buffer_list_phys +
3391                         ((info->rx_buf_count + i) * sizeof(SCADESC));
3392
3393                 /* calculate and store physical address of */
3394                 /* next entry in cirular list of entries */
3395
3396                 info->tx_buf_list[i].next = info->buffer_list_phys +
3397                         info->rx_buf_count * sizeof(SCADESC);
3398
3399                 if ( i < info->tx_buf_count - 1 )
3400                         info->tx_buf_list[i].next += (i + 1) * sizeof(SCADESC);
3401         }
3402
3403         return 0;
3404 }
3405
3406 /* Allocate the frame DMA buffers used by the specified buffer list.
3407  */
3408 int alloc_frame_bufs(SLMP_INFO *info, SCADESC *buf_list,SCADESC_EX *buf_list_ex,int count)
3409 {
3410         int i;
3411         unsigned long phys_addr;
3412
3413         for ( i = 0; i < count; i++ ) {
3414                 buf_list_ex[i].virt_addr = info->memory_base + info->port_array[0]->last_mem_alloc;
3415                 phys_addr = info->port_array[0]->last_mem_alloc;
3416                 info->port_array[0]->last_mem_alloc += SCABUFSIZE;
3417
3418                 buf_list[i].buf_ptr  = (unsigned short)phys_addr;
3419                 buf_list[i].buf_base = (unsigned char)(phys_addr >> 16);
3420         }
3421
3422         return 0;
3423 }
3424
3425 void free_dma_bufs(SLMP_INFO *info)
3426 {
3427         info->buffer_list = NULL;
3428         info->rx_buf_list = NULL;
3429         info->tx_buf_list = NULL;
3430 }
3431
3432 /* allocate buffer large enough to hold max_frame_size.
3433  * This buffer is used to pass an assembled frame to the line discipline.
3434  */
3435 int alloc_tmp_rx_buf(SLMP_INFO *info)
3436 {
3437         info->tmp_rx_buf = kmalloc(info->max_frame_size, GFP_KERNEL);
3438         if (info->tmp_rx_buf == NULL)
3439                 return -ENOMEM;
3440         return 0;
3441 }
3442
3443 void free_tmp_rx_buf(SLMP_INFO *info)
3444 {
3445         if (info->tmp_rx_buf)
3446                 kfree(info->tmp_rx_buf);
3447         info->tmp_rx_buf = NULL;
3448 }
3449
3450 int claim_resources(SLMP_INFO *info)
3451 {
3452         if (request_mem_region(info->phys_memory_base,0x40000,"synclinkmp") == NULL) {
3453                 printk( "%s(%d):%s mem addr conflict, Addr=%08X\n",
3454                         __FILE__,__LINE__,info->device_name, info->phys_memory_base);
3455                 goto errout;
3456         }
3457         else
3458                 info->shared_mem_requested = 1;
3459
3460         if (request_mem_region(info->phys_lcr_base + info->lcr_offset,128,"synclinkmp") == NULL) {
3461                 printk( "%s(%d):%s lcr mem addr conflict, Addr=%08X\n",
3462                         __FILE__,__LINE__,info->device_name, info->phys_lcr_base);
3463                 goto errout;
3464         }
3465         else
3466                 info->lcr_mem_requested = 1;
3467
3468         if (request_mem_region(info->phys_sca_base + info->sca_offset,512,"synclinkmp") == NULL) {
3469                 printk( "%s(%d):%s sca mem addr conflict, Addr=%08X\n",
3470                         __FILE__,__LINE__,info->device_name, info->phys_sca_base);
3471                 goto errout;
3472         }
3473         else
3474                 info->sca_base_requested = 1;
3475
3476         if (request_mem_region(info->phys_statctrl_base + info->statctrl_offset,16,"synclinkmp") == NULL) {
3477                 printk( "%s(%d):%s stat/ctrl mem addr conflict, Addr=%08X\n",
3478                         __FILE__,__LINE__,info->device_name, info->phys_statctrl_base);
3479                 goto errout;
3480         }
3481         else
3482                 info->sca_statctrl_requested = 1;
3483
3484         info->memory_base = ioremap(info->phys_memory_base,SCA_MEM_SIZE);
3485         if (!info->memory_base) {
3486                 printk( "%s(%d):%s Cant map shared memory, MemAddr=%08X\n",
3487                         __FILE__,__LINE__,info->device_name, info->phys_memory_base );
3488                 goto errout;
3489         }
3490
3491         if ( !memory_test(info) ) {
3492                 printk( "%s(%d):Shared Memory Test failed for device %s MemAddr=%08X\n",
3493                         __FILE__,__LINE__,info->device_name, info->phys_memory_base );
3494                 goto errout;
3495         }
3496
3497         info->lcr_base = ioremap(info->phys_lcr_base,PAGE_SIZE) + info->lcr_offset;
3498         if (!info->lcr_base) {
3499                 printk( "%s(%d):%s Cant map LCR memory, MemAddr=%08X\n",
3500                         __FILE__,__LINE__,info->device_name, info->phys_lcr_base );
3501                 goto errout;
3502         }
3503
3504         info->sca_base = ioremap(info->phys_sca_base,PAGE_SIZE) + info->sca_offset;
3505         if (!info->sca_base) {
3506                 printk( "%s(%d):%s Cant map SCA memory, MemAddr=%08X\n",
3507                         __FILE__,__LINE__,info->device_name, info->phys_sca_base );
3508                 goto errout;
3509         }
3510
3511         info->statctrl_base = ioremap(info->phys_statctrl_base,PAGE_SIZE) + info->statctrl_offset;
3512         if (!info->statctrl_base) {
3513                 printk( "%s(%d):%s Cant map SCA Status/Control memory, MemAddr=%08X\n",
3514                         __FILE__,__LINE__,info->device_name, info->phys_statctrl_base );
3515                 goto errout;
3516         }
3517
3518         return 0;
3519
3520 errout:
3521         release_resources( info );
3522         return -ENODEV;
3523 }
3524
3525 void release_resources(SLMP_INFO *info)
3526 {
3527         if ( debug_level >= DEBUG_LEVEL_INFO )
3528                 printk( "%s(%d):%s release_resources() entry\n",
3529                         __FILE__,__LINE__,info->device_name );
3530
3531         if ( info->irq_requested ) {
3532                 free_irq(info->irq_level, info);
3533                 info->irq_requested = 0;
3534         }
3535
3536         if ( info->shared_mem_requested ) {
3537                 release_mem_region(info->phys_memory_base,0x40000);
3538                 info->shared_mem_requested = 0;
3539         }
3540         if ( info->lcr_mem_requested ) {
3541                 release_mem_region(info->phys_lcr_base + info->lcr_offset,128);
3542                 info->lcr_mem_requested = 0;
3543         }
3544         if ( info->sca_base_requested ) {
3545                 release_mem_region(info->phys_sca_base + info->sca_offset,512);
3546                 info->sca_base_requested = 0;
3547         }
3548         if ( info->sca_statctrl_requested ) {
3549                 release_mem_region(info->phys_statctrl_base + info->statctrl_offset,16);
3550                 info->sca_statctrl_requested = 0;
3551         }
3552
3553         if (info->memory_base){
3554                 iounmap(info->memory_base);
3555                 info->memory_base = NULL;
3556         }
3557
3558         if (info->sca_base) {
3559                 iounmap(info->sca_base - info->sca_offset);
3560                 info->sca_base=NULL;
3561         }
3562
3563         if (info->statctrl_base) {
3564                 iounmap(info->statctrl_base - info->statctrl_offset);
3565                 info->statctrl_base=NULL;
3566         }
3567
3568         if (info->lcr_base){
3569                 iounmap(info->lcr_base - info->lcr_offset);
3570                 info->lcr_base = NULL;
3571         }
3572
3573         if ( debug_level >= DEBUG_LEVEL_INFO )
3574                 printk( "%s(%d):%s release_resources() exit\n",
3575                         __FILE__,__LINE__,info->device_name );
3576 }
3577
3578 /* Add the specified device instance data structure to the
3579  * global linked list of devices and increment the device count.
3580  */
3581 void add_device(SLMP_INFO *info)
3582 {
3583         info->next_device = NULL;
3584         info->line = synclinkmp_device_count;
3585         sprintf(info->device_name,"ttySLM%dp%d",info->adapter_num,info->port_num);
3586
3587         if (info->line < MAX_DEVICES) {
3588                 if (maxframe[info->line])
3589                         info->max_frame_size = maxframe[info->line];
3590                 info->dosyncppp = dosyncppp[info->line];
3591         }
3592
3593         synclinkmp_device_count++;
3594
3595         if ( !synclinkmp_device_list )
3596                 synclinkmp_device_list = info;
3597         else {
3598                 SLMP_INFO *current_dev = synclinkmp_device_list;
3599                 while( current_dev->next_device )
3600                         current_dev = current_dev->next_device;
3601                 current_dev->next_device = info;
3602         }
3603
3604         if ( info->max_frame_size < 4096 )
3605                 info->max_frame_size = 4096;
3606         else if ( info->max_frame_size > 65535 )
3607                 info->max_frame_size = 65535;
3608
3609         printk( "SyncLink MultiPort %s: "
3610                 "Mem=(%08x %08X %08x %08X) IRQ=%d MaxFrameSize=%u\n",
3611                 info->device_name,
3612                 info->phys_sca_base,
3613                 info->phys_memory_base,
3614                 info->phys_statctrl_base,
3615                 info->phys_lcr_base,
3616                 info->irq_level,
3617                 info->max_frame_size );
3618
3619 #ifdef CONFIG_SYNCLINK_SYNCPPP
3620         if (info->dosyncppp)
3621                 sppp_init(info);
3622 #endif
3623 }
3624
3625 /* Allocate and initialize a device instance structure
3626  *
3627  * Return Value:        pointer to SLMP_INFO if success, otherwise NULL
3628  */
3629 SLMP_INFO *alloc_dev(int adapter_num, int port_num, struct pci_dev *pdev)
3630 {
3631         SLMP_INFO *info;
3632
3633         info = (SLMP_INFO *)kmalloc(sizeof(SLMP_INFO),
3634                  GFP_KERNEL);
3635
3636         if (!info) {
3637                 printk("%s(%d) Error can't allocate device instance data for adapter %d, port %d\n",
3638                         __FILE__,__LINE__, adapter_num, port_num);
3639         } else {
3640                 memset(info, 0, sizeof(SLMP_INFO));
3641                 info->magic = MGSL_MAGIC;
3642                 INIT_WORK(&info->task, bh_handler, info);
3643                 info->max_frame_size = 4096;
3644                 info->close_delay = 5*HZ/10;
3645                 info->closing_wait = 30*HZ;
3646                 init_waitqueue_head(&info->open_wait);
3647                 init_waitqueue_head(&info->close_wait);
3648                 init_waitqueue_head(&info->status_event_wait_q);
3649                 init_waitqueue_head(&info->event_wait_q);
3650                 spin_lock_init(&info->netlock);
3651                 memcpy(&info->params,&default_params,sizeof(MGSL_PARAMS));
3652                 info->idle_mode = HDLC_TXIDLE_FLAGS;
3653                 info->adapter_num = adapter_num;
3654                 info->port_num = port_num;
3655
3656                 /* Copy configuration info to device instance data */
3657                 info->irq_level = pdev->irq;
3658                 info->phys_lcr_base = pci_resource_start(pdev,0);
3659                 info->phys_sca_base = pci_resource_start(pdev,2);
3660                 info->phys_memory_base = pci_resource_start(pdev,3);
3661                 info->phys_statctrl_base = pci_resource_start(pdev,4);
3662
3663                 /* Because veremap only works on page boundaries we must map
3664                  * a larger area than is actually implemented for the LCR
3665                  * memory range. We map a full page starting at the page boundary.
3666                  */
3667                 info->lcr_offset    = info->phys_lcr_base & (PAGE_SIZE-1);
3668                 info->phys_lcr_base &= ~(PAGE_SIZE-1);
3669
3670                 info->sca_offset    = info->phys_sca_base & (PAGE_SIZE-1);
3671                 info->phys_sca_base &= ~(PAGE_SIZE-1);
3672
3673                 info->statctrl_offset    = info->phys_statctrl_base & (PAGE_SIZE-1);
3674                 info->phys_statctrl_base &= ~(PAGE_SIZE-1);
3675
3676                 info->bus_type = MGSL_BUS_TYPE_PCI;
3677                 info->irq_flags = SA_SHIRQ;
3678
3679                 init_timer(&info->tx_timer);
3680                 info->tx_timer.data = (unsigned long)info;
3681                 info->tx_timer.function = tx_timeout;
3682
3683                 init_timer(&info->status_timer);
3684                 info->status_timer.data = (unsigned long)info;
3685                 info->status_timer.function = status_timeout;
3686
3687                 /* Store the PCI9050 misc control register value because a flaw
3688                  * in the PCI9050 prevents LCR registers from being read if
3689                  * BIOS assigns an LCR base address with bit 7 set.
3690                  *
3691                  * Only the misc control register is accessed for which only
3692                  * write access is needed, so set an initial value and change
3693                  * bits to the device instance data as we write the value
3694                  * to the actual misc control register.
3695                  */
3696                 info->misc_ctrl_value = 0x087e4546;
3697
3698                 /* initial port state is unknown - if startup errors
3699                  * occur, init_error will be set to indicate the
3700                  * problem. Once the port is fully initialized,
3701                  * this value will be set to 0 to indicate the
3702                  * port is available.
3703                  */
3704                 info->init_error = -1;
3705         }
3706
3707         return info;
3708 }
3709
3710 void device_init(int adapter_num, struct pci_dev *pdev)
3711 {
3712         SLMP_INFO *port_array[SCA_MAX_PORTS];
3713         int port;
3714
3715         /* allocate device instances for up to SCA_MAX_PORTS devices */
3716         for ( port = 0; port < SCA_MAX_PORTS; ++port ) {
3717                 port_array[port] = alloc_dev(adapter_num,port,pdev);
3718                 if( port_array[port] == NULL ) {
3719                         for ( --port; port >= 0; --port )
3720                                 kfree(port_array[port]);
3721                         return;
3722                 }
3723         }
3724
3725         /* give copy of port_array to all ports and add to device list  */
3726         for ( port = 0; port < SCA_MAX_PORTS; ++port ) {
3727                 memcpy(port_array[port]->port_array,port_array,sizeof(port_array));
3728                 add_device( port_array[port] );
3729                 spin_lock_init(&port_array[port]->lock);
3730         }
3731
3732         /* Allocate and claim adapter resources */
3733         if ( !claim_resources(port_array[0]) ) {
3734
3735                 alloc_dma_bufs(port_array[0]);
3736
3737                 /* copy resource information from first port to others */
3738                 for ( port = 1; port < SCA_MAX_PORTS; ++port ) {
3739                         port_array[port]->lock  = port_array[0]->lock;
3740                         port_array[port]->irq_level     = port_array[0]->irq_level;
3741                         port_array[port]->memory_base   = port_array[0]->memory_base;
3742                         port_array[port]->sca_base      = port_array[0]->sca_base;
3743                         port_array[port]->statctrl_base = port_array[0]->statctrl_base;
3744                         port_array[port]->lcr_base      = port_array[0]->lcr_base;
3745                         alloc_dma_bufs(port_array[port]);
3746                 }
3747
3748                 if ( request_irq(port_array[0]->irq_level,
3749                                         synclinkmp_interrupt,
3750                                         port_array[0]->irq_flags,
3751                                         port_array[0]->device_name,
3752                                         port_array[0]) < 0 ) {
3753                         printk( "%s(%d):%s Cant request interrupt, IRQ=%d\n",
3754                                 __FILE__,__LINE__,
3755                                 port_array[0]->device_name,
3756                                 port_array[0]->irq_level );
3757                 }
3758                 else {
3759                         port_array[0]->irq_requested = 1;
3760                         adapter_test(port_array[0]);
3761                 }
3762         }
3763 }
3764
3765 static struct tty_operations ops = {
3766         .open = open,
3767         .close = close,
3768         .write = write,
3769         .put_char = put_char,
3770         .flush_chars = flush_chars,
3771         .write_room = write_room,
3772         .chars_in_buffer = chars_in_buffer,
3773         .flush_buffer = flush_buffer,
3774         .ioctl = ioctl,
3775         .throttle = throttle,
3776         .unthrottle = unthrottle,
3777         .send_xchar = send_xchar,
3778         .break_ctl = set_break,
3779         .wait_until_sent = wait_until_sent,
3780         .read_proc = read_proc,
3781         .set_termios = set_termios,
3782         .stop = tx_hold,
3783         .start = tx_release,
3784         .hangup = hangup,
3785         .tiocmget = tiocmget,
3786         .tiocmset = tiocmset,
3787 };
3788
3789 static void synclinkmp_cleanup(void)
3790 {
3791         unsigned long flags;
3792         int rc;
3793         SLMP_INFO *info;
3794         SLMP_INFO *tmp;
3795
3796         printk("Unloading %s %s\n", driver_name, driver_version);
3797
3798         if (serial_driver) {
3799                 if ((rc = tty_unregister_driver(serial_driver)))
3800                         printk("%s(%d) failed to unregister tty driver err=%d\n",
3801                                __FILE__,__LINE__,rc);
3802                 put_tty_driver(serial_driver);
3803         }
3804
3805         info = synclinkmp_device_list;
3806         while(info) {
3807 #ifdef CONFIG_SYNCLINK_SYNCPPP
3808                 if (info->dosyncppp)
3809                         sppp_delete(info);
3810 #endif
3811                 reset_port(info);
3812                 if ( info->port_num == 0 ) {
3813                         if ( info->irq_requested ) {
3814                                 free_irq(info->irq_level, info);
3815                                 info->irq_requested = 0;
3816                         }
3817                 }
3818                 info = info->next_device;
3819         }
3820
3821         /* port 0 of each adapter originally claimed
3822          * all resources, release those now
3823          */
3824         info = synclinkmp_device_list;
3825         while(info) {
3826                 free_dma_bufs(info);
3827                 free_tmp_rx_buf(info);
3828                 if ( info->port_num == 0 ) {
3829                         spin_lock_irqsave(&info->lock,flags);
3830                         reset_adapter(info);
3831                         write_reg(info, LPR, 1);                /* set low power mode */
3832                         spin_unlock_irqrestore(&info->lock,flags);
3833                         release_resources(info);
3834                 }
3835                 tmp = info;
3836                 info = info->next_device;
3837                 kfree(tmp);
3838         }
3839
3840         pci_unregister_driver(&synclinkmp_pci_driver);
3841 }
3842
3843 /* Driver initialization entry point.
3844  */
3845
3846 static int __init synclinkmp_init(void)
3847 {
3848         int rc;
3849
3850         if (break_on_load) {
3851                 synclinkmp_get_text_ptr();
3852                 BREAKPOINT();
3853         }
3854
3855         printk("%s %s\n", driver_name, driver_version);
3856
3857         if ((rc = pci_register_driver(&synclinkmp_pci_driver)) < 0) {
3858                 printk("%s:failed to register PCI driver, error=%d\n",__FILE__,rc);
3859                 return rc;
3860         }
3861
3862         serial_driver = alloc_tty_driver(128);
3863         if (!serial_driver) {
3864                 rc = -ENOMEM;
3865                 goto error;
3866         }
3867
3868         /* Initialize the tty_driver structure */
3869
3870         serial_driver->owner = THIS_MODULE;
3871         serial_driver->driver_name = "synclinkmp";
3872         serial_driver->name = "ttySLM";
3873         serial_driver->major = ttymajor;
3874         serial_driver->minor_start = 64;
3875         serial_driver->type = TTY_DRIVER_TYPE_SERIAL;
3876         serial_driver->subtype = SERIAL_TYPE_NORMAL;
3877         serial_driver->init_termios = tty_std_termios;
3878         serial_driver->init_termios.c_cflag =
3879                 B9600 | CS8 | CREAD | HUPCL | CLOCAL;
3880         serial_driver->flags = TTY_DRIVER_REAL_RAW;
3881         tty_set_operations(serial_driver, &ops);
3882         if ((rc = tty_register_driver(serial_driver)) < 0) {
3883                 printk("%s(%d):Couldn't register serial driver\n",
3884                         __FILE__,__LINE__);
3885                 put_tty_driver(serial_driver);
3886                 serial_driver = NULL;
3887                 goto error;
3888         }
3889
3890         printk("%s %s, tty major#%d\n",
3891                 driver_name, driver_version,
3892                 serial_driver->major);
3893
3894         return 0;
3895
3896 error:
3897         synclinkmp_cleanup();
3898         return rc;
3899 }
3900
3901 static void __exit synclinkmp_exit(void)
3902 {
3903         synclinkmp_cleanup();
3904 }
3905
3906 module_init(synclinkmp_init);
3907 module_exit(synclinkmp_exit);
3908
3909 /* Set the port for internal loopback mode.
3910  * The TxCLK and RxCLK signals are generated from the BRG and
3911  * the TxD is looped back to the RxD internally.
3912  */
3913 void enable_loopback(SLMP_INFO *info, int enable)
3914 {
3915         if (enable) {
3916                 /* MD2 (Mode Register 2)
3917                  * 01..00  CNCT<1..0> Channel Connection 11=Local Loopback
3918                  */
3919                 write_reg(info, MD2, (unsigned char)(read_reg(info, MD2) | (BIT1 + BIT0)));
3920
3921                 /* degate external TxC clock source */
3922                 info->port_array[0]->ctrlreg_value |= (BIT0 << (info->port_num * 2));
3923                 write_control_reg(info);
3924
3925                 /* RXS/TXS (Rx/Tx clock source)
3926                  * 07      Reserved, must be 0
3927                  * 06..04  Clock Source, 100=BRG
3928                  * 03..00  Clock Divisor, 0000=1
3929                  */
3930                 write_reg(info, RXS, 0x40);
3931                 write_reg(info, TXS, 0x40);
3932
3933         } else {
3934                 /* MD2 (Mode Register 2)
3935                  * 01..00  CNCT<1..0> Channel connection, 0=normal
3936                  */
3937                 write_reg(info, MD2, (unsigned char)(read_reg(info, MD2) & ~(BIT1 + BIT0)));
3938
3939                 /* RXS/TXS (Rx/Tx clock source)
3940                  * 07      Reserved, must be 0
3941                  * 06..04  Clock Source, 000=RxC/TxC Pin
3942                  * 03..00  Clock Divisor, 0000=1
3943                  */
3944                 write_reg(info, RXS, 0x00);
3945                 write_reg(info, TXS, 0x00);
3946         }
3947
3948         /* set LinkSpeed if available, otherwise default to 2Mbps */
3949         if (info->params.clock_speed)
3950                 set_rate(info, info->params.clock_speed);
3951         else
3952                 set_rate(info, 3686400);
3953 }
3954
3955 /* Set the baud rate register to the desired speed
3956  *
3957  *      data_rate       data rate of clock in bits per second
3958  *                      A data rate of 0 disables the AUX clock.
3959  */
3960 void set_rate( SLMP_INFO *info, u32 data_rate )
3961 {
3962         u32 TMCValue;
3963         unsigned char BRValue;
3964         u32 Divisor=0;
3965
3966         /* fBRG = fCLK/(TMC * 2^BR)
3967          */
3968         if (data_rate != 0) {
3969                 Divisor = 14745600/data_rate;
3970                 if (!Divisor)
3971                         Divisor = 1;
3972
3973                 TMCValue = Divisor;
3974
3975                 BRValue = 0;
3976                 if (TMCValue != 1 && TMCValue != 2) {
3977                         /* BRValue of 0 provides 50/50 duty cycle *only* when
3978                          * TMCValue is 1 or 2. BRValue of 1 to 9 always provides
3979                          * 50/50 duty cycle.
3980                          */
3981                         BRValue = 1;
3982                         TMCValue >>= 1;
3983                 }
3984
3985                 /* while TMCValue is too big for TMC register, divide
3986                  * by 2 and increment BR exponent.
3987                  */
3988                 for(; TMCValue > 256 && BRValue < 10; BRValue++)
3989                         TMCValue >>= 1;
3990
3991                 write_reg(info, TXS,
3992                         (unsigned char)((read_reg(info, TXS) & 0xf0) | BRValue));
3993                 write_reg(info, RXS,
3994                         (unsigned char)((read_reg(info, RXS) & 0xf0) | BRValue));
3995                 write_reg(info, TMC, (unsigned char)TMCValue);
3996         }
3997         else {
3998                 write_reg(info, TXS,0);
3999                 write_reg(info, RXS,0);
4000                 write_reg(info, TMC, 0);
4001         }
4002 }
4003
4004 /* Disable receiver
4005  */
4006 void rx_stop(SLMP_INFO *info)
4007 {
4008         if (debug_level >= DEBUG_LEVEL_ISR)
4009                 printk("%s(%d):%s rx_stop()\n",
4010                          __FILE__,__LINE__, info->device_name );
4011
4012         write_reg(info, CMD, RXRESET);
4013
4014         info->ie0_value &= ~RXRDYE;
4015         write_reg(info, IE0, info->ie0_value);  /* disable Rx data interrupts */
4016
4017         write_reg(info, RXDMA + DSR, 0);        /* disable Rx DMA */
4018         write_reg(info, RXDMA + DCMD, SWABORT); /* reset/init Rx DMA */
4019         write_reg(info, RXDMA + DIR, 0);        /* disable Rx DMA interrupts */
4020
4021         info->rx_enabled = 0;
4022         info->rx_overflow = 0;
4023 }
4024
4025 /* enable the receiver
4026  */
4027 void rx_start(SLMP_INFO *info)
4028 {
4029         int i;
4030
4031         if (debug_level >= DEBUG_LEVEL_ISR)
4032                 printk("%s(%d):%s rx_start()\n",
4033                          __FILE__,__LINE__, info->device_name );
4034
4035         write_reg(info, CMD, RXRESET);
4036
4037         if ( info->params.mode == MGSL_MODE_HDLC ) {
4038                 /* HDLC, disabe IRQ on rxdata */
4039                 info->ie0_value &= ~RXRDYE;
4040                 write_reg(info, IE0, info->ie0_value);
4041
4042                 /* Reset all Rx DMA buffers and program rx dma */
4043                 write_reg(info, RXDMA + DSR, 0);                /* disable Rx DMA */
4044                 write_reg(info, RXDMA + DCMD, SWABORT); /* reset/init Rx DMA */
4045
4046                 for (i = 0; i < info->rx_buf_count; i++) {
4047                         info->rx_buf_list[i].status = 0xff;
4048
4049                         // throttle to 4 shared memory writes at a time to prevent
4050                         // hogging local bus (keep latency time for DMA requests low).
4051                         if (!(i % 4))
4052                                 read_status_reg(info);
4053                 }
4054                 info->current_rx_buf = 0;
4055
4056                 /* set current/1st descriptor address */
4057                 write_reg16(info, RXDMA + CDA,
4058                         info->rx_buf_list_ex[0].phys_entry);
4059
4060                 /* set new last rx descriptor address */
4061                 write_reg16(info, RXDMA + EDA,
4062                         info->rx_buf_list_ex[info->rx_buf_count - 1].phys_entry);
4063
4064                 /* set buffer length (shared by all rx dma data buffers) */
4065                 write_reg16(info, RXDMA + BFL, SCABUFSIZE);
4066
4067                 write_reg(info, RXDMA + DIR, 0x60);     /* enable Rx DMA interrupts (EOM/BOF) */
4068                 write_reg(info, RXDMA + DSR, 0xf2);     /* clear Rx DMA IRQs, enable Rx DMA */
4069         } else {
4070                 /* async, enable IRQ on rxdata */
4071                 info->ie0_value |= RXRDYE;
4072                 write_reg(info, IE0, info->ie0_value);
4073         }
4074
4075         write_reg(info, CMD, RXENABLE);
4076
4077         info->rx_overflow = FALSE;
4078         info->rx_enabled = 1;
4079 }
4080
4081 /* Enable the transmitter and send a transmit frame if
4082  * one is loaded in the DMA buffers.
4083  */
4084 void tx_start(SLMP_INFO *info)
4085 {
4086         if (debug_level >= DEBUG_LEVEL_ISR)
4087                 printk("%s(%d):%s tx_start() tx_count=%d\n",
4088                          __FILE__,__LINE__, info->device_name,info->tx_count );
4089
4090         if (!info->tx_enabled ) {
4091                 write_reg(info, CMD, TXRESET);
4092                 write_reg(info, CMD, TXENABLE);
4093                 info->tx_enabled = TRUE;
4094         }
4095
4096         if ( info->tx_count ) {
4097
4098                 /* If auto RTS enabled and RTS is inactive, then assert */
4099                 /* RTS and set a flag indicating that the driver should */
4100                 /* negate RTS when the transmission completes. */
4101
4102                 info->drop_rts_on_tx_done = 0;
4103
4104                 if (info->params.mode != MGSL_MODE_ASYNC) {
4105
4106                         if ( info->params.flags & HDLC_FLAG_AUTO_RTS ) {
4107                                 get_signals( info );
4108                                 if ( !(info->serial_signals & SerialSignal_RTS) ) {
4109                                         info->serial_signals |= SerialSignal_RTS;
4110                                         set_signals( info );
4111                                         info->drop_rts_on_tx_done = 1;
4112                                 }
4113                         }
4114
4115                         write_reg(info, TXDMA + DSR, 0);                /* disable DMA channel */
4116                         write_reg(info, TXDMA + DCMD, SWABORT); /* reset/init DMA channel */
4117
4118                         /* set TX CDA (current descriptor address) */
4119                         write_reg16(info, TXDMA + CDA,
4120                                 info->tx_buf_list_ex[0].phys_entry);
4121
4122                         /* set TX EDA (last descriptor address) */
4123                         write_reg16(info, TXDMA + EDA,
4124                                 info->tx_buf_list_ex[info->last_tx_buf].phys_entry);
4125
4126                         /* clear IDLE and UDRN status bit */
4127                         info->ie1_value &= ~(IDLE + UDRN);
4128                         if (info->params.mode != MGSL_MODE_ASYNC)
4129                                 info->ie1_value |= UDRN;                /* HDLC, IRQ on underrun */
4130                         write_reg(info, IE1, info->ie1_value);  /* enable MSCI interrupts */
4131                         write_reg(info, SR1, (unsigned char)(IDLE + UDRN));
4132
4133                         write_reg(info, TXDMA + DIR, 0x40);             /* enable Tx DMA interrupts (EOM) */
4134                         write_reg(info, TXDMA + DSR, 0xf2);             /* clear Tx DMA IRQs, enable Tx DMA */
4135
4136                         info->tx_timer.expires = jiffies + jiffies_from_ms(5000);
4137                         add_timer(&info->tx_timer);
4138                 }
4139                 else {
4140                         tx_load_fifo(info);
4141                         /* async, enable IRQ on txdata */
4142                         info->ie0_value |= TXRDYE;
4143                         write_reg(info, IE0, info->ie0_value);
4144                 }
4145
4146                 info->tx_active = 1;
4147         }
4148 }
4149
4150 /* stop the transmitter and DMA
4151  */
4152 void tx_stop( SLMP_INFO *info )
4153 {
4154         if (debug_level >= DEBUG_LEVEL_ISR)
4155                 printk("%s(%d):%s tx_stop()\n",
4156                          __FILE__,__LINE__, info->device_name );
4157
4158         del_timer(&info->tx_timer);
4159
4160         write_reg(info, TXDMA + DSR, 0);                /* disable DMA channel */
4161         write_reg(info, TXDMA + DCMD, SWABORT); /* reset/init DMA channel */
4162
4163         write_reg(info, CMD, TXRESET);
4164
4165         info->ie1_value &= ~(UDRN + IDLE);
4166         write_reg(info, IE1, info->ie1_value);  /* disable tx status interrupts */
4167         write_reg(info, SR1, (unsigned char)(IDLE + UDRN));     /* clear pending */
4168
4169         info->ie0_value &= ~TXRDYE;
4170         write_reg(info, IE0, info->ie0_value);  /* disable tx data interrupts */
4171
4172         info->tx_enabled = 0;
4173         info->tx_active  = 0;
4174 }
4175
4176 /* Fill the transmit FIFO until the FIFO is full or
4177  * there is no more data to load.
4178  */
4179 void tx_load_fifo(SLMP_INFO *info)
4180 {
4181         u8 TwoBytes[2];
4182
4183         /* do nothing is now tx data available and no XON/XOFF pending */
4184
4185         if ( !info->tx_count && !info->x_char )
4186                 return;
4187
4188         /* load the Transmit FIFO until FIFOs full or all data sent */
4189
4190         while( info->tx_count && (read_reg(info,SR0) & BIT1) ) {
4191
4192                 /* there is more space in the transmit FIFO and */
4193                 /* there is more data in transmit buffer */
4194
4195                 if ( (info->tx_count > 1) && !info->x_char ) {
4196                         /* write 16-bits */
4197                         TwoBytes[0] = info->tx_buf[info->tx_get++];
4198                         if (info->tx_get >= info->max_frame_size)
4199                                 info->tx_get -= info->max_frame_size;
4200                         TwoBytes[1] = info->tx_buf[info->tx_get++];
4201                         if (info->tx_get >= info->max_frame_size)
4202                                 info->tx_get -= info->max_frame_size;
4203
4204                         write_reg16(info, TRB, *((u16 *)TwoBytes));
4205
4206                         info->tx_count -= 2;
4207                         info->icount.tx += 2;
4208                 } else {
4209                         /* only 1 byte left to transmit or 1 FIFO slot left */
4210
4211                         if (info->x_char) {
4212                                 /* transmit pending high priority char */
4213                                 write_reg(info, TRB, info->x_char);
4214                                 info->x_char = 0;
4215                         } else {
4216                                 write_reg(info, TRB, info->tx_buf[info->tx_get++]);
4217                                 if (info->tx_get >= info->max_frame_size)
4218                                         info->tx_get -= info->max_frame_size;
4219                                 info->tx_count--;
4220                         }
4221                         info->icount.tx++;
4222                 }
4223         }
4224 }
4225
4226 /* Reset a port to a known state
4227  */
4228 void reset_port(SLMP_INFO *info)
4229 {
4230         if (info->sca_base) {
4231
4232                 tx_stop(info);
4233                 rx_stop(info);
4234
4235                 info->serial_signals &= ~(SerialSignal_DTR + SerialSignal_RTS);
4236                 set_signals(info);
4237
4238                 /* disable all port interrupts */
4239                 info->ie0_value = 0;
4240                 info->ie1_value = 0;
4241                 info->ie2_value = 0;
4242                 write_reg(info, IE0, info->ie0_value);
4243                 write_reg(info, IE1, info->ie1_value);
4244                 write_reg(info, IE2, info->ie2_value);
4245
4246                 write_reg(info, CMD, CHRESET);
4247         }
4248 }
4249
4250 /* Reset all the ports to a known state.
4251  */
4252 void reset_adapter(SLMP_INFO *info)
4253 {
4254         int i;
4255
4256         for ( i=0; i < SCA_MAX_PORTS; ++i) {
4257                 if (info->port_array[i])
4258                         reset_port(info->port_array[i]);
4259         }
4260 }
4261
4262 /* Program port for asynchronous communications.
4263  */
4264 void async_mode(SLMP_INFO *info)
4265 {
4266
4267         unsigned char RegValue;
4268
4269         tx_stop(info);
4270         rx_stop(info);
4271
4272         /* MD0, Mode Register 0
4273          *
4274          * 07..05  PRCTL<2..0>, Protocol Mode, 000=async
4275          * 04      AUTO, Auto-enable (RTS/CTS/DCD)
4276          * 03      Reserved, must be 0
4277          * 02      CRCCC, CRC Calculation, 0=disabled
4278          * 01..00  STOP<1..0> Stop bits (00=1,10=2)
4279          *
4280          * 0000 0000
4281          */
4282         RegValue = 0x00;
4283         if (info->params.stop_bits != 1)
4284                 RegValue |= BIT1;
4285         write_reg(info, MD0, RegValue);
4286
4287         /* MD1, Mode Register 1
4288          *
4289          * 07..06  BRATE<1..0>, bit rate, 00=1/1 01=1/16 10=1/32 11=1/64
4290          * 05..04  TXCHR<1..0>, tx char size, 00=8 bits,01=7,10=6,11=5
4291          * 03..02  RXCHR<1..0>, rx char size
4292          * 01..00  PMPM<1..0>, Parity mode, 00=none 10=even 11=odd
4293          *
4294          * 0100 0000
4295          */
4296         RegValue = 0x40;
4297         switch (info->params.data_bits) {
4298         case 7: RegValue |= BIT4 + BIT2; break;
4299         case 6: RegValue |= BIT5 + BIT3; break;
4300         case 5: RegValue |= BIT5 + BIT4 + BIT3 + BIT2; break;
4301         }
4302         if (info->params.parity != ASYNC_PARITY_NONE) {
4303                 RegValue |= BIT1;
4304                 if (info->params.parity == ASYNC_PARITY_ODD)
4305                         RegValue |= BIT0;
4306         }
4307         write_reg(info, MD1, RegValue);
4308
4309         /* MD2, Mode Register 2
4310          *
4311          * 07..02  Reserved, must be 0
4312          * 01..00  CNCT<1..0> Channel connection, 0=normal
4313          *
4314          * 0000 0000
4315          */
4316         RegValue = 0x00;
4317         write_reg(info, MD2, RegValue);
4318
4319         /* RXS, Receive clock source
4320          *
4321          * 07      Reserved, must be 0
4322          * 06..04  RXCS<2..0>, clock source, 000=RxC Pin, 100=BRG, 110=DPLL
4323          * 03..00  RXBR<3..0>, rate divisor, 0000=1
4324          */
4325         RegValue=BIT6;
4326         write_reg(info, RXS, RegValue);
4327
4328         /* TXS, Transmit clock source
4329          *
4330          * 07      Reserved, must be 0
4331          * 06..04  RXCS<2..0>, clock source, 000=TxC Pin, 100=BRG, 110=Receive Clock
4332          * 03..00  RXBR<3..0>, rate divisor, 0000=1
4333          */
4334         RegValue=BIT6;
4335         write_reg(info, TXS, RegValue);
4336
4337         /* Control Register
4338          *
4339          * 6,4,2,0  CLKSEL<3..0>, 0 = TcCLK in, 1 = Auxclk out
4340          */
4341         info->port_array[0]->ctrlreg_value |= (BIT0 << (info->port_num * 2));
4342         write_control_reg(info);
4343
4344         tx_set_idle(info);
4345
4346         /* RRC Receive Ready Control 0
4347          *
4348          * 07..05  Reserved, must be 0
4349          * 04..00  RRC<4..0> Rx FIFO trigger active 0x00 = 1 byte
4350          */
4351         write_reg(info, TRC0, 0x00);
4352
4353         /* TRC0 Transmit Ready Control 0
4354          *
4355          * 07..05  Reserved, must be 0
4356          * 04..00  TRC<4..0> Tx FIFO trigger active 0x10 = 16 bytes
4357          */
4358         write_reg(info, TRC0, 0x10);
4359
4360         /* TRC1 Transmit Ready Control 1
4361          *
4362          * 07..05  Reserved, must be 0
4363          * 04..00  TRC<4..0> Tx FIFO trigger inactive 0x1e = 31 bytes (full-1)
4364          */
4365         write_reg(info, TRC1, 0x1e);
4366
4367         /* CTL, MSCI control register
4368          *
4369          * 07..06  Reserved, set to 0
4370          * 05      UDRNC, underrun control, 0=abort 1=CRC+flag (HDLC/BSC)
4371          * 04      IDLC, idle control, 0=mark 1=idle register
4372          * 03      BRK, break, 0=off 1 =on (async)
4373          * 02      SYNCLD, sync char load enable (BSC) 1=enabled
4374          * 01      GOP, go active on poll (LOOP mode) 1=enabled
4375          * 00      RTS, RTS output control, 0=active 1=inactive
4376          *
4377          * 0001 0001
4378          */
4379         RegValue = 0x10;
4380         if (!(info->serial_signals & SerialSignal_RTS))
4381                 RegValue |= 0x01;
4382         write_reg(info, CTL, RegValue);
4383
4384         /* enable status interrupts */
4385         info->ie0_value |= TXINTE + RXINTE;
4386         write_reg(info, IE0, info->ie0_value);
4387
4388         /* enable break detect interrupt */
4389         info->ie1_value = BRKD;
4390         write_reg(info, IE1, info->ie1_value);
4391
4392         /* enable rx overrun interrupt */
4393         info->ie2_value = OVRN;
4394         write_reg(info, IE2, info->ie2_value);
4395
4396         set_rate( info, info->params.data_rate * 16 );
4397
4398         if (info->params.loopback)
4399                 enable_loopback(info,1);
4400 }
4401
4402 /* Program the SCA for HDLC communications.
4403  */
4404 void hdlc_mode(SLMP_INFO *info)
4405 {
4406         unsigned char RegValue;
4407         u32 DpllDivisor;
4408
4409         // Can't use DPLL because SCA outputs recovered clock on RxC when
4410         // DPLL mode selected. This causes output contention with RxC receiver.
4411         // Use of DPLL would require external hardware to disable RxC receiver
4412         // when DPLL mode selected.
4413         info->params.flags &= ~(HDLC_FLAG_TXC_DPLL + HDLC_FLAG_RXC_DPLL);
4414
4415         /* disable DMA interrupts */
4416         write_reg(info, TXDMA + DIR, 0);
4417         write_reg(info, RXDMA + DIR, 0);
4418
4419         /* MD0, Mode Register 0
4420          *
4421          * 07..05  PRCTL<2..0>, Protocol Mode, 100=HDLC
4422          * 04      AUTO, Auto-enable (RTS/CTS/DCD)
4423          * 03      Reserved, must be 0
4424          * 02      CRCCC, CRC Calculation, 1=enabled
4425          * 01      CRC1, CRC selection, 0=CRC-16,1=CRC-CCITT-16
4426          * 00      CRC0, CRC initial value, 1 = all 1s
4427          *
4428          * 1000 0001
4429          */
4430         RegValue = 0x81;
4431         if (info->params.flags & HDLC_FLAG_AUTO_CTS)
4432                 RegValue |= BIT4;
4433         if (info->params.flags & HDLC_FLAG_AUTO_DCD)
4434                 RegValue |= BIT4;
4435         if (info->params.crc_type == HDLC_CRC_16_CCITT)
4436                 RegValue |= BIT2 + BIT1;
4437         write_reg(info, MD0, RegValue);
4438
4439         /* MD1, Mode Register 1
4440          *
4441          * 07..06  ADDRS<1..0>, Address detect, 00=no addr check
4442          * 05..04  TXCHR<1..0>, tx char size, 00=8 bits
4443          * 03..02  RXCHR<1..0>, rx char size, 00=8 bits
4444          * 01..00  PMPM<1..0>, Parity mode, 00=no parity
4445          *
4446          * 0000 0000
4447          */
4448         RegValue = 0x00;
4449         write_reg(info, MD1, RegValue);
4450
4451         /* MD2, Mode Register 2
4452          *
4453          * 07      NRZFM, 0=NRZ, 1=FM
4454          * 06..05  CODE<1..0> Encoding, 00=NRZ
4455          * 04..03  DRATE<1..0> DPLL Divisor, 00=8
4456          * 02      Reserved, must be 0
4457          * 01..00  CNCT<1..0> Channel connection, 0=normal
4458          *
4459          * 0000 0000
4460          */
4461         RegValue = 0x00;
4462         switch(info->params.encoding) {
4463         case HDLC_ENCODING_NRZI:          RegValue |= BIT5; break;
4464         case HDLC_ENCODING_BIPHASE_MARK:  RegValue |= BIT7 + BIT5; break; /* aka FM1 */
4465         case HDLC_ENCODING_BIPHASE_SPACE: RegValue |= BIT7 + BIT6; break; /* aka FM0 */
4466         case HDLC_ENCODING_BIPHASE_LEVEL: RegValue |= BIT7; break;      /* aka Manchester */
4467 #if 0
4468         case HDLC_ENCODING_NRZB:                                        /* not supported */
4469         case HDLC_ENCODING_NRZI_MARK:                                   /* not supported */
4470         case HDLC_ENCODING_DIFF_BIPHASE_LEVEL:                          /* not supported */
4471 #endif
4472         }
4473         if ( info->params.flags & HDLC_FLAG_DPLL_DIV16 ) {
4474                 DpllDivisor = 16;
4475                 RegValue |= BIT3;
4476         } else if ( info->params.flags & HDLC_FLAG_DPLL_DIV8 ) {
4477                 DpllDivisor = 8;
4478         } else {
4479                 DpllDivisor = 32;
4480                 RegValue |= BIT4;
4481         }
4482         write_reg(info, MD2, RegValue);
4483
4484
4485         /* RXS, Receive clock source
4486          *
4487          * 07      Reserved, must be 0
4488          * 06..04  RXCS<2..0>, clock source, 000=RxC Pin, 100=BRG, 110=DPLL
4489          * 03..00  RXBR<3..0>, rate divisor, 0000=1
4490          */
4491         RegValue=0;
4492         if (info->params.flags & HDLC_FLAG_RXC_BRG)
4493                 RegValue |= BIT6;
4494         if (info->params.flags & HDLC_FLAG_RXC_DPLL)
4495                 RegValue |= BIT6 + BIT5;
4496         write_reg(info, RXS, RegValue);
4497
4498         /* TXS, Transmit clock source
4499          *
4500          * 07      Reserved, must be 0
4501          * 06..04  RXCS<2..0>, clock source, 000=TxC Pin, 100=BRG, 110=Receive Clock
4502          * 03..00  RXBR<3..0>, rate divisor, 0000=1
4503          */
4504         RegValue=0;
4505         if (info->params.flags & HDLC_FLAG_TXC_BRG)
4506                 RegValue |= BIT6;
4507         if (info->params.flags & HDLC_FLAG_TXC_DPLL)
4508                 RegValue |= BIT6 + BIT5;
4509         write_reg(info, TXS, RegValue);
4510
4511         if (info->params.flags & HDLC_FLAG_RXC_DPLL)
4512                 set_rate(info, info->params.clock_speed * DpllDivisor);
4513         else
4514                 set_rate(info, info->params.clock_speed);
4515
4516         /* GPDATA (General Purpose I/O Data Register)
4517          *
4518          * 6,4,2,0  CLKSEL<3..0>, 0 = TcCLK in, 1 = Auxclk out
4519          */
4520         if (info->params.flags & HDLC_FLAG_TXC_BRG)
4521                 info->port_array[0]->ctrlreg_value |= (BIT0 << (info->port_num * 2));
4522         else
4523                 info->port_array[0]->ctrlreg_value &= ~(BIT0 << (info->port_num * 2));
4524         write_control_reg(info);
4525
4526         /* RRC Receive Ready Control 0
4527          *
4528          * 07..05  Reserved, must be 0
4529          * 04..00  RRC<4..0> Rx FIFO trigger active
4530          */
4531         write_reg(info, RRC, rx_active_fifo_level);
4532
4533         /* TRC0 Transmit Ready Control 0
4534          *
4535          * 07..05  Reserved, must be 0
4536          * 04..00  TRC<4..0> Tx FIFO trigger active
4537          */
4538         write_reg(info, TRC0, tx_active_fifo_level);
4539
4540         /* TRC1 Transmit Ready Control 1
4541          *
4542          * 07..05  Reserved, must be 0
4543          * 04..00  TRC<4..0> Tx FIFO trigger inactive 0x1f = 32 bytes (full)
4544          */
4545         write_reg(info, TRC1, (unsigned char)(tx_negate_fifo_level - 1));
4546
4547         /* DMR, DMA Mode Register
4548          *
4549          * 07..05  Reserved, must be 0
4550          * 04      TMOD, Transfer Mode: 1=chained-block
4551          * 03      Reserved, must be 0
4552          * 02      NF, Number of Frames: 1=multi-frame
4553          * 01      CNTE, Frame End IRQ Counter enable: 0=disabled
4554          * 00      Reserved, must be 0
4555          *
4556          * 0001 0100
4557          */
4558         write_reg(info, TXDMA + DMR, 0x14);
4559         write_reg(info, RXDMA + DMR, 0x14);
4560
4561         /* Set chain pointer base (upper 8 bits of 24 bit addr) */
4562         write_reg(info, RXDMA + CPB,
4563                 (unsigned char)(info->buffer_list_phys >> 16));
4564
4565         /* Set chain pointer base (upper 8 bits of 24 bit addr) */
4566         write_reg(info, TXDMA + CPB,
4567                 (unsigned char)(info->buffer_list_phys >> 16));
4568
4569         /* enable status interrupts. other code enables/disables
4570          * the individual sources for these two interrupt classes.
4571          */
4572         info->ie0_value |= TXINTE + RXINTE;
4573         write_reg(info, IE0, info->ie0_value);
4574
4575         /* CTL, MSCI control register
4576          *
4577          * 07..06  Reserved, set to 0
4578          * 05      UDRNC, underrun control, 0=abort 1=CRC+flag (HDLC/BSC)
4579          * 04      IDLC, idle control, 0=mark 1=idle register
4580          * 03      BRK, break, 0=off 1 =on (async)
4581          * 02      SYNCLD, sync char load enable (BSC) 1=enabled
4582          * 01      GOP, go active on poll (LOOP mode) 1=enabled
4583          * 00      RTS, RTS output control, 0=active 1=inactive
4584          *
4585          * 0001 0001
4586          */
4587         RegValue = 0x10;
4588         if (!(info->serial_signals & SerialSignal_RTS))
4589                 RegValue |= 0x01;
4590         write_reg(info, CTL, RegValue);
4591
4592         /* preamble not supported ! */
4593
4594         tx_set_idle(info);
4595         tx_stop(info);
4596         rx_stop(info);
4597
4598         set_rate(info, info->params.clock_speed);
4599
4600         if (info->params.loopback)
4601                 enable_loopback(info,1);
4602 }
4603
4604 /* Set the transmit HDLC idle mode
4605  */
4606 void tx_set_idle(SLMP_INFO *info)
4607 {
4608         unsigned char RegValue = 0xff;
4609
4610         /* Map API idle mode to SCA register bits */
4611         switch(info->idle_mode) {
4612         case HDLC_TXIDLE_FLAGS:                 RegValue = 0x7e; break;
4613         case HDLC_TXIDLE_ALT_ZEROS_ONES:        RegValue = 0xaa; break;
4614         case HDLC_TXIDLE_ZEROS:                 RegValue = 0x00; break;
4615         case HDLC_TXIDLE_ONES:                  RegValue = 0xff; break;
4616         case HDLC_TXIDLE_ALT_MARK_SPACE:        RegValue = 0xaa; break;
4617         case HDLC_TXIDLE_SPACE:                 RegValue = 0x00; break;
4618         case HDLC_TXIDLE_MARK:                  RegValue = 0xff; break;
4619         }
4620
4621         write_reg(info, IDL, RegValue);
4622 }
4623
4624 /* Query the adapter for the state of the V24 status (input) signals.
4625  */
4626 void get_signals(SLMP_INFO *info)
4627 {
4628         u16 status = read_reg(info, SR3);
4629         u16 gpstatus = read_status_reg(info);
4630         u16 testbit;
4631
4632         /* clear all serial signals except DTR and RTS */
4633         info->serial_signals &= SerialSignal_DTR + SerialSignal_RTS;
4634
4635         /* set serial signal bits to reflect MISR */
4636
4637         if (!(status & BIT3))
4638                 info->serial_signals |= SerialSignal_CTS;
4639
4640         if ( !(status & BIT2))
4641                 info->serial_signals |= SerialSignal_DCD;
4642
4643         testbit = BIT1 << (info->port_num * 2); // Port 0..3 RI is GPDATA<1,3,5,7>
4644         if (!(gpstatus & testbit))
4645                 info->serial_signals |= SerialSignal_RI;
4646
4647         testbit = BIT0 << (info->port_num * 2); // Port 0..3 DSR is GPDATA<0,2,4,6>
4648         if (!(gpstatus & testbit))
4649                 info->serial_signals |= SerialSignal_DSR;
4650 }
4651
4652 /* Set the state of DTR and RTS based on contents of
4653  * serial_signals member of device context.
4654  */
4655 void set_signals(SLMP_INFO *info)
4656 {
4657         unsigned char RegValue;
4658         u16 EnableBit;
4659
4660         RegValue = read_reg(info, CTL);
4661         if (info->serial_signals & SerialSignal_RTS)
4662                 RegValue &= ~BIT0;
4663         else
4664                 RegValue |= BIT0;
4665         write_reg(info, CTL, RegValue);
4666
4667         // Port 0..3 DTR is ctrl reg <1,3,5,7>
4668         EnableBit = BIT1 << (info->port_num*2);
4669         if (info->serial_signals & SerialSignal_DTR)
4670                 info->port_array[0]->ctrlreg_value &= ~EnableBit;
4671         else
4672                 info->port_array[0]->ctrlreg_value |= EnableBit;
4673         write_control_reg(info);
4674 }
4675
4676 /*******************/
4677 /* DMA Buffer Code */
4678 /*******************/
4679
4680 /* Set the count for all receive buffers to SCABUFSIZE
4681  * and set the current buffer to the first buffer. This effectively
4682  * makes all buffers free and discards any data in buffers.
4683  */
4684 void rx_reset_buffers(SLMP_INFO *info)
4685 {
4686         rx_free_frame_buffers(info, 0, info->rx_buf_count - 1);
4687 }
4688
4689 /* Free the buffers used by a received frame
4690  *
4691  * info   pointer to device instance data
4692  * first  index of 1st receive buffer of frame
4693  * last   index of last receive buffer of frame
4694  */
4695 void rx_free_frame_buffers(SLMP_INFO *info, unsigned int first, unsigned int last)
4696 {
4697         int done = 0;
4698
4699         while(!done) {
4700                 /* reset current buffer for reuse */
4701                 info->rx_buf_list[first].status = 0xff;
4702
4703                 if (first == last) {
4704                         done = 1;
4705                         /* set new last rx descriptor address */
4706                         write_reg16(info, RXDMA + EDA, info->rx_buf_list_ex[first].phys_entry);
4707                 }
4708
4709                 first++;
4710                 if (first == info->rx_buf_count)
4711                         first = 0;
4712         }
4713
4714         /* set current buffer to next buffer after last buffer of frame */
4715         info->current_rx_buf = first;
4716 }
4717
4718 /* Return a received frame from the receive DMA buffers.
4719  * Only frames received without errors are returned.
4720  *
4721  * Return Value:        1 if frame returned, otherwise 0
4722  */
4723 int rx_get_frame(SLMP_INFO *info)
4724 {
4725         unsigned int StartIndex, EndIndex;      /* index of 1st and last buffers of Rx frame */
4726         unsigned short status;
4727         unsigned int framesize = 0;
4728         int ReturnCode = 0;
4729         unsigned long flags;
4730         struct tty_struct *tty = info->tty;
4731         unsigned char addr_field = 0xff;
4732         SCADESC *desc;
4733         SCADESC_EX *desc_ex;
4734
4735 CheckAgain:
4736         /* assume no frame returned, set zero length */
4737         framesize = 0;
4738         addr_field = 0xff;
4739
4740         /*
4741          * current_rx_buf points to the 1st buffer of the next available
4742          * receive frame. To find the last buffer of the frame look for
4743          * a non-zero status field in the buffer entries. (The status
4744          * field is set by the 16C32 after completing a receive frame.
4745          */
4746         StartIndex = EndIndex = info->current_rx_buf;
4747
4748         for ( ;; ) {
4749                 desc = &info->rx_buf_list[EndIndex];
4750                 desc_ex = &info->rx_buf_list_ex[EndIndex];
4751
4752                 if (desc->status == 0xff)
4753                         goto Cleanup;   /* current desc still in use, no frames available */
4754
4755                 if (framesize == 0 && info->params.addr_filter != 0xff)
4756                         addr_field = desc_ex->virt_addr[0];
4757
4758                 framesize += desc->length;
4759
4760                 /* Status != 0 means last buffer of frame */
4761                 if (desc->status)
4762                         break;
4763
4764                 EndIndex++;
4765                 if (EndIndex == info->rx_buf_count)
4766                         EndIndex = 0;
4767
4768                 if (EndIndex == info->current_rx_buf) {
4769                         /* all buffers have been 'used' but none mark      */
4770                         /* the end of a frame. Reset buffers and receiver. */
4771                         if ( info->rx_enabled ){
4772                                 spin_lock_irqsave(&info->lock,flags);
4773                                 rx_start(info);
4774                                 spin_unlock_irqrestore(&info->lock,flags);
4775                         }
4776                         goto Cleanup;
4777                 }
4778
4779         }
4780
4781         /* check status of receive frame */
4782
4783         /* frame status is byte stored after frame data
4784          *
4785          * 7 EOM (end of msg), 1 = last buffer of frame
4786          * 6 Short Frame, 1 = short frame
4787          * 5 Abort, 1 = frame aborted
4788          * 4 Residue, 1 = last byte is partial
4789          * 3 Overrun, 1 = overrun occurred during frame reception
4790          * 2 CRC,     1 = CRC error detected
4791          *
4792          */
4793         status = desc->status;
4794
4795         /* ignore CRC bit if not using CRC (bit is undefined) */
4796         /* Note:CRC is not save to data buffer */
4797         if (info->params.crc_type == HDLC_CRC_NONE)
4798                 status &= ~BIT2;
4799
4800         if (framesize == 0 ||
4801                  (addr_field != 0xff && addr_field != info->params.addr_filter)) {
4802                 /* discard 0 byte frames, this seems to occur sometime
4803                  * when remote is idling flags.
4804                  */
4805                 rx_free_frame_buffers(info, StartIndex, EndIndex);
4806                 goto CheckAgain;
4807         }
4808
4809         if (framesize < 2)
4810                 status |= BIT6;
4811
4812         if (status & (BIT6+BIT5+BIT3+BIT2)) {
4813                 /* received frame has errors,
4814                  * update counts and mark frame size as 0
4815                  */
4816                 if (status & BIT6)
4817                         info->icount.rxshort++;
4818                 else if (status & BIT5)
4819                         info->icount.rxabort++;
4820                 else if (status & BIT3)
4821                         info->icount.rxover++;
4822                 else
4823                         info->icount.rxcrc++;
4824
4825                 framesize = 0;
4826
4827 #ifdef CONFIG_SYNCLINK_SYNCPPP
4828                 info->netstats.rx_errors++;
4829                 info->netstats.rx_frame_errors++;
4830 #endif
4831         }
4832
4833         if ( debug_level >= DEBUG_LEVEL_BH )
4834                 printk("%s(%d):%s rx_get_frame() status=%04X size=%d\n",
4835                         __FILE__,__LINE__,info->device_name,status,framesize);
4836
4837         if ( debug_level >= DEBUG_LEVEL_DATA )
4838                 trace_block(info,info->rx_buf_list_ex[StartIndex].virt_addr,
4839                         MIN(framesize,SCABUFSIZE),0);
4840
4841         if (framesize) {
4842                 if (framesize > info->max_frame_size)
4843                         info->icount.rxlong++;
4844                 else {
4845                         /* copy dma buffer(s) to contiguous intermediate buffer */
4846                         int copy_count = framesize;
4847                         int index = StartIndex;
4848                         unsigned char *ptmp = info->tmp_rx_buf;
4849                         info->tmp_rx_buf_count = framesize;
4850
4851                         info->icount.rxok++;
4852
4853                         while(copy_count) {
4854                                 int partial_count = MIN(copy_count,SCABUFSIZE);
4855                                 memcpy( ptmp,
4856                                         info->rx_buf_list_ex[index].virt_addr,
4857                                         partial_count );
4858                                 ptmp += partial_count;
4859                                 copy_count -= partial_count;
4860
4861                                 if ( ++index == info->rx_buf_count )
4862                                         index = 0;
4863                         }
4864
4865 #ifdef CONFIG_SYNCLINK_SYNCPPP
4866                         if (info->netcount) {
4867                                 /* pass frame to syncppp device */
4868                                 sppp_rx_done(info,info->tmp_rx_buf,framesize);
4869                         }
4870                         else
4871 #endif
4872                         {
4873                                 if ( tty && tty->ldisc.receive_buf ) {
4874                                         /* Call the line discipline receive callback directly. */
4875                                         tty->ldisc.receive_buf(tty,
4876                                                 info->tmp_rx_buf,
4877                                                 info->flag_buf,
4878                                                 framesize);
4879                                 }
4880                         }
4881                 }
4882         }
4883         /* Free the buffers used by this frame. */
4884         rx_free_frame_buffers( info, StartIndex, EndIndex );
4885
4886         ReturnCode = 1;
4887
4888 Cleanup:
4889         if ( info->rx_enabled && info->rx_overflow ) {
4890                 /* Receiver is enabled, but needs to restarted due to
4891                  * rx buffer overflow. If buffers are empty, restart receiver.
4892                  */
4893                 if (info->rx_buf_list[EndIndex].status == 0xff) {
4894                         spin_lock_irqsave(&info->lock,flags);
4895                         rx_start(info);
4896                         spin_unlock_irqrestore(&info->lock,flags);
4897                 }
4898         }
4899
4900         return ReturnCode;
4901 }
4902
4903 /* load the transmit DMA buffer with data
4904  */
4905 void tx_load_dma_buffer(SLMP_INFO *info, const char *buf, unsigned int count)
4906 {
4907         unsigned short copy_count;
4908         unsigned int i = 0;
4909         SCADESC *desc;
4910         SCADESC_EX *desc_ex;
4911
4912         if ( debug_level >= DEBUG_LEVEL_DATA )
4913                 trace_block(info,buf, MIN(count,SCABUFSIZE), 1);
4914
4915         /* Copy source buffer to one or more DMA buffers, starting with
4916          * the first transmit dma buffer.
4917          */
4918         for(i=0;;)
4919         {
4920                 copy_count = MIN(count,SCABUFSIZE);
4921
4922                 desc = &info->tx_buf_list[i];
4923                 desc_ex = &info->tx_buf_list_ex[i];
4924
4925                 load_pci_memory(info, desc_ex->virt_addr,buf,copy_count);
4926
4927                 desc->length = copy_count;
4928                 desc->status = 0;
4929
4930                 buf += copy_count;
4931                 count -= copy_count;
4932
4933                 if (!count)
4934                         break;
4935
4936                 i++;
4937                 if (i >= info->tx_buf_count)
4938                         i = 0;
4939         }
4940
4941         info->tx_buf_list[i].status = 0x81;     /* set EOM and EOT status */
4942         info->last_tx_buf = ++i;
4943 }
4944
4945 int register_test(SLMP_INFO *info)
4946 {
4947         static unsigned char testval[] = {0x00, 0xff, 0xaa, 0x55, 0x69, 0x96};
4948         static unsigned int count = sizeof(testval)/sizeof(unsigned char);
4949         unsigned int i;
4950         int rc = TRUE;
4951         unsigned long flags;
4952
4953         spin_lock_irqsave(&info->lock,flags);
4954         reset_port(info);
4955
4956         /* assume failure */
4957         info->init_error = DiagStatus_AddressFailure;
4958
4959         /* Write bit patterns to various registers but do it out of */
4960         /* sync, then read back and verify values. */
4961
4962         for (i = 0 ; i < count ; i++) {
4963                 write_reg(info, TMC, testval[i]);
4964                 write_reg(info, IDL, testval[(i+1)%count]);
4965                 write_reg(info, SA0, testval[(i+2)%count]);
4966                 write_reg(info, SA1, testval[(i+3)%count]);
4967
4968                 if ( (read_reg(info, TMC) != testval[i]) ||
4969                           (read_reg(info, IDL) != testval[(i+1)%count]) ||
4970                           (read_reg(info, SA0) != testval[(i+2)%count]) ||
4971                           (read_reg(info, SA1) != testval[(i+3)%count]) )
4972                 {
4973                         rc = FALSE;
4974                         break;
4975                 }
4976         }
4977
4978         reset_port(info);
4979         spin_unlock_irqrestore(&info->lock,flags);
4980
4981         return rc;
4982 }
4983
4984 int irq_test(SLMP_INFO *info)
4985 {
4986         unsigned long timeout;
4987         unsigned long flags;
4988
4989         unsigned char timer = (info->port_num & 1) ? TIMER2 : TIMER0;
4990
4991         spin_lock_irqsave(&info->lock,flags);
4992         reset_port(info);
4993
4994         /* assume failure */
4995         info->init_error = DiagStatus_IrqFailure;
4996         info->irq_occurred = FALSE;
4997
4998         /* setup timer0 on SCA0 to interrupt */
4999
5000         /* IER2<7..4> = timer<3..0> interrupt enables (1=enabled) */
5001         write_reg(info, IER2, (unsigned char)((info->port_num & 1) ? BIT6 : BIT4));
5002
5003         write_reg(info, (unsigned char)(timer + TEPR), 0);      /* timer expand prescale */
5004         write_reg16(info, (unsigned char)(timer + TCONR), 1);   /* timer constant */
5005
5006
5007         /* TMCS, Timer Control/Status Register
5008          *
5009          * 07      CMF, Compare match flag (read only) 1=match
5010          * 06      ECMI, CMF Interrupt Enable: 1=enabled
5011          * 05      Reserved, must be 0
5012          * 04      TME, Timer Enable
5013          * 03..00  Reserved, must be 0
5014          *
5015          * 0101 0000
5016          */
5017         write_reg(info, (unsigned char)(timer + TMCS), 0x50);
5018
5019         spin_unlock_irqrestore(&info->lock,flags);
5020
5021         timeout=100;
5022         while( timeout-- && !info->irq_occurred ) {
5023                 set_current_state(TASK_INTERRUPTIBLE);
5024                 schedule_timeout(jiffies_from_ms(10));
5025         }
5026
5027         spin_lock_irqsave(&info->lock,flags);
5028         reset_port(info);
5029         spin_unlock_irqrestore(&info->lock,flags);
5030
5031         return info->irq_occurred;
5032 }
5033
5034 /* initialize individual SCA device (2 ports)
5035  */
5036 int sca_init(SLMP_INFO *info)
5037 {
5038         /* set wait controller to single mem partition (low), no wait states */
5039         write_reg(info, PABR0, 0);      /* wait controller addr boundary 0 */
5040         write_reg(info, PABR1, 0);      /* wait controller addr boundary 1 */
5041         write_reg(info, WCRL, 0);       /* wait controller low range */
5042         write_reg(info, WCRM, 0);       /* wait controller mid range */
5043         write_reg(info, WCRH, 0);       /* wait controller high range */
5044
5045         /* DPCR, DMA Priority Control
5046          *
5047          * 07..05  Not used, must be 0
5048          * 04      BRC, bus release condition: 0=all transfers complete
5049          * 03      CCC, channel change condition: 0=every cycle
5050          * 02..00  PR<2..0>, priority 100=round robin
5051          *
5052          * 00000100 = 0x04
5053          */
5054         write_reg(info, DPCR, dma_priority);
5055
5056         /* DMA Master Enable, BIT7: 1=enable all channels */
5057         write_reg(info, DMER, 0x80);
5058
5059         /* enable all interrupt classes */
5060         write_reg(info, IER0, 0xff);    /* TxRDY,RxRDY,TxINT,RxINT (ports 0-1) */
5061         write_reg(info, IER1, 0xff);    /* DMIB,DMIA (channels 0-3) */
5062         write_reg(info, IER2, 0xf0);    /* TIRQ (timers 0-3) */
5063
5064         /* ITCR, interrupt control register
5065          * 07      IPC, interrupt priority, 0=MSCI->DMA
5066          * 06..05  IAK<1..0>, Acknowledge cycle, 00=non-ack cycle
5067          * 04      VOS, Vector Output, 0=unmodified vector
5068          * 03..00  Reserved, must be 0
5069          */
5070         write_reg(info, ITCR, 0);
5071
5072         return TRUE;
5073 }
5074
5075 /* initialize adapter hardware
5076  */
5077 int init_adapter(SLMP_INFO *info)
5078 {
5079         int i;
5080
5081         /* Set BIT30 of Local Control Reg 0x50 to reset SCA */
5082         volatile u32 *MiscCtrl = (u32 *)(info->lcr_base + 0x50);
5083         u32 readval;
5084
5085         info->misc_ctrl_value |= BIT30;
5086         *MiscCtrl = info->misc_ctrl_value;
5087
5088         /*
5089          * Force at least 170ns delay before clearing
5090          * reset bit. Each read from LCR takes at least
5091          * 30ns so 10 times for 300ns to be safe.
5092          */
5093         for(i=0;i<10;i++)
5094                 readval = *MiscCtrl;
5095
5096         info->misc_ctrl_value &= ~BIT30;
5097         *MiscCtrl = info->misc_ctrl_value;
5098
5099         /* init control reg (all DTRs off, all clksel=input) */
5100         info->ctrlreg_value = 0xaa;
5101         write_control_reg(info);
5102
5103         {
5104                 volatile u32 *LCR1BRDR = (u32 *)(info->lcr_base + 0x2c);
5105                 lcr1_brdr_value &= ~(BIT5 + BIT4 + BIT3);
5106
5107                 switch(read_ahead_count)
5108                 {
5109                 case 16:
5110                         lcr1_brdr_value |= BIT5 + BIT4 + BIT3;
5111                         break;
5112                 case 8:
5113                         lcr1_brdr_value |= BIT5 + BIT4;
5114                         break;
5115                 case 4:
5116                         lcr1_brdr_value |= BIT5 + BIT3;
5117                         break;
5118                 case 0:
5119                         lcr1_brdr_value |= BIT5;
5120                         break;
5121                 }
5122
5123                 *LCR1BRDR = lcr1_brdr_value;
5124                 *MiscCtrl = misc_ctrl_value;
5125         }
5126
5127         sca_init(info->port_array[0]);
5128         sca_init(info->port_array[2]);
5129
5130         return TRUE;
5131 }
5132
5133 /* Loopback an HDLC frame to test the hardware
5134  * interrupt and DMA functions.
5135  */
5136 int loopback_test(SLMP_INFO *info)
5137 {
5138 #define TESTFRAMESIZE 20
5139
5140         unsigned long timeout;
5141         u16 count = TESTFRAMESIZE;
5142         unsigned char buf[TESTFRAMESIZE];
5143         int rc = FALSE;
5144         unsigned long flags;
5145
5146         struct tty_struct *oldtty = info->tty;
5147         u32 speed = info->params.clock_speed;
5148
5149         info->params.clock_speed = 3686400;
5150         info->tty = NULL;
5151
5152         /* assume failure */
5153         info->init_error = DiagStatus_DmaFailure;
5154
5155         /* build and send transmit frame */
5156         for (count = 0; count < TESTFRAMESIZE;++count)
5157                 buf[count] = (unsigned char)count;
5158
5159         memset(info->tmp_rx_buf,0,TESTFRAMESIZE);
5160
5161         /* program hardware for HDLC and enabled receiver */
5162         spin_lock_irqsave(&info->lock,flags);
5163         hdlc_mode(info);
5164         enable_loopback(info,1);
5165         rx_start(info);
5166         info->tx_count = count;
5167         tx_load_dma_buffer(info,buf,count);
5168         tx_start(info);
5169         spin_unlock_irqrestore(&info->lock,flags);
5170
5171         /* wait for receive complete */
5172         /* Set a timeout for waiting for interrupt. */
5173         for ( timeout = 100; timeout; --timeout ) {
5174                 set_current_state(TASK_INTERRUPTIBLE);
5175                 schedule_timeout(jiffies_from_ms(10));
5176
5177                 if (rx_get_frame(info)) {
5178                         rc = TRUE;
5179                         break;
5180                 }
5181         }
5182
5183         /* verify received frame length and contents */
5184         if (rc == TRUE &&
5185                 ( info->tmp_rx_buf_count != count ||
5186                   memcmp(buf, info->tmp_rx_buf,count))) {
5187                 rc = FALSE;
5188         }
5189
5190         spin_lock_irqsave(&info->lock,flags);
5191         reset_adapter(info);
5192         spin_unlock_irqrestore(&info->lock,flags);
5193
5194         info->params.clock_speed = speed;
5195         info->tty = oldtty;
5196
5197         return rc;
5198 }
5199
5200 /* Perform diagnostics on hardware
5201  */
5202 int adapter_test( SLMP_INFO *info )
5203 {
5204         unsigned long flags;
5205         if ( debug_level >= DEBUG_LEVEL_INFO )
5206                 printk( "%s(%d):Testing device %s\n",
5207                         __FILE__,__LINE__,info->device_name );
5208
5209         spin_lock_irqsave(&info->lock,flags);
5210         init_adapter(info);
5211         spin_unlock_irqrestore(&info->lock,flags);
5212
5213         info->port_array[0]->port_count = 0;
5214
5215         if ( register_test(info->port_array[0]) &&
5216                 register_test(info->port_array[1])) {
5217
5218                 info->port_array[0]->port_count = 2;
5219
5220                 if ( register_test(info->port_array[2]) &&
5221                         register_test(info->port_array[3]) )
5222                         info->port_array[0]->port_count += 2;
5223         }
5224         else {
5225                 printk( "%s(%d):Register test failure for device %s Addr=%08lX\n",
5226                         __FILE__,__LINE__,info->device_name, (unsigned long)(info->phys_sca_base));
5227                 return -ENODEV;
5228         }
5229
5230         if ( !irq_test(info->port_array[0]) ||
5231                 !irq_test(info->port_array[1]) ||
5232                  (info->port_count == 4 && !irq_test(info->port_array[2])) ||
5233                  (info->port_count == 4 && !irq_test(info->port_array[3]))) {
5234                 printk( "%s(%d):Interrupt test failure for device %s IRQ=%d\n",
5235                         __FILE__,__LINE__,info->device_name, (unsigned short)(info->irq_level) );
5236                 return -ENODEV;
5237         }
5238
5239         if (!loopback_test(info->port_array[0]) ||
5240                 !loopback_test(info->port_array[1]) ||
5241                  (info->port_count == 4 && !loopback_test(info->port_array[2])) ||
5242                  (info->port_count == 4 && !loopback_test(info->port_array[3]))) {
5243                 printk( "%s(%d):DMA test failure for device %s\n",
5244                         __FILE__,__LINE__,info->device_name);
5245                 return -ENODEV;
5246         }
5247
5248         if ( debug_level >= DEBUG_LEVEL_INFO )
5249                 printk( "%s(%d):device %s passed diagnostics\n",
5250                         __FILE__,__LINE__,info->device_name );
5251
5252         info->port_array[0]->init_error = 0;
5253         info->port_array[1]->init_error = 0;
5254         if ( info->port_count > 2 ) {
5255                 info->port_array[2]->init_error = 0;
5256                 info->port_array[3]->init_error = 0;
5257         }
5258
5259         return 0;
5260 }
5261
5262 /* Test the shared memory on a PCI adapter.
5263  */
5264 int memory_test(SLMP_INFO *info)
5265 {
5266         static unsigned long testval[] = { 0x0, 0x55555555, 0xaaaaaaaa,
5267                 0x66666666, 0x99999999, 0xffffffff, 0x12345678 };
5268         unsigned long count = sizeof(testval)/sizeof(unsigned long);
5269         unsigned long i;
5270         unsigned long limit = SCA_MEM_SIZE/sizeof(unsigned long);
5271         unsigned long * addr = (unsigned long *)info->memory_base;
5272
5273         /* Test data lines with test pattern at one location. */
5274
5275         for ( i = 0 ; i < count ; i++ ) {
5276                 *addr = testval[i];
5277                 if ( *addr != testval[i] )
5278                         return FALSE;
5279         }
5280
5281         /* Test address lines with incrementing pattern over */
5282         /* entire address range. */
5283
5284         for ( i = 0 ; i < limit ; i++ ) {
5285                 *addr = i * 4;
5286                 addr++;
5287         }
5288
5289         addr = (unsigned long *)info->memory_base;
5290
5291         for ( i = 0 ; i < limit ; i++ ) {
5292                 if ( *addr != i * 4 )
5293                         return FALSE;
5294                 addr++;
5295         }
5296
5297         memset( info->memory_base, 0, SCA_MEM_SIZE );
5298         return TRUE;
5299 }
5300
5301 /* Load data into PCI adapter shared memory.
5302  *
5303  * The PCI9050 releases control of the local bus
5304  * after completing the current read or write operation.
5305  *
5306  * While the PCI9050 write FIFO not empty, the
5307  * PCI9050 treats all of the writes as a single transaction
5308  * and does not release the bus. This causes DMA latency problems
5309  * at high speeds when copying large data blocks to the shared memory.
5310  *
5311  * This function breaks a write into multiple transations by
5312  * interleaving a read which flushes the write FIFO and 'completes'
5313  * the write transation. This allows any pending DMA request to gain control
5314  * of the local bus in a timely fasion.
5315  */
5316 void load_pci_memory(SLMP_INFO *info, char* dest, const char* src, unsigned short count)
5317 {
5318         /* A load interval of 16 allows for 4 32-bit writes at */
5319         /* 136ns each for a maximum latency of 542ns on the local bus.*/
5320
5321         unsigned short interval = count / sca_pci_load_interval;
5322         unsigned short i;
5323
5324         for ( i = 0 ; i < interval ; i++ )
5325         {
5326                 memcpy(dest, src, sca_pci_load_interval);
5327                 read_status_reg(info);
5328                 dest += sca_pci_load_interval;
5329                 src += sca_pci_load_interval;
5330         }
5331
5332         memcpy(dest, src, count % sca_pci_load_interval);
5333 }
5334
5335 void trace_block(SLMP_INFO *info,const char* data, int count, int xmit)
5336 {
5337         int i;
5338         int linecount;
5339         if (xmit)
5340                 printk("%s tx data:\n",info->device_name);
5341         else
5342                 printk("%s rx data:\n",info->device_name);
5343
5344         while(count) {
5345                 if (count > 16)
5346                         linecount = 16;
5347                 else
5348                         linecount = count;
5349
5350                 for(i=0;i<linecount;i++)
5351                         printk("%02X ",(unsigned char)data[i]);
5352                 for(;i<17;i++)
5353                         printk("   ");
5354                 for(i=0;i<linecount;i++) {
5355                         if (data[i]>=040 && data[i]<=0176)
5356                                 printk("%c",data[i]);
5357                         else
5358                                 printk(".");
5359                 }
5360                 printk("\n");
5361
5362                 data  += linecount;
5363                 count -= linecount;
5364         }
5365 }       /* end of trace_block() */
5366
5367 /* called when HDLC frame times out
5368  * update stats and do tx completion processing
5369  */
5370 void tx_timeout(unsigned long context)
5371 {
5372         SLMP_INFO *info = (SLMP_INFO*)context;
5373         unsigned long flags;
5374
5375         if ( debug_level >= DEBUG_LEVEL_INFO )
5376                 printk( "%s(%d):%s tx_timeout()\n",
5377                         __FILE__,__LINE__,info->device_name);
5378         if(info->tx_active && info->params.mode == MGSL_MODE_HDLC) {
5379                 info->icount.txtimeout++;
5380         }
5381         spin_lock_irqsave(&info->lock,flags);
5382         info->tx_active = 0;
5383         info->tx_count = info->tx_put = info->tx_get = 0;
5384
5385         spin_unlock_irqrestore(&info->lock,flags);
5386
5387 #ifdef CONFIG_SYNCLINK_SYNCPPP
5388         if (info->netcount)
5389                 sppp_tx_done(info);
5390         else
5391 #endif
5392                 bh_transmit(info);
5393 }
5394
5395 /* called to periodically check the DSR/RI modem signal input status
5396  */
5397 void status_timeout(unsigned long context)
5398 {
5399         u16 status = 0;
5400         SLMP_INFO *info = (SLMP_INFO*)context;
5401         unsigned long flags;
5402         unsigned char delta;
5403
5404
5405         spin_lock_irqsave(&info->lock,flags);
5406         get_signals(info);
5407         spin_unlock_irqrestore(&info->lock,flags);
5408
5409         /* check for DSR/RI state change */
5410
5411         delta = info->old_signals ^ info->serial_signals;
5412         info->old_signals = info->serial_signals;
5413
5414         if (delta & SerialSignal_DSR)
5415                 status |= MISCSTATUS_DSR_LATCHED|(info->serial_signals&SerialSignal_DSR);
5416
5417         if (delta & SerialSignal_RI)
5418                 status |= MISCSTATUS_RI_LATCHED|(info->serial_signals&SerialSignal_RI);
5419
5420         if (delta & SerialSignal_DCD)
5421                 status |= MISCSTATUS_DCD_LATCHED|(info->serial_signals&SerialSignal_DCD);
5422
5423         if (delta & SerialSignal_CTS)
5424                 status |= MISCSTATUS_CTS_LATCHED|(info->serial_signals&SerialSignal_CTS);
5425
5426         if (status)
5427                 isr_io_pin(info,status);
5428
5429         info->status_timer.data = (unsigned long)info;
5430         info->status_timer.function = status_timeout;
5431         info->status_timer.expires = jiffies + jiffies_from_ms(10);
5432         add_timer(&info->status_timer);
5433 }
5434
5435
5436 /* Register Access Routines -
5437  * All registers are memory mapped
5438  */
5439 #define CALC_REGADDR() \
5440         unsigned char * RegAddr = (unsigned char*)(info->sca_base + Addr); \
5441         if (info->port_num > 1) \
5442                 RegAddr += 256;                 /* port 0-1 SCA0, 2-3 SCA1 */ \
5443         if ( info->port_num & 1) { \
5444                 if (Addr > 0x7f) \
5445                         RegAddr += 0x40;        /* DMA access */ \
5446                 else if (Addr > 0x1f && Addr < 0x60) \
5447                         RegAddr += 0x20;        /* MSCI access */ \
5448         }
5449
5450
5451 unsigned char read_reg(SLMP_INFO * info, unsigned char Addr)
5452 {
5453         CALC_REGADDR();
5454         return *RegAddr;
5455 }
5456 void write_reg(SLMP_INFO * info, unsigned char Addr, unsigned char Value)
5457 {
5458         CALC_REGADDR();
5459         *RegAddr = Value;
5460 }
5461
5462 u16 read_reg16(SLMP_INFO * info, unsigned char Addr)
5463 {
5464         CALC_REGADDR();
5465         return *((u16 *)RegAddr);
5466 }
5467
5468 void write_reg16(SLMP_INFO * info, unsigned char Addr, u16 Value)
5469 {
5470         CALC_REGADDR();
5471         *((u16 *)RegAddr) = Value;
5472 }
5473
5474 unsigned char read_status_reg(SLMP_INFO * info)
5475 {
5476         unsigned char *RegAddr = (unsigned char *)info->statctrl_base;
5477         return *RegAddr;
5478 }
5479
5480 void write_control_reg(SLMP_INFO * info)
5481 {
5482         unsigned char *RegAddr = (unsigned char *)info->statctrl_base;
5483         *RegAddr = info->port_array[0]->ctrlreg_value;
5484 }
5485
5486
5487 static int __devinit synclinkmp_init_one (struct pci_dev *dev,
5488                                           const struct pci_device_id *ent)
5489 {
5490         if (pci_enable_device(dev)) {
5491                 printk("error enabling pci device %p\n", dev);
5492                 return -EIO;
5493         }
5494         device_init( ++synclinkmp_adapter_count, dev );
5495         return 0;
5496 }
5497
5498 static void __devexit synclinkmp_remove_one (struct pci_dev *dev)
5499 {
5500 }